inv_mpu_core.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3* Copyright (C) 2012 Invensense, Inc.
   4*/
   5
   6#include <linux/module.h>
   7#include <linux/slab.h>
   8#include <linux/i2c.h>
   9#include <linux/err.h>
  10#include <linux/delay.h>
  11#include <linux/sysfs.h>
  12#include <linux/jiffies.h>
  13#include <linux/irq.h>
  14#include <linux/interrupt.h>
  15#include <linux/acpi.h>
  16#include <linux/platform_device.h>
  17#include <linux/regulator/consumer.h>
  18#include <linux/math64.h>
  19#include <linux/minmax.h>
  20#include <linux/pm.h>
  21#include <linux/pm_runtime.h>
  22#include <linux/property.h>
  23
  24#include <linux/iio/common/inv_sensors_timestamp.h>
  25#include <linux/iio/iio.h>
  26
  27#include "inv_mpu_iio.h"
  28#include "inv_mpu_magn.h"
  29
  30/*
  31 * this is the gyro scale translated from dynamic range plus/minus
  32 * {250, 500, 1000, 2000} to rad/s
  33 */
  34static const int gyro_scale_6050[] = {133090, 266181, 532362, 1064724};
  35
  36/*
  37 * this is the accel scale translated from dynamic range plus/minus
  38 * {2, 4, 8, 16} to m/s^2
  39 */
  40static const int accel_scale[] = {598, 1196, 2392, 4785};
  41
  42static const struct inv_mpu6050_reg_map reg_set_icm20602 = {
  43	.sample_rate_div	= INV_MPU6050_REG_SAMPLE_RATE_DIV,
  44	.lpf                    = INV_MPU6050_REG_CONFIG,
  45	.accel_lpf              = INV_MPU6500_REG_ACCEL_CONFIG_2,
  46	.user_ctrl              = INV_MPU6050_REG_USER_CTRL,
  47	.fifo_en                = INV_MPU6050_REG_FIFO_EN,
  48	.gyro_config            = INV_MPU6050_REG_GYRO_CONFIG,
  49	.accl_config            = INV_MPU6050_REG_ACCEL_CONFIG,
  50	.fifo_count_h           = INV_MPU6050_REG_FIFO_COUNT_H,
  51	.fifo_r_w               = INV_MPU6050_REG_FIFO_R_W,
  52	.raw_gyro               = INV_MPU6050_REG_RAW_GYRO,
  53	.raw_accl               = INV_MPU6050_REG_RAW_ACCEL,
  54	.temperature            = INV_MPU6050_REG_TEMPERATURE,
  55	.int_enable             = INV_MPU6050_REG_INT_ENABLE,
  56	.int_status             = INV_MPU6050_REG_INT_STATUS,
  57	.pwr_mgmt_1             = INV_MPU6050_REG_PWR_MGMT_1,
  58	.pwr_mgmt_2             = INV_MPU6050_REG_PWR_MGMT_2,
  59	.int_pin_cfg            = INV_MPU6050_REG_INT_PIN_CFG,
  60	.accl_offset            = INV_MPU6500_REG_ACCEL_OFFSET,
  61	.gyro_offset            = INV_MPU6050_REG_GYRO_OFFSET,
  62	.i2c_if                 = INV_ICM20602_REG_I2C_IF,
  63};
  64
  65static const struct inv_mpu6050_reg_map reg_set_6500 = {
  66	.sample_rate_div	= INV_MPU6050_REG_SAMPLE_RATE_DIV,
  67	.lpf                    = INV_MPU6050_REG_CONFIG,
  68	.accel_lpf              = INV_MPU6500_REG_ACCEL_CONFIG_2,
  69	.user_ctrl              = INV_MPU6050_REG_USER_CTRL,
  70	.fifo_en                = INV_MPU6050_REG_FIFO_EN,
  71	.gyro_config            = INV_MPU6050_REG_GYRO_CONFIG,
  72	.accl_config            = INV_MPU6050_REG_ACCEL_CONFIG,
  73	.fifo_count_h           = INV_MPU6050_REG_FIFO_COUNT_H,
  74	.fifo_r_w               = INV_MPU6050_REG_FIFO_R_W,
  75	.raw_gyro               = INV_MPU6050_REG_RAW_GYRO,
  76	.raw_accl               = INV_MPU6050_REG_RAW_ACCEL,
  77	.temperature            = INV_MPU6050_REG_TEMPERATURE,
  78	.int_enable             = INV_MPU6050_REG_INT_ENABLE,
  79	.int_status             = INV_MPU6050_REG_INT_STATUS,
  80	.pwr_mgmt_1             = INV_MPU6050_REG_PWR_MGMT_1,
  81	.pwr_mgmt_2             = INV_MPU6050_REG_PWR_MGMT_2,
  82	.int_pin_cfg		= INV_MPU6050_REG_INT_PIN_CFG,
  83	.accl_offset		= INV_MPU6500_REG_ACCEL_OFFSET,
  84	.gyro_offset		= INV_MPU6050_REG_GYRO_OFFSET,
  85	.i2c_if                 = 0,
  86};
  87
  88static const struct inv_mpu6050_reg_map reg_set_6050 = {
  89	.sample_rate_div	= INV_MPU6050_REG_SAMPLE_RATE_DIV,
  90	.lpf                    = INV_MPU6050_REG_CONFIG,
  91	.user_ctrl              = INV_MPU6050_REG_USER_CTRL,
  92	.fifo_en                = INV_MPU6050_REG_FIFO_EN,
  93	.gyro_config            = INV_MPU6050_REG_GYRO_CONFIG,
  94	.accl_config            = INV_MPU6050_REG_ACCEL_CONFIG,
  95	.fifo_count_h           = INV_MPU6050_REG_FIFO_COUNT_H,
  96	.fifo_r_w               = INV_MPU6050_REG_FIFO_R_W,
  97	.raw_gyro               = INV_MPU6050_REG_RAW_GYRO,
  98	.raw_accl               = INV_MPU6050_REG_RAW_ACCEL,
  99	.temperature            = INV_MPU6050_REG_TEMPERATURE,
 100	.int_enable             = INV_MPU6050_REG_INT_ENABLE,
 101	.pwr_mgmt_1             = INV_MPU6050_REG_PWR_MGMT_1,
 102	.pwr_mgmt_2             = INV_MPU6050_REG_PWR_MGMT_2,
 103	.int_pin_cfg		= INV_MPU6050_REG_INT_PIN_CFG,
 104	.accl_offset		= INV_MPU6050_REG_ACCEL_OFFSET,
 105	.gyro_offset		= INV_MPU6050_REG_GYRO_OFFSET,
 106	.i2c_if                 = 0,
 107};
 108
 109static const struct inv_mpu6050_chip_config chip_config_6050 = {
 110	.clk = INV_CLK_INTERNAL,
 111	.fsr = INV_MPU6050_FSR_2000DPS,
 112	.lpf = INV_MPU6050_FILTER_20HZ,
 113	.divider = INV_MPU6050_FIFO_RATE_TO_DIVIDER(50),
 114	.gyro_en = true,
 115	.accl_en = true,
 116	.temp_en = true,
 117	.magn_en = false,
 118	.gyro_fifo_enable = false,
 119	.accl_fifo_enable = false,
 120	.temp_fifo_enable = false,
 121	.magn_fifo_enable = false,
 122	.accl_fs = INV_MPU6050_FS_02G,
 123	.user_ctrl = 0,
 124};
 125
 126static const struct inv_mpu6050_chip_config chip_config_6500 = {
 127	.clk = INV_CLK_PLL,
 128	.fsr = INV_MPU6050_FSR_2000DPS,
 129	.lpf = INV_MPU6050_FILTER_20HZ,
 130	.divider = INV_MPU6050_FIFO_RATE_TO_DIVIDER(50),
 131	.gyro_en = true,
 132	.accl_en = true,
 133	.temp_en = true,
 134	.magn_en = false,
 135	.gyro_fifo_enable = false,
 136	.accl_fifo_enable = false,
 137	.temp_fifo_enable = false,
 138	.magn_fifo_enable = false,
 139	.accl_fs = INV_MPU6050_FS_02G,
 140	.user_ctrl = 0,
 141};
 142
 143/* Indexed by enum inv_devices */
 144static const struct inv_mpu6050_hw hw_info[] = {
 145	{
 146		.whoami = INV_MPU6050_WHOAMI_VALUE,
 147		.name = "MPU6050",
 148		.reg = &reg_set_6050,
 149		.config = &chip_config_6050,
 150		.fifo_size = 1024,
 151		.temp = {INV_MPU6050_TEMP_OFFSET, INV_MPU6050_TEMP_SCALE},
 152		.startup_time = {INV_MPU6050_GYRO_STARTUP_TIME, INV_MPU6050_ACCEL_STARTUP_TIME},
 153	},
 154	{
 155		.whoami = INV_MPU6500_WHOAMI_VALUE,
 156		.name = "MPU6500",
 157		.reg = &reg_set_6500,
 158		.config = &chip_config_6500,
 159		.fifo_size = 512,
 160		.temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
 161		.startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
 162	},
 163	{
 164		.whoami = INV_MPU6515_WHOAMI_VALUE,
 165		.name = "MPU6515",
 166		.reg = &reg_set_6500,
 167		.config = &chip_config_6500,
 168		.fifo_size = 512,
 169		.temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
 170		.startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
 171	},
 172	{
 173		.whoami = INV_MPU6880_WHOAMI_VALUE,
 174		.name = "MPU6880",
 175		.reg = &reg_set_6500,
 176		.config = &chip_config_6500,
 177		.fifo_size = 4096,
 178		.temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
 179		.startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
 180	},
 181	{
 182		.whoami = INV_MPU6000_WHOAMI_VALUE,
 183		.name = "MPU6000",
 184		.reg = &reg_set_6050,
 185		.config = &chip_config_6050,
 186		.fifo_size = 1024,
 187		.temp = {INV_MPU6050_TEMP_OFFSET, INV_MPU6050_TEMP_SCALE},
 188		.startup_time = {INV_MPU6050_GYRO_STARTUP_TIME, INV_MPU6050_ACCEL_STARTUP_TIME},
 189	},
 190	{
 191		.whoami = INV_MPU9150_WHOAMI_VALUE,
 192		.name = "MPU9150",
 193		.reg = &reg_set_6050,
 194		.config = &chip_config_6050,
 195		.fifo_size = 1024,
 196		.temp = {INV_MPU6050_TEMP_OFFSET, INV_MPU6050_TEMP_SCALE},
 197		.startup_time = {INV_MPU6050_GYRO_STARTUP_TIME, INV_MPU6050_ACCEL_STARTUP_TIME},
 198	},
 199	{
 200		.whoami = INV_MPU9250_WHOAMI_VALUE,
 201		.name = "MPU9250",
 202		.reg = &reg_set_6500,
 203		.config = &chip_config_6500,
 204		.fifo_size = 512,
 205		.temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
 206		.startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
 207	},
 208	{
 209		.whoami = INV_MPU9255_WHOAMI_VALUE,
 210		.name = "MPU9255",
 211		.reg = &reg_set_6500,
 212		.config = &chip_config_6500,
 213		.fifo_size = 512,
 214		.temp = {INV_MPU6500_TEMP_OFFSET, INV_MPU6500_TEMP_SCALE},
 215		.startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
 216	},
 217	{
 218		.whoami = INV_ICM20608_WHOAMI_VALUE,
 219		.name = "ICM20608",
 220		.reg = &reg_set_6500,
 221		.config = &chip_config_6500,
 222		.fifo_size = 512,
 223		.temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
 224		.startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
 225	},
 226	{
 227		.whoami = INV_ICM20608D_WHOAMI_VALUE,
 228		.name = "ICM20608D",
 229		.reg = &reg_set_6500,
 230		.config = &chip_config_6500,
 231		.fifo_size = 512,
 232		.temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
 233		.startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
 234	},
 235	{
 236		.whoami = INV_ICM20609_WHOAMI_VALUE,
 237		.name = "ICM20609",
 238		.reg = &reg_set_6500,
 239		.config = &chip_config_6500,
 240		.fifo_size = 4 * 1024,
 241		.temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
 242		.startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
 243	},
 244	{
 245		.whoami = INV_ICM20689_WHOAMI_VALUE,
 246		.name = "ICM20689",
 247		.reg = &reg_set_6500,
 248		.config = &chip_config_6500,
 249		.fifo_size = 4 * 1024,
 250		.temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
 251		.startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
 252	},
 253	{
 254		.whoami = INV_ICM20600_WHOAMI_VALUE,
 255		.name = "ICM20600",
 256		.reg = &reg_set_icm20602,
 257		.config = &chip_config_6500,
 258		.fifo_size = 1008,
 259		.temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
 260		.startup_time = {INV_ICM20602_GYRO_STARTUP_TIME, INV_ICM20602_ACCEL_STARTUP_TIME},
 261	},
 262	{
 263		.whoami = INV_ICM20602_WHOAMI_VALUE,
 264		.name = "ICM20602",
 265		.reg = &reg_set_icm20602,
 266		.config = &chip_config_6500,
 267		.fifo_size = 1008,
 268		.temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
 269		.startup_time = {INV_ICM20602_GYRO_STARTUP_TIME, INV_ICM20602_ACCEL_STARTUP_TIME},
 270	},
 271	{
 272		.whoami = INV_ICM20690_WHOAMI_VALUE,
 273		.name = "ICM20690",
 274		.reg = &reg_set_6500,
 275		.config = &chip_config_6500,
 276		.fifo_size = 1024,
 277		.temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
 278		.startup_time = {INV_ICM20690_GYRO_STARTUP_TIME, INV_ICM20690_ACCEL_STARTUP_TIME},
 279	},
 280	{	.whoami = INV_IAM20380_WHOAMI_VALUE,
 281		.name = "IAM20380",
 282		.reg = &reg_set_6500,
 283		.config = &chip_config_6500,
 284		.fifo_size = 512,
 285		.temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
 286		.startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
 287	},
 288	{
 289		.whoami = INV_IAM20680_WHOAMI_VALUE,
 290		.name = "IAM20680",
 291		.reg = &reg_set_6500,
 292		.config = &chip_config_6500,
 293		.fifo_size = 512,
 294		.temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
 295		.startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
 296	},
 297	{
 298		.whoami = INV_IAM20680HP_WHOAMI_VALUE,
 299		.name = "IAM20680HP",
 300		.reg = &reg_set_6500,
 301		.config = &chip_config_6500,
 302		.fifo_size = 4 * 1024,
 303		.temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
 304		.startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
 305	},
 306	{
 307		.whoami = INV_IAM20680HT_WHOAMI_VALUE,
 308		.name = "IAM20680HT",
 309		.reg = &reg_set_6500,
 310		.config = &chip_config_6500,
 311		.fifo_size = 4 * 1024,
 312		.temp = {INV_ICM20608_TEMP_OFFSET, INV_ICM20608_TEMP_SCALE},
 313		.startup_time = {INV_MPU6500_GYRO_STARTUP_TIME, INV_MPU6500_ACCEL_STARTUP_TIME},
 314	},
 315};
 316
 317static int inv_mpu6050_pwr_mgmt_1_write(struct inv_mpu6050_state *st, bool sleep,
 318					bool cycle, int clock, int temp_dis)
 319{
 320	u8 val;
 321
 322	if (clock < 0)
 323		clock = st->chip_config.clk;
 324	if (temp_dis < 0)
 325		temp_dis = !st->chip_config.temp_en;
 326
 327	val = clock & INV_MPU6050_BIT_CLK_MASK;
 328	if (temp_dis)
 329		val |= INV_MPU6050_BIT_TEMP_DIS;
 330	if (sleep)
 331		val |= INV_MPU6050_BIT_SLEEP;
 332	if (cycle)
 333		val |= INV_MPU6050_BIT_CYCLE;
 334
 335	dev_dbg(regmap_get_device(st->map), "pwr_mgmt_1: 0x%x\n", val);
 336	return regmap_write(st->map, st->reg->pwr_mgmt_1, val);
 337}
 338
 339static int inv_mpu6050_clock_switch(struct inv_mpu6050_state *st,
 340				    unsigned int clock)
 341{
 342	int ret;
 343
 344	switch (st->chip_type) {
 345	case INV_MPU6050:
 346	case INV_MPU6000:
 347	case INV_MPU9150:
 348		/* old chips: switch clock manually */
 349		ret = inv_mpu6050_pwr_mgmt_1_write(st, false, false, clock, -1);
 350		if (ret)
 351			return ret;
 352		st->chip_config.clk = clock;
 353		break;
 354	default:
 355		/* automatic clock switching, nothing to do */
 356		break;
 357	}
 358
 359	return 0;
 360}
 361
 362int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en,
 363			      unsigned int mask)
 364{
 365	unsigned int sleep, val;
 366	u8 pwr_mgmt2, user_ctrl;
 367	int ret;
 368
 369	/* delete useless requests */
 370	if (mask & INV_MPU6050_SENSOR_ACCL && en == st->chip_config.accl_en)
 371		mask &= ~INV_MPU6050_SENSOR_ACCL;
 372	if (mask & INV_MPU6050_SENSOR_GYRO && en == st->chip_config.gyro_en)
 373		mask &= ~INV_MPU6050_SENSOR_GYRO;
 374	if (mask & INV_MPU6050_SENSOR_TEMP && en == st->chip_config.temp_en)
 375		mask &= ~INV_MPU6050_SENSOR_TEMP;
 376	if (mask & INV_MPU6050_SENSOR_MAGN && en == st->chip_config.magn_en)
 377		mask &= ~INV_MPU6050_SENSOR_MAGN;
 378	if (mask & INV_MPU6050_SENSOR_WOM && en == st->chip_config.wom_en)
 379		mask &= ~INV_MPU6050_SENSOR_WOM;
 380
 381	/* force accel on if WoM is on and not going off */
 382	if (!en && (mask & INV_MPU6050_SENSOR_ACCL) && st->chip_config.wom_en &&
 383			!(mask & INV_MPU6050_SENSOR_WOM))
 384		mask &= ~INV_MPU6050_SENSOR_ACCL;
 385
 386	if (mask == 0)
 387		return 0;
 388
 389	/* turn on/off temperature sensor */
 390	if (mask & INV_MPU6050_SENSOR_TEMP) {
 391		ret = inv_mpu6050_pwr_mgmt_1_write(st, false, false, -1, !en);
 392		if (ret)
 393			return ret;
 394		st->chip_config.temp_en = en;
 395	}
 396
 397	/* update user_crtl for driving magnetometer */
 398	if (mask & INV_MPU6050_SENSOR_MAGN) {
 399		user_ctrl = st->chip_config.user_ctrl;
 400		if (en)
 401			user_ctrl |= INV_MPU6050_BIT_I2C_MST_EN;
 402		else
 403			user_ctrl &= ~INV_MPU6050_BIT_I2C_MST_EN;
 404		ret = regmap_write(st->map, st->reg->user_ctrl, user_ctrl);
 405		if (ret)
 406			return ret;
 407		st->chip_config.user_ctrl = user_ctrl;
 408		st->chip_config.magn_en = en;
 409	}
 410
 411	/* manage accel & gyro engines */
 412	if (mask & (INV_MPU6050_SENSOR_ACCL | INV_MPU6050_SENSOR_GYRO)) {
 413		/* compute power management 2 current value */
 414		pwr_mgmt2 = 0;
 415		if (!st->chip_config.accl_en)
 416			pwr_mgmt2 |= INV_MPU6050_BIT_PWR_ACCL_STBY;
 417		if (!st->chip_config.gyro_en)
 418			pwr_mgmt2 |= INV_MPU6050_BIT_PWR_GYRO_STBY;
 419
 420		/* update to new requested value */
 421		if (mask & INV_MPU6050_SENSOR_ACCL) {
 422			if (en)
 423				pwr_mgmt2 &= ~INV_MPU6050_BIT_PWR_ACCL_STBY;
 424			else
 425				pwr_mgmt2 |= INV_MPU6050_BIT_PWR_ACCL_STBY;
 426		}
 427		if (mask & INV_MPU6050_SENSOR_GYRO) {
 428			if (en)
 429				pwr_mgmt2 &= ~INV_MPU6050_BIT_PWR_GYRO_STBY;
 430			else
 431				pwr_mgmt2 |= INV_MPU6050_BIT_PWR_GYRO_STBY;
 432		}
 433
 434		/* switch clock to internal when turning gyro off */
 435		if (mask & INV_MPU6050_SENSOR_GYRO && !en) {
 436			ret = inv_mpu6050_clock_switch(st, INV_CLK_INTERNAL);
 437			if (ret)
 438				return ret;
 439		}
 440
 441		/* update sensors engine */
 442		dev_dbg(regmap_get_device(st->map), "pwr_mgmt_2: 0x%x\n",
 443			pwr_mgmt2);
 444		ret = regmap_write(st->map, st->reg->pwr_mgmt_2, pwr_mgmt2);
 445		if (ret)
 446			return ret;
 447		if (mask & INV_MPU6050_SENSOR_ACCL)
 448			st->chip_config.accl_en = en;
 449		if (mask & INV_MPU6050_SENSOR_GYRO)
 450			st->chip_config.gyro_en = en;
 451
 452		/* compute required time to have sensors stabilized */
 453		sleep = 0;
 454		if (en) {
 455			if (mask & INV_MPU6050_SENSOR_ACCL) {
 456				if (sleep < st->hw->startup_time.accel)
 457					sleep = st->hw->startup_time.accel;
 458			}
 459			if (mask & INV_MPU6050_SENSOR_GYRO) {
 460				if (sleep < st->hw->startup_time.gyro)
 461					sleep = st->hw->startup_time.gyro;
 462			}
 463		} else {
 464			if (mask & INV_MPU6050_SENSOR_GYRO) {
 465				if (sleep < INV_MPU6050_GYRO_DOWN_TIME)
 466					sleep = INV_MPU6050_GYRO_DOWN_TIME;
 467			}
 468		}
 469		if (sleep)
 470			msleep(sleep);
 471
 472		/* switch clock to PLL when turning gyro on */
 473		if (mask & INV_MPU6050_SENSOR_GYRO && en) {
 474			ret = inv_mpu6050_clock_switch(st, INV_CLK_PLL);
 475			if (ret)
 476				return ret;
 477		}
 478	}
 479
 480	/* enable/disable accel intelligence control */
 481	if (mask & INV_MPU6050_SENSOR_WOM) {
 482		val = en ? INV_MPU6500_BIT_ACCEL_INTEL_EN |
 483			   INV_MPU6500_BIT_ACCEL_INTEL_MODE : 0;
 484		ret = regmap_write(st->map, INV_MPU6500_REG_ACCEL_INTEL_CTRL, val);
 485		if (ret)
 486			return ret;
 487		st->chip_config.wom_en = en;
 488	}
 489
 490	return 0;
 491}
 492
 493static int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st,
 494				     bool power_on)
 495{
 496	int result;
 497
 498	result = inv_mpu6050_pwr_mgmt_1_write(st, !power_on, false, -1, -1);
 499	if (result)
 500		return result;
 501
 502	if (power_on)
 503		usleep_range(INV_MPU6050_REG_UP_TIME_MIN,
 504			     INV_MPU6050_REG_UP_TIME_MAX);
 505
 506	return 0;
 507}
 508
 509static int inv_mpu6050_set_gyro_fsr(struct inv_mpu6050_state *st,
 510				    enum inv_mpu6050_fsr_e val)
 511{
 512	unsigned int gyro_shift;
 513	u8 data;
 514
 515	switch (st->chip_type) {
 516	case INV_ICM20690:
 517		gyro_shift = INV_ICM20690_GYRO_CONFIG_FSR_SHIFT;
 518		break;
 519	default:
 520		gyro_shift = INV_MPU6050_GYRO_CONFIG_FSR_SHIFT;
 521		break;
 522	}
 523
 524	data = val << gyro_shift;
 525	return regmap_write(st->map, st->reg->gyro_config, data);
 526}
 527
 528static int inv_mpu6050_set_accel_lpf_regs(struct inv_mpu6050_state *st,
 529					  enum inv_mpu6050_filter_e val)
 530{
 531	switch (st->chip_type) {
 532	case INV_MPU6050:
 533	case INV_MPU6000:
 534	case INV_MPU9150:
 535		/* old chips, nothing to do */
 536		return 0;
 537	case INV_ICM20689:
 538	case INV_ICM20690:
 539	case INV_IAM20680HT:
 540	case INV_IAM20680HP:
 541		/* set FIFO size to maximum value */
 542		val |= INV_ICM20689_BITS_FIFO_SIZE_MAX;
 543		break;
 544	default:
 545		break;
 546	}
 547
 548	return regmap_write(st->map, st->reg->accel_lpf, val);
 549}
 550
 551/*
 552 *  inv_mpu6050_set_lpf_regs() - set low pass filter registers, chip dependent
 553 *
 554 *  MPU60xx/MPU9150 use only 1 register for accelerometer + gyroscope
 555 *  MPU6500 and above have a dedicated register for accelerometer
 556 */
 557static int inv_mpu6050_set_lpf_regs(struct inv_mpu6050_state *st,
 558				    enum inv_mpu6050_filter_e val)
 559{
 560	int result;
 561
 562	result = regmap_write(st->map, st->reg->lpf, val);
 563	if (result)
 564		return result;
 565
 566	/* set accel lpf */
 567	return inv_mpu6050_set_accel_lpf_regs(st, val);
 568}
 569
 570/*
 571 *  inv_mpu6050_init_config() - Initialize hardware, disable FIFO.
 572 *
 573 *  Initial configuration:
 574 *  FSR: ± 2000DPS
 575 *  DLPF: 20Hz
 576 *  FIFO rate: 50Hz
 577 *  Clock source: Gyro PLL
 578 */
 579static int inv_mpu6050_init_config(struct iio_dev *indio_dev)
 580{
 581	int result;
 582	u8 d;
 583	struct inv_mpu6050_state *st = iio_priv(indio_dev);
 584	struct inv_sensors_timestamp_chip timestamp;
 585
 586	result = inv_mpu6050_set_gyro_fsr(st, st->chip_config.fsr);
 587	if (result)
 588		return result;
 589
 590	result = inv_mpu6050_set_lpf_regs(st, st->chip_config.lpf);
 591	if (result)
 592		return result;
 593
 594	d = st->chip_config.divider;
 595	result = regmap_write(st->map, st->reg->sample_rate_div, d);
 596	if (result)
 597		return result;
 598
 599	d = (st->chip_config.accl_fs << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT);
 600	result = regmap_write(st->map, st->reg->accl_config, d);
 601	if (result)
 602		return result;
 603
 604	result = regmap_write(st->map, st->reg->int_pin_cfg, st->irq_mask);
 605	if (result)
 606		return result;
 607
 608	/* clock jitter is +/- 2% */
 609	timestamp.clock_period = NSEC_PER_SEC / INV_MPU6050_INTERNAL_FREQ_HZ;
 610	timestamp.jitter = 20;
 611	timestamp.init_period =
 612			NSEC_PER_SEC / INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
 613	inv_sensors_timestamp_init(&st->timestamp, &timestamp);
 614
 615	/* magn chip init, noop if not present in the chip */
 616	result = inv_mpu_magn_probe(st);
 617	if (result)
 618		return result;
 619
 620	return 0;
 621}
 622
 623static int inv_mpu6050_sensor_set(struct inv_mpu6050_state  *st, int reg,
 624				int axis, int val)
 625{
 626	int ind;
 627	__be16 d = cpu_to_be16(val);
 628
 629	ind = (axis - IIO_MOD_X) * 2;
 630
 631	return regmap_bulk_write(st->map, reg + ind, &d, sizeof(d));
 632}
 633
 634static int inv_mpu6050_sensor_show(struct inv_mpu6050_state  *st, int reg,
 635				   int axis, int *val)
 636{
 637	int ind, result;
 638	__be16 d;
 639
 640	ind = (axis - IIO_MOD_X) * 2;
 641	result = regmap_bulk_read(st->map, reg + ind, &d, sizeof(d));
 642	if (result)
 643		return result;
 644	*val = (short)be16_to_cpup(&d);
 645
 646	return IIO_VAL_INT;
 647}
 648
 649static int inv_mpu6050_read_channel_data(struct iio_dev *indio_dev,
 650					 struct iio_chan_spec const *chan,
 651					 int *val)
 652{
 653	struct inv_mpu6050_state *st = iio_priv(indio_dev);
 654	struct device *pdev = regmap_get_device(st->map);
 655	unsigned int freq_hz, period_us, min_sleep_us, max_sleep_us;
 656	int result;
 657	int ret;
 658
 659	/* compute sample period */
 660	freq_hz = INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
 661	period_us = 1000000 / freq_hz;
 662
 663	result = pm_runtime_resume_and_get(pdev);
 664	if (result)
 665		return result;
 666
 667	switch (chan->type) {
 668	case IIO_ANGL_VEL:
 669		if (!st->chip_config.gyro_en) {
 670			result = inv_mpu6050_switch_engine(st, true,
 671					INV_MPU6050_SENSOR_GYRO);
 672			if (result)
 673				goto error_power_off;
 674			/* need to wait 2 periods to have first valid sample */
 675			min_sleep_us = 2 * period_us;
 676			max_sleep_us = 2 * (period_us + period_us / 2);
 677			usleep_range(min_sleep_us, max_sleep_us);
 678		}
 679		ret = inv_mpu6050_sensor_show(st, st->reg->raw_gyro,
 680					      chan->channel2, val);
 681		break;
 682	case IIO_ACCEL:
 683		if (!st->chip_config.accl_en) {
 684			result = inv_mpu6050_switch_engine(st, true,
 685					INV_MPU6050_SENSOR_ACCL);
 686			if (result)
 687				goto error_power_off;
 688			/* wait 1 period for first sample availability */
 689			min_sleep_us = period_us;
 690			max_sleep_us = period_us + period_us / 2;
 691			usleep_range(min_sleep_us, max_sleep_us);
 692		}
 693		ret = inv_mpu6050_sensor_show(st, st->reg->raw_accl,
 694					      chan->channel2, val);
 695		break;
 696	case IIO_TEMP:
 697		/* temperature sensor work only with accel and/or gyro */
 698		if (!st->chip_config.accl_en && !st->chip_config.gyro_en) {
 699			result = -EBUSY;
 700			goto error_power_off;
 701		}
 702		if (!st->chip_config.temp_en) {
 703			result = inv_mpu6050_switch_engine(st, true,
 704					INV_MPU6050_SENSOR_TEMP);
 705			if (result)
 706				goto error_power_off;
 707			/* wait 1 period for first sample availability */
 708			min_sleep_us = period_us;
 709			max_sleep_us = period_us + period_us / 2;
 710			usleep_range(min_sleep_us, max_sleep_us);
 711		}
 712		ret = inv_mpu6050_sensor_show(st, st->reg->temperature,
 713					      IIO_MOD_X, val);
 714		break;
 715	case IIO_MAGN:
 716		if (!st->chip_config.magn_en) {
 717			result = inv_mpu6050_switch_engine(st, true,
 718					INV_MPU6050_SENSOR_MAGN);
 719			if (result)
 720				goto error_power_off;
 721			/* frequency is limited for magnetometer */
 722			if (freq_hz > INV_MPU_MAGN_FREQ_HZ_MAX) {
 723				freq_hz = INV_MPU_MAGN_FREQ_HZ_MAX;
 724				period_us = 1000000 / freq_hz;
 725			}
 726			/* need to wait 2 periods to have first valid sample */
 727			min_sleep_us = 2 * period_us;
 728			max_sleep_us = 2 * (period_us + period_us / 2);
 729			usleep_range(min_sleep_us, max_sleep_us);
 730		}
 731		ret = inv_mpu_magn_read(st, chan->channel2, val);
 732		break;
 733	default:
 734		ret = -EINVAL;
 735		break;
 736	}
 737
 738	pm_runtime_put_autosuspend(pdev);
 739
 740	return ret;
 741
 742error_power_off:
 743	pm_runtime_put_autosuspend(pdev);
 744	return result;
 745}
 746
 747static int
 748inv_mpu6050_read_raw(struct iio_dev *indio_dev,
 749		     struct iio_chan_spec const *chan,
 750		     int *val, int *val2, long mask)
 751{
 752	struct inv_mpu6050_state  *st = iio_priv(indio_dev);
 753	int ret = 0;
 754
 755	switch (mask) {
 756	case IIO_CHAN_INFO_RAW:
 757		if (!iio_device_claim_direct(indio_dev))
 758			return -EBUSY;
 759		mutex_lock(&st->lock);
 760		ret = inv_mpu6050_read_channel_data(indio_dev, chan, val);
 761		mutex_unlock(&st->lock);
 762		iio_device_release_direct(indio_dev);
 763		return ret;
 764	case IIO_CHAN_INFO_SCALE:
 765		switch (chan->type) {
 766		case IIO_ANGL_VEL:
 767			mutex_lock(&st->lock);
 768			*val  = 0;
 769			*val2 = gyro_scale_6050[st->chip_config.fsr];
 770			mutex_unlock(&st->lock);
 771
 772			return IIO_VAL_INT_PLUS_NANO;
 773		case IIO_ACCEL:
 774			mutex_lock(&st->lock);
 775			*val = 0;
 776			*val2 = accel_scale[st->chip_config.accl_fs];
 777			mutex_unlock(&st->lock);
 778
 779			return IIO_VAL_INT_PLUS_MICRO;
 780		case IIO_TEMP:
 781			*val = st->hw->temp.scale / 1000000;
 782			*val2 = st->hw->temp.scale % 1000000;
 783			return IIO_VAL_INT_PLUS_MICRO;
 784		case IIO_MAGN:
 785			return inv_mpu_magn_get_scale(st, chan, val, val2);
 786		default:
 787			return -EINVAL;
 788		}
 789	case IIO_CHAN_INFO_OFFSET:
 790		switch (chan->type) {
 791		case IIO_TEMP:
 792			*val = st->hw->temp.offset;
 793			return IIO_VAL_INT;
 794		default:
 795			return -EINVAL;
 796		}
 797	case IIO_CHAN_INFO_CALIBBIAS:
 798		switch (chan->type) {
 799		case IIO_ANGL_VEL:
 800			mutex_lock(&st->lock);
 801			ret = inv_mpu6050_sensor_show(st, st->reg->gyro_offset,
 802						chan->channel2, val);
 803			mutex_unlock(&st->lock);
 804			return ret;
 805		case IIO_ACCEL:
 806			mutex_lock(&st->lock);
 807			ret = inv_mpu6050_sensor_show(st, st->reg->accl_offset,
 808						chan->channel2, val);
 809			mutex_unlock(&st->lock);
 810			return ret;
 811
 812		default:
 813			return -EINVAL;
 814		}
 815	default:
 816		return -EINVAL;
 817	}
 818}
 819
 820static int inv_mpu6050_write_gyro_scale(struct inv_mpu6050_state *st, int val,
 821					int val2)
 822{
 823	int result, i;
 824
 825	if (val != 0)
 826		return -EINVAL;
 827
 828	for (i = 0; i < ARRAY_SIZE(gyro_scale_6050); ++i) {
 829		if (gyro_scale_6050[i] == val2) {
 830			result = inv_mpu6050_set_gyro_fsr(st, i);
 831			if (result)
 832				return result;
 833
 834			st->chip_config.fsr = i;
 835			return 0;
 836		}
 837	}
 838
 839	return -EINVAL;
 840}
 841
 842static int inv_write_raw_get_fmt(struct iio_dev *indio_dev,
 843				 struct iio_chan_spec const *chan, long mask)
 844{
 845	switch (mask) {
 846	case IIO_CHAN_INFO_SCALE:
 847		switch (chan->type) {
 848		case IIO_ANGL_VEL:
 849			return IIO_VAL_INT_PLUS_NANO;
 850		default:
 851			return IIO_VAL_INT_PLUS_MICRO;
 852		}
 853	default:
 854		return IIO_VAL_INT_PLUS_MICRO;
 855	}
 856
 857	return -EINVAL;
 858}
 859
 860static int inv_mpu6050_write_accel_scale(struct inv_mpu6050_state *st, int val,
 861					 int val2)
 862{
 863	int result, i;
 864	u8 d;
 865
 866	if (val != 0)
 867		return -EINVAL;
 868
 869	for (i = 0; i < ARRAY_SIZE(accel_scale); ++i) {
 870		if (accel_scale[i] == val2) {
 871			d = (i << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT);
 872			result = regmap_write(st->map, st->reg->accl_config, d);
 873			if (result)
 874				return result;
 875
 876			st->chip_config.accl_fs = i;
 877			return 0;
 878		}
 879	}
 880
 881	return -EINVAL;
 882}
 883
 884static int inv_mpu6050_write_raw(struct iio_dev *indio_dev,
 885				 struct iio_chan_spec const *chan,
 886				 int val, int val2, long mask)
 887{
 888	struct inv_mpu6050_state  *st = iio_priv(indio_dev);
 889	struct device *pdev = regmap_get_device(st->map);
 890	int result;
 891
 892	/*
 893	 * we should only update scale when the chip is disabled, i.e.
 894	 * not running
 895	 */
 896	if (!iio_device_claim_direct(indio_dev))
 897		return -EBUSY;
 898
 899	mutex_lock(&st->lock);
 900	result = pm_runtime_resume_and_get(pdev);
 901	if (result)
 902		goto error_write_raw_unlock;
 903
 904	switch (mask) {
 905	case IIO_CHAN_INFO_SCALE:
 906		switch (chan->type) {
 907		case IIO_ANGL_VEL:
 908			result = inv_mpu6050_write_gyro_scale(st, val, val2);
 909			break;
 910		case IIO_ACCEL:
 911			result = inv_mpu6050_write_accel_scale(st, val, val2);
 912			break;
 913		default:
 914			result = -EINVAL;
 915			break;
 916		}
 917		break;
 918	case IIO_CHAN_INFO_CALIBBIAS:
 919		switch (chan->type) {
 920		case IIO_ANGL_VEL:
 921			result = inv_mpu6050_sensor_set(st,
 922							st->reg->gyro_offset,
 923							chan->channel2, val);
 924			break;
 925		case IIO_ACCEL:
 926			result = inv_mpu6050_sensor_set(st,
 927							st->reg->accl_offset,
 928							chan->channel2, val);
 929			break;
 930		default:
 931			result = -EINVAL;
 932			break;
 933		}
 934		break;
 935	default:
 936		result = -EINVAL;
 937		break;
 938	}
 939
 940	pm_runtime_put_autosuspend(pdev);
 941error_write_raw_unlock:
 942	mutex_unlock(&st->lock);
 943	iio_device_release_direct(indio_dev);
 944
 945	return result;
 946}
 947
 948static u64 inv_mpu6050_convert_wom_to_roc(unsigned int threshold, unsigned int freq_div)
 949{
 950	/* 4mg per LSB converted in m/s² in micro (1000000) */
 951	const unsigned int convert = 4U * 9807U;
 952	u64 value;
 953
 954	value = threshold * convert;
 955
 956	/* compute the differential by multiplying by the frequency */
 957	return div_u64(value * INV_MPU6050_INTERNAL_FREQ_HZ, freq_div);
 958}
 959
 960static unsigned int inv_mpu6050_convert_roc_to_wom(u64 roc, unsigned int freq_div)
 961{
 962	/* 4mg per LSB converted in m/s² in micro (1000000) */
 963	const unsigned int convert = 4U * 9807U;
 964	u64 value;
 965
 966	/* return 0 only if roc is 0 */
 967	if (roc == 0)
 968		return 0;
 969
 970	value = div_u64(roc * freq_div, convert * INV_MPU6050_INTERNAL_FREQ_HZ);
 971
 972	/* limit value to 8 bits and prevent 0 */
 973	return min(255, max(1, value));
 974}
 975
 976static int inv_mpu6050_set_wom_int(struct inv_mpu6050_state *st, bool on)
 977{
 978	unsigned int reg_val, val;
 979
 980	switch (st->chip_type) {
 981	case INV_MPU6050:
 982	case INV_MPU6500:
 983	case INV_MPU6515:
 984	case INV_MPU6880:
 985	case INV_MPU6000:
 986	case INV_MPU9150:
 987	case INV_MPU9250:
 988	case INV_MPU9255:
 989		reg_val = INV_MPU6500_BIT_WOM_INT_EN;
 990		break;
 991	default:
 992		reg_val = INV_ICM20608_BIT_WOM_INT_EN;
 993		break;
 994	}
 995
 996	val = on ? reg_val : 0;
 997
 998	return regmap_update_bits(st->map, st->reg->int_enable, reg_val, val);
 999}
1000
1001static int inv_mpu6050_set_wom_threshold(struct inv_mpu6050_state *st, u64 value,
1002					 unsigned int freq_div)
1003{
1004	unsigned int threshold;
1005	int result;
1006
1007	/* convert roc to wom threshold and convert back to handle clipping */
1008	threshold = inv_mpu6050_convert_roc_to_wom(value, freq_div);
1009	value = inv_mpu6050_convert_wom_to_roc(threshold, freq_div);
1010
1011	dev_dbg(regmap_get_device(st->map), "wom_threshold: 0x%x\n", threshold);
1012
1013	switch (st->chip_type) {
1014	case INV_ICM20609:
1015	case INV_ICM20689:
1016	case INV_ICM20600:
1017	case INV_ICM20602:
1018	case INV_ICM20690:
1019		st->data[0] = threshold;
1020		st->data[1] = threshold;
1021		st->data[2] = threshold;
1022		result = regmap_bulk_write(st->map, INV_ICM20609_REG_ACCEL_WOM_X_THR,
1023					   st->data, 3);
1024		break;
1025	default:
1026		result = regmap_write(st->map, INV_MPU6500_REG_WOM_THRESHOLD, threshold);
1027		break;
1028	}
1029	if (result)
1030		return result;
1031
1032	st->chip_config.roc_threshold = value;
1033
1034	return 0;
1035}
1036
1037static int inv_mpu6050_set_lp_odr(struct inv_mpu6050_state *st, unsigned int freq_div,
1038				  unsigned int *lp_div)
1039{
1040	static const unsigned int freq_dividers[] = {2, 4, 8, 16, 32, 64, 128, 256};
1041	static const unsigned int reg_values[] = {
1042		INV_MPU6050_LPOSC_500HZ, INV_MPU6050_LPOSC_250HZ,
1043		INV_MPU6050_LPOSC_125HZ, INV_MPU6050_LPOSC_62HZ,
1044		INV_MPU6050_LPOSC_31HZ, INV_MPU6050_LPOSC_16HZ,
1045		INV_MPU6050_LPOSC_8HZ, INV_MPU6050_LPOSC_4HZ,
1046	};
1047	unsigned int val, i;
1048
1049	switch (st->chip_type) {
1050	case INV_ICM20609:
1051	case INV_ICM20689:
1052	case INV_ICM20600:
1053	case INV_ICM20602:
1054	case INV_ICM20690:
1055		/* nothing to do */
1056		*lp_div = INV_MPU6050_FREQ_DIVIDER(st);
1057		return 0;
1058	default:
1059		break;
1060	}
1061
1062	/* found the nearest superior frequency divider */
1063	i = ARRAY_SIZE(reg_values) - 1;
1064	val = reg_values[i];
1065	*lp_div = freq_dividers[i];
1066	for (i = 0; i < ARRAY_SIZE(freq_dividers); ++i) {
1067		if (freq_div <= freq_dividers[i]) {
1068			val = reg_values[i];
1069			*lp_div = freq_dividers[i];
1070			break;
1071		}
1072	}
1073
1074	dev_dbg(regmap_get_device(st->map), "lp_odr: 0x%x\n", val);
1075	return regmap_write(st->map, INV_MPU6500_REG_LP_ODR, val);
1076}
1077
1078static int inv_mpu6050_set_wom_lp(struct inv_mpu6050_state *st, bool on)
1079{
1080	unsigned int lp_div;
1081	int result;
1082
1083	if (on) {
1084		/* set low power ODR */
1085		result = inv_mpu6050_set_lp_odr(st, INV_MPU6050_FREQ_DIVIDER(st), &lp_div);
1086		if (result)
1087			return result;
1088		/* disable accel low pass filter */
1089		result = inv_mpu6050_set_accel_lpf_regs(st, INV_MPU6050_FILTER_NOLPF);
1090		if (result)
1091			return result;
1092		/* update wom threshold with new low-power frequency divider */
1093		result = inv_mpu6050_set_wom_threshold(st, st->chip_config.roc_threshold, lp_div);
1094		if (result)
1095			return result;
1096		/* set cycle mode */
1097		result = inv_mpu6050_pwr_mgmt_1_write(st, false, true, -1, -1);
1098	} else {
1099		/* disable cycle mode */
1100		result = inv_mpu6050_pwr_mgmt_1_write(st, false, false, -1, -1);
1101		if (result)
1102			return result;
1103		/* restore wom threshold */
1104		result = inv_mpu6050_set_wom_threshold(st, st->chip_config.roc_threshold,
1105						       INV_MPU6050_FREQ_DIVIDER(st));
1106		if (result)
1107			return result;
1108		/* restore accel low pass filter */
1109		result = inv_mpu6050_set_accel_lpf_regs(st, st->chip_config.lpf);
1110	}
1111
1112	return result;
1113}
1114
1115static int inv_mpu6050_enable_wom(struct inv_mpu6050_state *st, bool en)
1116{
1117	struct device *pdev = regmap_get_device(st->map);
1118	unsigned int mask;
1119	int result;
1120
1121	if (en) {
1122		result = pm_runtime_resume_and_get(pdev);
1123		if (result)
1124			return result;
1125
1126		mask = INV_MPU6050_SENSOR_ACCL | INV_MPU6050_SENSOR_WOM;
1127		result = inv_mpu6050_switch_engine(st, true, mask);
1128		if (result)
1129			goto error_suspend;
1130
1131		result = inv_mpu6050_set_wom_int(st, true);
1132		if (result)
1133			goto error_suspend;
1134	} else {
1135		result = inv_mpu6050_set_wom_int(st, false);
1136		if (result)
1137			dev_err(pdev, "error %d disabling WoM interrupt bit", result);
1138
1139		/* disable only WoM and let accel be disabled by autosuspend */
1140		result = inv_mpu6050_switch_engine(st, false, INV_MPU6050_SENSOR_WOM);
1141		if (result) {
1142			dev_err(pdev, "error %d disabling WoM force off", result);
1143			/* force WoM off */
1144			st->chip_config.wom_en = false;
1145		}
1146
1147		pm_runtime_put_autosuspend(pdev);
1148	}
1149
1150	return result;
1151
1152error_suspend:
1153	pm_runtime_put_autosuspend(pdev);
1154	return result;
1155}
1156
1157static int inv_mpu6050_read_event_config(struct iio_dev *indio_dev,
1158					 const struct iio_chan_spec *chan,
1159					 enum iio_event_type type,
1160					 enum iio_event_direction dir)
1161{
1162	struct inv_mpu6050_state *st = iio_priv(indio_dev);
1163
1164	/* support only WoM (accel roc rising) event */
1165	if (chan->type != IIO_ACCEL || type != IIO_EV_TYPE_ROC ||
1166	    dir != IIO_EV_DIR_RISING)
1167		return -EINVAL;
1168
1169	guard(mutex)(&st->lock);
1170
1171	return st->chip_config.wom_en ? 1 : 0;
1172}
1173
1174static int inv_mpu6050_write_event_config(struct iio_dev *indio_dev,
1175					  const struct iio_chan_spec *chan,
1176					  enum iio_event_type type,
1177					  enum iio_event_direction dir,
1178					  bool state)
1179{
1180	struct inv_mpu6050_state *st = iio_priv(indio_dev);
1181
1182	/* support only WoM (accel roc rising) event */
1183	if (chan->type != IIO_ACCEL || type != IIO_EV_TYPE_ROC ||
1184	    dir != IIO_EV_DIR_RISING)
1185		return -EINVAL;
1186
1187	guard(mutex)(&st->lock);
1188
1189	if (st->chip_config.wom_en == state)
1190		return 0;
1191
1192	return inv_mpu6050_enable_wom(st, state);
1193}
1194
1195static int inv_mpu6050_read_event_value(struct iio_dev *indio_dev,
1196					const struct iio_chan_spec *chan,
1197					enum iio_event_type type,
1198					enum iio_event_direction dir,
1199					enum iio_event_info info,
1200					int *val, int *val2)
1201{
1202	struct inv_mpu6050_state *st = iio_priv(indio_dev);
1203	u32 rem;
1204
1205	/* support only WoM (accel roc rising) event value */
1206	if (chan->type != IIO_ACCEL || type != IIO_EV_TYPE_ROC ||
1207	    dir != IIO_EV_DIR_RISING || info != IIO_EV_INFO_VALUE)
1208		return -EINVAL;
1209
1210	guard(mutex)(&st->lock);
1211
1212	/* return value in micro */
1213	*val = div_u64_rem(st->chip_config.roc_threshold, 1000000U, &rem);
1214	*val2 = rem;
1215
1216	return IIO_VAL_INT_PLUS_MICRO;
1217}
1218
1219static int inv_mpu6050_write_event_value(struct iio_dev *indio_dev,
1220					 const struct iio_chan_spec *chan,
1221					 enum iio_event_type type,
1222					 enum iio_event_direction dir,
1223					 enum iio_event_info info,
1224					 int val, int val2)
1225{
1226	struct inv_mpu6050_state *st = iio_priv(indio_dev);
1227	struct device *pdev = regmap_get_device(st->map);
1228	u64 value;
1229	int result;
1230
1231	/* support only WoM (accel roc rising) event value */
1232	if (chan->type != IIO_ACCEL || type != IIO_EV_TYPE_ROC ||
1233	    dir != IIO_EV_DIR_RISING || info != IIO_EV_INFO_VALUE)
1234		return -EINVAL;
1235
1236	if (val < 0 || val2 < 0)
1237		return -EINVAL;
1238
1239	guard(mutex)(&st->lock);
1240
1241	result = pm_runtime_resume_and_get(pdev);
1242	if (result)
1243		return result;
1244
1245	value = (u64)val * 1000000ULL + (u64)val2;
1246	result = inv_mpu6050_set_wom_threshold(st, value, INV_MPU6050_FREQ_DIVIDER(st));
1247
1248	pm_runtime_put_autosuspend(pdev);
1249
1250	return result;
1251}
1252
1253/*
1254 *  inv_mpu6050_set_lpf() - set low pass filer based on fifo rate.
1255 *
1256 *                  Based on the Nyquist principle, the bandwidth of the low
1257 *                  pass filter must not exceed the signal sampling rate divided
1258 *                  by 2, or there would be aliasing.
1259 *                  This function basically search for the correct low pass
1260 *                  parameters based on the fifo rate, e.g, sampling frequency.
1261 *
1262 *  lpf is set automatically when setting sampling rate to avoid any aliases.
1263 */
1264static int inv_mpu6050_set_lpf(struct inv_mpu6050_state *st, int rate)
1265{
1266	static const int hz[] = {400, 200, 90, 40, 20, 10};
1267	static const int d[] = {
1268		INV_MPU6050_FILTER_200HZ, INV_MPU6050_FILTER_100HZ,
1269		INV_MPU6050_FILTER_45HZ, INV_MPU6050_FILTER_20HZ,
1270		INV_MPU6050_FILTER_10HZ, INV_MPU6050_FILTER_5HZ
1271	};
1272	int i, result;
1273	u8 data;
1274
1275	data = INV_MPU6050_FILTER_5HZ;
1276	for (i = 0; i < ARRAY_SIZE(hz); ++i) {
1277		if (rate >= hz[i]) {
1278			data = d[i];
1279			break;
1280		}
1281	}
1282	result = inv_mpu6050_set_lpf_regs(st, data);
1283	if (result)
1284		return result;
1285	st->chip_config.lpf = data;
1286
1287	return 0;
1288}
1289
1290/*
1291 * inv_mpu6050_fifo_rate_store() - Set fifo rate.
1292 */
1293static ssize_t
1294inv_mpu6050_fifo_rate_store(struct device *dev, struct device_attribute *attr,
1295			    const char *buf, size_t count)
1296{
1297	int fifo_rate;
1298	u32 fifo_period;
1299	bool fifo_on;
1300	u8 d;
1301	int result;
1302	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
1303	struct inv_mpu6050_state *st = iio_priv(indio_dev);
1304	struct device *pdev = regmap_get_device(st->map);
1305
1306	if (kstrtoint(buf, 10, &fifo_rate))
1307		return -EINVAL;
1308	if (fifo_rate < INV_MPU6050_MIN_FIFO_RATE ||
1309	    fifo_rate > INV_MPU6050_MAX_FIFO_RATE)
1310		return -EINVAL;
1311
1312	/* compute the chip sample rate divider */
1313	d = INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate);
1314	/* compute back the fifo rate to handle truncation cases */
1315	fifo_rate = INV_MPU6050_DIVIDER_TO_FIFO_RATE(d);
1316	fifo_period = NSEC_PER_SEC / fifo_rate;
1317
1318	mutex_lock(&st->lock);
1319	if (d == st->chip_config.divider) {
1320		result = 0;
1321		goto fifo_rate_fail_unlock;
1322	}
1323
1324	fifo_on = st->chip_config.accl_fifo_enable ||
1325		  st->chip_config.gyro_fifo_enable ||
1326		  st->chip_config.magn_fifo_enable;
1327	result = inv_sensors_timestamp_update_odr(&st->timestamp, fifo_period, fifo_on);
1328	if (result)
1329		goto fifo_rate_fail_unlock;
1330
1331	result = pm_runtime_resume_and_get(pdev);
1332	if (result)
1333		goto fifo_rate_fail_unlock;
1334
1335	result = regmap_write(st->map, st->reg->sample_rate_div, d);
1336	if (result)
1337		goto fifo_rate_fail_power_off;
1338	st->chip_config.divider = d;
1339
1340	result = inv_mpu6050_set_lpf(st, fifo_rate);
1341	if (result)
1342		goto fifo_rate_fail_power_off;
1343
1344	/* update rate for magn, noop if not present in chip */
1345	result = inv_mpu_magn_set_rate(st, fifo_rate);
1346	if (result)
1347		goto fifo_rate_fail_power_off;
1348
1349	/* update wom threshold since roc is dependent on sampling frequency */
1350	result = inv_mpu6050_set_wom_threshold(st, st->chip_config.roc_threshold,
1351					       INV_MPU6050_FREQ_DIVIDER(st));
1352	if (result)
1353		goto fifo_rate_fail_power_off;
1354
1355fifo_rate_fail_power_off:
1356	pm_runtime_put_autosuspend(pdev);
1357fifo_rate_fail_unlock:
1358	mutex_unlock(&st->lock);
1359	if (result)
1360		return result;
1361
1362	return count;
1363}
1364
1365/*
1366 * inv_fifo_rate_show() - Get the current sampling rate.
1367 */
1368static ssize_t
1369inv_fifo_rate_show(struct device *dev, struct device_attribute *attr,
1370		   char *buf)
1371{
1372	struct inv_mpu6050_state *st = iio_priv(dev_to_iio_dev(dev));
1373	unsigned fifo_rate;
1374
1375	mutex_lock(&st->lock);
1376	fifo_rate = INV_MPU6050_DIVIDER_TO_FIFO_RATE(st->chip_config.divider);
1377	mutex_unlock(&st->lock);
1378
1379	return sysfs_emit(buf, "%u\n", fifo_rate);
1380}
1381
1382/*
1383 * inv_attr_show() - calling this function will show current
1384 *                    parameters.
1385 *
1386 * Deprecated in favor of IIO mounting matrix API.
1387 *
1388 * See inv_get_mount_matrix()
1389 */
1390static ssize_t inv_attr_show(struct device *dev, struct device_attribute *attr,
1391			     char *buf)
1392{
1393	struct inv_mpu6050_state *st = iio_priv(dev_to_iio_dev(dev));
1394	struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
1395	s8 *m;
1396
1397	switch (this_attr->address) {
1398	/*
1399	 * In MPU6050, the two matrix are the same because gyro and accel
1400	 * are integrated in one chip
1401	 */
1402	case ATTR_GYRO_MATRIX:
1403	case ATTR_ACCL_MATRIX:
1404		m = st->plat_data.orientation;
1405
1406		return sysfs_emit(buf, "%d, %d, %d; %d, %d, %d; %d, %d, %d\n",
1407			m[0], m[1], m[2], m[3], m[4], m[5], m[6], m[7], m[8]);
1408	default:
1409		return -EINVAL;
1410	}
1411}
1412
1413/**
1414 * inv_mpu6050_validate_trigger() - validate_trigger callback for invensense
1415 *                                  MPU6050 device.
1416 * @indio_dev: The IIO device
1417 * @trig: The new trigger
1418 *
1419 * Returns: 0 if the 'trig' matches the trigger registered by the MPU6050
1420 * device, -EINVAL otherwise.
1421 */
1422static int inv_mpu6050_validate_trigger(struct iio_dev *indio_dev,
1423					struct iio_trigger *trig)
1424{
1425	struct inv_mpu6050_state *st = iio_priv(indio_dev);
1426
1427	if (st->trig != trig)
1428		return -EINVAL;
1429
1430	return 0;
1431}
1432
1433static const struct iio_mount_matrix *
1434inv_get_mount_matrix(const struct iio_dev *indio_dev,
1435		     const struct iio_chan_spec *chan)
1436{
1437	struct inv_mpu6050_state *data = iio_priv(indio_dev);
1438	const struct iio_mount_matrix *matrix;
1439
1440	if (chan->type == IIO_MAGN)
1441		matrix = &data->magn_orient;
1442	else
1443		matrix = &data->orientation;
1444
1445	return matrix;
1446}
1447
1448static const struct iio_chan_spec_ext_info inv_ext_info[] = {
1449	IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, inv_get_mount_matrix),
1450	{ }
1451};
1452
1453static const struct iio_event_spec inv_wom_events[] = {
1454	{
1455		.type = IIO_EV_TYPE_ROC,
1456		.dir = IIO_EV_DIR_RISING,
1457		.mask_separate = BIT(IIO_EV_INFO_ENABLE) |
1458				 BIT(IIO_EV_INFO_VALUE),
1459	},
1460};
1461
1462#define INV_MPU6050_CHAN(_type, _channel2, _index)                    \
1463	{                                                             \
1464		.type = _type,                                        \
1465		.modified = 1,                                        \
1466		.channel2 = _channel2,                                \
1467		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
1468		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |	      \
1469				      BIT(IIO_CHAN_INFO_CALIBBIAS),   \
1470		.scan_index = _index,                                 \
1471		.scan_type = {                                        \
1472				.sign = 's',                          \
1473				.realbits = 16,                       \
1474				.storagebits = 16,                    \
1475				.shift = 0,                           \
1476				.endianness = IIO_BE,                 \
1477			     },                                       \
1478		.ext_info = inv_ext_info,                             \
1479	}
1480
1481#define INV_MPU6050_TEMP_CHAN(_index)				\
1482	{							\
1483		.type = IIO_TEMP,				\
1484		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW)	\
1485				| BIT(IIO_CHAN_INFO_OFFSET)	\
1486				| BIT(IIO_CHAN_INFO_SCALE),	\
1487		.scan_index = _index,				\
1488		.scan_type = {					\
1489			.sign = 's',				\
1490			.realbits = 16,				\
1491			.storagebits = 16,			\
1492			.shift = 0,				\
1493			.endianness = IIO_BE,			\
1494		},						\
1495	}
1496
1497#define INV_MPU6050_EVENT_CHAN(_type, _channel2, _events, _events_nb)	\
1498{									\
1499	.type = _type,							\
1500	.modified = 1,							\
1501	.channel2 = _channel2,						\
1502	.event_spec = _events,						\
1503	.num_event_specs = _events_nb,					\
1504	.scan_index = -1,						\
1505}
1506
1507static const struct iio_chan_spec inv_mpu6050_channels[] = {
1508	IIO_CHAN_SOFT_TIMESTAMP(INV_MPU6050_SCAN_TIMESTAMP),
1509
1510	INV_MPU6050_TEMP_CHAN(INV_MPU6050_SCAN_TEMP),
1511
1512	INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_MPU6050_SCAN_GYRO_X),
1513	INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_MPU6050_SCAN_GYRO_Y),
1514	INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_MPU6050_SCAN_GYRO_Z),
1515
1516	INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_MPU6050_SCAN_ACCL_X),
1517	INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_MPU6050_SCAN_ACCL_Y),
1518	INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),
1519};
1520
1521static const struct iio_chan_spec inv_iam20380_channels[] = {
1522	IIO_CHAN_SOFT_TIMESTAMP(INV_MPU6050_SCAN_TIMESTAMP),
1523
1524	INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_MPU6050_SCAN_GYRO_X),
1525	INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_MPU6050_SCAN_GYRO_Y),
1526	INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_MPU6050_SCAN_GYRO_Z),
1527};
1528
1529static const struct iio_chan_spec inv_mpu6500_channels[] = {
1530	IIO_CHAN_SOFT_TIMESTAMP(INV_MPU6050_SCAN_TIMESTAMP),
1531
1532	INV_MPU6050_TEMP_CHAN(INV_MPU6050_SCAN_TEMP),
1533
1534	INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_MPU6050_SCAN_GYRO_X),
1535	INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_MPU6050_SCAN_GYRO_Y),
1536	INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_MPU6050_SCAN_GYRO_Z),
1537
1538	INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_MPU6050_SCAN_ACCL_X),
1539	INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_MPU6050_SCAN_ACCL_Y),
1540	INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),
1541
1542	INV_MPU6050_EVENT_CHAN(IIO_ACCEL, IIO_MOD_X_OR_Y_OR_Z,
1543			       inv_wom_events, ARRAY_SIZE(inv_wom_events)),
1544};
1545
1546#define INV_MPU6050_SCAN_MASK_3AXIS_ACCEL	\
1547	(BIT(INV_MPU6050_SCAN_ACCL_X)		\
1548	| BIT(INV_MPU6050_SCAN_ACCL_Y)		\
1549	| BIT(INV_MPU6050_SCAN_ACCL_Z))
1550
1551#define INV_MPU6050_SCAN_MASK_3AXIS_GYRO	\
1552	(BIT(INV_MPU6050_SCAN_GYRO_X)		\
1553	| BIT(INV_MPU6050_SCAN_GYRO_Y)		\
1554	| BIT(INV_MPU6050_SCAN_GYRO_Z))
1555
1556#define INV_MPU6050_SCAN_MASK_TEMP		(BIT(INV_MPU6050_SCAN_TEMP))
1557
1558static const unsigned long inv_mpu_scan_masks[] = {
1559	/* 3-axis accel */
1560	INV_MPU6050_SCAN_MASK_3AXIS_ACCEL,
1561	INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_TEMP,
1562	/* 3-axis gyro */
1563	INV_MPU6050_SCAN_MASK_3AXIS_GYRO,
1564	INV_MPU6050_SCAN_MASK_3AXIS_GYRO | INV_MPU6050_SCAN_MASK_TEMP,
1565	/* 6-axis accel + gyro */
1566	INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO,
1567	INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO
1568		| INV_MPU6050_SCAN_MASK_TEMP,
1569	0,
1570};
1571
1572#define INV_MPU9X50_MAGN_CHAN(_chan2, _bits, _index)			\
1573	{								\
1574		.type = IIO_MAGN,					\
1575		.modified = 1,						\
1576		.channel2 = _chan2,					\
1577		.info_mask_separate = BIT(IIO_CHAN_INFO_SCALE) |	\
1578				      BIT(IIO_CHAN_INFO_RAW),		\
1579		.scan_index = _index,					\
1580		.scan_type = {						\
1581			.sign = 's',					\
1582			.realbits = _bits,				\
1583			.storagebits = 16,				\
1584			.shift = 0,					\
1585			.endianness = IIO_BE,				\
1586		},							\
1587		.ext_info = inv_ext_info,				\
1588	}
1589
1590static const struct iio_chan_spec inv_mpu9150_channels[] = {
1591	IIO_CHAN_SOFT_TIMESTAMP(INV_MPU9X50_SCAN_TIMESTAMP),
1592
1593	INV_MPU6050_TEMP_CHAN(INV_MPU6050_SCAN_TEMP),
1594
1595	INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_MPU6050_SCAN_GYRO_X),
1596	INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_MPU6050_SCAN_GYRO_Y),
1597	INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_MPU6050_SCAN_GYRO_Z),
1598
1599	INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_MPU6050_SCAN_ACCL_X),
1600	INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_MPU6050_SCAN_ACCL_Y),
1601	INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),
1602
1603	/* Magnetometer resolution is 13 bits */
1604	INV_MPU9X50_MAGN_CHAN(IIO_MOD_X, 13, INV_MPU9X50_SCAN_MAGN_X),
1605	INV_MPU9X50_MAGN_CHAN(IIO_MOD_Y, 13, INV_MPU9X50_SCAN_MAGN_Y),
1606	INV_MPU9X50_MAGN_CHAN(IIO_MOD_Z, 13, INV_MPU9X50_SCAN_MAGN_Z),
1607};
1608
1609static const struct iio_chan_spec inv_mpu9250_channels[] = {
1610	IIO_CHAN_SOFT_TIMESTAMP(INV_MPU9X50_SCAN_TIMESTAMP),
1611
1612	INV_MPU6050_TEMP_CHAN(INV_MPU6050_SCAN_TEMP),
1613
1614	INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_MPU6050_SCAN_GYRO_X),
1615	INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_MPU6050_SCAN_GYRO_Y),
1616	INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_MPU6050_SCAN_GYRO_Z),
1617
1618	INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_MPU6050_SCAN_ACCL_X),
1619	INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_MPU6050_SCAN_ACCL_Y),
1620	INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),
1621
1622	/* Magnetometer resolution is 16 bits */
1623	INV_MPU9X50_MAGN_CHAN(IIO_MOD_X, 16, INV_MPU9X50_SCAN_MAGN_X),
1624	INV_MPU9X50_MAGN_CHAN(IIO_MOD_Y, 16, INV_MPU9X50_SCAN_MAGN_Y),
1625	INV_MPU9X50_MAGN_CHAN(IIO_MOD_Z, 16, INV_MPU9X50_SCAN_MAGN_Z),
1626};
1627
1628#define INV_MPU9X50_SCAN_MASK_3AXIS_MAGN	\
1629	(BIT(INV_MPU9X50_SCAN_MAGN_X)		\
1630	| BIT(INV_MPU9X50_SCAN_MAGN_Y)		\
1631	| BIT(INV_MPU9X50_SCAN_MAGN_Z))
1632
1633static const unsigned long inv_iam20380_scan_masks[] = {
1634	INV_MPU6050_SCAN_MASK_3AXIS_GYRO,
1635};
1636
1637static const unsigned long inv_mpu9x50_scan_masks[] = {
1638	/* 3-axis accel */
1639	INV_MPU6050_SCAN_MASK_3AXIS_ACCEL,
1640	INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_TEMP,
1641	/* 3-axis gyro */
1642	INV_MPU6050_SCAN_MASK_3AXIS_GYRO,
1643	INV_MPU6050_SCAN_MASK_3AXIS_GYRO | INV_MPU6050_SCAN_MASK_TEMP,
1644	/* 3-axis magn */
1645	INV_MPU9X50_SCAN_MASK_3AXIS_MAGN,
1646	INV_MPU9X50_SCAN_MASK_3AXIS_MAGN | INV_MPU6050_SCAN_MASK_TEMP,
1647	/* 6-axis accel + gyro */
1648	INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO,
1649	INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO
1650		| INV_MPU6050_SCAN_MASK_TEMP,
1651	/* 6-axis accel + magn */
1652	INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN,
1653	INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN
1654		| INV_MPU6050_SCAN_MASK_TEMP,
1655	/* 6-axis gyro + magn */
1656	INV_MPU6050_SCAN_MASK_3AXIS_GYRO | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN,
1657	INV_MPU6050_SCAN_MASK_3AXIS_GYRO | INV_MPU9X50_SCAN_MASK_3AXIS_MAGN
1658		| INV_MPU6050_SCAN_MASK_TEMP,
1659	/* 9-axis accel + gyro + magn */
1660	INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO
1661		| INV_MPU9X50_SCAN_MASK_3AXIS_MAGN,
1662	INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO
1663		| INV_MPU9X50_SCAN_MASK_3AXIS_MAGN
1664		| INV_MPU6050_SCAN_MASK_TEMP,
1665	0,
1666};
1667
1668static const unsigned long inv_icm20602_scan_masks[] = {
1669	/* 3-axis accel + temp (mandatory) */
1670	INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_TEMP,
1671	/* 3-axis gyro + temp (mandatory) */
1672	INV_MPU6050_SCAN_MASK_3AXIS_GYRO | INV_MPU6050_SCAN_MASK_TEMP,
1673	/* 6-axis accel + gyro + temp (mandatory) */
1674	INV_MPU6050_SCAN_MASK_3AXIS_ACCEL | INV_MPU6050_SCAN_MASK_3AXIS_GYRO
1675		| INV_MPU6050_SCAN_MASK_TEMP,
1676	0,
1677};
1678
1679/*
1680 * The user can choose any frequency between INV_MPU6050_MIN_FIFO_RATE and
1681 * INV_MPU6050_MAX_FIFO_RATE, but only these frequencies are matched by the
1682 * low-pass filter. Specifically, each of these sampling rates are about twice
1683 * the bandwidth of a corresponding low-pass filter, which should eliminate
1684 * aliasing following the Nyquist principle. By picking a frequency different
1685 * from these, the user risks aliasing effects.
1686 */
1687static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("10 20 50 100 200 500");
1688static IIO_CONST_ATTR(in_anglvel_scale_available,
1689					  "0.000133090 0.000266181 0.000532362 0.001064724");
1690static IIO_CONST_ATTR(in_accel_scale_available,
1691					  "0.000598 0.001196 0.002392 0.004785");
1692static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR, inv_fifo_rate_show,
1693	inv_mpu6050_fifo_rate_store);
1694
1695/* Deprecated: kept for userspace backward compatibility. */
1696static IIO_DEVICE_ATTR(in_gyro_matrix, S_IRUGO, inv_attr_show, NULL,
1697	ATTR_GYRO_MATRIX);
1698static IIO_DEVICE_ATTR(in_accel_matrix, S_IRUGO, inv_attr_show, NULL,
1699	ATTR_ACCL_MATRIX);
1700
1701static struct attribute *inv_attributes[] = {
1702	&iio_dev_attr_in_gyro_matrix.dev_attr.attr,  /* deprecated */
1703	&iio_dev_attr_in_accel_matrix.dev_attr.attr, /* deprecated */
1704	&iio_dev_attr_sampling_frequency.dev_attr.attr,
1705	&iio_const_attr_sampling_frequency_available.dev_attr.attr,
1706	&iio_const_attr_in_accel_scale_available.dev_attr.attr,
1707	&iio_const_attr_in_anglvel_scale_available.dev_attr.attr,
1708	NULL,
1709};
1710
1711static const struct attribute_group inv_attribute_group = {
1712	.attrs = inv_attributes
1713};
1714
1715static int inv_mpu6050_reg_access(struct iio_dev *indio_dev,
1716				  unsigned int reg,
1717				  unsigned int writeval,
1718				  unsigned int *readval)
1719{
1720	struct inv_mpu6050_state *st = iio_priv(indio_dev);
1721	int ret;
1722
1723	mutex_lock(&st->lock);
1724	if (readval)
1725		ret = regmap_read(st->map, reg, readval);
1726	else
1727		ret = regmap_write(st->map, reg, writeval);
1728	mutex_unlock(&st->lock);
1729
1730	return ret;
1731}
1732
1733static const struct iio_info mpu_info = {
1734	.read_raw = &inv_mpu6050_read_raw,
1735	.write_raw = &inv_mpu6050_write_raw,
1736	.write_raw_get_fmt = &inv_write_raw_get_fmt,
1737	.attrs = &inv_attribute_group,
1738	.read_event_config = inv_mpu6050_read_event_config,
1739	.write_event_config = inv_mpu6050_write_event_config,
1740	.read_event_value = inv_mpu6050_read_event_value,
1741	.write_event_value = inv_mpu6050_write_event_value,
1742	.validate_trigger = inv_mpu6050_validate_trigger,
1743	.debugfs_reg_access = &inv_mpu6050_reg_access,
1744};
1745
1746/*
1747 *  inv_check_and_setup_chip() - check and setup chip.
1748 */
1749static int inv_check_and_setup_chip(struct inv_mpu6050_state *st)
1750{
1751	int result;
1752	unsigned int regval, mask;
1753	int i;
1754
1755	st->hw  = &hw_info[st->chip_type];
1756	st->reg = hw_info[st->chip_type].reg;
1757	memcpy(&st->chip_config, hw_info[st->chip_type].config,
1758	       sizeof(st->chip_config));
1759	st->data = devm_kzalloc(regmap_get_device(st->map), st->hw->fifo_size, GFP_KERNEL);
1760	if (st->data == NULL)
1761		return -ENOMEM;
1762
1763	/* check chip self-identification */
1764	result = regmap_read(st->map, INV_MPU6050_REG_WHOAMI, &regval);
1765	if (result)
1766		return result;
1767	if (regval != st->hw->whoami) {
1768		/* check whoami against all possible values */
1769		for (i = 0; i < INV_NUM_PARTS; ++i) {
1770			if (regval == hw_info[i].whoami) {
1771				dev_warn(regmap_get_device(st->map),
1772					"whoami mismatch got 0x%02x (%s) expected 0x%02x (%s)\n",
1773					regval, hw_info[i].name,
1774					st->hw->whoami, st->hw->name);
1775				break;
1776			}
1777		}
1778		if (i >= INV_NUM_PARTS) {
1779			dev_err(regmap_get_device(st->map),
1780				"invalid whoami 0x%02x expected 0x%02x (%s)\n",
1781				regval, st->hw->whoami, st->hw->name);
1782			return -ENODEV;
1783		}
1784	}
1785
1786	/* reset to make sure previous state are not there */
1787	result = regmap_write(st->map, st->reg->pwr_mgmt_1,
1788			      INV_MPU6050_BIT_H_RESET);
1789	if (result)
1790		return result;
1791	msleep(INV_MPU6050_POWER_UP_TIME);
1792	switch (st->chip_type) {
1793	case INV_MPU6000:
1794	case INV_MPU6500:
1795	case INV_MPU6515:
1796	case INV_MPU6880:
1797	case INV_MPU9250:
1798	case INV_MPU9255:
1799		/* reset signal path (required for spi connection) */
1800		regval = INV_MPU6050_BIT_TEMP_RST | INV_MPU6050_BIT_ACCEL_RST |
1801			 INV_MPU6050_BIT_GYRO_RST;
1802		result = regmap_write(st->map, INV_MPU6050_REG_SIGNAL_PATH_RESET,
1803				      regval);
1804		if (result)
1805			return result;
1806		msleep(INV_MPU6050_POWER_UP_TIME);
1807		break;
1808	default:
1809		break;
1810	}
1811
1812	/*
1813	 * Turn power on. After reset, the sleep bit could be on
1814	 * or off depending on the OTP settings. Turning power on
1815	 * make it in a definite state as well as making the hardware
1816	 * state align with the software state
1817	 */
1818	result = inv_mpu6050_set_power_itg(st, true);
1819	if (result)
1820		return result;
1821	mask = INV_MPU6050_SENSOR_ACCL | INV_MPU6050_SENSOR_GYRO |
1822			INV_MPU6050_SENSOR_TEMP | INV_MPU6050_SENSOR_MAGN;
1823	result = inv_mpu6050_switch_engine(st, false, mask);
1824	if (result)
1825		goto error_power_off;
1826
1827	return 0;
1828
1829error_power_off:
1830	inv_mpu6050_set_power_itg(st, false);
1831	return result;
1832}
1833
1834static int inv_mpu_core_enable_regulator_vddio(struct inv_mpu6050_state *st)
1835{
1836	int result;
1837
1838	result = regulator_enable(st->vddio_supply);
1839	if (result) {
1840		dev_err(regmap_get_device(st->map),
1841			"Failed to enable vddio regulator: %d\n", result);
1842	} else {
1843		/* Give the device a little bit of time to start up. */
1844		usleep_range(3000, 5000);
1845	}
1846
1847	return result;
1848}
1849
1850static int inv_mpu_core_disable_regulator_vddio(struct inv_mpu6050_state *st)
1851{
1852	int result;
1853
1854	result = regulator_disable(st->vddio_supply);
1855	if (result)
1856		dev_err(regmap_get_device(st->map),
1857			"Failed to disable vddio regulator: %d\n", result);
1858
1859	return result;
1860}
1861
1862static void inv_mpu_core_disable_regulator_action(void *_data)
1863{
1864	struct inv_mpu6050_state *st = _data;
1865	int result;
1866
1867	result = regulator_disable(st->vdd_supply);
1868	if (result)
1869		dev_err(regmap_get_device(st->map),
1870			"Failed to disable vdd regulator: %d\n", result);
1871
1872	inv_mpu_core_disable_regulator_vddio(st);
1873}
1874
1875static void inv_mpu_pm_disable(void *data)
1876{
1877	struct device *dev = data;
1878
1879	pm_runtime_disable(dev);
1880}
1881
1882int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
1883		int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type)
1884{
1885	struct inv_mpu6050_state *st;
1886	struct iio_dev *indio_dev;
1887	struct inv_mpu6050_platform_data *pdata;
1888	struct device *dev = regmap_get_device(regmap);
1889	int result;
1890	int irq_type;
1891
1892	indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1893	if (!indio_dev)
1894		return -ENOMEM;
1895
1896	BUILD_BUG_ON(ARRAY_SIZE(hw_info) != INV_NUM_PARTS);
1897	if (chip_type < 0 || chip_type >= INV_NUM_PARTS) {
1898		dev_err(dev, "Bad invensense chip_type=%d name=%s\n",
1899				chip_type, name);
1900		return -ENODEV;
1901	}
1902	st = iio_priv(indio_dev);
1903	mutex_init(&st->lock);
1904	st->chip_type = chip_type;
1905	st->irq = irq;
1906	st->map = regmap;
1907
1908	st->level_shifter = device_property_read_bool(dev,
1909						      "invensense,level-shifter");
1910	pdata = dev_get_platdata(dev);
1911	if (!pdata) {
1912		result = iio_read_mount_matrix(dev, &st->orientation);
1913		if (result) {
1914			dev_err(dev, "Failed to retrieve mounting matrix %d\n",
1915				result);
1916			return result;
1917		}
1918	} else {
1919		st->plat_data = *pdata;
1920	}
1921
1922	if (irq > 0) {
1923		irq_type = irq_get_trigger_type(irq);
1924		if (!irq_type)
1925			irq_type = IRQF_TRIGGER_RISING;
1926	} else {
1927		/* Doesn't really matter, use the default */
1928		irq_type = IRQF_TRIGGER_RISING;
1929	}
1930
1931	if (irq_type & IRQF_TRIGGER_RISING)	// rising or both-edge
1932		st->irq_mask = INV_MPU6050_ACTIVE_HIGH;
1933	else if (irq_type == IRQF_TRIGGER_FALLING)
1934		st->irq_mask = INV_MPU6050_ACTIVE_LOW;
1935	else if (irq_type == IRQF_TRIGGER_HIGH)
1936		st->irq_mask = INV_MPU6050_ACTIVE_HIGH |
1937			INV_MPU6050_LATCH_INT_EN;
1938	else if (irq_type == IRQF_TRIGGER_LOW)
1939		st->irq_mask = INV_MPU6050_ACTIVE_LOW |
1940			INV_MPU6050_LATCH_INT_EN;
1941	else {
1942		dev_err(dev, "Invalid interrupt type 0x%x specified\n",
1943			irq_type);
1944		return -EINVAL;
1945	}
1946
1947	/*
1948	 * Acking interrupts by status register does not work reliably
1949	 * but seem to work when this bit is set.
1950	 */
1951	if (st->chip_type == INV_MPU9150)
1952		st->irq_mask |= INV_MPU6050_INT_RD_CLEAR;
1953
1954	device_set_wakeup_capable(dev, true);
1955
1956	st->vdd_supply = devm_regulator_get(dev, "vdd");
1957	if (IS_ERR(st->vdd_supply))
1958		return dev_err_probe(dev, PTR_ERR(st->vdd_supply),
1959				     "Failed to get vdd regulator\n");
1960
1961	st->vddio_supply = devm_regulator_get(dev, "vddio");
1962	if (IS_ERR(st->vddio_supply))
1963		return dev_err_probe(dev, PTR_ERR(st->vddio_supply),
1964				     "Failed to get vddio regulator\n");
1965
1966	result = regulator_enable(st->vdd_supply);
1967	if (result) {
1968		dev_err(dev, "Failed to enable vdd regulator: %d\n", result);
1969		return result;
1970	}
1971	msleep(INV_MPU6050_POWER_UP_TIME);
1972
1973	result = inv_mpu_core_enable_regulator_vddio(st);
1974	if (result) {
1975		regulator_disable(st->vdd_supply);
1976		return result;
1977	}
1978
1979	result = devm_add_action_or_reset(dev, inv_mpu_core_disable_regulator_action,
1980				 st);
1981	if (result) {
1982		dev_err(dev, "Failed to setup regulator cleanup action %d\n",
1983			result);
1984		return result;
1985	}
1986
1987	/* fill magnetometer orientation */
1988	result = inv_mpu_magn_set_orient(st);
1989	if (result)
1990		return result;
1991
1992	/* power is turned on inside check chip type*/
1993	result = inv_check_and_setup_chip(st);
1994	if (result)
1995		return result;
1996
1997	result = inv_mpu6050_init_config(indio_dev);
1998	if (result) {
1999		dev_err(dev, "Could not initialize device.\n");
2000		goto error_power_off;
2001	}
2002
2003	dev_set_drvdata(dev, indio_dev);
2004	/* name will be NULL when enumerated via ACPI */
2005	if (name)
2006		indio_dev->name = name;
2007	else
2008		indio_dev->name = dev_name(dev);
2009
2010	/* requires parent device set in indio_dev */
2011	if (inv_mpu_bus_setup) {
2012		result = inv_mpu_bus_setup(indio_dev);
2013		if (result)
2014			goto error_power_off;
2015	}
2016
2017	/* chip init is done, turning on runtime power management */
2018	result = pm_runtime_set_active(dev);
2019	if (result)
2020		goto error_power_off;
2021	pm_runtime_get_noresume(dev);
2022	pm_runtime_enable(dev);
2023	pm_runtime_set_autosuspend_delay(dev, INV_MPU6050_SUSPEND_DELAY_MS);
2024	pm_runtime_use_autosuspend(dev);
2025	pm_runtime_put(dev);
2026	result = devm_add_action_or_reset(dev, inv_mpu_pm_disable, dev);
2027	if (result)
2028		return result;
2029
2030	switch (chip_type) {
2031	case INV_MPU6000:
2032	case INV_MPU6050:
2033		indio_dev->channels = inv_mpu6050_channels;
2034		indio_dev->num_channels = ARRAY_SIZE(inv_mpu6050_channels);
2035		indio_dev->available_scan_masks = inv_mpu_scan_masks;
2036		break;
2037	case INV_MPU9150:
2038		indio_dev->channels = inv_mpu9150_channels;
2039		indio_dev->num_channels = ARRAY_SIZE(inv_mpu9150_channels);
2040		indio_dev->available_scan_masks = inv_mpu9x50_scan_masks;
2041		break;
2042	case INV_MPU9250:
2043	case INV_MPU9255:
2044		indio_dev->channels = inv_mpu9250_channels;
2045		indio_dev->num_channels = ARRAY_SIZE(inv_mpu9250_channels);
2046		indio_dev->available_scan_masks = inv_mpu9x50_scan_masks;
2047		break;
2048	case INV_IAM20380:
2049		indio_dev->channels = inv_iam20380_channels;
2050		indio_dev->num_channels = ARRAY_SIZE(inv_iam20380_channels);
2051		indio_dev->available_scan_masks = inv_iam20380_scan_masks;
2052		break;
2053	case INV_ICM20600:
2054	case INV_ICM20602:
2055		indio_dev->channels = inv_mpu6500_channels;
2056		indio_dev->num_channels = ARRAY_SIZE(inv_mpu6500_channels);
2057		indio_dev->available_scan_masks = inv_icm20602_scan_masks;
2058		break;
2059	default:
2060		indio_dev->channels = inv_mpu6500_channels;
2061		indio_dev->num_channels = ARRAY_SIZE(inv_mpu6500_channels);
2062		indio_dev->available_scan_masks = inv_mpu_scan_masks;
2063		break;
2064	}
2065	/*
2066	 * Use magnetometer inside the chip only if there is no i2c
2067	 * auxiliary device in use. Otherwise Going back to 6-axis only.
2068	 */
2069	if (st->magn_disabled) {
2070		switch (chip_type) {
2071		case INV_MPU9150:
2072			indio_dev->channels = inv_mpu6050_channels;
2073			indio_dev->num_channels = ARRAY_SIZE(inv_mpu6050_channels);
2074			indio_dev->available_scan_masks = inv_mpu_scan_masks;
2075			break;
2076		default:
2077			indio_dev->channels = inv_mpu6500_channels;
2078			indio_dev->num_channels = ARRAY_SIZE(inv_mpu6500_channels);
2079			indio_dev->available_scan_masks = inv_mpu_scan_masks;
2080			break;
2081		}
2082	}
2083
2084	indio_dev->info = &mpu_info;
2085
2086	if (irq > 0) {
2087		/*
2088		 * The driver currently only supports buffered capture with its
2089		 * own trigger. So no IRQ, no trigger, no buffer
2090		 */
2091		result = devm_iio_triggered_buffer_setup(dev, indio_dev,
2092							 iio_pollfunc_store_time,
2093							 inv_mpu6050_read_fifo,
2094							 NULL);
2095		if (result) {
2096			dev_err(dev, "configure buffer fail %d\n", result);
2097			return result;
2098		}
2099
2100		result = inv_mpu6050_probe_trigger(indio_dev, irq_type);
2101		if (result) {
2102			dev_err(dev, "trigger probe fail %d\n", result);
2103			return result;
2104		}
2105	}
2106
2107	result = devm_iio_device_register(dev, indio_dev);
2108	if (result) {
2109		dev_err(dev, "IIO register fail %d\n", result);
2110		return result;
2111	}
2112
2113	return 0;
2114
2115error_power_off:
2116	inv_mpu6050_set_power_itg(st, false);
2117	return result;
2118}
2119EXPORT_SYMBOL_NS_GPL(inv_mpu_core_probe, "IIO_MPU6050");
2120
2121static int inv_mpu_resume(struct device *dev)
2122{
2123	struct iio_dev *indio_dev = dev_get_drvdata(dev);
2124	struct inv_mpu6050_state *st = iio_priv(indio_dev);
2125	bool wakeup;
2126	int result;
2127
2128	guard(mutex)(&st->lock);
2129
2130	wakeup = device_may_wakeup(dev) && st->chip_config.wom_en;
2131
2132	if (wakeup) {
2133		enable_irq(st->irq);
2134		disable_irq_wake(st->irq);
2135		result = inv_mpu6050_set_wom_lp(st, false);
2136		if (result)
2137			return result;
2138	} else {
2139		result = inv_mpu_core_enable_regulator_vddio(st);
2140		if (result)
2141			return result;
2142		result = inv_mpu6050_set_power_itg(st, true);
2143		if (result)
2144			return result;
2145	}
2146
2147	pm_runtime_disable(dev);
2148	pm_runtime_set_active(dev);
2149	pm_runtime_enable(dev);
2150
2151	result = inv_mpu6050_switch_engine(st, true, st->suspended_sensors);
2152	if (result)
2153		return result;
2154
2155	if (st->chip_config.wom_en && !wakeup) {
2156		result = inv_mpu6050_set_wom_int(st, true);
2157		if (result)
2158			return result;
2159	}
2160
2161	if (iio_buffer_enabled(indio_dev))
2162		result = inv_mpu6050_prepare_fifo(st, true);
2163
2164	return result;
2165}
2166
2167static int inv_mpu_suspend(struct device *dev)
2168{
2169	struct iio_dev *indio_dev = dev_get_drvdata(dev);
2170	struct inv_mpu6050_state *st = iio_priv(indio_dev);
2171	bool wakeup;
2172	int result;
2173
2174	guard(mutex)(&st->lock);
2175
2176	st->suspended_sensors = 0;
2177	if (pm_runtime_suspended(dev))
2178		return 0;
2179
2180	if (iio_buffer_enabled(indio_dev)) {
2181		result = inv_mpu6050_prepare_fifo(st, false);
2182		if (result)
2183			return result;
2184	}
2185
2186	wakeup = device_may_wakeup(dev) && st->chip_config.wom_en;
2187
2188	if (st->chip_config.wom_en && !wakeup) {
2189		result = inv_mpu6050_set_wom_int(st, false);
2190		if (result)
2191			return result;
2192	}
2193
2194	if (st->chip_config.accl_en && !wakeup)
2195		st->suspended_sensors |= INV_MPU6050_SENSOR_ACCL;
2196	if (st->chip_config.gyro_en)
2197		st->suspended_sensors |= INV_MPU6050_SENSOR_GYRO;
2198	if (st->chip_config.temp_en)
2199		st->suspended_sensors |= INV_MPU6050_SENSOR_TEMP;
2200	if (st->chip_config.magn_en)
2201		st->suspended_sensors |= INV_MPU6050_SENSOR_MAGN;
2202	if (st->chip_config.wom_en && !wakeup)
2203		st->suspended_sensors |= INV_MPU6050_SENSOR_WOM;
2204	result = inv_mpu6050_switch_engine(st, false, st->suspended_sensors);
2205	if (result)
2206		return result;
2207
2208	if (wakeup) {
2209		result = inv_mpu6050_set_wom_lp(st, true);
2210		if (result)
2211			return result;
2212		enable_irq_wake(st->irq);
2213		disable_irq(st->irq);
2214	} else {
2215		result = inv_mpu6050_set_power_itg(st, false);
2216		if (result)
2217			return result;
2218		inv_mpu_core_disable_regulator_vddio(st);
2219	}
2220
2221	return 0;
2222}
2223
2224static int inv_mpu_runtime_suspend(struct device *dev)
2225{
2226	struct inv_mpu6050_state *st = iio_priv(dev_get_drvdata(dev));
2227	unsigned int sensors;
2228	int ret;
2229
2230	mutex_lock(&st->lock);
2231
2232	sensors = INV_MPU6050_SENSOR_ACCL | INV_MPU6050_SENSOR_GYRO |
2233			INV_MPU6050_SENSOR_TEMP | INV_MPU6050_SENSOR_MAGN |
2234			INV_MPU6050_SENSOR_WOM;
2235	ret = inv_mpu6050_switch_engine(st, false, sensors);
2236	if (ret)
2237		goto out_unlock;
2238
2239	ret = inv_mpu6050_set_power_itg(st, false);
2240	if (ret)
2241		goto out_unlock;
2242
2243	inv_mpu_core_disable_regulator_vddio(st);
2244
2245out_unlock:
2246	mutex_unlock(&st->lock);
2247	return ret;
2248}
2249
2250static int inv_mpu_runtime_resume(struct device *dev)
2251{
2252	struct inv_mpu6050_state *st = iio_priv(dev_get_drvdata(dev));
2253	int ret;
2254
2255	ret = inv_mpu_core_enable_regulator_vddio(st);
2256	if (ret)
2257		return ret;
2258
2259	return inv_mpu6050_set_power_itg(st, true);
2260}
2261
2262EXPORT_NS_GPL_DEV_PM_OPS(inv_mpu_pmops, IIO_MPU6050) = {
2263	SYSTEM_SLEEP_PM_OPS(inv_mpu_suspend, inv_mpu_resume)
2264	RUNTIME_PM_OPS(inv_mpu_runtime_suspend, inv_mpu_runtime_resume, NULL)
2265};
2266
2267MODULE_AUTHOR("Invensense Corporation");
2268MODULE_DESCRIPTION("Invensense device MPU6050 driver");
2269MODULE_LICENSE("GPL");
2270MODULE_IMPORT_NS("IIO_INV_SENSORS_TIMESTAMP");