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adis16550.c
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linux-6.19.14/drivers/iio/imu/adis16550.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * ADIS16550 IMU driver 4 * 5 * Copyright 2024 Analog Devices Inc. 6 */ 7#include <linux/bitfield.h> 8#include <linux/bitops.h> 9#include <linux/clk.h> 10#include <linux/crc32.h> 11#include <linux/debugfs.h> 12#include <linux/iio/buffer.h> 13#include <linux/iio/iio.h> 14#include <linux/iio/imu/adis.h> 15#include <linux/iio/trigger_consumer.h> 16#include <linux/interrupt.h> 17#include <linux/kernel.h> 18#include <linux/lcm.h> 19#include <linux/math.h> 20#include <linux/module.h> 21#include <linux/mod_devicetable.h> 22#include <linux/regulator/consumer.h> 23#include <linux/spi/spi.h> 24#include <linux/swab.h> 25#include <linux/unaligned.h> 26 27#define ADIS16550_REG_BURST_GYRO_ACCEL 0x0a 28#define ADIS16550_REG_BURST_DELTA_ANG_VEL 0x0b 29#define ADIS16550_BURST_DATA_GYRO_ACCEL_MASK GENMASK(6, 1) 30#define ADIS16550_BURST_DATA_DELTA_ANG_VEL_MASK GENMASK(12, 7) 31 32#define ADIS16550_REG_STATUS 0x0e 33#define ADIS16550_REG_TEMP 0x10 34#define ADIS16550_REG_X_GYRO 0x12 35#define ADIS16550_REG_Y_GYRO 0x14 36#define ADIS16550_REG_Z_GYRO 0x16 37#define ADIS16550_REG_X_ACCEL 0x18 38#define ADIS16550_REG_Y_ACCEL 0x1a 39#define ADIS16550_REG_Z_ACCEL 0x1c 40#define ADIS16550_REG_X_DELTANG_L 0x1E 41#define ADIS16550_REG_Y_DELTANG_L 0x20 42#define ADIS16550_REG_Z_DELTANG_L 0x22 43#define ADIS16550_REG_X_DELTVEL_L 0x24 44#define ADIS16550_REG_Y_DELTVEL_L 0x26 45#define ADIS16550_REG_Z_DELTVEL_L 0x28 46#define ADIS16550_REG_X_GYRO_SCALE 0x30 47#define ADIS16550_REG_Y_GYRO_SCALE 0x32 48#define ADIS16550_REG_Z_GYRO_SCALE 0x34 49#define ADIS16550_REG_X_ACCEL_SCALE 0x36 50#define ADIS16550_REG_Y_ACCEL_SCALE 0x38 51#define ADIS16550_REG_Z_ACCEL_SCALE 0x3a 52#define ADIS16550_REG_X_GYRO_BIAS 0x40 53#define ADIS16550_REG_Y_GYRO_BIAS 0x42 54#define ADIS16550_REG_Z_GYRO_BIAS 0x44 55#define ADIS16550_REG_X_ACCEL_BIAS 0x46 56#define ADIS16550_REG_Y_ACCEL_BIAS 0x48 57#define ADIS16550_REG_Z_ACCEL_BIAS 0x4a 58#define ADIS16550_REG_COMMAND 0x50 59#define ADIS16550_REG_CONFIG 0x52 60#define ADIS16550_GYRO_FIR_EN_MASK BIT(3) 61#define ADIS16550_ACCL_FIR_EN_MASK BIT(2) 62#define ADIS16550_SYNC_MASK \ 63 (ADIS16550_SYNC_EN_MASK | ADIS16550_SYNC_MODE_MASK) 64#define ADIS16550_SYNC_MODE_MASK BIT(1) 65#define ADIS16550_SYNC_EN_MASK BIT(0) 66/* max of 4000 SPS in scale sync */ 67#define ADIS16550_SYNC_SCALE_MAX_RATE (4000 * 1000) 68#define ADIS16550_REG_DEC_RATE 0x54 69#define ADIS16550_REG_SYNC_SCALE 0x56 70#define ADIS16550_REG_SERIAL_NUM 0x76 71#define ADIS16550_REG_FW_REV 0x7A 72#define ADIS16550_REG_FW_DATE 0x7C 73#define ADIS16550_REG_PROD_ID 0x7E 74#define ADIS16550_REG_FLASH_CNT 0x72 75/* SPI protocol*/ 76#define ADIS16550_SPI_DATA_MASK GENMASK(31, 16) 77#define ADIS16550_SPI_REG_MASK GENMASK(14, 8) 78#define ADIS16550_SPI_R_W_MASK BIT(7) 79#define ADIS16550_SPI_CRC_MASK GENMASK(3, 0) 80#define ADIS16550_SPI_SV_MASK GENMASK(7, 6) 81/* burst read */ 82#define ADIS16550_BURST_N_ELEM 12 83#define ADIS16550_BURST_DATA_LEN (ADIS16550_BURST_N_ELEM * 4) 84#define ADIS16550_MAX_SCAN_DATA 12 85 86struct adis16550_sync { 87 u16 sync_mode; 88 u16 min_rate; 89 u16 max_rate; 90}; 91 92struct adis16550_chip_info { 93 const struct iio_chan_spec *channels; 94 const struct adis16550_sync *sync_mode; 95 char *name; 96 u32 num_channels; 97 u32 gyro_max_val; 98 u32 gyro_max_scale; 99 u32 accel_max_val; 100 u32 accel_max_scale; 101 u32 temp_scale; 102 u32 deltang_max_val; 103 u32 deltvel_max_val; 104 u32 int_clk; 105 u16 max_dec; 106 u16 num_sync; 107}; 108 109struct adis16550 { 110 const struct adis16550_chip_info *info; 111 struct adis adis; 112 unsigned long clk_freq_hz; 113 u32 sync_mode; 114 struct spi_transfer xfer[2]; 115 u8 buffer[ADIS16550_BURST_DATA_LEN + sizeof(u32)] __aligned(IIO_DMA_MINALIGN); 116 __be32 din[2]; 117 __be32 dout[2]; 118}; 119 120enum { 121 ADIS16550_SV_INIT, 122 ADIS16550_SV_OK, 123 ADIS16550_SV_NOK, 124 ADIS16550_SV_SPI_ERROR, 125}; 126 127/* 128 * This is a simplified implementation of lib/crc4.c. It could not be used 129 * directly since the polynomial used is different from the one used by the 130 * 16550 which is 0b10001 131 */ 132static u8 spi_crc4(const u32 val) 133{ 134 int i; 135 const int bits = 28; 136 u8 crc = 0xa; 137 /* ignore 4lsb */ 138 const u32 __val = val >> 4; 139 140 /* Calculate crc4 over four-bit nibbles, starting at the MSbit */ 141 for (i = bits - 4; i >= 0; i -= 4) 142 crc = crc ^ ((__val >> i) & 0xf); 143 144 return crc; 145} 146 147static int adis16550_spi_validate(const struct adis *adis, __be32 dout, 148 u16 *data) 149{ 150 u32 __dout; 151 u8 crc, crc_rcv, sv; 152 153 __dout = be32_to_cpu(dout); 154 155 /* validate received message */ 156 crc_rcv = FIELD_GET(ADIS16550_SPI_CRC_MASK, __dout); 157 crc = spi_crc4(__dout); 158 if (crc_rcv != crc) { 159 dev_err(&adis->spi->dev, 160 "Invalid crc, rcv: 0x%02x, calc: 0x%02x!\n", 161 crc_rcv, crc); 162 return -EIO; 163 } 164 sv = FIELD_GET(ADIS16550_SPI_SV_MASK, __dout); 165 if (sv >= ADIS16550_SV_NOK) { 166 dev_err(&adis->spi->dev, 167 "State vector error detected: %02X", sv); 168 return -EIO; 169 } 170 *data = FIELD_GET(ADIS16550_SPI_DATA_MASK, __dout); 171 172 return 0; 173} 174 175static void adis16550_spi_msg_prepare(const u32 reg, const bool write, 176 const u16 data, __be32 *din) 177{ 178 u8 crc; 179 u32 __din; 180 181 __din = FIELD_PREP(ADIS16550_SPI_REG_MASK, reg); 182 183 if (write) { 184 __din |= FIELD_PREP(ADIS16550_SPI_R_W_MASK, 1); 185 __din |= FIELD_PREP(ADIS16550_SPI_DATA_MASK, data); 186 } 187 188 crc = spi_crc4(__din); 189 __din |= FIELD_PREP(ADIS16550_SPI_CRC_MASK, crc); 190 191 *din = cpu_to_be32(__din); 192} 193 194static int adis16550_spi_xfer(const struct adis *adis, u32 reg, u32 len, 195 u32 *readval, u32 writeval) 196{ 197 int ret; 198 u16 data = 0; 199 struct spi_message msg; 200 bool wr = readval ? false : true; 201 struct spi_device *spi = adis->spi; 202 struct adis16550 *st = container_of(adis, struct adis16550, adis); 203 struct spi_transfer xfers[] = { 204 { 205 .tx_buf = &st->din[0], 206 .len = 4, 207 .cs_change = 1, 208 }, { 209 .tx_buf = &st->din[1], 210 .len = 4, 211 .cs_change = 1, 212 .rx_buf = st->dout, 213 }, { 214 .tx_buf = &st->din[1], 215 .rx_buf = &st->dout[1], 216 .len = 4, 217 }, 218 }; 219 220 spi_message_init(&msg); 221 222 switch (len) { 223 case 4: 224 adis16550_spi_msg_prepare(reg + 1, wr, writeval >> 16, 225 &st->din[0]); 226 spi_message_add_tail(&xfers[0], &msg); 227 fallthrough; 228 case 2: 229 adis16550_spi_msg_prepare(reg, wr, writeval, &st->din[1]); 230 spi_message_add_tail(&xfers[1], &msg); 231 spi_message_add_tail(&xfers[2], &msg); 232 break; 233 default: 234 return -EINVAL; 235 } 236 237 ret = spi_sync(spi, &msg); 238 if (ret) { 239 dev_err(&spi->dev, "Spi failure %d\n", ret); 240 return ret; 241 } 242 /* 243 * When writing a register, the device will reply with a readback on the 244 * transfer so that we can validate if our data was actually written.. 245 */ 246 switch (len) { 247 case 4: 248 ret = adis16550_spi_validate(adis, st->dout[0], &data); 249 if (ret) 250 return ret; 251 252 if (readval) { 253 *readval = data << 16; 254 } else if ((writeval >> 16) != data && reg != ADIS16550_REG_COMMAND) { 255 dev_err(&spi->dev, 256 "Data not written: wr: 0x%04X, rcv: 0x%04X\n", 257 writeval >> 16, data); 258 return -EIO; 259 } 260 261 fallthrough; 262 case 2: 263 ret = adis16550_spi_validate(adis, st->dout[1], &data); 264 if (ret) 265 return ret; 266 267 if (readval) { 268 *readval = (*readval & GENMASK(31, 16)) | data; 269 } else if ((writeval & GENMASK(15, 0)) != data && reg != ADIS16550_REG_COMMAND) { 270 dev_err(&spi->dev, 271 "Data not written: wr: 0x%04X, rcv: 0x%04X\n", 272 (u16)writeval, data); 273 return -EIO; 274 } 275 } 276 277 return 0; 278} 279 280static int adis16550_spi_read(struct adis *adis, const u32 reg, 281 u32 *value, const u32 len) 282{ 283 return adis16550_spi_xfer(adis, reg, len, value, 0); 284} 285 286static int adis16550_spi_write(struct adis *adis, const u32 reg, 287 const u32 value, const u32 len) 288{ 289 return adis16550_spi_xfer(adis, reg, len, NULL, value); 290} 291 292static ssize_t adis16550_show_firmware_revision(struct file *file, 293 char __user *userbuf, 294 size_t count, loff_t *ppos) 295{ 296 struct adis16550 *st = file->private_data; 297 char buf[7]; 298 size_t len; 299 u16 rev; 300 int ret; 301 302 ret = adis_read_reg_16(&st->adis, ADIS16550_REG_FW_REV, &rev); 303 if (ret) 304 return ret; 305 306 len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff); 307 308 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 309} 310 311static const struct file_operations adis16550_firmware_revision_fops = { 312 .open = simple_open, 313 .read = adis16550_show_firmware_revision, 314 .llseek = default_llseek, 315 .owner = THIS_MODULE, 316}; 317 318static ssize_t adis16550_show_firmware_date(struct file *file, 319 char __user *userbuf, 320 size_t count, loff_t *ppos) 321{ 322 struct adis16550 *st = file->private_data; 323 char buf[12]; 324 size_t len; 325 u32 date; 326 int ret; 327 328 ret = adis_read_reg_32(&st->adis, ADIS16550_REG_FW_DATE, &date); 329 if (ret) 330 return ret; 331 332 len = scnprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n", date & 0xff, 333 (date >> 8) & 0xff, date >> 16); 334 335 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 336} 337 338static const struct file_operations adis16550_firmware_date_fops = { 339 .open = simple_open, 340 .read = adis16550_show_firmware_date, 341 .llseek = default_llseek, 342 .owner = THIS_MODULE, 343}; 344 345static int adis16550_show_serial_number(void *arg, u64 *val) 346{ 347 struct adis16550 *st = arg; 348 u32 serial; 349 int ret; 350 351 ret = adis_read_reg_32(&st->adis, ADIS16550_REG_SERIAL_NUM, &serial); 352 if (ret) 353 return ret; 354 355 *val = serial; 356 357 return 0; 358} 359DEFINE_DEBUGFS_ATTRIBUTE(adis16550_serial_number_fops, 360 adis16550_show_serial_number, NULL, "0x%.8llx\n"); 361 362static int adis16550_show_product_id(void *arg, u64 *val) 363{ 364 struct adis16550 *st = arg; 365 u16 prod_id; 366 int ret; 367 368 ret = adis_read_reg_16(&st->adis, ADIS16550_REG_PROD_ID, &prod_id); 369 if (ret) 370 return ret; 371 372 *val = prod_id; 373 374 return 0; 375} 376DEFINE_DEBUGFS_ATTRIBUTE(adis16550_product_id_fops, 377 adis16550_show_product_id, NULL, "%llu\n"); 378 379static int adis16550_show_flash_count(void *arg, u64 *val) 380{ 381 struct adis16550 *st = arg; 382 u16 flash_count; 383 int ret; 384 385 ret = adis_read_reg_16(&st->adis, ADIS16550_REG_FLASH_CNT, &flash_count); 386 if (ret) 387 return ret; 388 389 *val = flash_count; 390 391 return 0; 392} 393DEFINE_DEBUGFS_ATTRIBUTE(adis16550_flash_count_fops, 394 adis16550_show_flash_count, NULL, "%lld\n"); 395 396static void adis16550_debugfs_init(struct iio_dev *indio_dev) 397{ 398 struct adis16550 *st = iio_priv(indio_dev); 399 struct dentry *d = iio_get_debugfs_dentry(indio_dev); 400 401 debugfs_create_file_unsafe("serial_number", 0400, d, st, 402 &adis16550_serial_number_fops); 403 debugfs_create_file_unsafe("product_id", 0400, d, st, 404 &adis16550_product_id_fops); 405 debugfs_create_file("firmware_revision", 0400, d, st, 406 &adis16550_firmware_revision_fops); 407 debugfs_create_file("firmware_date", 0400, d, st, 408 &adis16550_firmware_date_fops); 409 debugfs_create_file_unsafe("flash_count", 0400, d, st, 410 &adis16550_flash_count_fops); 411} 412 413enum { 414 ADIS16550_SYNC_MODE_DIRECT, 415 ADIS16550_SYNC_MODE_SCALED, 416}; 417 418static int adis16550_get_freq(struct adis16550 *st, u32 *freq) 419{ 420 int ret; 421 u16 dec = 0; 422 u32 sample_rate = st->clk_freq_hz; 423 424 adis_dev_auto_lock(&st->adis); 425 426 if (st->sync_mode == ADIS16550_SYNC_MODE_SCALED) { 427 u16 sync_scale; 428 429 ret = __adis_read_reg_16(&st->adis, ADIS16550_REG_SYNC_SCALE, &sync_scale); 430 if (ret) 431 return ret; 432 433 sample_rate = st->clk_freq_hz * sync_scale; 434 } 435 436 ret = __adis_read_reg_16(&st->adis, ADIS16550_REG_DEC_RATE, &dec); 437 if (ret) 438 return -EINVAL; 439 *freq = DIV_ROUND_CLOSEST(sample_rate, dec + 1); 440 441 return 0; 442} 443 444static int adis16550_set_freq_hz(struct adis16550 *st, u32 freq_hz) 445{ 446 u16 dec; 447 int ret; 448 u32 sample_rate = st->clk_freq_hz; 449 /* 450 * The optimal sample rate for the supported IMUs is between 451 * int_clk - 1000 and int_clk + 500. 452 */ 453 u32 max_sample_rate = st->info->int_clk * 1000 + 500000; 454 u32 min_sample_rate = st->info->int_clk * 1000 - 1000000; 455 456 if (!freq_hz) 457 return -EINVAL; 458 459 adis_dev_auto_lock(&st->adis); 460 461 if (st->sync_mode == ADIS16550_SYNC_MODE_SCALED) { 462 unsigned long scaled_rate = lcm(st->clk_freq_hz, freq_hz); 463 int sync_scale; 464 465 if (scaled_rate > max_sample_rate) 466 scaled_rate = max_sample_rate / st->clk_freq_hz * st->clk_freq_hz; 467 else 468 scaled_rate = max_sample_rate / scaled_rate * scaled_rate; 469 470 if (scaled_rate < min_sample_rate) 471 scaled_rate = roundup(min_sample_rate, st->clk_freq_hz); 472 473 sync_scale = scaled_rate / st->clk_freq_hz; 474 ret = __adis_write_reg_16(&st->adis, ADIS16550_REG_SYNC_SCALE, 475 sync_scale); 476 if (ret) 477 return ret; 478 479 sample_rate = scaled_rate; 480 } 481 482 dec = DIV_ROUND_CLOSEST(sample_rate, freq_hz); 483 484 if (dec) 485 dec--; 486 487 dec = min(dec, st->info->max_dec); 488 489 return __adis_write_reg_16(&st->adis, ADIS16550_REG_DEC_RATE, dec); 490} 491 492static int adis16550_get_accl_filter_freq(struct adis16550 *st, int *freq_hz) 493{ 494 int ret; 495 u16 config = 0; 496 497 ret = adis_read_reg_16(&st->adis, ADIS16550_REG_CONFIG, &config); 498 if (ret) 499 return -EINVAL; 500 501 if (FIELD_GET(ADIS16550_ACCL_FIR_EN_MASK, config)) 502 *freq_hz = 100; 503 else 504 *freq_hz = 0; 505 506 return 0; 507} 508 509static int adis16550_set_accl_filter_freq(struct adis16550 *st, int freq_hz) 510{ 511 u8 en = freq_hz ? 1 : 0; 512 u16 val = FIELD_PREP(ADIS16550_ACCL_FIR_EN_MASK, en); 513 514 return __adis_update_bits(&st->adis, ADIS16550_REG_CONFIG, 515 ADIS16550_ACCL_FIR_EN_MASK, val); 516} 517 518static int adis16550_get_gyro_filter_freq(struct adis16550 *st, int *freq_hz) 519{ 520 int ret; 521 u16 config = 0; 522 523 ret = adis_read_reg_16(&st->adis, ADIS16550_REG_CONFIG, &config); 524 if (ret) 525 return -EINVAL; 526 527 if (FIELD_GET(ADIS16550_GYRO_FIR_EN_MASK, config)) 528 *freq_hz = 100; 529 else 530 *freq_hz = 0; 531 532 return 0; 533} 534 535static int adis16550_set_gyro_filter_freq(struct adis16550 *st, int freq_hz) 536{ 537 u8 en = freq_hz ? 1 : 0; 538 u16 val = FIELD_PREP(ADIS16550_GYRO_FIR_EN_MASK, en); 539 540 return __adis_update_bits(&st->adis, ADIS16550_REG_CONFIG, 541 ADIS16550_GYRO_FIR_EN_MASK, val); 542} 543 544enum { 545 ADIS16550_SCAN_TEMP, 546 ADIS16550_SCAN_GYRO_X, 547 ADIS16550_SCAN_GYRO_Y, 548 ADIS16550_SCAN_GYRO_Z, 549 ADIS16550_SCAN_ACCEL_X, 550 ADIS16550_SCAN_ACCEL_Y, 551 ADIS16550_SCAN_ACCEL_Z, 552 ADIS16550_SCAN_DELTANG_X, 553 ADIS16550_SCAN_DELTANG_Y, 554 ADIS16550_SCAN_DELTANG_Z, 555 ADIS16550_SCAN_DELTVEL_X, 556 ADIS16550_SCAN_DELTVEL_Y, 557 ADIS16550_SCAN_DELTVEL_Z, 558}; 559 560static const u32 adis16550_calib_bias[] = { 561 [ADIS16550_SCAN_GYRO_X] = ADIS16550_REG_X_GYRO_BIAS, 562 [ADIS16550_SCAN_GYRO_Y] = ADIS16550_REG_Y_GYRO_BIAS, 563 [ADIS16550_SCAN_GYRO_Z] = ADIS16550_REG_Z_GYRO_BIAS, 564 [ADIS16550_SCAN_ACCEL_X] = ADIS16550_REG_X_ACCEL_BIAS, 565 [ADIS16550_SCAN_ACCEL_Y] = ADIS16550_REG_Y_ACCEL_BIAS, 566 [ADIS16550_SCAN_ACCEL_Z] = ADIS16550_REG_Z_ACCEL_BIAS, 567 568}; 569 570static const u32 adis16550_calib_scale[] = { 571 [ADIS16550_SCAN_GYRO_X] = ADIS16550_REG_X_GYRO_SCALE, 572 [ADIS16550_SCAN_GYRO_Y] = ADIS16550_REG_Y_GYRO_SCALE, 573 [ADIS16550_SCAN_GYRO_Z] = ADIS16550_REG_Z_GYRO_SCALE, 574 [ADIS16550_SCAN_ACCEL_X] = ADIS16550_REG_X_ACCEL_SCALE, 575 [ADIS16550_SCAN_ACCEL_Y] = ADIS16550_REG_Y_ACCEL_SCALE, 576 [ADIS16550_SCAN_ACCEL_Z] = ADIS16550_REG_Z_ACCEL_SCALE, 577}; 578 579static int adis16550_read_raw(struct iio_dev *indio_dev, 580 const struct iio_chan_spec *chan, 581 int *val, int *val2, long info) 582{ 583 struct adis16550 *st = iio_priv(indio_dev); 584 const int idx = chan->scan_index; 585 u16 scale; 586 int ret; 587 u32 tmp; 588 589 switch (info) { 590 case IIO_CHAN_INFO_RAW: 591 return adis_single_conversion(indio_dev, chan, 0, val); 592 case IIO_CHAN_INFO_SCALE: 593 switch (chan->type) { 594 case IIO_ANGL_VEL: 595 *val = st->info->gyro_max_val; 596 *val2 = st->info->gyro_max_scale; 597 return IIO_VAL_FRACTIONAL; 598 case IIO_ACCEL: 599 *val = st->info->accel_max_val; 600 *val2 = st->info->accel_max_scale; 601 return IIO_VAL_FRACTIONAL; 602 case IIO_TEMP: 603 *val = st->info->temp_scale; 604 return IIO_VAL_INT; 605 case IIO_DELTA_ANGL: 606 *val = st->info->deltang_max_val; 607 *val2 = 31; 608 return IIO_VAL_FRACTIONAL_LOG2; 609 case IIO_DELTA_VELOCITY: 610 *val = st->info->deltvel_max_val; 611 *val2 = 31; 612 return IIO_VAL_FRACTIONAL_LOG2; 613 default: 614 return -EINVAL; 615 } 616 case IIO_CHAN_INFO_OFFSET: 617 /* temperature centered at 25°C */ 618 *val = DIV_ROUND_CLOSEST(25000, st->info->temp_scale); 619 return IIO_VAL_INT; 620 case IIO_CHAN_INFO_CALIBBIAS: 621 ret = adis_read_reg_32(&st->adis, 622 adis16550_calib_bias[idx], val); 623 if (ret) 624 return ret; 625 626 return IIO_VAL_INT; 627 case IIO_CHAN_INFO_CALIBSCALE: 628 ret = adis_read_reg_16(&st->adis, 629 adis16550_calib_scale[idx], &scale); 630 if (ret) 631 return ret; 632 633 *val = scale; 634 return IIO_VAL_INT; 635 case IIO_CHAN_INFO_SAMP_FREQ: 636 ret = adis16550_get_freq(st, &tmp); 637 if (ret) 638 return ret; 639 640 *val = tmp / 1000; 641 *val2 = (tmp % 1000) * 1000; 642 return IIO_VAL_INT_PLUS_MICRO; 643 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 644 switch (chan->type) { 645 case IIO_ANGL_VEL: 646 ret = adis16550_get_gyro_filter_freq(st, val); 647 if (ret) 648 return ret; 649 return IIO_VAL_INT; 650 case IIO_ACCEL: 651 ret = adis16550_get_accl_filter_freq(st, val); 652 if (ret) 653 return ret; 654 return IIO_VAL_INT; 655 default: 656 return -EINVAL; 657 } 658 default: 659 return -EINVAL; 660 } 661} 662 663static int adis16550_write_raw(struct iio_dev *indio_dev, 664 const struct iio_chan_spec *chan, 665 int val, int val2, long info) 666{ 667 struct adis16550 *st = iio_priv(indio_dev); 668 const int idx = chan->scan_index; 669 u32 tmp; 670 671 switch (info) { 672 case IIO_CHAN_INFO_SAMP_FREQ: 673 tmp = val * 1000 + val2 / 1000; 674 return adis16550_set_freq_hz(st, tmp); 675 case IIO_CHAN_INFO_CALIBBIAS: 676 return adis_write_reg_32(&st->adis, adis16550_calib_bias[idx], 677 val); 678 case IIO_CHAN_INFO_CALIBSCALE: 679 return adis_write_reg_16(&st->adis, adis16550_calib_scale[idx], 680 val); 681 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 682 switch (chan->type) { 683 case IIO_ANGL_VEL: 684 return adis16550_set_gyro_filter_freq(st, val); 685 case IIO_ACCEL: 686 return adis16550_set_accl_filter_freq(st, val); 687 default: 688 return -EINVAL; 689 } 690 default: 691 return -EINVAL; 692 } 693} 694 695#define ADIS16550_MOD_CHAN(_type, _mod, _address, _si) \ 696 { \ 697 .type = (_type), \ 698 .modified = 1, \ 699 .channel2 = (_mod), \ 700 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 701 BIT(IIO_CHAN_INFO_CALIBBIAS) | \ 702 BIT(IIO_CHAN_INFO_CALIBSCALE), \ 703 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 704 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 705 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 706 .address = (_address), \ 707 .scan_index = (_si), \ 708 .scan_type = { \ 709 .sign = 's', \ 710 .realbits = 32, \ 711 .storagebits = 32, \ 712 .endianness = IIO_BE, \ 713 }, \ 714 } 715 716#define ADIS16550_GYRO_CHANNEL(_mod) \ 717 ADIS16550_MOD_CHAN(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \ 718 ADIS16550_REG_ ## _mod ## _GYRO, ADIS16550_SCAN_GYRO_ ## _mod) 719 720#define ADIS16550_ACCEL_CHANNEL(_mod) \ 721 ADIS16550_MOD_CHAN(IIO_ACCEL, IIO_MOD_ ## _mod, \ 722 ADIS16550_REG_ ## _mod ## _ACCEL, ADIS16550_SCAN_ACCEL_ ## _mod) 723 724#define ADIS16550_TEMP_CHANNEL() { \ 725 .type = IIO_TEMP, \ 726 .indexed = 1, \ 727 .channel = 0, \ 728 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 729 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET), \ 730 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 731 .address = ADIS16550_REG_TEMP, \ 732 .scan_index = ADIS16550_SCAN_TEMP, \ 733 .scan_type = { \ 734 .sign = 's', \ 735 .realbits = 16, \ 736 .storagebits = 32, \ 737 .endianness = IIO_BE, \ 738 }, \ 739 } 740 741#define ADIS16550_MOD_CHAN_DELTA(_type, _mod, _address, _si) { \ 742 .type = (_type), \ 743 .modified = 1, \ 744 .channel2 = (_mod), \ 745 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 746 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 747 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 748 .address = (_address), \ 749 .scan_index = _si, \ 750 .scan_type = { \ 751 .sign = 's', \ 752 .realbits = 32, \ 753 .storagebits = 32, \ 754 .endianness = IIO_BE, \ 755 }, \ 756 } 757 758#define ADIS16550_DELTANG_CHAN(_mod) \ 759 ADIS16550_MOD_CHAN_DELTA(IIO_DELTA_ANGL, IIO_MOD_ ## _mod, \ 760 ADIS16550_REG_ ## _mod ## _DELTANG_L, ADIS16550_SCAN_DELTANG_ ## _mod) 761 762#define ADIS16550_DELTVEL_CHAN(_mod) \ 763 ADIS16550_MOD_CHAN_DELTA(IIO_DELTA_VELOCITY, IIO_MOD_ ## _mod, \ 764 ADIS16550_REG_ ## _mod ## _DELTVEL_L, ADIS16550_SCAN_DELTVEL_ ## _mod) 765 766#define ADIS16550_DELTANG_CHAN_NO_SCAN(_mod) \ 767 ADIS16550_MOD_CHAN_DELTA(IIO_DELTA_ANGL, IIO_MOD_ ## _mod, \ 768 ADIS16550_REG_ ## _mod ## _DELTANG_L, -1) 769 770#define ADIS16550_DELTVEL_CHAN_NO_SCAN(_mod) \ 771 ADIS16550_MOD_CHAN_DELTA(IIO_DELTA_VELOCITY, IIO_MOD_ ## _mod, \ 772 ADIS16550_REG_ ## _mod ## _DELTVEL_L, -1) 773 774static const struct iio_chan_spec adis16550_channels[] = { 775 ADIS16550_TEMP_CHANNEL(), 776 ADIS16550_GYRO_CHANNEL(X), 777 ADIS16550_GYRO_CHANNEL(Y), 778 ADIS16550_GYRO_CHANNEL(Z), 779 ADIS16550_ACCEL_CHANNEL(X), 780 ADIS16550_ACCEL_CHANNEL(Y), 781 ADIS16550_ACCEL_CHANNEL(Z), 782 ADIS16550_DELTANG_CHAN(X), 783 ADIS16550_DELTANG_CHAN(Y), 784 ADIS16550_DELTANG_CHAN(Z), 785 ADIS16550_DELTVEL_CHAN(X), 786 ADIS16550_DELTVEL_CHAN(Y), 787 ADIS16550_DELTVEL_CHAN(Z), 788 IIO_CHAN_SOFT_TIMESTAMP(13), 789}; 790 791static const struct adis16550_sync adis16550_sync_modes[] = { 792 { ADIS16550_SYNC_MODE_DIRECT, 3000, 4500 }, 793 { ADIS16550_SYNC_MODE_SCALED, 1, 128 }, 794}; 795 796static const struct adis16550_chip_info adis16550_chip_info = { 797 .num_channels = ARRAY_SIZE(adis16550_channels), 798 .channels = adis16550_channels, 799 .name = "adis16550", 800 .gyro_max_val = 1, 801 .gyro_max_scale = IIO_RAD_TO_DEGREE(80 << 16), 802 .accel_max_val = 1, 803 .accel_max_scale = IIO_M_S_2_TO_G(102400000), 804 .temp_scale = 4, 805 .deltang_max_val = IIO_DEGREE_TO_RAD(720), 806 .deltvel_max_val = 125, 807 .int_clk = 4000, 808 .max_dec = 4095, 809 .sync_mode = adis16550_sync_modes, 810 .num_sync = ARRAY_SIZE(adis16550_sync_modes), 811}; 812 813static u32 adis16550_validate_crc(__be32 *buffer, const u8 n_elem) 814{ 815 int i; 816 u32 crc_calc; 817 u32 crc_buf[ADIS16550_BURST_N_ELEM - 2]; 818 u32 crc = be32_to_cpu(buffer[ADIS16550_BURST_N_ELEM - 1]); 819 /* 820 * The crc calculation of the data is done in little endian. Hence, we 821 * always swap the 32bit elements making sure that the data LSB is 822 * always on address 0... 823 */ 824 for (i = 0; i < n_elem; i++) 825 crc_buf[i] = be32_to_cpu(buffer[i]); 826 827 crc_calc = crc32(~0, crc_buf, n_elem * 4); 828 crc_calc ^= ~0; 829 830 return (crc_calc == crc); 831} 832 833static irqreturn_t adis16550_trigger_handler(int irq, void *p) 834{ 835 int ret; 836 u16 dummy; 837 bool valid; 838 struct iio_poll_func *pf = p; 839 __be32 data[ADIS16550_MAX_SCAN_DATA] __aligned(8); 840 struct iio_dev *indio_dev = pf->indio_dev; 841 struct adis16550 *st = iio_priv(indio_dev); 842 struct adis *adis = iio_device_get_drvdata(indio_dev); 843 __be32 *buffer = (__be32 *)st->buffer; 844 845 ret = spi_sync(adis->spi, &adis->msg); 846 if (ret) 847 goto done; 848 /* 849 * Validate the header. The header is a normal spi reply with state 850 * vector and crc4. 851 */ 852 ret = adis16550_spi_validate(&st->adis, buffer[0], &dummy); 853 if (ret) 854 goto done; 855 856 /* the header is not included in the crc */ 857 valid = adis16550_validate_crc(buffer, ADIS16550_BURST_N_ELEM - 2); 858 if (!valid) { 859 dev_err(&adis->spi->dev, "Burst Invalid crc!\n"); 860 goto done; 861 } 862 863 /* copy the temperature together with sensor data */ 864 memcpy(data, &buffer[3], 865 (ADIS16550_SCAN_ACCEL_Z - ADIS16550_SCAN_GYRO_X + 2) * 866 sizeof(__be32)); 867 iio_push_to_buffers_with_timestamp(indio_dev, data, pf->timestamp); 868done: 869 iio_trigger_notify_done(indio_dev->trig); 870 return IRQ_HANDLED; 871} 872 873static const unsigned long adis16550_channel_masks[] = { 874 ADIS16550_BURST_DATA_GYRO_ACCEL_MASK | BIT(ADIS16550_SCAN_TEMP), 875 ADIS16550_BURST_DATA_DELTA_ANG_VEL_MASK | BIT(ADIS16550_SCAN_TEMP), 876 0 877}; 878 879static int adis16550_update_scan_mode(struct iio_dev *indio_dev, 880 const unsigned long *scan_mask) 881{ 882 u16 burst_length = ADIS16550_BURST_DATA_LEN; 883 struct adis16550 *st = iio_priv(indio_dev); 884 u8 burst_cmd; 885 u8 *tx; 886 887 memset(st->buffer, 0, burst_length + sizeof(u32)); 888 889 if (*scan_mask & ADIS16550_BURST_DATA_GYRO_ACCEL_MASK) 890 burst_cmd = ADIS16550_REG_BURST_GYRO_ACCEL; 891 else 892 burst_cmd = ADIS16550_REG_BURST_DELTA_ANG_VEL; 893 894 tx = st->buffer + burst_length; 895 tx[0] = 0x00; 896 tx[1] = 0x00; 897 tx[2] = burst_cmd; 898 /* crc4 is 0 on burst command */ 899 tx[3] = spi_crc4(get_unaligned_le32(tx)); 900 901 return 0; 902} 903 904static int adis16550_reset(struct adis *adis) 905{ 906 return __adis_write_reg_16(adis, ADIS16550_REG_COMMAND, BIT(15)); 907} 908 909static int adis16550_config_sync(struct adis16550 *st) 910{ 911 struct device *dev = &st->adis.spi->dev; 912 const struct adis16550_sync *sync_mode_data; 913 struct clk *clk; 914 int ret, i; 915 u16 mode; 916 917 clk = devm_clk_get_optional_enabled(dev, NULL); 918 if (IS_ERR(clk)) 919 return PTR_ERR(clk); 920 if (!clk) { 921 st->clk_freq_hz = st->info->int_clk * 1000; 922 return 0; 923 } 924 925 st->clk_freq_hz = clk_get_rate(clk); 926 927 for (i = 0; i < st->info->num_sync; i++) { 928 if (st->clk_freq_hz >= st->info->sync_mode[i].min_rate && 929 st->clk_freq_hz <= st->info->sync_mode[i].max_rate) { 930 sync_mode_data = &st->info->sync_mode[i]; 931 break; 932 } 933 } 934 935 if (i == st->info->num_sync) 936 return dev_err_probe(dev, -EINVAL, "Clk rate: %lu not in a valid range", 937 st->clk_freq_hz); 938 939 if (sync_mode_data->sync_mode == ADIS16550_SYNC_MODE_SCALED) { 940 u16 sync_scale; 941 /* 942 * In sps scaled sync we must scale the input clock to a range 943 * of [3000 4500]. 944 */ 945 946 sync_scale = DIV_ROUND_CLOSEST(st->info->int_clk, st->clk_freq_hz); 947 948 if (3000 > sync_scale || 4500 < sync_scale) 949 return dev_err_probe(dev, -EINVAL, 950 "Invalid value:%u for sync_scale", 951 sync_scale); 952 953 ret = adis_write_reg_16(&st->adis, ADIS16550_REG_SYNC_SCALE, 954 sync_scale); 955 if (ret) 956 return ret; 957 958 st->clk_freq_hz = st->info->int_clk; 959 } 960 961 st->clk_freq_hz *= 1000; 962 963 mode = FIELD_PREP(ADIS16550_SYNC_MODE_MASK, sync_mode_data->sync_mode) | 964 FIELD_PREP(ADIS16550_SYNC_EN_MASK, true); 965 966 return __adis_update_bits(&st->adis, ADIS16550_REG_CONFIG, 967 ADIS16550_SYNC_MASK, mode); 968} 969 970static const struct iio_info adis16550_info = { 971 .read_raw = &adis16550_read_raw, 972 .write_raw = &adis16550_write_raw, 973 .update_scan_mode = adis16550_update_scan_mode, 974 .debugfs_reg_access = adis_debugfs_reg_access, 975}; 976 977enum { 978 ADIS16550_STATUS_CRC_CODE, 979 ADIS16550_STATUS_CRC_CONFIG, 980 ADIS16550_STATUS_FLASH_UPDATE, 981 ADIS16550_STATUS_INERIAL, 982 ADIS16550_STATUS_SENSOR, 983 ADIS16550_STATUS_TEMPERATURE, 984 ADIS16550_STATUS_SPI, 985 ADIS16550_STATUS_PROCESSING, 986 ADIS16550_STATUS_POWER, 987 ADIS16550_STATUS_BOOT, 988 ADIS16550_STATUS_WATCHDOG = 15, 989 ADIS16550_STATUS_REGULATOR = 28, 990 ADIS16550_STATUS_SENSOR_SUPPLY, 991 ADIS16550_STATUS_CPU_SUPPLY, 992 ADIS16550_STATUS_5V_SUPPLY, 993}; 994 995static const char * const adis16550_status_error_msgs[] = { 996 [ADIS16550_STATUS_CRC_CODE] = "Code CRC Error", 997 [ADIS16550_STATUS_CRC_CONFIG] = "Configuration/Calibration CRC Error", 998 [ADIS16550_STATUS_FLASH_UPDATE] = "Flash Update Error", 999 [ADIS16550_STATUS_INERIAL] = "Overrange for Inertial Signals", 1000 [ADIS16550_STATUS_SENSOR] = "Sensor failure", 1001 [ADIS16550_STATUS_TEMPERATURE] = "Temperature Error", 1002 [ADIS16550_STATUS_SPI] = "SPI Communication Error", 1003 [ADIS16550_STATUS_PROCESSING] = "Processing Overrun Error", 1004 [ADIS16550_STATUS_POWER] = "Power Supply Failure", 1005 [ADIS16550_STATUS_BOOT] = "Boot Memory Failure", 1006 [ADIS16550_STATUS_WATCHDOG] = "Watchdog timer flag", 1007 [ADIS16550_STATUS_REGULATOR] = "Internal Regulator Error", 1008 [ADIS16550_STATUS_SENSOR_SUPPLY] = "Internal Sensor Supply Error.", 1009 [ADIS16550_STATUS_CPU_SUPPLY] = "Internal Processor Supply Error.", 1010 [ADIS16550_STATUS_5V_SUPPLY] = "External 5V Supply Error", 1011}; 1012 1013static const struct adis_timeout adis16550_timeouts = { 1014 .reset_ms = 1000, 1015 .sw_reset_ms = 1000, 1016 .self_test_ms = 1000, 1017}; 1018 1019static const struct adis_data adis16550_data = { 1020 .diag_stat_reg = ADIS16550_REG_STATUS, 1021 .diag_stat_size = 4, 1022 .prod_id_reg = ADIS16550_REG_PROD_ID, 1023 .prod_id = 16550, 1024 .self_test_mask = BIT(1), 1025 .self_test_reg = ADIS16550_REG_COMMAND, 1026 .cs_change_delay = 5, 1027 .unmasked_drdy = true, 1028 .status_error_msgs = adis16550_status_error_msgs, 1029 .status_error_mask = BIT(ADIS16550_STATUS_CRC_CODE) | 1030 BIT(ADIS16550_STATUS_CRC_CONFIG) | 1031 BIT(ADIS16550_STATUS_FLASH_UPDATE) | 1032 BIT(ADIS16550_STATUS_INERIAL) | 1033 BIT(ADIS16550_STATUS_SENSOR) | 1034 BIT(ADIS16550_STATUS_TEMPERATURE) | 1035 BIT(ADIS16550_STATUS_SPI) | 1036 BIT(ADIS16550_STATUS_PROCESSING) | 1037 BIT(ADIS16550_STATUS_POWER) | 1038 BIT(ADIS16550_STATUS_BOOT) | 1039 BIT(ADIS16550_STATUS_WATCHDOG) | 1040 BIT(ADIS16550_STATUS_REGULATOR) | 1041 BIT(ADIS16550_STATUS_SENSOR_SUPPLY) | 1042 BIT(ADIS16550_STATUS_CPU_SUPPLY) | 1043 BIT(ADIS16550_STATUS_5V_SUPPLY), 1044 .timeouts = &adis16550_timeouts, 1045}; 1046 1047static const struct adis_ops adis16550_ops = { 1048 .write = adis16550_spi_write, 1049 .read = adis16550_spi_read, 1050 .reset = adis16550_reset, 1051}; 1052 1053static int adis16550_probe(struct spi_device *spi) 1054{ 1055 u16 burst_length = ADIS16550_BURST_DATA_LEN; 1056 struct device *dev = &spi->dev; 1057 struct iio_dev *indio_dev; 1058 struct adis16550 *st; 1059 struct adis *adis; 1060 int ret; 1061 1062 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1063 if (!indio_dev) 1064 return -ENOMEM; 1065 1066 st = iio_priv(indio_dev); 1067 st->info = spi_get_device_match_data(spi); 1068 if (!st->info) 1069 return -EINVAL; 1070 adis = &st->adis; 1071 indio_dev->name = st->info->name; 1072 indio_dev->channels = st->info->channels; 1073 indio_dev->num_channels = st->info->num_channels; 1074 indio_dev->available_scan_masks = adis16550_channel_masks; 1075 indio_dev->info = &adis16550_info; 1076 indio_dev->modes = INDIO_DIRECT_MODE; 1077 1078 st->adis.ops = &adis16550_ops; 1079 st->xfer[0].tx_buf = st->buffer + burst_length; 1080 st->xfer[0].len = 4; 1081 st->xfer[0].cs_change = 1; 1082 st->xfer[0].delay.value = 8; 1083 st->xfer[0].delay.unit = SPI_DELAY_UNIT_USECS; 1084 st->xfer[1].rx_buf = st->buffer; 1085 st->xfer[1].len = burst_length; 1086 1087 spi_message_init_with_transfers(&adis->msg, st->xfer, 2); 1088 1089 ret = devm_regulator_get_enable(dev, "vdd"); 1090 if (ret) 1091 return dev_err_probe(dev, ret, "Failed to get vdd regulator\n"); 1092 1093 ret = adis_init(&st->adis, indio_dev, spi, &adis16550_data); 1094 if (ret) 1095 return ret; 1096 1097 ret = __adis_initial_startup(&st->adis); 1098 if (ret) 1099 return ret; 1100 1101 ret = adis16550_config_sync(st); 1102 if (ret) 1103 return ret; 1104 1105 ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev, 1106 adis16550_trigger_handler); 1107 if (ret) 1108 return ret; 1109 1110 ret = devm_iio_device_register(dev, indio_dev); 1111 if (ret) 1112 return ret; 1113 1114 adis16550_debugfs_init(indio_dev); 1115 1116 return 0; 1117} 1118 1119static const struct spi_device_id adis16550_id[] = { 1120 { "adis16550", (kernel_ulong_t)&adis16550_chip_info}, 1121 { } 1122}; 1123MODULE_DEVICE_TABLE(spi, adis16550_id); 1124 1125static const struct of_device_id adis16550_of_match[] = { 1126 { .compatible = "adi,adis16550", .data = &adis16550_chip_info }, 1127 { } 1128}; 1129MODULE_DEVICE_TABLE(of, adis16550_of_match); 1130 1131static struct spi_driver adis16550_driver = { 1132 .driver = { 1133 .name = "adis16550", 1134 .of_match_table = adis16550_of_match, 1135 }, 1136 .probe = adis16550_probe, 1137 .id_table = adis16550_id, 1138}; 1139module_spi_driver(adis16550_driver); 1140 1141MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>"); 1142MODULE_AUTHOR("Ramona Gradinariu <ramona.gradinariu@analog.com>"); 1143MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com>"); 1144MODULE_AUTHOR("Robert Budai <robert.budai@analog.com>"); 1145MODULE_DESCRIPTION("Analog Devices ADIS16550 IMU driver"); 1146MODULE_IMPORT_NS("IIO_ADISLIB"); 1147MODULE_LICENSE("GPL");
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