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adis16475.c
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linux-6.19.14/drivers/iio/imu/adis16475.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * ADIS16475 IMU driver 4 * 5 * Copyright 2019 Analog Devices Inc. 6 */ 7#include <linux/bitfield.h> 8#include <linux/bitops.h> 9#include <linux/clk.h> 10#include <linux/debugfs.h> 11#include <linux/delay.h> 12#include <linux/device.h> 13#include <linux/kernel.h> 14#include <linux/iio/buffer.h> 15#include <linux/iio/iio.h> 16#include <linux/iio/imu/adis.h> 17#include <linux/iio/sysfs.h> 18#include <linux/iio/trigger_consumer.h> 19#include <linux/irq.h> 20#include <linux/lcm.h> 21#include <linux/math.h> 22#include <linux/module.h> 23#include <linux/mod_devicetable.h> 24#include <linux/property.h> 25#include <linux/spi/spi.h> 26 27#define ADIS16475_REG_DIAG_STAT 0x02 28#define ADIS16475_REG_X_GYRO_L 0x04 29#define ADIS16475_REG_Y_GYRO_L 0x08 30#define ADIS16475_REG_Z_GYRO_L 0x0C 31#define ADIS16475_REG_X_ACCEL_L 0x10 32#define ADIS16475_REG_Y_ACCEL_L 0x14 33#define ADIS16475_REG_Z_ACCEL_L 0x18 34#define ADIS16475_REG_TEMP_OUT 0x1c 35#define ADIS16475_REG_X_DELTANG_L 0x24 36#define ADIS16475_REG_Y_DELTANG_L 0x28 37#define ADIS16475_REG_Z_DELTANG_L 0x2C 38#define ADIS16475_REG_X_DELTVEL_L 0x30 39#define ADIS16475_REG_Y_DELTVEL_L 0x34 40#define ADIS16475_REG_Z_DELTVEL_L 0x38 41#define ADIS16475_REG_X_GYRO_BIAS_L 0x40 42#define ADIS16475_REG_Y_GYRO_BIAS_L 0x44 43#define ADIS16475_REG_Z_GYRO_BIAS_L 0x48 44#define ADIS16475_REG_X_ACCEL_BIAS_L 0x4c 45#define ADIS16475_REG_Y_ACCEL_BIAS_L 0x50 46#define ADIS16475_REG_Z_ACCEL_BIAS_L 0x54 47#define ADIS16475_REG_FILT_CTRL 0x5c 48#define ADIS16475_FILT_CTRL_MASK GENMASK(2, 0) 49#define ADIS16475_FILT_CTRL(x) FIELD_PREP(ADIS16475_FILT_CTRL_MASK, x) 50#define ADIS16475_REG_MSG_CTRL 0x60 51#define ADIS16475_MSG_CTRL_DR_POL_MASK BIT(0) 52#define ADIS16475_MSG_CTRL_DR_POL(x) \ 53 FIELD_PREP(ADIS16475_MSG_CTRL_DR_POL_MASK, x) 54#define ADIS16475_SYNC_MODE_MASK GENMASK(4, 2) 55#define ADIS16475_SYNC_MODE(x) FIELD_PREP(ADIS16475_SYNC_MODE_MASK, x) 56#define ADIS16575_SYNC_4KHZ_MASK BIT(11) 57#define ADIS16575_SYNC_4KHZ(x) FIELD_PREP(ADIS16575_SYNC_4KHZ_MASK, x) 58#define ADIS16475_REG_UP_SCALE 0x62 59#define ADIS16475_REG_DEC_RATE 0x64 60#define ADIS16475_REG_GLOB_CMD 0x68 61#define ADIS16475_REG_FIRM_REV 0x6c 62#define ADIS16475_REG_FIRM_DM 0x6e 63#define ADIS16475_REG_FIRM_Y 0x70 64#define ADIS16475_REG_PROD_ID 0x72 65#define ADIS16475_REG_SERIAL_NUM 0x74 66#define ADIS16475_REG_FLASH_CNT 0x7c 67#define ADIS16500_BURST_DATA_SEL_MASK BIT(8) 68#define ADIS16500_BURST32_MASK BIT(9) 69#define ADIS16500_BURST32(x) FIELD_PREP(ADIS16500_BURST32_MASK, x) 70/* number of data elements in burst mode */ 71#define ADIS16475_BURST32_MAX_DATA_NO_TS32 32 72#define ADIS16575_BURST32_DATA_TS32 34 73#define ADIS16475_BURST_MAX_DATA 20 74#define ADIS16475_MAX_SCAN_DATA 20 75/* spi max speed in brust mode */ 76#define ADIS16475_BURST_MAX_SPEED 1000000 77#define ADIS16575_BURST_MAX_SPEED 8000000 78#define ADIS16475_LSB_DEC_MASK 0 79#define ADIS16475_LSB_FIR_MASK 1 80#define ADIS16500_BURST_DATA_SEL_0_CHN_MASK GENMASK(5, 0) 81#define ADIS16500_BURST_DATA_SEL_1_CHN_MASK GENMASK(12, 7) 82#define ADIS16575_MAX_FIFO_WM 511UL 83#define ADIS16475_REG_FIFO_CTRL 0x5A 84#define ADIS16575_WM_LVL_MASK GENMASK(15, 4) 85#define ADIS16575_WM_LVL(x) FIELD_PREP(ADIS16575_WM_LVL_MASK, x) 86#define ADIS16575_WM_POL_MASK BIT(3) 87#define ADIS16575_WM_POL(x) FIELD_PREP(ADIS16575_WM_POL_MASK, x) 88#define ADIS16575_WM_EN_MASK BIT(2) 89#define ADIS16575_WM_EN(x) FIELD_PREP(ADIS16575_WM_EN_MASK, x) 90#define ADIS16575_OVERFLOW_MASK BIT(1) 91#define ADIS16575_STOP_ENQUEUE FIELD_PREP(ADIS16575_OVERFLOW_MASK, 0) 92#define ADIS16575_OVERWRITE_OLDEST FIELD_PREP(ADIS16575_OVERFLOW_MASK, 1) 93#define ADIS16575_FIFO_EN_MASK BIT(0) 94#define ADIS16575_FIFO_EN(x) FIELD_PREP(ADIS16575_FIFO_EN_MASK, x) 95#define ADIS16575_FIFO_FLUSH_CMD BIT(5) 96#define ADIS16575_REG_FIFO_CNT 0x3C 97 98enum { 99 ADIS16475_SYNC_DIRECT = 1, 100 ADIS16475_SYNC_SCALED, 101 ADIS16475_SYNC_OUTPUT, 102 ADIS16475_SYNC_PULSE = 5, 103}; 104 105struct adis16475_sync { 106 u16 sync_mode; 107 u16 min_rate; 108 u16 max_rate; 109}; 110 111struct adis16475_chip_info { 112 const struct iio_chan_spec *channels; 113 const struct adis16475_sync *sync; 114 const struct adis_data adis_data; 115 const char *name; 116#define ADIS16475_HAS_BURST32 BIT(0) 117#define ADIS16475_HAS_BURST_DELTA_DATA BIT(1) 118#define ADIS16475_HAS_TIMESTAMP32 BIT(2) 119#define ADIS16475_NEEDS_BURST_REQUEST BIT(3) 120 const long flags; 121 u32 num_channels; 122 u32 gyro_max_val; 123 u32 gyro_max_scale; 124 u32 accel_max_val; 125 u32 accel_max_scale; 126 u32 temp_scale; 127 u32 deltang_max_val; 128 u32 deltvel_max_val; 129 u32 int_clk; 130 u16 max_dec; 131 u8 num_sync; 132}; 133 134struct adis16475 { 135 const struct adis16475_chip_info *info; 136 struct adis adis; 137 u32 clk_freq; 138 bool burst32; 139 unsigned long lsb_flag; 140 u16 sync_mode; 141 u16 fifo_watermark; 142 /* Alignment needed for the timestamp */ 143 __be16 data[ADIS16475_MAX_SCAN_DATA] __aligned(8); 144}; 145 146enum { 147 ADIS16475_SCAN_GYRO_X, 148 ADIS16475_SCAN_GYRO_Y, 149 ADIS16475_SCAN_GYRO_Z, 150 ADIS16475_SCAN_ACCEL_X, 151 ADIS16475_SCAN_ACCEL_Y, 152 ADIS16475_SCAN_ACCEL_Z, 153 ADIS16475_SCAN_TEMP, 154 ADIS16475_SCAN_DELTANG_X, 155 ADIS16475_SCAN_DELTANG_Y, 156 ADIS16475_SCAN_DELTANG_Z, 157 ADIS16475_SCAN_DELTVEL_X, 158 ADIS16475_SCAN_DELTVEL_Y, 159 ADIS16475_SCAN_DELTVEL_Z, 160}; 161 162static bool low_rate_allow; 163module_param(low_rate_allow, bool, 0444); 164MODULE_PARM_DESC(low_rate_allow, 165 "Allow IMU rates below the minimum advisable when external clk is used in SCALED mode (default: N)"); 166 167static ssize_t adis16475_show_firmware_revision(struct file *file, 168 char __user *userbuf, 169 size_t count, loff_t *ppos) 170{ 171 struct adis16475 *st = file->private_data; 172 char buf[7]; 173 size_t len; 174 u16 rev; 175 int ret; 176 177 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_REV, &rev); 178 if (ret) 179 return ret; 180 181 len = scnprintf(buf, sizeof(buf), "%x.%x\n", rev >> 8, rev & 0xff); 182 183 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 184} 185 186static const struct file_operations adis16475_firmware_revision_fops = { 187 .open = simple_open, 188 .read = adis16475_show_firmware_revision, 189 .llseek = default_llseek, 190 .owner = THIS_MODULE, 191}; 192 193static ssize_t adis16475_show_firmware_date(struct file *file, 194 char __user *userbuf, 195 size_t count, loff_t *ppos) 196{ 197 struct adis16475 *st = file->private_data; 198 u16 md, year; 199 char buf[12]; 200 size_t len; 201 int ret; 202 203 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_Y, &year); 204 if (ret) 205 return ret; 206 207 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIRM_DM, &md); 208 if (ret) 209 return ret; 210 211 len = snprintf(buf, sizeof(buf), "%.2x-%.2x-%.4x\n", md >> 8, md & 0xff, 212 year); 213 214 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 215} 216 217static const struct file_operations adis16475_firmware_date_fops = { 218 .open = simple_open, 219 .read = adis16475_show_firmware_date, 220 .llseek = default_llseek, 221 .owner = THIS_MODULE, 222}; 223 224static int adis16475_show_serial_number(void *arg, u64 *val) 225{ 226 struct adis16475 *st = arg; 227 u16 serial; 228 int ret; 229 230 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_SERIAL_NUM, &serial); 231 if (ret) 232 return ret; 233 234 *val = serial; 235 236 return 0; 237} 238DEFINE_DEBUGFS_ATTRIBUTE(adis16475_serial_number_fops, 239 adis16475_show_serial_number, NULL, "0x%.4llx\n"); 240 241static int adis16475_show_product_id(void *arg, u64 *val) 242{ 243 struct adis16475 *st = arg; 244 u16 prod_id; 245 int ret; 246 247 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_PROD_ID, &prod_id); 248 if (ret) 249 return ret; 250 251 *val = prod_id; 252 253 return 0; 254} 255DEFINE_DEBUGFS_ATTRIBUTE(adis16475_product_id_fops, 256 adis16475_show_product_id, NULL, "%llu\n"); 257 258static int adis16475_show_flash_count(void *arg, u64 *val) 259{ 260 struct adis16475 *st = arg; 261 u32 flash_count; 262 int ret; 263 264 ret = adis_read_reg_32(&st->adis, ADIS16475_REG_FLASH_CNT, 265 &flash_count); 266 if (ret) 267 return ret; 268 269 *val = flash_count; 270 271 return 0; 272} 273DEFINE_DEBUGFS_ATTRIBUTE(adis16475_flash_count_fops, 274 adis16475_show_flash_count, NULL, "%lld\n"); 275 276static void adis16475_debugfs_init(struct iio_dev *indio_dev) 277{ 278 struct adis16475 *st = iio_priv(indio_dev); 279 struct dentry *d = iio_get_debugfs_dentry(indio_dev); 280 281 if (!IS_ENABLED(CONFIG_DEBUG_FS)) 282 return; 283 284 debugfs_create_file_unsafe("serial_number", 0400, 285 d, st, &adis16475_serial_number_fops); 286 debugfs_create_file_unsafe("product_id", 0400, 287 d, st, &adis16475_product_id_fops); 288 debugfs_create_file_unsafe("flash_count", 0400, 289 d, st, &adis16475_flash_count_fops); 290 debugfs_create_file("firmware_revision", 0400, 291 d, st, &adis16475_firmware_revision_fops); 292 debugfs_create_file("firmware_date", 0400, d, 293 st, &adis16475_firmware_date_fops); 294} 295 296static int adis16475_get_freq(struct adis16475 *st, u32 *freq) 297{ 298 int ret; 299 u16 dec; 300 u32 sample_rate = st->clk_freq; 301 302 adis_dev_auto_lock(&st->adis); 303 304 if (st->sync_mode == ADIS16475_SYNC_SCALED) { 305 u16 sync_scale; 306 307 ret = __adis_read_reg_16(&st->adis, ADIS16475_REG_UP_SCALE, &sync_scale); 308 if (ret) 309 return ret; 310 311 sample_rate = st->clk_freq * sync_scale; 312 } 313 314 ret = __adis_read_reg_16(&st->adis, ADIS16475_REG_DEC_RATE, &dec); 315 if (ret) 316 return ret; 317 318 *freq = DIV_ROUND_CLOSEST(sample_rate, dec + 1); 319 320 return 0; 321} 322 323static int adis16475_set_freq(struct adis16475 *st, const u32 freq) 324{ 325 u16 dec; 326 int ret; 327 u32 sample_rate = st->clk_freq; 328 /* The optimal sample rate for the supported IMUs is between int_clk - 100 and int_clk + 100. */ 329 u32 max_sample_rate = st->info->int_clk * 1000 + 100000; 330 u32 min_sample_rate = st->info->int_clk * 1000 - 100000; 331 332 if (!freq) 333 return -EINVAL; 334 335 adis_dev_auto_lock(&st->adis); 336 /* 337 * When using sync scaled mode, the input clock needs to be scaled so that we have 338 * an IMU sample rate between (optimally) int_clk - 100 and int_clk + 100. 339 * After this, we can use the decimation filter to lower the sampling rate in order 340 * to get what the user wants. 341 * Optimally, the user sample rate is a multiple of both the IMU sample rate and 342 * the input clock. Hence, calculating the sync_scale dynamically gives us better 343 * chances of achieving a perfect/integer value for DEC_RATE. The math here is: 344 * 1. lcm of the input clock and the desired output rate. 345 * 2. get the highest multiple of the previous result lower than the adis max rate. 346 * 3. The last result becomes the IMU sample rate. Use that to calculate SYNC_SCALE 347 * and DEC_RATE (to get the user output rate) 348 */ 349 if (st->sync_mode == ADIS16475_SYNC_SCALED) { 350 unsigned long scaled_rate = lcm(st->clk_freq, freq); 351 int sync_scale; 352 353 /* 354 * If lcm is bigger than the IMU maximum sampling rate there's no perfect 355 * solution. In this case, we get the highest multiple of the input clock 356 * lower than the IMU max sample rate. 357 */ 358 if (scaled_rate > max_sample_rate) 359 scaled_rate = max_sample_rate / st->clk_freq * st->clk_freq; 360 else 361 scaled_rate = max_sample_rate / scaled_rate * scaled_rate; 362 363 /* 364 * This is not an hard requirement but it's not advised to run the IMU 365 * with a sample rate lower than internal clock frequency, due to possible 366 * undersampling issues. However, there are users that might really want 367 * to take the risk. Hence, we provide a module parameter for them. If set, 368 * we allow sample rates lower than internal clock frequency. 369 * By default, we won't allow this and we just roundup the rate to the next 370 * multiple of the input clock. This is done like this as in some cases 371 * (when DEC_RATE is 0) might give us the closest value to the one desired 372 * by the user... 373 */ 374 if (scaled_rate < min_sample_rate && !low_rate_allow) 375 scaled_rate = roundup(min_sample_rate, st->clk_freq); 376 377 sync_scale = scaled_rate / st->clk_freq; 378 ret = __adis_write_reg_16(&st->adis, ADIS16475_REG_UP_SCALE, sync_scale); 379 if (ret) 380 return ret; 381 382 sample_rate = scaled_rate; 383 } 384 385 dec = DIV_ROUND_CLOSEST(sample_rate, freq); 386 387 if (dec) 388 dec--; 389 390 if (dec > st->info->max_dec) 391 dec = st->info->max_dec; 392 393 ret = __adis_write_reg_16(&st->adis, ADIS16475_REG_DEC_RATE, dec); 394 if (ret) 395 return ret; 396 397 /* 398 * If decimation is used, then gyro and accel data will have meaningful 399 * bits on the LSB registers. This info is used on the trigger handler. 400 */ 401 assign_bit(ADIS16475_LSB_DEC_MASK, &st->lsb_flag, dec); 402 403 return 0; 404} 405 406/* The values are approximated. */ 407static const u32 adis16475_3db_freqs[] = { 408 [0] = 720, /* Filter disabled, full BW (~720Hz) */ 409 [1] = 360, 410 [2] = 164, 411 [3] = 80, 412 [4] = 40, 413 [5] = 20, 414 [6] = 10, 415}; 416 417static int adis16475_get_filter(struct adis16475 *st, u32 *filter) 418{ 419 u16 filter_sz; 420 int ret; 421 const int mask = ADIS16475_FILT_CTRL_MASK; 422 423 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FILT_CTRL, &filter_sz); 424 if (ret) 425 return ret; 426 427 *filter = adis16475_3db_freqs[filter_sz & mask]; 428 429 return 0; 430} 431 432static int adis16475_set_filter(struct adis16475 *st, const u32 filter) 433{ 434 int i = ARRAY_SIZE(adis16475_3db_freqs); 435 int ret; 436 437 while (--i) { 438 if (adis16475_3db_freqs[i] >= filter) 439 break; 440 } 441 442 ret = adis_write_reg_16(&st->adis, ADIS16475_REG_FILT_CTRL, 443 ADIS16475_FILT_CTRL(i)); 444 if (ret) 445 return ret; 446 447 /* 448 * If FIR is used, then gyro and accel data will have meaningful 449 * bits on the LSB registers. This info is used on the trigger handler. 450 */ 451 assign_bit(ADIS16475_LSB_FIR_MASK, &st->lsb_flag, i); 452 453 return 0; 454} 455 456static ssize_t adis16475_get_fifo_enabled(struct device *dev, 457 struct device_attribute *attr, 458 char *buf) 459{ 460 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 461 struct adis16475 *st = iio_priv(indio_dev); 462 int ret; 463 u16 val; 464 465 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIFO_CTRL, &val); 466 if (ret) 467 return ret; 468 469 return sysfs_emit(buf, "%lu\n", FIELD_GET(ADIS16575_FIFO_EN_MASK, val)); 470} 471 472static ssize_t adis16475_get_fifo_watermark(struct device *dev, 473 struct device_attribute *attr, 474 char *buf) 475{ 476 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 477 struct adis16475 *st = iio_priv(indio_dev); 478 int ret; 479 u16 val; 480 481 ret = adis_read_reg_16(&st->adis, ADIS16475_REG_FIFO_CTRL, &val); 482 if (ret) 483 return ret; 484 485 return sysfs_emit(buf, "%lu\n", FIELD_GET(ADIS16575_WM_LVL_MASK, val) + 1); 486} 487 488static ssize_t hwfifo_watermark_min_show(struct device *dev, 489 struct device_attribute *attr, 490 char *buf) 491{ 492 return sysfs_emit(buf, "1\n"); 493} 494 495static ssize_t hwfifo_watermark_max_show(struct device *dev, 496 struct device_attribute *attr, 497 char *buf) 498{ 499 return sysfs_emit(buf, "%lu\n", ADIS16575_MAX_FIFO_WM); 500} 501 502static IIO_DEVICE_ATTR_RO(hwfifo_watermark_min, 0); 503static IIO_DEVICE_ATTR_RO(hwfifo_watermark_max, 0); 504static IIO_DEVICE_ATTR(hwfifo_watermark, 0444, 505 adis16475_get_fifo_watermark, NULL, 0); 506static IIO_DEVICE_ATTR(hwfifo_enabled, 0444, 507 adis16475_get_fifo_enabled, NULL, 0); 508 509static const struct iio_dev_attr *adis16475_fifo_attributes[] = { 510 &iio_dev_attr_hwfifo_watermark_min, 511 &iio_dev_attr_hwfifo_watermark_max, 512 &iio_dev_attr_hwfifo_watermark, 513 &iio_dev_attr_hwfifo_enabled, 514 NULL 515}; 516 517static int adis16475_buffer_postenable(struct iio_dev *indio_dev) 518{ 519 struct adis16475 *st = iio_priv(indio_dev); 520 struct adis *adis = &st->adis; 521 522 return adis_update_bits(adis, ADIS16475_REG_FIFO_CTRL, 523 ADIS16575_FIFO_EN_MASK, (u16)ADIS16575_FIFO_EN(1)); 524} 525 526static int adis16475_buffer_postdisable(struct iio_dev *indio_dev) 527{ 528 struct adis16475 *st = iio_priv(indio_dev); 529 struct adis *adis = &st->adis; 530 int ret; 531 532 adis_dev_auto_lock(&st->adis); 533 534 ret = __adis_update_bits(adis, ADIS16475_REG_FIFO_CTRL, 535 ADIS16575_FIFO_EN_MASK, (u16)ADIS16575_FIFO_EN(0)); 536 if (ret) 537 return ret; 538 539 return __adis_write_reg_16(adis, ADIS16475_REG_GLOB_CMD, 540 ADIS16575_FIFO_FLUSH_CMD); 541} 542 543static const struct iio_buffer_setup_ops adis16475_buffer_ops = { 544 .postenable = adis16475_buffer_postenable, 545 .postdisable = adis16475_buffer_postdisable, 546}; 547 548static int adis16475_set_watermark(struct iio_dev *indio_dev, unsigned int val) 549{ 550 struct adis16475 *st = iio_priv(indio_dev); 551 int ret; 552 u16 wm_lvl; 553 554 adis_dev_auto_lock(&st->adis); 555 556 val = min_t(unsigned int, val, ADIS16575_MAX_FIFO_WM); 557 558 wm_lvl = ADIS16575_WM_LVL(val - 1); 559 ret = __adis_update_bits(&st->adis, ADIS16475_REG_FIFO_CTRL, ADIS16575_WM_LVL_MASK, wm_lvl); 560 if (ret) 561 return ret; 562 563 st->fifo_watermark = val; 564 565 return 0; 566} 567 568static const u32 adis16475_calib_regs[] = { 569 [ADIS16475_SCAN_GYRO_X] = ADIS16475_REG_X_GYRO_BIAS_L, 570 [ADIS16475_SCAN_GYRO_Y] = ADIS16475_REG_Y_GYRO_BIAS_L, 571 [ADIS16475_SCAN_GYRO_Z] = ADIS16475_REG_Z_GYRO_BIAS_L, 572 [ADIS16475_SCAN_ACCEL_X] = ADIS16475_REG_X_ACCEL_BIAS_L, 573 [ADIS16475_SCAN_ACCEL_Y] = ADIS16475_REG_Y_ACCEL_BIAS_L, 574 [ADIS16475_SCAN_ACCEL_Z] = ADIS16475_REG_Z_ACCEL_BIAS_L, 575}; 576 577static int adis16475_read_raw(struct iio_dev *indio_dev, 578 const struct iio_chan_spec *chan, 579 int *val, int *val2, long info) 580{ 581 struct adis16475 *st = iio_priv(indio_dev); 582 int ret; 583 u32 tmp; 584 585 switch (info) { 586 case IIO_CHAN_INFO_RAW: 587 return adis_single_conversion(indio_dev, chan, 0, val); 588 case IIO_CHAN_INFO_SCALE: 589 switch (chan->type) { 590 case IIO_ANGL_VEL: 591 *val = st->info->gyro_max_val; 592 *val2 = st->info->gyro_max_scale; 593 return IIO_VAL_FRACTIONAL; 594 case IIO_ACCEL: 595 *val = st->info->accel_max_val; 596 *val2 = st->info->accel_max_scale; 597 return IIO_VAL_FRACTIONAL; 598 case IIO_TEMP: 599 *val = st->info->temp_scale; 600 return IIO_VAL_INT; 601 case IIO_DELTA_ANGL: 602 *val = st->info->deltang_max_val; 603 *val2 = 31; 604 return IIO_VAL_FRACTIONAL_LOG2; 605 case IIO_DELTA_VELOCITY: 606 *val = st->info->deltvel_max_val; 607 *val2 = 31; 608 return IIO_VAL_FRACTIONAL_LOG2; 609 default: 610 return -EINVAL; 611 } 612 case IIO_CHAN_INFO_CALIBBIAS: 613 ret = adis_read_reg_32(&st->adis, 614 adis16475_calib_regs[chan->scan_index], 615 val); 616 if (ret) 617 return ret; 618 619 return IIO_VAL_INT; 620 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 621 ret = adis16475_get_filter(st, val); 622 if (ret) 623 return ret; 624 625 return IIO_VAL_INT; 626 case IIO_CHAN_INFO_SAMP_FREQ: 627 ret = adis16475_get_freq(st, &tmp); 628 if (ret) 629 return ret; 630 631 *val = tmp / 1000; 632 *val2 = (tmp % 1000) * 1000; 633 return IIO_VAL_INT_PLUS_MICRO; 634 default: 635 return -EINVAL; 636 } 637} 638 639static int adis16475_write_raw(struct iio_dev *indio_dev, 640 const struct iio_chan_spec *chan, 641 int val, int val2, long info) 642{ 643 struct adis16475 *st = iio_priv(indio_dev); 644 u32 tmp; 645 646 switch (info) { 647 case IIO_CHAN_INFO_SAMP_FREQ: 648 tmp = val * 1000 + val2 / 1000; 649 return adis16475_set_freq(st, tmp); 650 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 651 return adis16475_set_filter(st, val); 652 case IIO_CHAN_INFO_CALIBBIAS: 653 return adis_write_reg_32(&st->adis, 654 adis16475_calib_regs[chan->scan_index], 655 val); 656 default: 657 return -EINVAL; 658 } 659} 660 661#define ADIS16475_MOD_CHAN(_type, _mod, _address, _si, _r_bits, _s_bits) \ 662 { \ 663 .type = (_type), \ 664 .modified = 1, \ 665 .channel2 = (_mod), \ 666 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 667 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 668 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 669 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 670 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 671 .address = (_address), \ 672 .scan_index = (_si), \ 673 .scan_type = { \ 674 .sign = 's', \ 675 .realbits = (_r_bits), \ 676 .storagebits = (_s_bits), \ 677 .endianness = IIO_BE, \ 678 }, \ 679 } 680 681#define ADIS16475_GYRO_CHANNEL(_mod) \ 682 ADIS16475_MOD_CHAN(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \ 683 ADIS16475_REG_ ## _mod ## _GYRO_L, \ 684 ADIS16475_SCAN_GYRO_ ## _mod, 32, 32) 685 686#define ADIS16475_ACCEL_CHANNEL(_mod) \ 687 ADIS16475_MOD_CHAN(IIO_ACCEL, IIO_MOD_ ## _mod, \ 688 ADIS16475_REG_ ## _mod ## _ACCEL_L, \ 689 ADIS16475_SCAN_ACCEL_ ## _mod, 32, 32) 690 691#define ADIS16475_TEMP_CHANNEL() { \ 692 .type = IIO_TEMP, \ 693 .indexed = 1, \ 694 .channel = 0, \ 695 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 696 BIT(IIO_CHAN_INFO_SCALE), \ 697 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 698 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 699 .address = ADIS16475_REG_TEMP_OUT, \ 700 .scan_index = ADIS16475_SCAN_TEMP, \ 701 .scan_type = { \ 702 .sign = 's', \ 703 .realbits = 16, \ 704 .storagebits = 16, \ 705 .endianness = IIO_BE, \ 706 }, \ 707 } 708 709#define ADIS16475_MOD_CHAN_DELTA(_type, _mod, _address, _si, _r_bits, _s_bits) { \ 710 .type = (_type), \ 711 .modified = 1, \ 712 .channel2 = (_mod), \ 713 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 714 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 715 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 716 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 717 .address = (_address), \ 718 .scan_index = _si, \ 719 .scan_type = { \ 720 .sign = 's', \ 721 .realbits = (_r_bits), \ 722 .storagebits = (_s_bits), \ 723 .endianness = IIO_BE, \ 724 }, \ 725 } 726 727#define ADIS16475_DELTANG_CHAN(_mod) \ 728 ADIS16475_MOD_CHAN_DELTA(IIO_DELTA_ANGL, IIO_MOD_ ## _mod, \ 729 ADIS16475_REG_ ## _mod ## _DELTANG_L, ADIS16475_SCAN_DELTANG_ ## _mod, 32, 32) 730 731#define ADIS16475_DELTVEL_CHAN(_mod) \ 732 ADIS16475_MOD_CHAN_DELTA(IIO_DELTA_VELOCITY, IIO_MOD_ ## _mod, \ 733 ADIS16475_REG_ ## _mod ## _DELTVEL_L, ADIS16475_SCAN_DELTVEL_ ## _mod, 32, 32) 734 735#define ADIS16475_DELTANG_CHAN_NO_SCAN(_mod) \ 736 ADIS16475_MOD_CHAN_DELTA(IIO_DELTA_ANGL, IIO_MOD_ ## _mod, \ 737 ADIS16475_REG_ ## _mod ## _DELTANG_L, -1, 32, 32) 738 739#define ADIS16475_DELTVEL_CHAN_NO_SCAN(_mod) \ 740 ADIS16475_MOD_CHAN_DELTA(IIO_DELTA_VELOCITY, IIO_MOD_ ## _mod, \ 741 ADIS16475_REG_ ## _mod ## _DELTVEL_L, -1, 32, 32) 742 743static const struct iio_chan_spec adis16477_channels[] = { 744 ADIS16475_GYRO_CHANNEL(X), 745 ADIS16475_GYRO_CHANNEL(Y), 746 ADIS16475_GYRO_CHANNEL(Z), 747 ADIS16475_ACCEL_CHANNEL(X), 748 ADIS16475_ACCEL_CHANNEL(Y), 749 ADIS16475_ACCEL_CHANNEL(Z), 750 ADIS16475_TEMP_CHANNEL(), 751 ADIS16475_DELTANG_CHAN(X), 752 ADIS16475_DELTANG_CHAN(Y), 753 ADIS16475_DELTANG_CHAN(Z), 754 ADIS16475_DELTVEL_CHAN(X), 755 ADIS16475_DELTVEL_CHAN(Y), 756 ADIS16475_DELTVEL_CHAN(Z), 757 IIO_CHAN_SOFT_TIMESTAMP(13) 758}; 759 760static const struct iio_chan_spec adis16475_channels[] = { 761 ADIS16475_GYRO_CHANNEL(X), 762 ADIS16475_GYRO_CHANNEL(Y), 763 ADIS16475_GYRO_CHANNEL(Z), 764 ADIS16475_ACCEL_CHANNEL(X), 765 ADIS16475_ACCEL_CHANNEL(Y), 766 ADIS16475_ACCEL_CHANNEL(Z), 767 ADIS16475_TEMP_CHANNEL(), 768 ADIS16475_DELTANG_CHAN_NO_SCAN(X), 769 ADIS16475_DELTANG_CHAN_NO_SCAN(Y), 770 ADIS16475_DELTANG_CHAN_NO_SCAN(Z), 771 ADIS16475_DELTVEL_CHAN_NO_SCAN(X), 772 ADIS16475_DELTVEL_CHAN_NO_SCAN(Y), 773 ADIS16475_DELTVEL_CHAN_NO_SCAN(Z), 774 IIO_CHAN_SOFT_TIMESTAMP(7) 775}; 776 777static const struct iio_chan_spec adis16575_channels[] = { 778 ADIS16475_GYRO_CHANNEL(X), 779 ADIS16475_GYRO_CHANNEL(Y), 780 ADIS16475_GYRO_CHANNEL(Z), 781 ADIS16475_ACCEL_CHANNEL(X), 782 ADIS16475_ACCEL_CHANNEL(Y), 783 ADIS16475_ACCEL_CHANNEL(Z), 784 ADIS16475_TEMP_CHANNEL(), 785 ADIS16475_DELTANG_CHAN(X), 786 ADIS16475_DELTANG_CHAN(Y), 787 ADIS16475_DELTANG_CHAN(Z), 788 ADIS16475_DELTVEL_CHAN(X), 789 ADIS16475_DELTVEL_CHAN(Y), 790 ADIS16475_DELTVEL_CHAN(Z), 791}; 792 793enum adis16475_variant { 794 ADIS16470, 795 ADIS16475_1, 796 ADIS16475_2, 797 ADIS16475_3, 798 ADIS16477_1, 799 ADIS16477_2, 800 ADIS16477_3, 801 ADIS16465_1, 802 ADIS16465_2, 803 ADIS16465_3, 804 ADIS16467_1, 805 ADIS16467_2, 806 ADIS16467_3, 807 ADIS16500, 808 ADIS16501, 809 ADIS16505_1, 810 ADIS16505_2, 811 ADIS16505_3, 812 ADIS16507_1, 813 ADIS16507_2, 814 ADIS16507_3, 815 ADIS16575_2, 816 ADIS16575_3, 817 ADIS16576_2, 818 ADIS16576_3, 819 ADIS16577_2, 820 ADIS16577_3, 821}; 822 823enum { 824 ADIS16475_DIAG_STAT_DATA_PATH = 1, 825 ADIS16475_DIAG_STAT_FLASH_MEM, 826 ADIS16475_DIAG_STAT_SPI, 827 ADIS16475_DIAG_STAT_STANDBY, 828 ADIS16475_DIAG_STAT_SENSOR, 829 ADIS16475_DIAG_STAT_MEMORY, 830 ADIS16475_DIAG_STAT_CLK, 831}; 832 833static const char * const adis16475_status_error_msgs[] = { 834 [ADIS16475_DIAG_STAT_DATA_PATH] = "Data Path Overrun", 835 [ADIS16475_DIAG_STAT_FLASH_MEM] = "Flash memory update failure", 836 [ADIS16475_DIAG_STAT_SPI] = "SPI communication error", 837 [ADIS16475_DIAG_STAT_STANDBY] = "Standby mode", 838 [ADIS16475_DIAG_STAT_SENSOR] = "Sensor failure", 839 [ADIS16475_DIAG_STAT_MEMORY] = "Memory failure", 840 [ADIS16475_DIAG_STAT_CLK] = "Clock error", 841}; 842 843#define ADIS16475_DATA(_prod_id, _timeouts, _burst_max_len, _burst_max_speed_hz, _has_fifo) \ 844{ \ 845 .msc_ctrl_reg = ADIS16475_REG_MSG_CTRL, \ 846 .glob_cmd_reg = ADIS16475_REG_GLOB_CMD, \ 847 .diag_stat_reg = ADIS16475_REG_DIAG_STAT, \ 848 .prod_id_reg = ADIS16475_REG_PROD_ID, \ 849 .prod_id = (_prod_id), \ 850 .self_test_mask = BIT(2), \ 851 .self_test_reg = ADIS16475_REG_GLOB_CMD, \ 852 .cs_change_delay = 16, \ 853 .read_delay = 5, \ 854 .write_delay = 5, \ 855 .status_error_msgs = adis16475_status_error_msgs, \ 856 .status_error_mask = BIT(ADIS16475_DIAG_STAT_DATA_PATH) | \ 857 BIT(ADIS16475_DIAG_STAT_FLASH_MEM) | \ 858 BIT(ADIS16475_DIAG_STAT_SPI) | \ 859 BIT(ADIS16475_DIAG_STAT_STANDBY) | \ 860 BIT(ADIS16475_DIAG_STAT_SENSOR) | \ 861 BIT(ADIS16475_DIAG_STAT_MEMORY) | \ 862 BIT(ADIS16475_DIAG_STAT_CLK), \ 863 .unmasked_drdy = true, \ 864 .has_fifo = _has_fifo, \ 865 .timeouts = (_timeouts), \ 866 .burst_reg_cmd = ADIS16475_REG_GLOB_CMD, \ 867 .burst_len = ADIS16475_BURST_MAX_DATA, \ 868 .burst_max_len = _burst_max_len, \ 869 .burst_max_speed_hz = _burst_max_speed_hz \ 870} 871 872static const struct adis16475_sync adis16475_sync_mode[] = { 873 { ADIS16475_SYNC_OUTPUT }, 874 { ADIS16475_SYNC_DIRECT, 1900, 2100 }, 875 { ADIS16475_SYNC_SCALED, 1, 128 }, 876 { ADIS16475_SYNC_PULSE, 1000, 2100 }, 877}; 878 879static const struct adis16475_sync adis16575_sync_mode[] = { 880 { ADIS16475_SYNC_OUTPUT }, 881 { ADIS16475_SYNC_DIRECT, 1900, 4100 }, 882 { ADIS16475_SYNC_SCALED, 1, 400 }, 883}; 884 885static const struct adis_timeout adis16475_timeouts = { 886 .reset_ms = 200, 887 .sw_reset_ms = 200, 888 .self_test_ms = 20, 889}; 890 891static const struct adis_timeout adis1650x_timeouts = { 892 .reset_ms = 260, 893 .sw_reset_ms = 260, 894 .self_test_ms = 30, 895}; 896 897static const struct adis16475_chip_info adis16475_chip_info[] = { 898 [ADIS16470] = { 899 .name = "adis16470", 900 .num_channels = ARRAY_SIZE(adis16475_channels), 901 .channels = adis16475_channels, 902 .gyro_max_val = 1, 903 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 904 .accel_max_val = 1, 905 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 906 .temp_scale = 100, 907 .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 908 .deltvel_max_val = 400, 909 .int_clk = 2000, 910 .max_dec = 1999, 911 .sync = adis16475_sync_mode, 912 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 913 .adis_data = ADIS16475_DATA(16470, &adis16475_timeouts, 914 ADIS16475_BURST32_MAX_DATA_NO_TS32, 915 ADIS16475_BURST_MAX_SPEED, false), 916 }, 917 [ADIS16475_1] = { 918 .name = "adis16475-1", 919 .num_channels = ARRAY_SIZE(adis16475_channels), 920 .channels = adis16475_channels, 921 .gyro_max_val = 1, 922 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 923 .accel_max_val = 1, 924 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 925 .temp_scale = 100, 926 .deltang_max_val = IIO_DEGREE_TO_RAD(360), 927 .deltvel_max_val = 100, 928 .int_clk = 2000, 929 .max_dec = 1999, 930 .sync = adis16475_sync_mode, 931 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 932 .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts, 933 ADIS16475_BURST32_MAX_DATA_NO_TS32, 934 ADIS16475_BURST_MAX_SPEED, false), 935 }, 936 [ADIS16475_2] = { 937 .name = "adis16475-2", 938 .num_channels = ARRAY_SIZE(adis16475_channels), 939 .channels = adis16475_channels, 940 .gyro_max_val = 1, 941 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 942 .accel_max_val = 1, 943 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 944 .temp_scale = 100, 945 .deltang_max_val = IIO_DEGREE_TO_RAD(720), 946 .deltvel_max_val = 100, 947 .int_clk = 2000, 948 .max_dec = 1999, 949 .sync = adis16475_sync_mode, 950 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 951 .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts, 952 ADIS16475_BURST32_MAX_DATA_NO_TS32, 953 ADIS16475_BURST_MAX_SPEED, false), 954 }, 955 [ADIS16475_3] = { 956 .name = "adis16475-3", 957 .num_channels = ARRAY_SIZE(adis16475_channels), 958 .channels = adis16475_channels, 959 .gyro_max_val = 1, 960 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 961 .accel_max_val = 1, 962 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 963 .temp_scale = 100, 964 .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 965 .deltvel_max_val = 100, 966 .int_clk = 2000, 967 .max_dec = 1999, 968 .sync = adis16475_sync_mode, 969 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 970 .adis_data = ADIS16475_DATA(16475, &adis16475_timeouts, 971 ADIS16475_BURST32_MAX_DATA_NO_TS32, 972 ADIS16475_BURST_MAX_SPEED, false), 973 }, 974 [ADIS16477_1] = { 975 .name = "adis16477-1", 976 .num_channels = ARRAY_SIZE(adis16477_channels), 977 .channels = adis16477_channels, 978 .gyro_max_val = 1, 979 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 980 .accel_max_val = 1, 981 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 982 .temp_scale = 100, 983 .deltang_max_val = IIO_DEGREE_TO_RAD(360), 984 .deltvel_max_val = 400, 985 .int_clk = 2000, 986 .max_dec = 1999, 987 .sync = adis16475_sync_mode, 988 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 989 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 990 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts, 991 ADIS16475_BURST32_MAX_DATA_NO_TS32, 992 ADIS16475_BURST_MAX_SPEED, false), 993 }, 994 [ADIS16477_2] = { 995 .name = "adis16477-2", 996 .num_channels = ARRAY_SIZE(adis16477_channels), 997 .channels = adis16477_channels, 998 .gyro_max_val = 1, 999 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 1000 .accel_max_val = 1, 1001 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 1002 .temp_scale = 100, 1003 .deltang_max_val = IIO_DEGREE_TO_RAD(720), 1004 .deltvel_max_val = 400, 1005 .int_clk = 2000, 1006 .max_dec = 1999, 1007 .sync = adis16475_sync_mode, 1008 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 1009 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 1010 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts, 1011 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1012 ADIS16475_BURST_MAX_SPEED, false), 1013 }, 1014 [ADIS16477_3] = { 1015 .name = "adis16477-3", 1016 .num_channels = ARRAY_SIZE(adis16477_channels), 1017 .channels = adis16477_channels, 1018 .gyro_max_val = 1, 1019 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 1020 .accel_max_val = 1, 1021 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 1022 .temp_scale = 100, 1023 .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 1024 .deltvel_max_val = 400, 1025 .int_clk = 2000, 1026 .max_dec = 1999, 1027 .sync = adis16475_sync_mode, 1028 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 1029 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 1030 .adis_data = ADIS16475_DATA(16477, &adis16475_timeouts, 1031 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1032 ADIS16475_BURST_MAX_SPEED, false), 1033 }, 1034 [ADIS16465_1] = { 1035 .name = "adis16465-1", 1036 .num_channels = ARRAY_SIZE(adis16475_channels), 1037 .channels = adis16475_channels, 1038 .gyro_max_val = 1, 1039 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 1040 .accel_max_val = 1, 1041 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 1042 .temp_scale = 100, 1043 .deltang_max_val = IIO_DEGREE_TO_RAD(360), 1044 .deltvel_max_val = 100, 1045 .int_clk = 2000, 1046 .max_dec = 1999, 1047 .sync = adis16475_sync_mode, 1048 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 1049 .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts, 1050 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1051 ADIS16475_BURST_MAX_SPEED, false), 1052 }, 1053 [ADIS16465_2] = { 1054 .name = "adis16465-2", 1055 .num_channels = ARRAY_SIZE(adis16475_channels), 1056 .channels = adis16475_channels, 1057 .gyro_max_val = 1, 1058 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 1059 .accel_max_val = 1, 1060 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 1061 .temp_scale = 100, 1062 .deltang_max_val = IIO_DEGREE_TO_RAD(720), 1063 .deltvel_max_val = 100, 1064 .int_clk = 2000, 1065 .max_dec = 1999, 1066 .sync = adis16475_sync_mode, 1067 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 1068 .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts, 1069 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1070 ADIS16475_BURST_MAX_SPEED, false), 1071 }, 1072 [ADIS16465_3] = { 1073 .name = "adis16465-3", 1074 .num_channels = ARRAY_SIZE(adis16475_channels), 1075 .channels = adis16475_channels, 1076 .gyro_max_val = 1, 1077 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 1078 .accel_max_val = 1, 1079 .accel_max_scale = IIO_M_S_2_TO_G(4000 << 16), 1080 .temp_scale = 100, 1081 .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 1082 .deltvel_max_val = 100, 1083 .int_clk = 2000, 1084 .max_dec = 1999, 1085 .sync = adis16475_sync_mode, 1086 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 1087 .adis_data = ADIS16475_DATA(16465, &adis16475_timeouts, 1088 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1089 ADIS16475_BURST_MAX_SPEED, false), 1090 }, 1091 [ADIS16467_1] = { 1092 .name = "adis16467-1", 1093 .num_channels = ARRAY_SIZE(adis16475_channels), 1094 .channels = adis16475_channels, 1095 .gyro_max_val = 1, 1096 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 1097 .accel_max_val = 1, 1098 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 1099 .temp_scale = 100, 1100 .deltang_max_val = IIO_DEGREE_TO_RAD(360), 1101 .deltvel_max_val = 400, 1102 .int_clk = 2000, 1103 .max_dec = 1999, 1104 .sync = adis16475_sync_mode, 1105 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 1106 .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts, 1107 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1108 ADIS16475_BURST_MAX_SPEED, false), 1109 }, 1110 [ADIS16467_2] = { 1111 .name = "adis16467-2", 1112 .num_channels = ARRAY_SIZE(adis16475_channels), 1113 .channels = adis16475_channels, 1114 .gyro_max_val = 1, 1115 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 1116 .accel_max_val = 1, 1117 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 1118 .temp_scale = 100, 1119 .deltang_max_val = IIO_DEGREE_TO_RAD(720), 1120 .deltvel_max_val = 400, 1121 .int_clk = 2000, 1122 .max_dec = 1999, 1123 .sync = adis16475_sync_mode, 1124 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 1125 .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts, 1126 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1127 ADIS16475_BURST_MAX_SPEED, false), 1128 }, 1129 [ADIS16467_3] = { 1130 .name = "adis16467-3", 1131 .num_channels = ARRAY_SIZE(adis16475_channels), 1132 .channels = adis16475_channels, 1133 .gyro_max_val = 1, 1134 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 1135 .accel_max_val = 1, 1136 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 1137 .temp_scale = 100, 1138 .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 1139 .deltvel_max_val = 400, 1140 .int_clk = 2000, 1141 .max_dec = 1999, 1142 .sync = adis16475_sync_mode, 1143 .num_sync = ARRAY_SIZE(adis16475_sync_mode), 1144 .adis_data = ADIS16475_DATA(16467, &adis16475_timeouts, 1145 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1146 ADIS16475_BURST_MAX_SPEED, false), 1147 }, 1148 [ADIS16500] = { 1149 .name = "adis16500", 1150 .num_channels = ARRAY_SIZE(adis16477_channels), 1151 .channels = adis16477_channels, 1152 .gyro_max_val = 1, 1153 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 1154 .accel_max_val = 392, 1155 .accel_max_scale = 32000 << 16, 1156 .temp_scale = 100, 1157 .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 1158 .deltvel_max_val = 400, 1159 .int_clk = 2000, 1160 .max_dec = 1999, 1161 .sync = adis16475_sync_mode, 1162 /* pulse sync not supported */ 1163 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 1164 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 1165 .adis_data = ADIS16475_DATA(16500, &adis1650x_timeouts, 1166 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1167 ADIS16475_BURST_MAX_SPEED, false), 1168 }, 1169 [ADIS16501] = { 1170 .name = "adis16501", 1171 .num_channels = ARRAY_SIZE(adis16477_channels), 1172 .channels = adis16477_channels, 1173 .gyro_max_val = 1, 1174 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 1175 .accel_max_val = 1, 1176 .accel_max_scale = IIO_M_S_2_TO_G(800 << 16), 1177 .temp_scale = 100, 1178 .deltang_max_val = IIO_DEGREE_TO_RAD(720), 1179 .deltvel_max_val = 125, 1180 .int_clk = 2000, 1181 .max_dec = 1999, 1182 .sync = adis16475_sync_mode, 1183 /* pulse sync not supported */ 1184 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 1185 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 1186 .adis_data = ADIS16475_DATA(16501, &adis1650x_timeouts, 1187 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1188 ADIS16475_BURST_MAX_SPEED, false), 1189 }, 1190 [ADIS16505_1] = { 1191 .name = "adis16505-1", 1192 .num_channels = ARRAY_SIZE(adis16477_channels), 1193 .channels = adis16477_channels, 1194 .gyro_max_val = 1, 1195 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 1196 .accel_max_val = 78, 1197 .accel_max_scale = 32000 << 16, 1198 .temp_scale = 100, 1199 .deltang_max_val = IIO_DEGREE_TO_RAD(360), 1200 .deltvel_max_val = 100, 1201 .int_clk = 2000, 1202 .max_dec = 1999, 1203 .sync = adis16475_sync_mode, 1204 /* pulse sync not supported */ 1205 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 1206 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 1207 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts, 1208 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1209 ADIS16475_BURST_MAX_SPEED, false), 1210 }, 1211 [ADIS16505_2] = { 1212 .name = "adis16505-2", 1213 .num_channels = ARRAY_SIZE(adis16477_channels), 1214 .channels = adis16477_channels, 1215 .gyro_max_val = 1, 1216 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 1217 .accel_max_val = 78, 1218 .accel_max_scale = 32000 << 16, 1219 .temp_scale = 100, 1220 .deltang_max_val = IIO_DEGREE_TO_RAD(720), 1221 .deltvel_max_val = 100, 1222 .int_clk = 2000, 1223 .max_dec = 1999, 1224 .sync = adis16475_sync_mode, 1225 /* pulse sync not supported */ 1226 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 1227 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 1228 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts, 1229 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1230 ADIS16475_BURST_MAX_SPEED, false), 1231 }, 1232 [ADIS16505_3] = { 1233 .name = "adis16505-3", 1234 .num_channels = ARRAY_SIZE(adis16477_channels), 1235 .channels = adis16477_channels, 1236 .gyro_max_val = 1, 1237 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 1238 .accel_max_val = 78, 1239 .accel_max_scale = 32000 << 16, 1240 .temp_scale = 100, 1241 .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 1242 .deltvel_max_val = 100, 1243 .int_clk = 2000, 1244 .max_dec = 1999, 1245 .sync = adis16475_sync_mode, 1246 /* pulse sync not supported */ 1247 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 1248 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 1249 .adis_data = ADIS16475_DATA(16505, &adis1650x_timeouts, 1250 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1251 ADIS16475_BURST_MAX_SPEED, false), 1252 }, 1253 [ADIS16507_1] = { 1254 .name = "adis16507-1", 1255 .num_channels = ARRAY_SIZE(adis16477_channels), 1256 .channels = adis16477_channels, 1257 .gyro_max_val = 1, 1258 .gyro_max_scale = IIO_RAD_TO_DEGREE(160 << 16), 1259 .accel_max_val = 392, 1260 .accel_max_scale = 32000 << 16, 1261 .temp_scale = 100, 1262 .deltang_max_val = IIO_DEGREE_TO_RAD(360), 1263 .deltvel_max_val = 400, 1264 .int_clk = 2000, 1265 .max_dec = 1999, 1266 .sync = adis16475_sync_mode, 1267 /* pulse sync not supported */ 1268 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 1269 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 1270 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts, 1271 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1272 ADIS16475_BURST_MAX_SPEED, false), 1273 }, 1274 [ADIS16507_2] = { 1275 .name = "adis16507-2", 1276 .num_channels = ARRAY_SIZE(adis16477_channels), 1277 .channels = adis16477_channels, 1278 .gyro_max_val = 1, 1279 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 1280 .accel_max_val = 392, 1281 .accel_max_scale = 32000 << 16, 1282 .temp_scale = 100, 1283 .deltang_max_val = IIO_DEGREE_TO_RAD(720), 1284 .deltvel_max_val = 400, 1285 .int_clk = 2000, 1286 .max_dec = 1999, 1287 .sync = adis16475_sync_mode, 1288 /* pulse sync not supported */ 1289 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 1290 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 1291 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts, 1292 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1293 ADIS16475_BURST_MAX_SPEED, false), 1294 }, 1295 [ADIS16507_3] = { 1296 .name = "adis16507-3", 1297 .num_channels = ARRAY_SIZE(adis16477_channels), 1298 .channels = adis16477_channels, 1299 .gyro_max_val = 1, 1300 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 1301 .accel_max_val = 392, 1302 .accel_max_scale = 32000 << 16, 1303 .temp_scale = 100, 1304 .deltang_max_val = IIO_DEGREE_TO_RAD(2160), 1305 .deltvel_max_val = 400, 1306 .int_clk = 2000, 1307 .max_dec = 1999, 1308 .sync = adis16475_sync_mode, 1309 /* pulse sync not supported */ 1310 .num_sync = ARRAY_SIZE(adis16475_sync_mode) - 1, 1311 .flags = ADIS16475_HAS_BURST32 | ADIS16475_HAS_BURST_DELTA_DATA, 1312 .adis_data = ADIS16475_DATA(16507, &adis1650x_timeouts, 1313 ADIS16475_BURST32_MAX_DATA_NO_TS32, 1314 ADIS16475_BURST_MAX_SPEED, false), 1315 }, 1316 [ADIS16575_2] = { 1317 .name = "adis16575-2", 1318 .num_channels = ARRAY_SIZE(adis16575_channels), 1319 .channels = adis16575_channels, 1320 .gyro_max_val = 1, 1321 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 1322 .accel_max_val = 8, 1323 .accel_max_scale = IIO_M_S_2_TO_G(32000 << 16), 1324 .temp_scale = 100, 1325 .deltang_max_val = IIO_DEGREE_TO_RAD(450), 1326 .deltvel_max_val = 100, 1327 .int_clk = 4000, 1328 .max_dec = 3999, 1329 .sync = adis16575_sync_mode, 1330 .num_sync = ARRAY_SIZE(adis16575_sync_mode), 1331 .flags = ADIS16475_HAS_BURST32 | 1332 ADIS16475_HAS_BURST_DELTA_DATA | 1333 ADIS16475_NEEDS_BURST_REQUEST | 1334 ADIS16475_HAS_TIMESTAMP32, 1335 .adis_data = ADIS16475_DATA(16575, &adis16475_timeouts, 1336 ADIS16575_BURST32_DATA_TS32, 1337 ADIS16575_BURST_MAX_SPEED, true), 1338 }, 1339 [ADIS16575_3] = { 1340 .name = "adis16575-3", 1341 .num_channels = ARRAY_SIZE(adis16575_channels), 1342 .channels = adis16575_channels, 1343 .gyro_max_val = 1, 1344 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 1345 .accel_max_val = 8, 1346 .accel_max_scale = IIO_M_S_2_TO_G(32000 << 16), 1347 .temp_scale = 100, 1348 .deltang_max_val = IIO_DEGREE_TO_RAD(2000), 1349 .deltvel_max_val = 100, 1350 .int_clk = 4000, 1351 .max_dec = 3999, 1352 .sync = adis16575_sync_mode, 1353 .num_sync = ARRAY_SIZE(adis16575_sync_mode), 1354 .flags = ADIS16475_HAS_BURST32 | 1355 ADIS16475_HAS_BURST_DELTA_DATA | 1356 ADIS16475_NEEDS_BURST_REQUEST | 1357 ADIS16475_HAS_TIMESTAMP32, 1358 .adis_data = ADIS16475_DATA(16575, &adis16475_timeouts, 1359 ADIS16575_BURST32_DATA_TS32, 1360 ADIS16575_BURST_MAX_SPEED, true), 1361 }, 1362 [ADIS16576_2] = { 1363 .name = "adis16576-2", 1364 .num_channels = ARRAY_SIZE(adis16575_channels), 1365 .channels = adis16575_channels, 1366 .gyro_max_val = 1, 1367 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 1368 .accel_max_val = 40, 1369 .accel_max_scale = IIO_M_S_2_TO_G(32000 << 16), 1370 .temp_scale = 100, 1371 .deltang_max_val = IIO_DEGREE_TO_RAD(450), 1372 .deltvel_max_val = 125, 1373 .int_clk = 4000, 1374 .max_dec = 3999, 1375 .sync = adis16575_sync_mode, 1376 .num_sync = ARRAY_SIZE(adis16575_sync_mode), 1377 .flags = ADIS16475_HAS_BURST32 | 1378 ADIS16475_HAS_BURST_DELTA_DATA | 1379 ADIS16475_NEEDS_BURST_REQUEST | 1380 ADIS16475_HAS_TIMESTAMP32, 1381 .adis_data = ADIS16475_DATA(16576, &adis16475_timeouts, 1382 ADIS16575_BURST32_DATA_TS32, 1383 ADIS16575_BURST_MAX_SPEED, true), 1384 }, 1385 [ADIS16576_3] = { 1386 .name = "adis16576-3", 1387 .num_channels = ARRAY_SIZE(adis16575_channels), 1388 .channels = adis16575_channels, 1389 .gyro_max_val = 1, 1390 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 1391 .accel_max_val = 40, 1392 .accel_max_scale = IIO_M_S_2_TO_G(32000 << 16), 1393 .temp_scale = 100, 1394 .deltang_max_val = IIO_DEGREE_TO_RAD(2000), 1395 .deltvel_max_val = 125, 1396 .int_clk = 4000, 1397 .max_dec = 3999, 1398 .sync = adis16575_sync_mode, 1399 .num_sync = ARRAY_SIZE(adis16575_sync_mode), 1400 .flags = ADIS16475_HAS_BURST32 | 1401 ADIS16475_HAS_BURST_DELTA_DATA | 1402 ADIS16475_NEEDS_BURST_REQUEST | 1403 ADIS16475_HAS_TIMESTAMP32, 1404 .adis_data = ADIS16475_DATA(16576, &adis16475_timeouts, 1405 ADIS16575_BURST32_DATA_TS32, 1406 ADIS16575_BURST_MAX_SPEED, true), 1407 }, 1408 [ADIS16577_2] = { 1409 .name = "adis16577-2", 1410 .num_channels = ARRAY_SIZE(adis16575_channels), 1411 .channels = adis16575_channels, 1412 .gyro_max_val = 1, 1413 .gyro_max_scale = IIO_RAD_TO_DEGREE(40 << 16), 1414 .accel_max_val = 40, 1415 .accel_max_scale = IIO_M_S_2_TO_G(32000 << 16), 1416 .temp_scale = 100, 1417 .deltang_max_val = IIO_DEGREE_TO_RAD(450), 1418 .deltvel_max_val = 400, 1419 .int_clk = 4000, 1420 .max_dec = 3999, 1421 .sync = adis16575_sync_mode, 1422 .num_sync = ARRAY_SIZE(adis16575_sync_mode), 1423 .flags = ADIS16475_HAS_BURST32 | 1424 ADIS16475_HAS_BURST_DELTA_DATA | 1425 ADIS16475_NEEDS_BURST_REQUEST | 1426 ADIS16475_HAS_TIMESTAMP32, 1427 .adis_data = ADIS16475_DATA(16577, &adis16475_timeouts, 1428 ADIS16575_BURST32_DATA_TS32, 1429 ADIS16575_BURST_MAX_SPEED, true), 1430 }, 1431 [ADIS16577_3] = { 1432 .name = "adis16577-3", 1433 .num_channels = ARRAY_SIZE(adis16575_channels), 1434 .channels = adis16575_channels, 1435 .gyro_max_val = 1, 1436 .gyro_max_scale = IIO_RAD_TO_DEGREE(10 << 16), 1437 .accel_max_val = 40, 1438 .accel_max_scale = IIO_M_S_2_TO_G(32000 << 16), 1439 .temp_scale = 100, 1440 .deltang_max_val = IIO_DEGREE_TO_RAD(2000), 1441 .deltvel_max_val = 400, 1442 .int_clk = 4000, 1443 .max_dec = 3999, 1444 .sync = adis16575_sync_mode, 1445 .num_sync = ARRAY_SIZE(adis16575_sync_mode), 1446 .flags = ADIS16475_HAS_BURST32 | 1447 ADIS16475_HAS_BURST_DELTA_DATA | 1448 ADIS16475_NEEDS_BURST_REQUEST | 1449 ADIS16475_HAS_TIMESTAMP32, 1450 .adis_data = ADIS16475_DATA(16577, &adis16475_timeouts, 1451 ADIS16575_BURST32_DATA_TS32, 1452 ADIS16575_BURST_MAX_SPEED, true), 1453 }, 1454}; 1455 1456static int adis16475_update_scan_mode(struct iio_dev *indio_dev, 1457 const unsigned long *scan_mask) 1458{ 1459 u16 en; 1460 int ret; 1461 struct adis16475 *st = iio_priv(indio_dev); 1462 1463 if (st->info->flags & ADIS16475_HAS_BURST_DELTA_DATA) { 1464 if ((*scan_mask & ADIS16500_BURST_DATA_SEL_0_CHN_MASK) && 1465 (*scan_mask & ADIS16500_BURST_DATA_SEL_1_CHN_MASK)) 1466 return -EINVAL; 1467 if (*scan_mask & ADIS16500_BURST_DATA_SEL_0_CHN_MASK) 1468 en = FIELD_PREP(ADIS16500_BURST_DATA_SEL_MASK, 0); 1469 else 1470 en = FIELD_PREP(ADIS16500_BURST_DATA_SEL_MASK, 1); 1471 1472 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, 1473 ADIS16500_BURST_DATA_SEL_MASK, en); 1474 if (ret) 1475 return ret; 1476 } 1477 1478 return adis_update_scan_mode(indio_dev, scan_mask); 1479} 1480 1481static const struct iio_info adis16475_info = { 1482 .read_raw = &adis16475_read_raw, 1483 .write_raw = &adis16475_write_raw, 1484 .update_scan_mode = adis16475_update_scan_mode, 1485 .debugfs_reg_access = adis_debugfs_reg_access, 1486}; 1487 1488static const struct iio_info adis16575_info = { 1489 .read_raw = &adis16475_read_raw, 1490 .write_raw = &adis16475_write_raw, 1491 .update_scan_mode = adis16475_update_scan_mode, 1492 .debugfs_reg_access = adis_debugfs_reg_access, 1493 .hwfifo_set_watermark = adis16475_set_watermark, 1494}; 1495 1496static bool adis16475_validate_crc(const u8 *buffer, u16 crc, 1497 u16 burst_size, u16 start_idx) 1498{ 1499 int i; 1500 1501 for (i = start_idx; i < burst_size - 2; i++) 1502 crc -= buffer[i]; 1503 1504 return crc == 0; 1505} 1506 1507static void adis16475_burst32_check(struct adis16475 *st) 1508{ 1509 int ret; 1510 struct adis *adis = &st->adis; 1511 u8 timestamp32 = 0; 1512 1513 if (!(st->info->flags & ADIS16475_HAS_BURST32)) 1514 return; 1515 1516 if (st->info->flags & ADIS16475_HAS_TIMESTAMP32) 1517 timestamp32 = 1; 1518 1519 if (st->lsb_flag && !st->burst32) { 1520 const u16 en = ADIS16500_BURST32(1); 1521 1522 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, 1523 ADIS16500_BURST32_MASK, en); 1524 if (ret) 1525 return; 1526 1527 st->burst32 = true; 1528 1529 /* 1530 * In 32-bit mode we need extra 2 bytes for all gyro 1531 * and accel channels. 1532 * If the device has 32-bit timestamp value we need 2 extra 1533 * bytes for it. 1534 */ 1535 adis->burst_extra_len = (6 + timestamp32) * sizeof(u16); 1536 adis->xfer[1].len += (6 + timestamp32) * sizeof(u16); 1537 1538 dev_dbg(&adis->spi->dev, "Enable burst32 mode, xfer:%d", 1539 adis->xfer[1].len); 1540 1541 } else if (!st->lsb_flag && st->burst32) { 1542 const u16 en = ADIS16500_BURST32(0); 1543 1544 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, 1545 ADIS16500_BURST32_MASK, en); 1546 if (ret) 1547 return; 1548 1549 st->burst32 = false; 1550 1551 /* Remove the extra bits */ 1552 adis->burst_extra_len = 0; 1553 adis->xfer[1].len -= (6 + timestamp32) * sizeof(u16); 1554 dev_dbg(&adis->spi->dev, "Disable burst32 mode, xfer:%d\n", 1555 adis->xfer[1].len); 1556 } 1557} 1558 1559static int adis16475_push_single_sample(struct iio_poll_func *pf) 1560{ 1561 struct iio_dev *indio_dev = pf->indio_dev; 1562 struct adis16475 *st = iio_priv(indio_dev); 1563 struct adis *adis = &st->adis; 1564 int ret, bit, buff_offset = 0, i = 0; 1565 __be16 *buffer; 1566 u16 crc; 1567 bool valid; 1568 u8 crc_offset = 9; 1569 u16 burst_size = ADIS16475_BURST_MAX_DATA; 1570 u16 start_idx = (st->info->flags & ADIS16475_HAS_TIMESTAMP32) ? 2 : 0; 1571 1572 /* offset until the first element after gyro and accel */ 1573 const u8 offset = st->burst32 ? 13 : 7; 1574 1575 if (st->burst32) { 1576 crc_offset = (st->info->flags & ADIS16475_HAS_TIMESTAMP32) ? 16 : 15; 1577 burst_size = adis->data->burst_max_len; 1578 } 1579 1580 ret = spi_sync(adis->spi, &adis->msg); 1581 if (ret) 1582 return ret; 1583 1584 buffer = adis->buffer; 1585 1586 crc = be16_to_cpu(buffer[crc_offset]); 1587 valid = adis16475_validate_crc(adis->buffer, crc, burst_size, start_idx); 1588 if (!valid) { 1589 dev_err(&adis->spi->dev, "Invalid crc\n"); 1590 return -EINVAL; 1591 } 1592 1593 iio_for_each_active_channel(indio_dev, bit) { 1594 /* 1595 * When burst mode is used, system flags is the first data 1596 * channel in the sequence, but the scan index is 7. 1597 */ 1598 switch (bit) { 1599 case ADIS16475_SCAN_TEMP: 1600 st->data[i++] = buffer[offset]; 1601 /* 1602 * The temperature channel has 16-bit storage size. 1603 * We need to perform the padding to have the buffer 1604 * elements naturally aligned in case there are any 1605 * 32-bit storage size channels enabled which have a 1606 * scan index higher than the temperature channel scan 1607 * index. 1608 */ 1609 if (*indio_dev->active_scan_mask & GENMASK(ADIS16475_SCAN_DELTVEL_Z, ADIS16475_SCAN_DELTANG_X)) 1610 st->data[i++] = 0; 1611 break; 1612 case ADIS16475_SCAN_DELTANG_X ... ADIS16475_SCAN_DELTVEL_Z: 1613 buff_offset = ADIS16475_SCAN_DELTANG_X; 1614 fallthrough; 1615 case ADIS16475_SCAN_GYRO_X ... ADIS16475_SCAN_ACCEL_Z: 1616 /* 1617 * The first 2 bytes on the received data are the 1618 * DIAG_STAT reg, hence the +1 offset here... 1619 */ 1620 if (st->burst32) { 1621 /* upper 16 */ 1622 st->data[i++] = buffer[(bit - buff_offset) * 2 + 2]; 1623 /* lower 16 */ 1624 st->data[i++] = buffer[(bit - buff_offset) * 2 + 1]; 1625 } else { 1626 st->data[i++] = buffer[(bit - buff_offset) + 1]; 1627 /* 1628 * Don't bother in doing the manual read if the 1629 * device supports burst32. burst32 will be 1630 * enabled in the next call to 1631 * adis16475_burst32_check()... 1632 */ 1633 if (st->lsb_flag && !(st->info->flags & ADIS16475_HAS_BURST32)) { 1634 u16 val = 0; 1635 const u32 reg = ADIS16475_REG_X_GYRO_L + 1636 bit * 4; 1637 1638 adis_read_reg_16(adis, reg, &val); 1639 st->data[i++] = cpu_to_be16(val); 1640 } else { 1641 /* lower not used */ 1642 st->data[i++] = 0; 1643 } 1644 } 1645 break; 1646 } 1647 } 1648 1649 /* There might not be a timestamp option for some devices. */ 1650 iio_push_to_buffers_with_timestamp(indio_dev, st->data, pf->timestamp); 1651 1652 return 0; 1653} 1654 1655static irqreturn_t adis16475_trigger_handler(int irq, void *p) 1656{ 1657 struct iio_poll_func *pf = p; 1658 struct iio_dev *indio_dev = pf->indio_dev; 1659 struct adis16475 *st = iio_priv(indio_dev); 1660 1661 adis16475_push_single_sample(pf); 1662 /* 1663 * We only check the burst mode at the end of the current capture since 1664 * it takes a full data ready cycle for the device to update the burst 1665 * array. 1666 */ 1667 adis16475_burst32_check(st); 1668 1669 iio_trigger_notify_done(indio_dev->trig); 1670 1671 return IRQ_HANDLED; 1672} 1673 1674/* 1675 * This function updates the first tx byte from the adis message based on the 1676 * given burst request. 1677 */ 1678static void adis16575_update_msg_for_burst(struct adis *adis, u8 burst_req) 1679{ 1680 unsigned int burst_max_length; 1681 u8 *tx; 1682 1683 if (adis->data->burst_max_len) 1684 burst_max_length = adis->data->burst_max_len; 1685 else 1686 burst_max_length = adis->data->burst_len + adis->burst_extra_len; 1687 1688 tx = adis->buffer + burst_max_length; 1689 tx[0] = ADIS_READ_REG(burst_req); 1690} 1691 1692static int adis16575_custom_burst_read(struct iio_poll_func *pf, u8 burst_req) 1693{ 1694 struct iio_dev *indio_dev = pf->indio_dev; 1695 struct adis16475 *st = iio_priv(indio_dev); 1696 struct adis *adis = &st->adis; 1697 1698 adis16575_update_msg_for_burst(adis, burst_req); 1699 1700 if (burst_req) 1701 return spi_sync(adis->spi, &adis->msg); 1702 1703 return adis16475_push_single_sample(pf); 1704} 1705 1706/* 1707 * This handler is meant to be used for devices which support burst readings 1708 * from FIFO (namely devices from adis1657x family). 1709 * In order to pop the FIFO the 0x68 0x00 FIFO pop burst request has to be sent. 1710 * If the previous device command was not a FIFO pop burst request, the FIFO pop 1711 * burst request will simply pop the FIFO without returning valid data. 1712 * For the nth consecutive burst request, thedevice will send the data popped 1713 * with the (n-1)th consecutive burst request. 1714 * In order to read the data which was popped previously, without popping the 1715 * FIFO, the 0x00 0x00 burst request has to be sent. 1716 * If after a 0x68 0x00 FIFO pop burst request, there is any other device access 1717 * different from a 0x68 0x00 or a 0x00 0x00 burst request, the FIFO data popped 1718 * previously will be lost. 1719 */ 1720static irqreturn_t adis16475_trigger_handler_with_fifo(int irq, void *p) 1721{ 1722 struct iio_poll_func *pf = p; 1723 struct iio_dev *indio_dev = pf->indio_dev; 1724 struct adis16475 *st = iio_priv(indio_dev); 1725 struct adis *adis = &st->adis; 1726 int ret; 1727 u16 fifo_cnt, i; 1728 1729 adis_dev_auto_lock(&st->adis); 1730 1731 ret = __adis_read_reg_16(adis, ADIS16575_REG_FIFO_CNT, &fifo_cnt); 1732 if (ret) 1733 goto unlock; 1734 1735 /* 1736 * If no sample is available, nothing can be read. This can happen if 1737 * a the used trigger has a higher frequency than the selected sample rate. 1738 */ 1739 if (!fifo_cnt) 1740 goto unlock; 1741 1742 /* 1743 * First burst request - FIFO pop: popped data will be returned in the 1744 * next burst request. 1745 */ 1746 ret = adis16575_custom_burst_read(pf, adis->data->burst_reg_cmd); 1747 if (ret) 1748 goto unlock; 1749 1750 for (i = 0; i < fifo_cnt - 1; i++) { 1751 ret = adis16475_push_single_sample(pf); 1752 if (ret) 1753 goto unlock; 1754 } 1755 1756 /* FIFO read without popping */ 1757 ret = adis16575_custom_burst_read(pf, 0); 1758 1759unlock: 1760 /* 1761 * We only check the burst mode at the end of the current capture since 1762 * reading data from registers will impact the FIFO reading. 1763 */ 1764 adis16475_burst32_check(st); 1765 iio_trigger_notify_done(indio_dev->trig); 1766 1767 return IRQ_HANDLED; 1768} 1769 1770static int adis16475_config_sync_mode(struct adis16475 *st) 1771{ 1772 int ret; 1773 struct device *dev = &st->adis.spi->dev; 1774 const struct adis16475_sync *sync; 1775 u32 sync_mode; 1776 u16 max_sample_rate = st->info->int_clk + 100; 1777 u16 val; 1778 1779 /* if available, enable 4khz internal clock */ 1780 if (st->info->int_clk == 4000) { 1781 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, 1782 ADIS16575_SYNC_4KHZ_MASK, 1783 (u16)ADIS16575_SYNC_4KHZ(1)); 1784 if (ret) 1785 return ret; 1786 } 1787 1788 /* default to internal clk */ 1789 st->clk_freq = st->info->int_clk * 1000; 1790 1791 ret = device_property_read_u32(dev, "adi,sync-mode", &sync_mode); 1792 if (ret) 1793 return 0; 1794 1795 if (sync_mode >= st->info->num_sync) { 1796 dev_err(dev, "Invalid sync mode: %u for %s\n", sync_mode, 1797 st->info->name); 1798 return -EINVAL; 1799 } 1800 1801 sync = &st->info->sync[sync_mode]; 1802 st->sync_mode = sync->sync_mode; 1803 1804 /* All the other modes require external input signal */ 1805 if (sync->sync_mode != ADIS16475_SYNC_OUTPUT) { 1806 struct clk *clk = devm_clk_get_enabled(dev, NULL); 1807 1808 if (IS_ERR(clk)) 1809 return PTR_ERR(clk); 1810 1811 st->clk_freq = clk_get_rate(clk); 1812 if (st->clk_freq < sync->min_rate || 1813 st->clk_freq > sync->max_rate) { 1814 dev_err(dev, 1815 "Clk rate:%u not in a valid range:[%u %u]\n", 1816 st->clk_freq, sync->min_rate, sync->max_rate); 1817 return -EINVAL; 1818 } 1819 1820 if (sync->sync_mode == ADIS16475_SYNC_SCALED) { 1821 u16 up_scale; 1822 1823 /* 1824 * In sync scaled mode, the IMU sample rate is the clk_freq * sync_scale. 1825 * Hence, default the IMU sample rate to the highest multiple of the input 1826 * clock lower than the IMU max sample rate. 1827 */ 1828 up_scale = max_sample_rate / st->clk_freq; 1829 1830 ret = __adis_write_reg_16(&st->adis, 1831 ADIS16475_REG_UP_SCALE, 1832 up_scale); 1833 if (ret) 1834 return ret; 1835 } 1836 1837 st->clk_freq *= 1000; 1838 } 1839 /* 1840 * Keep in mind that the mask for the clk modes in adis1650* 1841 * chips is different (1100 instead of 11100). However, we 1842 * are not configuring BIT(4) in these chips and the default 1843 * value is 0, so we are fine in doing the below operations. 1844 * I'm keeping this for simplicity and avoiding extra variables 1845 * in chip_info. 1846 */ 1847 val = ADIS16475_SYNC_MODE(sync->sync_mode); 1848 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, 1849 ADIS16475_SYNC_MODE_MASK, val); 1850 if (ret) 1851 return ret; 1852 1853 usleep_range(250, 260); 1854 1855 return 0; 1856} 1857 1858static int adis16475_config_irq_pin(struct adis16475 *st) 1859{ 1860 int ret; 1861 u32 irq_type; 1862 u16 val = 0; 1863 u8 polarity; 1864 struct spi_device *spi = st->adis.spi; 1865 1866 irq_type = irq_get_trigger_type(spi->irq); 1867 1868 if (st->adis.data->has_fifo) { 1869 /* 1870 * It is possible to configure the fifo watermark pin polarity. 1871 * Furthermore, we need to update the adis struct if we want the 1872 * watermark pin active low. 1873 */ 1874 if (irq_type == IRQ_TYPE_LEVEL_HIGH) { 1875 polarity = 1; 1876 st->adis.irq_flag = IRQF_TRIGGER_HIGH; 1877 } else if (irq_type == IRQ_TYPE_LEVEL_LOW) { 1878 polarity = 0; 1879 st->adis.irq_flag = IRQF_TRIGGER_LOW; 1880 } else { 1881 dev_err(&spi->dev, "Invalid interrupt type 0x%x specified\n", 1882 irq_type); 1883 return -EINVAL; 1884 } 1885 1886 /* Configure the watermark pin polarity. */ 1887 val = ADIS16575_WM_POL(polarity); 1888 ret = adis_update_bits(&st->adis, ADIS16475_REG_FIFO_CTRL, 1889 ADIS16575_WM_POL_MASK, val); 1890 if (ret) 1891 return ret; 1892 1893 /* Enable watermark interrupt pin. */ 1894 ret = adis_update_bits(&st->adis, ADIS16475_REG_FIFO_CTRL, 1895 ADIS16575_WM_EN_MASK, 1896 (u16)ADIS16575_WM_EN(1)); 1897 if (ret) 1898 return ret; 1899 1900 } else { 1901 /* 1902 * It is possible to configure the data ready polarity. Furthermore, we 1903 * need to update the adis struct if we want data ready as active low. 1904 */ 1905 if (irq_type == IRQ_TYPE_EDGE_RISING) { 1906 polarity = 1; 1907 st->adis.irq_flag = IRQF_TRIGGER_RISING; 1908 } else if (irq_type == IRQ_TYPE_EDGE_FALLING) { 1909 polarity = 0; 1910 st->adis.irq_flag = IRQF_TRIGGER_FALLING; 1911 } else { 1912 dev_err(&spi->dev, "Invalid interrupt type 0x%x specified\n", 1913 irq_type); 1914 return -EINVAL; 1915 } 1916 1917 val = ADIS16475_MSG_CTRL_DR_POL(polarity); 1918 ret = __adis_update_bits(&st->adis, ADIS16475_REG_MSG_CTRL, 1919 ADIS16475_MSG_CTRL_DR_POL_MASK, val); 1920 if (ret) 1921 return ret; 1922 /* 1923 * There is a delay writing to any bits written to the MSC_CTRL 1924 * register. It should not be bigger than 200us, so 250 should be more 1925 * than enough! 1926 */ 1927 usleep_range(250, 260); 1928 } 1929 1930 return 0; 1931} 1932 1933static int adis16475_probe(struct spi_device *spi) 1934{ 1935 struct iio_dev *indio_dev; 1936 struct adis16475 *st; 1937 int ret; 1938 u16 val; 1939 1940 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1941 if (!indio_dev) 1942 return -ENOMEM; 1943 1944 st = iio_priv(indio_dev); 1945 1946 st->info = spi_get_device_match_data(spi); 1947 if (!st->info) 1948 return -EINVAL; 1949 1950 ret = adis_init(&st->adis, indio_dev, spi, &st->info->adis_data); 1951 if (ret) 1952 return ret; 1953 1954 indio_dev->name = st->info->name; 1955 indio_dev->channels = st->info->channels; 1956 indio_dev->num_channels = st->info->num_channels; 1957 if (st->adis.data->has_fifo) 1958 indio_dev->info = &adis16575_info; 1959 else 1960 indio_dev->info = &adis16475_info; 1961 indio_dev->modes = INDIO_DIRECT_MODE; 1962 1963 ret = __adis_initial_startup(&st->adis); 1964 if (ret) 1965 return ret; 1966 1967 ret = adis16475_config_irq_pin(st); 1968 if (ret) 1969 return ret; 1970 1971 ret = adis16475_config_sync_mode(st); 1972 if (ret) 1973 return ret; 1974 1975 if (st->adis.data->has_fifo) { 1976 ret = devm_adis_setup_buffer_and_trigger_with_attrs(&st->adis, indio_dev, 1977 adis16475_trigger_handler_with_fifo, 1978 &adis16475_buffer_ops, 1979 adis16475_fifo_attributes); 1980 if (ret) 1981 return ret; 1982 1983 /* Update overflow behavior to always overwrite the oldest sample. */ 1984 val = ADIS16575_OVERWRITE_OLDEST; 1985 ret = adis_update_bits(&st->adis, ADIS16475_REG_FIFO_CTRL, 1986 ADIS16575_OVERFLOW_MASK, val); 1987 if (ret) 1988 return ret; 1989 } else { 1990 ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev, 1991 adis16475_trigger_handler); 1992 if (ret) 1993 return ret; 1994 } 1995 1996 ret = devm_iio_device_register(&spi->dev, indio_dev); 1997 if (ret) 1998 return ret; 1999 2000 adis16475_debugfs_init(indio_dev); 2001 2002 return 0; 2003} 2004 2005static const struct of_device_id adis16475_of_match[] = { 2006 { .compatible = "adi,adis16470", 2007 .data = &adis16475_chip_info[ADIS16470] }, 2008 { .compatible = "adi,adis16475-1", 2009 .data = &adis16475_chip_info[ADIS16475_1] }, 2010 { .compatible = "adi,adis16475-2", 2011 .data = &adis16475_chip_info[ADIS16475_2] }, 2012 { .compatible = "adi,adis16475-3", 2013 .data = &adis16475_chip_info[ADIS16475_3] }, 2014 { .compatible = "adi,adis16477-1", 2015 .data = &adis16475_chip_info[ADIS16477_1] }, 2016 { .compatible = "adi,adis16477-2", 2017 .data = &adis16475_chip_info[ADIS16477_2] }, 2018 { .compatible = "adi,adis16477-3", 2019 .data = &adis16475_chip_info[ADIS16477_3] }, 2020 { .compatible = "adi,adis16465-1", 2021 .data = &adis16475_chip_info[ADIS16465_1] }, 2022 { .compatible = "adi,adis16465-2", 2023 .data = &adis16475_chip_info[ADIS16465_2] }, 2024 { .compatible = "adi,adis16465-3", 2025 .data = &adis16475_chip_info[ADIS16465_3] }, 2026 { .compatible = "adi,adis16467-1", 2027 .data = &adis16475_chip_info[ADIS16467_1] }, 2028 { .compatible = "adi,adis16467-2", 2029 .data = &adis16475_chip_info[ADIS16467_2] }, 2030 { .compatible = "adi,adis16467-3", 2031 .data = &adis16475_chip_info[ADIS16467_3] }, 2032 { .compatible = "adi,adis16500", 2033 .data = &adis16475_chip_info[ADIS16500] }, 2034 { .compatible = "adi,adis16501", 2035 .data = &adis16475_chip_info[ADIS16501] }, 2036 { .compatible = "adi,adis16505-1", 2037 .data = &adis16475_chip_info[ADIS16505_1] }, 2038 { .compatible = "adi,adis16505-2", 2039 .data = &adis16475_chip_info[ADIS16505_2] }, 2040 { .compatible = "adi,adis16505-3", 2041 .data = &adis16475_chip_info[ADIS16505_3] }, 2042 { .compatible = "adi,adis16507-1", 2043 .data = &adis16475_chip_info[ADIS16507_1] }, 2044 { .compatible = "adi,adis16507-2", 2045 .data = &adis16475_chip_info[ADIS16507_2] }, 2046 { .compatible = "adi,adis16507-3", 2047 .data = &adis16475_chip_info[ADIS16507_3] }, 2048 { .compatible = "adi,adis16575-2", 2049 .data = &adis16475_chip_info[ADIS16575_2] }, 2050 { .compatible = "adi,adis16575-3", 2051 .data = &adis16475_chip_info[ADIS16575_3] }, 2052 { .compatible = "adi,adis16576-2", 2053 .data = &adis16475_chip_info[ADIS16576_2] }, 2054 { .compatible = "adi,adis16576-3", 2055 .data = &adis16475_chip_info[ADIS16576_3] }, 2056 { .compatible = "adi,adis16577-2", 2057 .data = &adis16475_chip_info[ADIS16577_2] }, 2058 { .compatible = "adi,adis16577-3", 2059 .data = &adis16475_chip_info[ADIS16577_3] }, 2060 { } 2061}; 2062MODULE_DEVICE_TABLE(of, adis16475_of_match); 2063 2064static const struct spi_device_id adis16475_ids[] = { 2065 { "adis16470", (kernel_ulong_t)&adis16475_chip_info[ADIS16470] }, 2066 { "adis16475-1", (kernel_ulong_t)&adis16475_chip_info[ADIS16475_1] }, 2067 { "adis16475-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16475_2] }, 2068 { "adis16475-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16475_3] }, 2069 { "adis16477-1", (kernel_ulong_t)&adis16475_chip_info[ADIS16477_1] }, 2070 { "adis16477-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16477_2] }, 2071 { "adis16477-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16477_3] }, 2072 { "adis16465-1", (kernel_ulong_t)&adis16475_chip_info[ADIS16465_1] }, 2073 { "adis16465-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16465_2] }, 2074 { "adis16465-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16465_3] }, 2075 { "adis16467-1", (kernel_ulong_t)&adis16475_chip_info[ADIS16467_1] }, 2076 { "adis16467-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16467_2] }, 2077 { "adis16467-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16467_3] }, 2078 { "adis16500", (kernel_ulong_t)&adis16475_chip_info[ADIS16500] }, 2079 { "adis16501", (kernel_ulong_t)&adis16475_chip_info[ADIS16501] }, 2080 { "adis16505-1", (kernel_ulong_t)&adis16475_chip_info[ADIS16505_1] }, 2081 { "adis16505-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16505_2] }, 2082 { "adis16505-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16505_3] }, 2083 { "adis16507-1", (kernel_ulong_t)&adis16475_chip_info[ADIS16507_1] }, 2084 { "adis16507-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16507_2] }, 2085 { "adis16507-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16507_3] }, 2086 { "adis16575-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16575_2] }, 2087 { "adis16575-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16575_3] }, 2088 { "adis16576-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16576_2] }, 2089 { "adis16576-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16576_3] }, 2090 { "adis16577-2", (kernel_ulong_t)&adis16475_chip_info[ADIS16577_2] }, 2091 { "adis16577-3", (kernel_ulong_t)&adis16475_chip_info[ADIS16577_3] }, 2092 { } 2093}; 2094MODULE_DEVICE_TABLE(spi, adis16475_ids); 2095 2096static struct spi_driver adis16475_driver = { 2097 .driver = { 2098 .name = "adis16475", 2099 .of_match_table = adis16475_of_match, 2100 }, 2101 .probe = adis16475_probe, 2102 .id_table = adis16475_ids, 2103}; 2104module_spi_driver(adis16475_driver); 2105 2106MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>"); 2107MODULE_DESCRIPTION("Analog Devices ADIS16475 IMU driver"); 2108MODULE_LICENSE("GPL"); 2109MODULE_IMPORT_NS("IIO_ADISLIB");
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