adxrs450.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * ADXRS450/ADXRS453 Digital Output Gyroscope Driver
  4 *
  5 * Copyright 2011 Analog Devices Inc.
  6 */
  7
  8#include <linux/interrupt.h>
  9#include <linux/irq.h>
 10#include <linux/delay.h>
 11#include <linux/mutex.h>
 12#include <linux/device.h>
 13#include <linux/kernel.h>
 14#include <linux/spi/spi.h>
 15#include <linux/slab.h>
 16#include <linux/sysfs.h>
 17#include <linux/list.h>
 18#include <linux/module.h>
 19
 20#include <linux/iio/iio.h>
 21#include <linux/iio/sysfs.h>
 22
 23#define ADXRS450_STARTUP_DELAY	50 /* ms */
 24
 25/* The MSB for the spi commands */
 26#define ADXRS450_SENSOR_DATA    (0x20 << 24)
 27#define ADXRS450_WRITE_DATA	(0x40 << 24)
 28#define ADXRS450_READ_DATA	(0x80 << 24)
 29
 30#define ADXRS450_RATE1	0x00	/* Rate Registers */
 31#define ADXRS450_TEMP1	0x02	/* Temperature Registers */
 32#define ADXRS450_LOCST1	0x04	/* Low CST Memory Registers */
 33#define ADXRS450_HICST1	0x06	/* High CST Memory Registers */
 34#define ADXRS450_QUAD1	0x08	/* Quad Memory Registers */
 35#define ADXRS450_FAULT1	0x0A	/* Fault Registers */
 36#define ADXRS450_PID1	0x0C	/* Part ID Register 1 */
 37#define ADXRS450_SNH	0x0E	/* Serial Number Registers, 4 bytes */
 38#define ADXRS450_SNL	0x10
 39#define ADXRS450_DNC1	0x12	/* Dynamic Null Correction Registers */
 40/* Check bits */
 41#define ADXRS450_P	0x01
 42#define ADXRS450_CHK	0x02
 43#define ADXRS450_CST	0x04
 44#define ADXRS450_PWR	0x08
 45#define ADXRS450_POR	0x10
 46#define ADXRS450_NVM	0x20
 47#define ADXRS450_Q	0x40
 48#define ADXRS450_PLL	0x80
 49#define ADXRS450_UV	0x100
 50#define ADXRS450_OV	0x200
 51#define ADXRS450_AMP	0x400
 52#define ADXRS450_FAIL	0x800
 53
 54#define ADXRS450_WRERR_MASK	(0x7 << 29)
 55
 56#define ADXRS450_MAX_RX 4
 57#define ADXRS450_MAX_TX 4
 58
 59#define ADXRS450_GET_ST(a)	((a >> 26) & 0x3)
 60
 61enum {
 62	ID_ADXRS450,
 63	ID_ADXRS453,
 64};
 65
 66/**
 67 * struct adxrs450_state - device instance specific data
 68 * @us:			actual spi_device
 69 * @buf_lock:		mutex to protect tx and rx
 70 * @tx:			transmit buffer
 71 * @rx:			receive buffer
 72 **/
 73struct adxrs450_state {
 74	struct spi_device	*us;
 75	struct mutex		buf_lock;
 76	__be32			tx __aligned(IIO_DMA_MINALIGN);
 77	__be32			rx;
 78
 79};
 80
 81/**
 82 * adxrs450_spi_read_reg_16() - read 2 bytes from a register pair
 83 * @indio_dev: device associated with child of actual iio_dev
 84 * @reg_address: the address of the lower of the two registers, which should be
 85 *	an even address, the second register's address is reg_address + 1.
 86 * @val: somewhere to pass back the value read
 87 **/
 88static int adxrs450_spi_read_reg_16(struct iio_dev *indio_dev,
 89				    u8 reg_address,
 90				    u16 *val)
 91{
 92	struct adxrs450_state *st = iio_priv(indio_dev);
 93	u32 tx;
 94	int ret;
 95	struct spi_transfer xfers[] = {
 96		{
 97			.tx_buf = &st->tx,
 98			.len = sizeof(st->tx),
 99			.cs_change = 1,
100		}, {
101			.rx_buf = &st->rx,
102			.len = sizeof(st->rx),
103		},
104	};
105
106	mutex_lock(&st->buf_lock);
107	tx = ADXRS450_READ_DATA | (reg_address << 17);
108
109	if (!(hweight32(tx) & 1))
110		tx |= ADXRS450_P;
111
112	st->tx = cpu_to_be32(tx);
113	ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
114	if (ret) {
115		dev_err(&st->us->dev, "problem while reading 16 bit register 0x%02x\n",
116				reg_address);
117		goto error_ret;
118	}
119
120	*val = (be32_to_cpu(st->rx) >> 5) & 0xFFFF;
121
122error_ret:
123	mutex_unlock(&st->buf_lock);
124	return ret;
125}
126
127/**
128 * adxrs450_spi_write_reg_16() - write 2 bytes data to a register pair
129 * @indio_dev: device associated with child of actual actual iio_dev
130 * @reg_address: the address of the lower of the two registers,which should be
131 *	an even address, the second register's address is reg_address + 1.
132 * @val: value to be written.
133 **/
134static int adxrs450_spi_write_reg_16(struct iio_dev *indio_dev,
135				     u8 reg_address,
136				     u16 val)
137{
138	struct adxrs450_state *st = iio_priv(indio_dev);
139	u32 tx;
140	int ret;
141
142	mutex_lock(&st->buf_lock);
143	tx = ADXRS450_WRITE_DATA | (reg_address << 17) | (val << 1);
144
145	if (!(hweight32(tx) & 1))
146		tx |= ADXRS450_P;
147
148	st->tx = cpu_to_be32(tx);
149	ret = spi_write(st->us, &st->tx, sizeof(st->tx));
150	if (ret)
151		dev_err(&st->us->dev, "problem while writing 16 bit register 0x%02x\n",
152			reg_address);
153	usleep_range(100, 1000); /* enforce sequential transfer delay 0.1ms */
154	mutex_unlock(&st->buf_lock);
155	return ret;
156}
157
158/**
159 * adxrs450_spi_sensor_data() - read 2 bytes sensor data
160 * @indio_dev: device associated with child of actual iio_dev
161 * @val: somewhere to pass back the value read
162 **/
163static int adxrs450_spi_sensor_data(struct iio_dev *indio_dev, s16 *val)
164{
165	struct adxrs450_state *st = iio_priv(indio_dev);
166	int ret;
167	struct spi_transfer xfers[] = {
168		{
169			.tx_buf = &st->tx,
170			.len = sizeof(st->tx),
171			.cs_change = 1,
172		}, {
173			.rx_buf = &st->rx,
174			.len = sizeof(st->rx),
175		},
176	};
177
178	mutex_lock(&st->buf_lock);
179	st->tx = cpu_to_be32(ADXRS450_SENSOR_DATA);
180
181	ret = spi_sync_transfer(st->us, xfers, ARRAY_SIZE(xfers));
182	if (ret) {
183		dev_err(&st->us->dev, "Problem while reading sensor data\n");
184		goto error_ret;
185	}
186
187	*val = (be32_to_cpu(st->rx) >> 10) & 0xFFFF;
188
189error_ret:
190	mutex_unlock(&st->buf_lock);
191	return ret;
192}
193
194/**
195 * adxrs450_spi_initial() - use for initializing procedure.
196 * @st: device instance specific data
197 * @val: somewhere to pass back the value read
198 * @chk: Whether to perform fault check
199 **/
200static int adxrs450_spi_initial(struct adxrs450_state *st,
201		u32 *val, char chk)
202{
203	int ret;
204	u32 tx;
205	struct spi_transfer xfers = {
206		.tx_buf = &st->tx,
207		.rx_buf = &st->rx,
208		.len = sizeof(st->tx),
209	};
210
211	mutex_lock(&st->buf_lock);
212	tx = ADXRS450_SENSOR_DATA;
213	if (chk)
214		tx |= (ADXRS450_CHK | ADXRS450_P);
215	st->tx = cpu_to_be32(tx);
216	ret = spi_sync_transfer(st->us, &xfers, 1);
217	if (ret) {
218		dev_err(&st->us->dev, "Problem while reading initializing data\n");
219		goto error_ret;
220	}
221
222	*val = be32_to_cpu(st->rx);
223
224error_ret:
225	mutex_unlock(&st->buf_lock);
226	return ret;
227}
228
229/* Recommended Startup Sequence by spec */
230static int adxrs450_initial_setup(struct iio_dev *indio_dev)
231{
232	u32 t;
233	u16 data;
234	int ret;
235	struct adxrs450_state *st = iio_priv(indio_dev);
236
237	msleep(ADXRS450_STARTUP_DELAY*2);
238	ret = adxrs450_spi_initial(st, &t, 1);
239	if (ret)
240		return ret;
241	if (t != 0x01)
242		dev_warn(&st->us->dev, "The initial power on response is not correct! Restart without reset?\n");
243
244	msleep(ADXRS450_STARTUP_DELAY);
245	ret = adxrs450_spi_initial(st, &t, 0);
246	if (ret)
247		return ret;
248
249	msleep(ADXRS450_STARTUP_DELAY);
250	ret = adxrs450_spi_initial(st, &t, 0);
251	if (ret)
252		return ret;
253	if (((t & 0xff) | 0x01) != 0xff || ADXRS450_GET_ST(t) != 2) {
254		dev_err(&st->us->dev, "The second response is not correct!\n");
255		return -EIO;
256
257	}
258	ret = adxrs450_spi_initial(st, &t, 0);
259	if (ret)
260		return ret;
261	if (((t & 0xff) | 0x01) != 0xff || ADXRS450_GET_ST(t) != 2) {
262		dev_err(&st->us->dev, "The third response is not correct!\n");
263		return -EIO;
264
265	}
266	ret = adxrs450_spi_read_reg_16(indio_dev, ADXRS450_FAULT1, &data);
267	if (ret)
268		return ret;
269	if (data & 0x0fff) {
270		dev_err(&st->us->dev, "The device is not in normal status!\n");
271		return -EINVAL;
272	}
273
274	return 0;
275}
276
277static int adxrs450_write_raw(struct iio_dev *indio_dev,
278			      struct iio_chan_spec const *chan,
279			      int val,
280			      int val2,
281			      long mask)
282{
283	int ret;
284	switch (mask) {
285	case IIO_CHAN_INFO_CALIBBIAS:
286		if (val < -0x400 || val >= 0x400)
287			return -EINVAL;
288		ret = adxrs450_spi_write_reg_16(indio_dev,
289						ADXRS450_DNC1, val);
290		break;
291	default:
292		ret = -EINVAL;
293		break;
294	}
295	return ret;
296}
297
298static int adxrs450_read_raw(struct iio_dev *indio_dev,
299			     struct iio_chan_spec const *chan,
300			     int *val,
301			     int *val2,
302			     long mask)
303{
304	int ret;
305	s16 t;
306
307	switch (mask) {
308	case IIO_CHAN_INFO_RAW:
309		switch (chan->type) {
310		case IIO_ANGL_VEL:
311			ret = adxrs450_spi_sensor_data(indio_dev, &t);
312			if (ret)
313				break;
314			*val = t;
315			ret = IIO_VAL_INT;
316			break;
317		case IIO_TEMP:
318			ret = adxrs450_spi_read_reg_16(indio_dev,
319						       ADXRS450_TEMP1, &t);
320			if (ret)
321				break;
322			*val = (t >> 6) + 225;
323			ret = IIO_VAL_INT;
324			break;
325		default:
326			ret = -EINVAL;
327			break;
328		}
329		break;
330	case IIO_CHAN_INFO_SCALE:
331		switch (chan->type) {
332		case IIO_ANGL_VEL:
333			*val = 0;
334			*val2 = 218166;
335			return IIO_VAL_INT_PLUS_NANO;
336		case IIO_TEMP:
337			*val = 200;
338			*val2 = 0;
339			return IIO_VAL_INT;
340		default:
341			return -EINVAL;
342		}
343	case IIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW:
344		ret = adxrs450_spi_read_reg_16(indio_dev, ADXRS450_QUAD1, &t);
345		if (ret)
346			break;
347		*val = t;
348		ret = IIO_VAL_INT;
349		break;
350	case IIO_CHAN_INFO_CALIBBIAS:
351		ret = adxrs450_spi_read_reg_16(indio_dev, ADXRS450_DNC1, &t);
352		if (ret)
353			break;
354		*val = sign_extend32(t, 9);
355		ret = IIO_VAL_INT;
356		break;
357	default:
358		ret = -EINVAL;
359		break;
360	}
361
362	return ret;
363}
364
365static const struct iio_chan_spec adxrs450_channels[2][2] = {
366	[ID_ADXRS450] = {
367		{
368			.type = IIO_ANGL_VEL,
369			.modified = 1,
370			.channel2 = IIO_MOD_Z,
371			.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
372			BIT(IIO_CHAN_INFO_CALIBBIAS) |
373			BIT(IIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW) |
374			BIT(IIO_CHAN_INFO_SCALE),
375		}, {
376			.type = IIO_TEMP,
377			.indexed = 1,
378			.channel = 0,
379			.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
380			BIT(IIO_CHAN_INFO_SCALE),
381		}
382	},
383	[ID_ADXRS453] = {
384		{
385			.type = IIO_ANGL_VEL,
386			.modified = 1,
387			.channel2 = IIO_MOD_Z,
388			.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
389			BIT(IIO_CHAN_INFO_SCALE) |
390			BIT(IIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW),
391		}, {
392			.type = IIO_TEMP,
393			.indexed = 1,
394			.channel = 0,
395			.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
396			BIT(IIO_CHAN_INFO_SCALE),
397		}
398	},
399};
400
401static const struct iio_info adxrs450_info = {
402	.read_raw = &adxrs450_read_raw,
403	.write_raw = &adxrs450_write_raw,
404};
405
406static int adxrs450_probe(struct spi_device *spi)
407{
408	int ret;
409	struct adxrs450_state *st;
410	struct iio_dev *indio_dev;
411
412	/* setup the industrialio driver allocated elements */
413	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
414	if (!indio_dev)
415		return -ENOMEM;
416	st = iio_priv(indio_dev);
417	st->us = spi;
418	mutex_init(&st->buf_lock);
419	/* This is only used for removal purposes */
420	spi_set_drvdata(spi, indio_dev);
421
422	indio_dev->info = &adxrs450_info;
423	indio_dev->modes = INDIO_DIRECT_MODE;
424	indio_dev->channels =
425		adxrs450_channels[spi_get_device_id(spi)->driver_data];
426	indio_dev->num_channels = ARRAY_SIZE(adxrs450_channels);
427	indio_dev->name = spi->dev.driver->name;
428
429	ret = devm_iio_device_register(&spi->dev, indio_dev);
430	if (ret)
431		return ret;
432
433	/* Get the device into a sane initial state */
434	ret = adxrs450_initial_setup(indio_dev);
435	if (ret)
436		return ret;
437
438	return 0;
439}
440
441static const struct spi_device_id adxrs450_id[] = {
442	{"adxrs450", ID_ADXRS450},
443	{"adxrs453", ID_ADXRS453},
444	{ }
445};
446MODULE_DEVICE_TABLE(spi, adxrs450_id);
447
448static struct spi_driver adxrs450_driver = {
449	.driver = {
450		.name = "adxrs450",
451	},
452	.probe = adxrs450_probe,
453	.id_table	= adxrs450_id,
454};
455module_spi_driver(adxrs450_driver);
456
457MODULE_AUTHOR("Cliff Cai <cliff.cai@xxxxxxxxxx>");
458MODULE_DESCRIPTION("Analog Devices ADXRS450/ADXRS453 Gyroscope SPI driver");
459MODULE_LICENSE("GPL v2");