stm32-dac.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * This file is part of STM32 DAC driver
  4 *
  5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
  6 * Authors: Amelie Delaunay <amelie.delaunay@st.com>
  7 *	    Fabrice Gasnier <fabrice.gasnier@st.com>
  8 */
  9
 10#include <linux/bitfield.h>
 11#include <linux/delay.h>
 12#include <linux/iio/iio.h>
 13#include <linux/kernel.h>
 14#include <linux/kstrtox.h>
 15#include <linux/module.h>
 16#include <linux/mod_devicetable.h>
 17#include <linux/of.h>
 18#include <linux/platform_device.h>
 19#include <linux/pm_runtime.h>
 20#include <linux/string_choices.h>
 21
 22#include "stm32-dac-core.h"
 23
 24#define STM32_DAC_CHANNEL_1		1
 25#define STM32_DAC_CHANNEL_2		2
 26#define STM32_DAC_IS_CHAN_1(ch)		((ch) & STM32_DAC_CHANNEL_1)
 27
 28#define STM32_DAC_AUTO_SUSPEND_DELAY_MS	2000
 29
 30/**
 31 * struct stm32_dac - private data of DAC driver
 32 * @common:		reference to DAC common data
 33 * @lock:		lock to protect against potential races when reading
 34 *			and update CR, to keep it in sync with pm_runtime
 35 */
 36struct stm32_dac {
 37	struct stm32_dac_common *common;
 38	struct mutex		lock;
 39};
 40
 41static int stm32_dac_is_enabled(struct iio_dev *indio_dev, int channel)
 42{
 43	struct stm32_dac *dac = iio_priv(indio_dev);
 44	u32 en, val;
 45	int ret;
 46
 47	ret = regmap_read(dac->common->regmap, STM32_DAC_CR, &val);
 48	if (ret < 0)
 49		return ret;
 50	if (STM32_DAC_IS_CHAN_1(channel))
 51		en = FIELD_GET(STM32_DAC_CR_EN1, val);
 52	else
 53		en = FIELD_GET(STM32_DAC_CR_EN2, val);
 54
 55	return !!en;
 56}
 57
 58static int stm32_dac_set_enable_state(struct iio_dev *indio_dev, int ch,
 59				      bool enable)
 60{
 61	struct stm32_dac *dac = iio_priv(indio_dev);
 62	struct device *dev = indio_dev->dev.parent;
 63	u32 msk = STM32_DAC_IS_CHAN_1(ch) ? STM32_DAC_CR_EN1 : STM32_DAC_CR_EN2;
 64	u32 en = enable ? msk : 0;
 65	int ret;
 66
 67	/* already enabled / disabled ? */
 68	mutex_lock(&dac->lock);
 69	ret = stm32_dac_is_enabled(indio_dev, ch);
 70	if (ret < 0 || enable == !!ret) {
 71		mutex_unlock(&dac->lock);
 72		return ret < 0 ? ret : 0;
 73	}
 74
 75	if (enable) {
 76		ret = pm_runtime_resume_and_get(dev);
 77		if (ret < 0) {
 78			mutex_unlock(&dac->lock);
 79			return ret;
 80		}
 81	}
 82
 83	ret = regmap_update_bits(dac->common->regmap, STM32_DAC_CR, msk, en);
 84	mutex_unlock(&dac->lock);
 85	if (ret) {
 86		dev_err(&indio_dev->dev, "%s failed\n", str_enable_disable(en));
 87		if (enable)
 88			pm_runtime_put_autosuspend(dev);
 89		return ret;
 90	}
 91
 92	/*
 93	 * When HFSEL is set, it is not allowed to write the DHRx register
 94	 * during 8 clock cycles after the ENx bit is set. It is not allowed
 95	 * to make software/hardware trigger during this period either.
 96	 */
 97	if (en && dac->common->hfsel)
 98		udelay(1);
 99
100	if (!enable)
101		pm_runtime_put_autosuspend(dev);
102
103	return 0;
104}
105
106static int stm32_dac_get_value(struct stm32_dac *dac, int channel, int *val)
107{
108	int ret;
109
110	if (STM32_DAC_IS_CHAN_1(channel))
111		ret = regmap_read(dac->common->regmap, STM32_DAC_DOR1, val);
112	else
113		ret = regmap_read(dac->common->regmap, STM32_DAC_DOR2, val);
114
115	return ret ? ret : IIO_VAL_INT;
116}
117
118static int stm32_dac_set_value(struct stm32_dac *dac, int channel, int val)
119{
120	int ret;
121
122	if (STM32_DAC_IS_CHAN_1(channel))
123		ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R1, val);
124	else
125		ret = regmap_write(dac->common->regmap, STM32_DAC_DHR12R2, val);
126
127	return ret;
128}
129
130static int stm32_dac_read_raw(struct iio_dev *indio_dev,
131			      struct iio_chan_spec const *chan,
132			      int *val, int *val2, long mask)
133{
134	struct stm32_dac *dac = iio_priv(indio_dev);
135
136	switch (mask) {
137	case IIO_CHAN_INFO_RAW:
138		return stm32_dac_get_value(dac, chan->channel, val);
139	case IIO_CHAN_INFO_SCALE:
140		*val = dac->common->vref_mv;
141		*val2 = chan->scan_type.realbits;
142		return IIO_VAL_FRACTIONAL_LOG2;
143	default:
144		return -EINVAL;
145	}
146}
147
148static int stm32_dac_write_raw(struct iio_dev *indio_dev,
149			       struct iio_chan_spec const *chan,
150			       int val, int val2, long mask)
151{
152	struct stm32_dac *dac = iio_priv(indio_dev);
153
154	switch (mask) {
155	case IIO_CHAN_INFO_RAW:
156		return stm32_dac_set_value(dac, chan->channel, val);
157	default:
158		return -EINVAL;
159	}
160}
161
162static int stm32_dac_debugfs_reg_access(struct iio_dev *indio_dev,
163					unsigned reg, unsigned writeval,
164					unsigned *readval)
165{
166	struct stm32_dac *dac = iio_priv(indio_dev);
167
168	if (!readval)
169		return regmap_write(dac->common->regmap, reg, writeval);
170	else
171		return regmap_read(dac->common->regmap, reg, readval);
172}
173
174static const struct iio_info stm32_dac_iio_info = {
175	.read_raw = stm32_dac_read_raw,
176	.write_raw = stm32_dac_write_raw,
177	.debugfs_reg_access = stm32_dac_debugfs_reg_access,
178};
179
180static const char * const stm32_dac_powerdown_modes[] = {
181	"three_state",
182};
183
184static int stm32_dac_get_powerdown_mode(struct iio_dev *indio_dev,
185					const struct iio_chan_spec *chan)
186{
187	return 0;
188}
189
190static int stm32_dac_set_powerdown_mode(struct iio_dev *indio_dev,
191					const struct iio_chan_spec *chan,
192					unsigned int type)
193{
194	return 0;
195}
196
197static ssize_t stm32_dac_read_powerdown(struct iio_dev *indio_dev,
198					uintptr_t private,
199					const struct iio_chan_spec *chan,
200					char *buf)
201{
202	int ret = stm32_dac_is_enabled(indio_dev, chan->channel);
203
204	if (ret < 0)
205		return ret;
206
207	return sysfs_emit(buf, "%d\n", ret ? 0 : 1);
208}
209
210static ssize_t stm32_dac_write_powerdown(struct iio_dev *indio_dev,
211					 uintptr_t private,
212					 const struct iio_chan_spec *chan,
213					 const char *buf, size_t len)
214{
215	bool powerdown;
216	int ret;
217
218	ret = kstrtobool(buf, &powerdown);
219	if (ret)
220		return ret;
221
222	ret = stm32_dac_set_enable_state(indio_dev, chan->channel, !powerdown);
223	if (ret)
224		return ret;
225
226	return len;
227}
228
229static const struct iio_enum stm32_dac_powerdown_mode_en = {
230	.items = stm32_dac_powerdown_modes,
231	.num_items = ARRAY_SIZE(stm32_dac_powerdown_modes),
232	.get = stm32_dac_get_powerdown_mode,
233	.set = stm32_dac_set_powerdown_mode,
234};
235
236static const struct iio_chan_spec_ext_info stm32_dac_ext_info[] = {
237	{
238		.name = "powerdown",
239		.read = stm32_dac_read_powerdown,
240		.write = stm32_dac_write_powerdown,
241		.shared = IIO_SEPARATE,
242	},
243	IIO_ENUM("powerdown_mode", IIO_SEPARATE, &stm32_dac_powerdown_mode_en),
244	IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE, &stm32_dac_powerdown_mode_en),
245	{ }
246};
247
248#define STM32_DAC_CHANNEL(chan, name) {			\
249	.type = IIO_VOLTAGE,				\
250	.indexed = 1,					\
251	.output = 1,					\
252	.channel = chan,				\
253	.info_mask_separate =				\
254		BIT(IIO_CHAN_INFO_RAW) |		\
255		BIT(IIO_CHAN_INFO_SCALE),		\
256	/* scan_index is always 0 as num_channels is 1 */ \
257	.scan_type = {					\
258		.sign = 'u',				\
259		.realbits = 12,				\
260		.storagebits = 16,			\
261	},						\
262	.datasheet_name = name,				\
263	.ext_info = stm32_dac_ext_info			\
264}
265
266static const struct iio_chan_spec stm32_dac_channels[] = {
267	STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_1, "out1"),
268	STM32_DAC_CHANNEL(STM32_DAC_CHANNEL_2, "out2"),
269};
270
271static int stm32_dac_chan_of_init(struct iio_dev *indio_dev)
272{
273	struct device_node *np = indio_dev->dev.of_node;
274	unsigned int i;
275	u32 channel;
276	int ret;
277
278	ret = of_property_read_u32(np, "reg", &channel);
279	if (ret) {
280		dev_err(&indio_dev->dev, "Failed to read reg property\n");
281		return ret;
282	}
283
284	for (i = 0; i < ARRAY_SIZE(stm32_dac_channels); i++) {
285		if (stm32_dac_channels[i].channel == channel)
286			break;
287	}
288	if (i >= ARRAY_SIZE(stm32_dac_channels)) {
289		dev_err(&indio_dev->dev, "Invalid reg property\n");
290		return -EINVAL;
291	}
292
293	indio_dev->channels = &stm32_dac_channels[i];
294	/*
295	 * Expose only one channel here, as they can be used independently,
296	 * with separate trigger. Then separate IIO devices are instantiated
297	 * to manage this.
298	 */
299	indio_dev->num_channels = 1;
300
301	return 0;
302};
303
304static int stm32_dac_probe(struct platform_device *pdev)
305{
306	struct device_node *np = pdev->dev.of_node;
307	struct device *dev = &pdev->dev;
308	struct iio_dev *indio_dev;
309	struct stm32_dac *dac;
310	int ret;
311
312	if (!np)
313		return -ENODEV;
314
315	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*dac));
316	if (!indio_dev)
317		return -ENOMEM;
318	platform_set_drvdata(pdev, indio_dev);
319
320	dac = iio_priv(indio_dev);
321	dac->common = dev_get_drvdata(pdev->dev.parent);
322	indio_dev->name = dev_name(&pdev->dev);
323	indio_dev->dev.of_node = pdev->dev.of_node;
324	indio_dev->info = &stm32_dac_iio_info;
325	indio_dev->modes = INDIO_DIRECT_MODE;
326
327	mutex_init(&dac->lock);
328
329	ret = stm32_dac_chan_of_init(indio_dev);
330	if (ret < 0)
331		return ret;
332
333	/* Get stm32-dac-core PM online */
334	pm_runtime_get_noresume(dev);
335	pm_runtime_set_active(dev);
336	pm_runtime_set_autosuspend_delay(dev, STM32_DAC_AUTO_SUSPEND_DELAY_MS);
337	pm_runtime_use_autosuspend(dev);
338	pm_runtime_enable(dev);
339
340	ret = iio_device_register(indio_dev);
341	if (ret)
342		goto err_pm_put;
343
344	pm_runtime_put_autosuspend(dev);
345
346	return 0;
347
348err_pm_put:
349	pm_runtime_disable(dev);
350	pm_runtime_set_suspended(dev);
351	pm_runtime_put_noidle(dev);
352
353	return ret;
354}
355
356static void stm32_dac_remove(struct platform_device *pdev)
357{
358	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
359
360	pm_runtime_get_sync(&pdev->dev);
361	iio_device_unregister(indio_dev);
362	pm_runtime_disable(&pdev->dev);
363	pm_runtime_set_suspended(&pdev->dev);
364	pm_runtime_put_noidle(&pdev->dev);
365}
366
367static int stm32_dac_suspend(struct device *dev)
368{
369	struct iio_dev *indio_dev = dev_get_drvdata(dev);
370	int channel = indio_dev->channels[0].channel;
371	int ret;
372
373	/* Ensure DAC is disabled before suspend */
374	ret = stm32_dac_is_enabled(indio_dev, channel);
375	if (ret)
376		return ret < 0 ? ret : -EBUSY;
377
378	return pm_runtime_force_suspend(dev);
379}
380
381static DEFINE_SIMPLE_DEV_PM_OPS(stm32_dac_pm_ops, stm32_dac_suspend,
382				pm_runtime_force_resume);
383
384static const struct of_device_id stm32_dac_of_match[] = {
385	{ .compatible = "st,stm32-dac", },
386	{ }
387};
388MODULE_DEVICE_TABLE(of, stm32_dac_of_match);
389
390static struct platform_driver stm32_dac_driver = {
391	.probe = stm32_dac_probe,
392	.remove = stm32_dac_remove,
393	.driver = {
394		.name = "stm32-dac",
395		.of_match_table = stm32_dac_of_match,
396		.pm = pm_sleep_ptr(&stm32_dac_pm_ops),
397	},
398};
399module_platform_driver(stm32_dac_driver);
400
401MODULE_ALIAS("platform:stm32-dac");
402MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
403MODULE_DESCRIPTION("STMicroelectronics STM32 DAC driver");
404MODULE_LICENSE("GPL v2");