adi-axi-dac.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Analog Devices Generic AXI DAC IP core
   4 * Link: https://wiki.analog.com/resources/fpga/docs/axi_dac_ip
   5 *
   6 * Copyright 2016-2024 Analog Devices Inc.
   7 */
   8#include <linux/adi-axi-common.h>
   9#include <linux/bitfield.h>
  10#include <linux/bits.h>
  11#include <linux/cleanup.h>
  12#include <linux/clk.h>
  13#include <linux/device.h>
  14#include <linux/err.h>
  15#include <linux/limits.h>
  16#include <linux/kstrtox.h>
  17#include <linux/math.h>
  18#include <linux/math64.h>
  19#include <linux/module.h>
  20#include <linux/mod_devicetable.h>
  21#include <linux/mutex.h>
  22#include <linux/platform_device.h>
  23#include <linux/property.h>
  24#include <linux/regmap.h>
  25#include <linux/units.h>
  26
  27#include <linux/iio/backend.h>
  28#include <linux/iio/buffer-dmaengine.h>
  29#include <linux/iio/buffer.h>
  30#include <linux/iio/iio.h>
  31
  32#include "ad3552r-hs.h"
  33
  34/*
  35 * Register definitions:
  36 *   https://wiki.analog.com/resources/fpga/docs/axi_dac_ip#register_map
  37 */
  38
  39/* Base controls */
  40#define AXI_DAC_CONFIG_REG			0x0c
  41#define   AXI_DAC_CONFIG_DDS_DISABLE		BIT(6)
  42
  43 /* DAC controls */
  44#define AXI_DAC_RSTN_REG			0x0040
  45#define   AXI_DAC_RSTN_CE_N			BIT(2)
  46#define   AXI_DAC_RSTN_MMCM_RSTN		BIT(1)
  47#define   AXI_DAC_RSTN_RSTN			BIT(0)
  48#define AXI_DAC_CNTRL_1_REG			0x0044
  49#define   AXI_DAC_CNTRL_1_SYNC			BIT(0)
  50#define AXI_DAC_CNTRL_2_REG			0x0048
  51#define   AXI_DAC_CNTRL_2_SDR_DDR_N		BIT(16)
  52#define   AXI_DAC_CNTRL_2_SYMB_8B		BIT(14)
  53#define   ADI_DAC_CNTRL_2_R1_MODE		BIT(5)
  54#define   AXI_DAC_CNTRL_2_UNSIGNED_DATA		BIT(4)
  55#define AXI_DAC_STATUS_1_REG			0x0054
  56#define AXI_DAC_STATUS_2_REG			0x0058
  57#define AXI_DAC_DRP_STATUS_REG			0x0074
  58#define   AXI_DAC_DRP_STATUS_DRP_LOCKED		BIT(17)
  59#define AXI_DAC_CUSTOM_RD_REG			0x0080
  60#define AXI_DAC_CUSTOM_WR_REG			0x0084
  61#define   AXI_DAC_CUSTOM_WR_DATA_8		GENMASK(23, 16)
  62#define   AXI_DAC_CUSTOM_WR_DATA_16		GENMASK(23, 8)
  63#define AXI_DAC_UI_STATUS_REG			0x0088
  64#define   AXI_DAC_UI_STATUS_IF_BUSY		BIT(4)
  65#define AXI_DAC_CUSTOM_CTRL_REG			0x008C
  66#define   AXI_DAC_CUSTOM_CTRL_ADDRESS		GENMASK(31, 24)
  67#define   AXI_DAC_CUSTOM_CTRL_MULTI_IO_MODE	GENMASK(3, 2)
  68#define   AXI_DAC_CUSTOM_CTRL_STREAM		BIT(1)
  69#define   AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA	BIT(0)
  70
  71#define AXI_DAC_CUSTOM_CTRL_STREAM_ENABLE	(AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA | \
  72						 AXI_DAC_CUSTOM_CTRL_STREAM)
  73
  74/* DAC Channel controls */
  75#define AXI_DAC_CHAN_CNTRL_1_REG(c)		(0x0400 + (c) * 0x40)
  76#define AXI_DAC_CHAN_CNTRL_3_REG(c)		(0x0408 + (c) * 0x40)
  77#define   AXI_DAC_CHAN_CNTRL_3_SCALE_SIGN	BIT(15)
  78#define   AXI_DAC_CHAN_CNTRL_3_SCALE_INT	BIT(14)
  79#define   AXI_DAC_CHAN_CNTRL_3_SCALE		GENMASK(14, 0)
  80#define AXI_DAC_CHAN_CNTRL_2_REG(c)		(0x0404 + (c) * 0x40)
  81#define   AXI_DAC_CHAN_CNTRL_2_PHASE		GENMASK(31, 16)
  82#define   AXI_DAC_CHAN_CNTRL_2_FREQUENCY	GENMASK(15, 0)
  83#define AXI_DAC_CHAN_CNTRL_4_REG(c)		(0x040c + (c) * 0x40)
  84#define AXI_DAC_CHAN_CNTRL_7_REG(c)		(0x0418 + (c) * 0x40)
  85#define   AXI_DAC_CHAN_CNTRL_7_DATA_SEL		GENMASK(3, 0)
  86
  87#define AXI_DAC_CHAN_CNTRL_MAX			15
  88#define AXI_DAC_RD_ADDR(x)			(BIT(7) | (x))
  89
  90/* 360 degrees in rad */
  91#define AXI_DAC_2_PI_MEGA			6283190
  92
  93enum {
  94	AXI_DAC_DATA_INTERNAL_TONE,
  95	AXI_DAC_DATA_DMA = 2,
  96	AXI_DAC_DATA_INTERNAL_RAMP_16BIT = 11,
  97};
  98
  99struct axi_dac_info {
 100	unsigned int version;
 101	const struct iio_backend_info *backend_info;
 102	bool has_dac_clk;
 103	bool has_child_nodes;
 104};
 105
 106struct axi_dac_state {
 107	struct regmap *regmap;
 108	struct device *dev;
 109	/*
 110	 * lock to protect multiple accesses to the device registers and global
 111	 * data/variables.
 112	 */
 113	struct mutex lock;
 114	const struct axi_dac_info *info;
 115	u64 dac_clk;
 116	u32 reg_config;
 117	bool int_tone;
 118	int dac_clk_rate;
 119};
 120
 121static int axi_dac_enable(struct iio_backend *back)
 122{
 123	struct axi_dac_state *st = iio_backend_get_priv(back);
 124	unsigned int __val;
 125	int ret;
 126
 127	guard(mutex)(&st->lock);
 128	ret = regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG,
 129			      AXI_DAC_RSTN_MMCM_RSTN);
 130	if (ret)
 131		return ret;
 132	/*
 133	 * Make sure the DRP (Dynamic Reconfiguration Port) is locked. Not all
 134	 * designs really use it but if they don't we still get the lock bit
 135	 * set. So let's do it all the time so the code is generic.
 136	 */
 137	ret = regmap_read_poll_timeout(st->regmap, AXI_DAC_DRP_STATUS_REG,
 138				       __val,
 139				       __val & AXI_DAC_DRP_STATUS_DRP_LOCKED,
 140				       100, 1000);
 141	if (ret)
 142		return ret;
 143
 144	return regmap_set_bits(st->regmap, AXI_DAC_RSTN_REG,
 145			       AXI_DAC_RSTN_RSTN | AXI_DAC_RSTN_MMCM_RSTN);
 146}
 147
 148static void axi_dac_disable(struct iio_backend *back)
 149{
 150	struct axi_dac_state *st = iio_backend_get_priv(back);
 151
 152	guard(mutex)(&st->lock);
 153	regmap_write(st->regmap, AXI_DAC_RSTN_REG, 0);
 154}
 155
 156static struct iio_buffer *axi_dac_request_buffer(struct iio_backend *back,
 157						 struct iio_dev *indio_dev)
 158{
 159	struct axi_dac_state *st = iio_backend_get_priv(back);
 160	const char *dma_name;
 161
 162	if (device_property_read_string(st->dev, "dma-names", &dma_name))
 163		dma_name = "tx";
 164
 165	return iio_dmaengine_buffer_setup_ext(st->dev, indio_dev, dma_name,
 166					      IIO_BUFFER_DIRECTION_OUT);
 167}
 168
 169static void axi_dac_free_buffer(struct iio_backend *back,
 170				struct iio_buffer *buffer)
 171{
 172	iio_dmaengine_buffer_teardown(buffer);
 173}
 174
 175enum {
 176	AXI_DAC_FREQ_TONE_1,
 177	AXI_DAC_FREQ_TONE_2,
 178	AXI_DAC_SCALE_TONE_1,
 179	AXI_DAC_SCALE_TONE_2,
 180	AXI_DAC_PHASE_TONE_1,
 181	AXI_DAC_PHASE_TONE_2,
 182};
 183
 184static int __axi_dac_frequency_get(struct axi_dac_state *st, unsigned int chan,
 185				   unsigned int tone_2, unsigned int *freq)
 186{
 187	u32 reg, raw;
 188	int ret;
 189
 190	if (chan > AXI_DAC_CHAN_CNTRL_MAX)
 191		return -EINVAL;
 192
 193	if (!st->dac_clk) {
 194		dev_err(st->dev, "Sampling rate is 0...\n");
 195		return -EINVAL;
 196	}
 197
 198	if (tone_2)
 199		reg = AXI_DAC_CHAN_CNTRL_4_REG(chan);
 200	else
 201		reg = AXI_DAC_CHAN_CNTRL_2_REG(chan);
 202
 203	ret = regmap_read(st->regmap, reg, &raw);
 204	if (ret)
 205		return ret;
 206
 207	raw = FIELD_GET(AXI_DAC_CHAN_CNTRL_2_FREQUENCY, raw);
 208	*freq = DIV_ROUND_CLOSEST_ULL(raw * st->dac_clk, BIT(16));
 209
 210	return 0;
 211}
 212
 213static int axi_dac_frequency_get(struct axi_dac_state *st,
 214				 const struct iio_chan_spec *chan, char *buf,
 215				 unsigned int tone_2)
 216{
 217	unsigned int freq;
 218	int ret;
 219
 220	scoped_guard(mutex, &st->lock) {
 221		ret = __axi_dac_frequency_get(st, chan->channel, tone_2, &freq);
 222		if (ret)
 223			return ret;
 224	}
 225
 226	return sysfs_emit(buf, "%u\n", freq);
 227}
 228
 229static int axi_dac_scale_get(struct axi_dac_state *st,
 230			     const struct iio_chan_spec *chan, char *buf,
 231			     unsigned int tone_2)
 232{
 233	unsigned int scale, sign;
 234	int ret, vals[2];
 235	u32 reg, raw;
 236
 237	if (chan->channel > AXI_DAC_CHAN_CNTRL_MAX)
 238		return -EINVAL;
 239
 240	if (tone_2)
 241		reg = AXI_DAC_CHAN_CNTRL_3_REG(chan->channel);
 242	else
 243		reg = AXI_DAC_CHAN_CNTRL_1_REG(chan->channel);
 244
 245	ret = regmap_read(st->regmap, reg, &raw);
 246	if (ret)
 247		return ret;
 248
 249	sign = FIELD_GET(AXI_DAC_CHAN_CNTRL_3_SCALE_SIGN, raw);
 250	raw = FIELD_GET(AXI_DAC_CHAN_CNTRL_3_SCALE, raw);
 251	scale = DIV_ROUND_CLOSEST_ULL((u64)raw * MEGA,
 252				      AXI_DAC_CHAN_CNTRL_3_SCALE_INT);
 253
 254	vals[0] = scale / MEGA;
 255	vals[1] = scale % MEGA;
 256
 257	if (sign) {
 258		vals[0] *= -1;
 259		if (!vals[0])
 260			vals[1] *= -1;
 261	}
 262
 263	return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, ARRAY_SIZE(vals),
 264				vals);
 265}
 266
 267static int axi_dac_phase_get(struct axi_dac_state *st,
 268			     const struct iio_chan_spec *chan, char *buf,
 269			     unsigned int tone_2)
 270{
 271	u32 reg, raw, phase;
 272	int ret, vals[2];
 273
 274	if (chan->channel > AXI_DAC_CHAN_CNTRL_MAX)
 275		return -EINVAL;
 276
 277	if (tone_2)
 278		reg = AXI_DAC_CHAN_CNTRL_4_REG(chan->channel);
 279	else
 280		reg = AXI_DAC_CHAN_CNTRL_2_REG(chan->channel);
 281
 282	ret = regmap_read(st->regmap, reg, &raw);
 283	if (ret)
 284		return ret;
 285
 286	raw = FIELD_GET(AXI_DAC_CHAN_CNTRL_2_PHASE, raw);
 287	phase = DIV_ROUND_CLOSEST_ULL((u64)raw * AXI_DAC_2_PI_MEGA, U16_MAX);
 288
 289	vals[0] = phase / MEGA;
 290	vals[1] = phase % MEGA;
 291
 292	return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, ARRAY_SIZE(vals),
 293				vals);
 294}
 295
 296static int __axi_dac_frequency_set(struct axi_dac_state *st, unsigned int chan,
 297				   u64 sample_rate, unsigned int freq,
 298				   unsigned int tone_2)
 299{
 300	u32 reg;
 301	u16 raw;
 302	int ret;
 303
 304	if (chan > AXI_DAC_CHAN_CNTRL_MAX)
 305		return -EINVAL;
 306
 307	if (!sample_rate || freq > sample_rate / 2) {
 308		dev_err(st->dev, "Invalid frequency(%u) dac_clk(%llu)\n",
 309			freq, sample_rate);
 310		return -EINVAL;
 311	}
 312
 313	if (tone_2)
 314		reg = AXI_DAC_CHAN_CNTRL_4_REG(chan);
 315	else
 316		reg = AXI_DAC_CHAN_CNTRL_2_REG(chan);
 317
 318	raw = DIV64_U64_ROUND_CLOSEST((u64)freq * BIT(16), sample_rate);
 319
 320	ret = regmap_update_bits(st->regmap, reg,
 321				 AXI_DAC_CHAN_CNTRL_2_FREQUENCY, raw);
 322	if (ret)
 323		return ret;
 324
 325	/* synchronize channels */
 326	return regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG,
 327			       AXI_DAC_CNTRL_1_SYNC);
 328}
 329
 330static int axi_dac_frequency_set(struct axi_dac_state *st,
 331				 const struct iio_chan_spec *chan,
 332				 const char *buf, size_t len, unsigned int tone_2)
 333{
 334	unsigned int freq;
 335	int ret;
 336
 337	ret = kstrtou32(buf, 10, &freq);
 338	if (ret)
 339		return ret;
 340
 341	guard(mutex)(&st->lock);
 342	ret = __axi_dac_frequency_set(st, chan->channel, st->dac_clk, freq,
 343				      tone_2);
 344	if (ret)
 345		return ret;
 346
 347	return len;
 348}
 349
 350static int axi_dac_scale_set(struct axi_dac_state *st,
 351			     const struct iio_chan_spec *chan,
 352			     const char *buf, size_t len, unsigned int tone_2)
 353{
 354	int integer, frac, scale;
 355	u32 raw = 0, reg;
 356	int ret;
 357
 358	if (chan->channel > AXI_DAC_CHAN_CNTRL_MAX)
 359		return -EINVAL;
 360
 361	ret = iio_str_to_fixpoint(buf, 100000, &integer, &frac);
 362	if (ret)
 363		return ret;
 364
 365	scale = integer * MEGA + frac;
 366	if (scale <= -2 * (int)MEGA || scale >= 2 * (int)MEGA)
 367		return -EINVAL;
 368
 369	/*  format is 1.1.14 (sign, integer and fractional bits) */
 370	if (scale < 0) {
 371		raw = FIELD_PREP(AXI_DAC_CHAN_CNTRL_3_SCALE_SIGN, 1);
 372		scale *= -1;
 373	}
 374
 375	raw |= div_u64((u64)scale * AXI_DAC_CHAN_CNTRL_3_SCALE_INT, MEGA);
 376
 377	if (tone_2)
 378		reg = AXI_DAC_CHAN_CNTRL_3_REG(chan->channel);
 379	else
 380		reg = AXI_DAC_CHAN_CNTRL_1_REG(chan->channel);
 381
 382	guard(mutex)(&st->lock);
 383	ret = regmap_write(st->regmap, reg, raw);
 384	if (ret)
 385		return ret;
 386
 387	/* synchronize channels */
 388	ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG,
 389			      AXI_DAC_CNTRL_1_SYNC);
 390	if (ret)
 391		return ret;
 392
 393	return len;
 394}
 395
 396static int axi_dac_phase_set(struct axi_dac_state *st,
 397			     const struct iio_chan_spec *chan,
 398			     const char *buf, size_t len, unsigned int tone_2)
 399{
 400	int integer, frac, phase;
 401	u32 raw, reg;
 402	int ret;
 403
 404	if (chan->channel > AXI_DAC_CHAN_CNTRL_MAX)
 405		return -EINVAL;
 406
 407	ret = iio_str_to_fixpoint(buf, 100000, &integer, &frac);
 408	if (ret)
 409		return ret;
 410
 411	phase = integer * MEGA + frac;
 412	if (phase < 0 || phase > AXI_DAC_2_PI_MEGA)
 413		return -EINVAL;
 414
 415	raw = DIV_ROUND_CLOSEST_ULL((u64)phase * U16_MAX, AXI_DAC_2_PI_MEGA);
 416
 417	if (tone_2)
 418		reg = AXI_DAC_CHAN_CNTRL_4_REG(chan->channel);
 419	else
 420		reg = AXI_DAC_CHAN_CNTRL_2_REG(chan->channel);
 421
 422	guard(mutex)(&st->lock);
 423	ret = regmap_update_bits(st->regmap, reg, AXI_DAC_CHAN_CNTRL_2_PHASE,
 424				 FIELD_PREP(AXI_DAC_CHAN_CNTRL_2_PHASE, raw));
 425	if (ret)
 426		return ret;
 427
 428	/* synchronize channels */
 429	ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_1_REG,
 430			      AXI_DAC_CNTRL_1_SYNC);
 431	if (ret)
 432		return ret;
 433
 434	return len;
 435}
 436
 437static int axi_dac_ext_info_set(struct iio_backend *back, uintptr_t private,
 438				const struct iio_chan_spec *chan,
 439				const char *buf, size_t len)
 440{
 441	struct axi_dac_state *st = iio_backend_get_priv(back);
 442
 443	switch (private) {
 444	case AXI_DAC_FREQ_TONE_1:
 445	case AXI_DAC_FREQ_TONE_2:
 446		return axi_dac_frequency_set(st, chan, buf, len,
 447					     private == AXI_DAC_FREQ_TONE_2);
 448	case AXI_DAC_SCALE_TONE_1:
 449	case AXI_DAC_SCALE_TONE_2:
 450		return axi_dac_scale_set(st, chan, buf, len,
 451					 private == AXI_DAC_SCALE_TONE_2);
 452	case AXI_DAC_PHASE_TONE_1:
 453	case AXI_DAC_PHASE_TONE_2:
 454		return axi_dac_phase_set(st, chan, buf, len,
 455					 private == AXI_DAC_PHASE_TONE_2);
 456	default:
 457		return -EOPNOTSUPP;
 458	}
 459}
 460
 461static int axi_dac_ext_info_get(struct iio_backend *back, uintptr_t private,
 462				const struct iio_chan_spec *chan, char *buf)
 463{
 464	struct axi_dac_state *st = iio_backend_get_priv(back);
 465
 466	switch (private) {
 467	case AXI_DAC_FREQ_TONE_1:
 468	case AXI_DAC_FREQ_TONE_2:
 469		return axi_dac_frequency_get(st, chan, buf,
 470					     private - AXI_DAC_FREQ_TONE_1);
 471	case AXI_DAC_SCALE_TONE_1:
 472	case AXI_DAC_SCALE_TONE_2:
 473		return axi_dac_scale_get(st, chan, buf,
 474					 private - AXI_DAC_SCALE_TONE_1);
 475	case AXI_DAC_PHASE_TONE_1:
 476	case AXI_DAC_PHASE_TONE_2:
 477		return axi_dac_phase_get(st, chan, buf,
 478					 private - AXI_DAC_PHASE_TONE_1);
 479	default:
 480		return -EOPNOTSUPP;
 481	}
 482}
 483
 484static const struct iio_chan_spec_ext_info axi_dac_ext_info[] = {
 485	IIO_BACKEND_EX_INFO("frequency0", IIO_SEPARATE, AXI_DAC_FREQ_TONE_1),
 486	IIO_BACKEND_EX_INFO("frequency1", IIO_SEPARATE, AXI_DAC_FREQ_TONE_2),
 487	IIO_BACKEND_EX_INFO("scale0", IIO_SEPARATE, AXI_DAC_SCALE_TONE_1),
 488	IIO_BACKEND_EX_INFO("scale1", IIO_SEPARATE, AXI_DAC_SCALE_TONE_2),
 489	IIO_BACKEND_EX_INFO("phase0", IIO_SEPARATE, AXI_DAC_PHASE_TONE_1),
 490	IIO_BACKEND_EX_INFO("phase1", IIO_SEPARATE, AXI_DAC_PHASE_TONE_2),
 491	{ }
 492};
 493
 494static int axi_dac_extend_chan(struct iio_backend *back,
 495			       struct iio_chan_spec *chan)
 496{
 497	struct axi_dac_state *st = iio_backend_get_priv(back);
 498
 499	if (chan->type != IIO_ALTVOLTAGE)
 500		return -EINVAL;
 501	if (st->reg_config & AXI_DAC_CONFIG_DDS_DISABLE)
 502		/* nothing to extend */
 503		return 0;
 504
 505	chan->ext_info = axi_dac_ext_info;
 506
 507	return 0;
 508}
 509
 510static int axi_dac_data_source_set(struct iio_backend *back, unsigned int chan,
 511				   enum iio_backend_data_source data)
 512{
 513	struct axi_dac_state *st = iio_backend_get_priv(back);
 514
 515	if (chan > AXI_DAC_CHAN_CNTRL_MAX)
 516		return -EINVAL;
 517
 518	switch (data) {
 519	case IIO_BACKEND_INTERNAL_CONTINUOUS_WAVE:
 520		return regmap_update_bits(st->regmap,
 521					  AXI_DAC_CHAN_CNTRL_7_REG(chan),
 522					  AXI_DAC_CHAN_CNTRL_7_DATA_SEL,
 523					  AXI_DAC_DATA_INTERNAL_TONE);
 524	case IIO_BACKEND_EXTERNAL:
 525		return regmap_update_bits(st->regmap,
 526					  AXI_DAC_CHAN_CNTRL_7_REG(chan),
 527					  AXI_DAC_CHAN_CNTRL_7_DATA_SEL,
 528					  AXI_DAC_DATA_DMA);
 529	case IIO_BACKEND_INTERNAL_RAMP_16BIT:
 530		return regmap_update_bits(st->regmap,
 531					  AXI_DAC_CHAN_CNTRL_7_REG(chan),
 532					  AXI_DAC_CHAN_CNTRL_7_DATA_SEL,
 533					  AXI_DAC_DATA_INTERNAL_RAMP_16BIT);
 534	default:
 535		return -EINVAL;
 536	}
 537}
 538
 539static int axi_dac_data_source_get(struct iio_backend *back, unsigned int chan,
 540				   enum iio_backend_data_source *data)
 541{
 542	struct axi_dac_state *st = iio_backend_get_priv(back);
 543	int ret;
 544	u32 val;
 545
 546	if (chan > AXI_DAC_CHAN_CNTRL_MAX)
 547		return -EINVAL;
 548
 549	ret = regmap_read(st->regmap, AXI_DAC_CHAN_CNTRL_7_REG(chan), &val);
 550	if (ret)
 551		return ret;
 552
 553	switch (val) {
 554	case AXI_DAC_DATA_INTERNAL_TONE:
 555		*data = IIO_BACKEND_INTERNAL_CONTINUOUS_WAVE;
 556		return 0;
 557	case AXI_DAC_DATA_DMA:
 558		*data = IIO_BACKEND_EXTERNAL;
 559		return 0;
 560	case AXI_DAC_DATA_INTERNAL_RAMP_16BIT:
 561		*data = IIO_BACKEND_INTERNAL_RAMP_16BIT;
 562		return 0;
 563	default:
 564		return -EIO;
 565	}
 566}
 567
 568static int axi_dac_set_sample_rate(struct iio_backend *back, unsigned int chan,
 569				   u64 sample_rate)
 570{
 571	struct axi_dac_state *st = iio_backend_get_priv(back);
 572	unsigned int freq;
 573	int ret, tone;
 574
 575	if (chan > AXI_DAC_CHAN_CNTRL_MAX)
 576		return -EINVAL;
 577	if (!sample_rate)
 578		return -EINVAL;
 579	if (st->reg_config & AXI_DAC_CONFIG_DDS_DISABLE)
 580		/* sample_rate has no meaning if DDS is disabled */
 581		return 0;
 582
 583	guard(mutex)(&st->lock);
 584	/*
 585	 * If dac_clk is 0 then this must be the first time we're being notified
 586	 * about the interface sample rate. Hence, just update our internal
 587	 * variable and bail... If it's not 0, then we get the current DDS
 588	 * frequency (for the old rate) and update the registers for the new
 589	 * sample rate.
 590	 */
 591	if (!st->dac_clk) {
 592		st->dac_clk = sample_rate;
 593		return 0;
 594	}
 595
 596	for (tone = 0; tone <= AXI_DAC_FREQ_TONE_2; tone++) {
 597		ret = __axi_dac_frequency_get(st, chan, tone, &freq);
 598		if (ret)
 599			return ret;
 600
 601		ret = __axi_dac_frequency_set(st, chan, sample_rate, tone, freq);
 602		if (ret)
 603			return ret;
 604	}
 605
 606	st->dac_clk = sample_rate;
 607
 608	return 0;
 609}
 610
 611static int axi_dac_reg_access(struct iio_backend *back, unsigned int reg,
 612			      unsigned int writeval, unsigned int *readval)
 613{
 614	struct axi_dac_state *st = iio_backend_get_priv(back);
 615
 616	if (readval)
 617		return regmap_read(st->regmap, reg, readval);
 618
 619	return regmap_write(st->regmap, reg, writeval);
 620}
 621
 622static int axi_dac_ddr_enable(struct iio_backend *back)
 623{
 624	struct axi_dac_state *st = iio_backend_get_priv(back);
 625
 626	return regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG,
 627				 AXI_DAC_CNTRL_2_SDR_DDR_N);
 628}
 629
 630static int axi_dac_ddr_disable(struct iio_backend *back)
 631{
 632	struct axi_dac_state *st = iio_backend_get_priv(back);
 633
 634	return regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG,
 635			       AXI_DAC_CNTRL_2_SDR_DDR_N);
 636}
 637
 638static int axi_dac_wait_bus_free(struct axi_dac_state *st)
 639{
 640	u32 val;
 641	int ret;
 642
 643	ret = regmap_read_poll_timeout(st->regmap, AXI_DAC_UI_STATUS_REG, val,
 644		FIELD_GET(AXI_DAC_UI_STATUS_IF_BUSY, val) == 0, 10,
 645		100 * KILO);
 646	if (ret == -ETIMEDOUT)
 647		dev_err(st->dev, "AXI bus timeout\n");
 648
 649	return ret;
 650}
 651
 652static int axi_dac_data_stream_enable(struct iio_backend *back)
 653{
 654	struct axi_dac_state *st = iio_backend_get_priv(back);
 655	int ret;
 656
 657	ret = axi_dac_wait_bus_free(st);
 658	if (ret)
 659		return ret;
 660
 661	return regmap_set_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
 662			       AXI_DAC_CUSTOM_CTRL_STREAM_ENABLE);
 663}
 664
 665static int axi_dac_data_stream_disable(struct iio_backend *back)
 666{
 667	struct axi_dac_state *st = iio_backend_get_priv(back);
 668
 669	return regmap_clear_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
 670				 AXI_DAC_CUSTOM_CTRL_STREAM_ENABLE);
 671}
 672
 673static int axi_dac_data_transfer_addr(struct iio_backend *back, u32 address)
 674{
 675	struct axi_dac_state *st = iio_backend_get_priv(back);
 676
 677	if (address > FIELD_MAX(AXI_DAC_CUSTOM_CTRL_ADDRESS))
 678		return -EINVAL;
 679
 680	/*
 681	 * Sample register address, when the DAC is configured, or stream
 682	 * start address when the FSM is in stream state.
 683	 */
 684	return regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
 685				  AXI_DAC_CUSTOM_CTRL_ADDRESS,
 686				  FIELD_PREP(AXI_DAC_CUSTOM_CTRL_ADDRESS,
 687				  address));
 688}
 689
 690static int axi_dac_data_format_set(struct iio_backend *back, unsigned int ch,
 691				   const struct iio_backend_data_fmt *data)
 692{
 693	struct axi_dac_state *st = iio_backend_get_priv(back);
 694
 695	switch (data->type) {
 696	case IIO_BACKEND_DATA_UNSIGNED:
 697		return regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG,
 698					 AXI_DAC_CNTRL_2_UNSIGNED_DATA);
 699	default:
 700		return -EINVAL;
 701	}
 702}
 703
 704static int __axi_dac_bus_reg_write(struct iio_backend *back, u32 reg,
 705				 u32 val, size_t data_size)
 706{
 707	struct axi_dac_state *st = iio_backend_get_priv(back);
 708	int ret;
 709	u32 ival;
 710
 711	/*
 712	 * Both AXI_DAC_CNTRL_2_REG and AXI_DAC_CUSTOM_WR_REG need to know
 713	 * the data size. So keeping data size control here only,
 714	 * since data size is mandatory for the current transfer.
 715	 * DDR state handled separately by specific backend calls,
 716	 * generally all raw register writes are SDR.
 717	 */
 718	if (data_size == sizeof(u16))
 719		ival = FIELD_PREP(AXI_DAC_CUSTOM_WR_DATA_16, val);
 720	else
 721		ival = FIELD_PREP(AXI_DAC_CUSTOM_WR_DATA_8, val);
 722
 723	ret = regmap_write(st->regmap, AXI_DAC_CUSTOM_WR_REG, ival);
 724	if (ret)
 725		return ret;
 726
 727	if (data_size == sizeof(u8))
 728		ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG,
 729				      AXI_DAC_CNTRL_2_SYMB_8B);
 730	else
 731		ret = regmap_clear_bits(st->regmap, AXI_DAC_CNTRL_2_REG,
 732					AXI_DAC_CNTRL_2_SYMB_8B);
 733	if (ret)
 734		return ret;
 735
 736	ret = regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
 737				 AXI_DAC_CUSTOM_CTRL_ADDRESS,
 738				 FIELD_PREP(AXI_DAC_CUSTOM_CTRL_ADDRESS, reg));
 739	if (ret)
 740		return ret;
 741
 742	ret = regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
 743				 AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA,
 744				 AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA);
 745	if (ret)
 746		return ret;
 747
 748	ret = axi_dac_wait_bus_free(st);
 749	if (ret)
 750		return ret;
 751
 752	/* Cleaning always AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA */
 753	return regmap_clear_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
 754				 AXI_DAC_CUSTOM_CTRL_TRANSFER_DATA);
 755}
 756
 757static int axi_dac_bus_reg_write(struct iio_backend *back, u32 reg,
 758					u32 val, size_t data_size)
 759{
 760	struct axi_dac_state *st = iio_backend_get_priv(back);
 761
 762	guard(mutex)(&st->lock);
 763	return __axi_dac_bus_reg_write(back, reg, val, data_size);
 764}
 765
 766static int axi_dac_bus_reg_read(struct iio_backend *back, u32 reg, u32 *val,
 767				size_t data_size)
 768{
 769	struct axi_dac_state *st = iio_backend_get_priv(back);
 770	int ret;
 771
 772	guard(mutex)(&st->lock);
 773
 774	/*
 775	 * SPI, we write with read flag, then we read just at the AXI
 776	 * io address space to get data read.
 777	 */
 778	ret = __axi_dac_bus_reg_write(back, AXI_DAC_RD_ADDR(reg), 0,
 779				      data_size);
 780	if (ret)
 781		return ret;
 782
 783	ret = axi_dac_wait_bus_free(st);
 784	if (ret)
 785		return ret;
 786
 787	return regmap_read(st->regmap, AXI_DAC_CUSTOM_RD_REG, val);
 788}
 789
 790static int axi_dac_bus_set_io_mode(struct iio_backend *back,
 791				   enum ad3552r_io_mode mode)
 792{
 793	struct axi_dac_state *st = iio_backend_get_priv(back);
 794	int ret;
 795
 796	if (mode > AD3552R_IO_MODE_QSPI)
 797		return -EINVAL;
 798
 799	guard(mutex)(&st->lock);
 800
 801	ret = regmap_update_bits(st->regmap, AXI_DAC_CUSTOM_CTRL_REG,
 802			AXI_DAC_CUSTOM_CTRL_MULTI_IO_MODE,
 803			FIELD_PREP(AXI_DAC_CUSTOM_CTRL_MULTI_IO_MODE, mode));
 804	if (ret)
 805		return ret;
 806
 807	return axi_dac_wait_bus_free(st);
 808}
 809
 810static void axi_dac_child_remove(void *data)
 811{
 812	platform_device_unregister(data);
 813}
 814
 815static int axi_dac_create_platform_device(struct axi_dac_state *st,
 816					  struct fwnode_handle *child)
 817{
 818	struct ad3552r_hs_platform_data pdata = {
 819		.bus_reg_read = axi_dac_bus_reg_read,
 820		.bus_reg_write = axi_dac_bus_reg_write,
 821		.bus_set_io_mode = axi_dac_bus_set_io_mode,
 822		.bus_sample_data_clock_hz = st->dac_clk_rate,
 823	};
 824	struct platform_device_info pi = {
 825		.parent = st->dev,
 826		.name = fwnode_get_name(child),
 827		.id = PLATFORM_DEVID_AUTO,
 828		.fwnode = child,
 829		.data = &pdata,
 830		.size_data = sizeof(pdata),
 831	};
 832	struct platform_device *pdev;
 833
 834	pdev = platform_device_register_full(&pi);
 835	if (IS_ERR(pdev))
 836		return PTR_ERR(pdev);
 837
 838	return devm_add_action_or_reset(st->dev, axi_dac_child_remove, pdev);
 839}
 840
 841static const struct iio_backend_ops axi_dac_generic_ops = {
 842	.enable = axi_dac_enable,
 843	.disable = axi_dac_disable,
 844	.request_buffer = axi_dac_request_buffer,
 845	.free_buffer = axi_dac_free_buffer,
 846	.extend_chan_spec = axi_dac_extend_chan,
 847	.ext_info_set = axi_dac_ext_info_set,
 848	.ext_info_get = axi_dac_ext_info_get,
 849	.data_source_set = axi_dac_data_source_set,
 850	.set_sample_rate = axi_dac_set_sample_rate,
 851	.debugfs_reg_access = iio_backend_debugfs_ptr(axi_dac_reg_access),
 852};
 853
 854static const struct iio_backend_ops axi_ad3552r_ops = {
 855	.enable = axi_dac_enable,
 856	.disable = axi_dac_disable,
 857	.request_buffer = axi_dac_request_buffer,
 858	.free_buffer = axi_dac_free_buffer,
 859	.data_source_set = axi_dac_data_source_set,
 860	.data_source_get = axi_dac_data_source_get,
 861	.ddr_enable = axi_dac_ddr_enable,
 862	.ddr_disable = axi_dac_ddr_disable,
 863	.data_stream_enable = axi_dac_data_stream_enable,
 864	.data_stream_disable = axi_dac_data_stream_disable,
 865	.data_format_set = axi_dac_data_format_set,
 866	.data_transfer_addr = axi_dac_data_transfer_addr,
 867};
 868
 869static const struct iio_backend_info axi_dac_generic = {
 870	.name = "axi-dac",
 871	.ops = &axi_dac_generic_ops,
 872};
 873
 874static const struct iio_backend_info axi_ad3552r = {
 875	.name = "axi-ad3552r",
 876	.ops = &axi_ad3552r_ops,
 877};
 878
 879static const struct regmap_config axi_dac_regmap_config = {
 880	.val_bits = 32,
 881	.reg_bits = 32,
 882	.reg_stride = 4,
 883	.max_register = 0x0800,
 884};
 885
 886static int axi_dac_probe(struct platform_device *pdev)
 887{
 888	struct axi_dac_state *st;
 889	void __iomem *base;
 890	unsigned int ver;
 891	struct clk *clk;
 892	int ret;
 893
 894	st = devm_kzalloc(&pdev->dev, sizeof(*st), GFP_KERNEL);
 895	if (!st)
 896		return -ENOMEM;
 897
 898	st->info = device_get_match_data(&pdev->dev);
 899	if (!st->info)
 900		return -ENODEV;
 901	clk = devm_clk_get_enabled(&pdev->dev, "s_axi_aclk");
 902	if (IS_ERR(clk)) {
 903		/* Backward compat., old fdt versions without clock-names. */
 904		clk = devm_clk_get_enabled(&pdev->dev, NULL);
 905		if (IS_ERR(clk))
 906			return dev_err_probe(&pdev->dev, PTR_ERR(clk),
 907					"failed to get clock\n");
 908	}
 909
 910	if (st->info->has_dac_clk) {
 911		struct clk *dac_clk;
 912
 913		dac_clk = devm_clk_get_enabled(&pdev->dev, "dac_clk");
 914		if (IS_ERR(dac_clk))
 915			return dev_err_probe(&pdev->dev, PTR_ERR(dac_clk),
 916					     "failed to get dac_clk clock\n");
 917
 918		/* We only care about the streaming mode rate */
 919		st->dac_clk_rate = clk_get_rate(dac_clk) / 2;
 920	}
 921
 922	base = devm_platform_ioremap_resource(pdev, 0);
 923	if (IS_ERR(base))
 924		return PTR_ERR(base);
 925
 926	st->dev = &pdev->dev;
 927	st->regmap = devm_regmap_init_mmio(&pdev->dev, base,
 928					   &axi_dac_regmap_config);
 929	if (IS_ERR(st->regmap))
 930		return dev_err_probe(&pdev->dev, PTR_ERR(st->regmap),
 931				     "failed to init register map\n");
 932
 933	/*
 934	 * Force disable the core. Up to the frontend to enable us. And we can
 935	 * still read/write registers...
 936	 */
 937	ret = regmap_write(st->regmap, AXI_DAC_RSTN_REG, 0);
 938	if (ret)
 939		return ret;
 940
 941	ret = regmap_read(st->regmap, ADI_AXI_REG_VERSION, &ver);
 942	if (ret)
 943		return ret;
 944
 945	if (ADI_AXI_PCORE_VER_MAJOR(ver) !=
 946		ADI_AXI_PCORE_VER_MAJOR(st->info->version)) {
 947		dev_err(&pdev->dev,
 948			"Major version mismatch. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n",
 949			ADI_AXI_PCORE_VER_MAJOR(st->info->version),
 950			ADI_AXI_PCORE_VER_MINOR(st->info->version),
 951			ADI_AXI_PCORE_VER_PATCH(st->info->version),
 952			ADI_AXI_PCORE_VER_MAJOR(ver),
 953			ADI_AXI_PCORE_VER_MINOR(ver),
 954			ADI_AXI_PCORE_VER_PATCH(ver));
 955		return -ENODEV;
 956	}
 957
 958	/* Let's get the core read only configuration */
 959	ret = regmap_read(st->regmap, AXI_DAC_CONFIG_REG, &st->reg_config);
 960	if (ret)
 961		return ret;
 962
 963	/*
 964	 * In some designs, setting the R1_MODE bit to 0 (which is the default
 965	 * value) causes all channels of the frontend to be routed to the same
 966	 * DMA (so they are sampled together). This is for things like
 967	 * Multiple-Input and Multiple-Output (MIMO). As most of the times we
 968	 * want independent channels let's override the core's default value and
 969	 * set the R1_MODE bit.
 970	 */
 971	ret = regmap_set_bits(st->regmap, AXI_DAC_CNTRL_2_REG,
 972			      ADI_DAC_CNTRL_2_R1_MODE);
 973	if (ret)
 974		return ret;
 975
 976	mutex_init(&st->lock);
 977
 978	ret = devm_iio_backend_register(&pdev->dev, st->info->backend_info, st);
 979	if (ret)
 980		return dev_err_probe(&pdev->dev, ret,
 981				     "failed to register iio backend\n");
 982
 983	device_for_each_child_node_scoped(&pdev->dev, child) {
 984		int val;
 985
 986		if (!st->info->has_child_nodes)
 987			return dev_err_probe(&pdev->dev, -EINVAL,
 988					     "invalid fdt axi-dac compatible.");
 989
 990		/* Processing only reg 0 node */
 991		ret = fwnode_property_read_u32(child, "reg", &val);
 992		if (ret)
 993			return dev_err_probe(&pdev->dev, ret,
 994						"invalid reg property.");
 995		if (val != 0)
 996			return dev_err_probe(&pdev->dev, -EINVAL,
 997						"invalid node address.");
 998
 999		ret = axi_dac_create_platform_device(st, child);
1000		if (ret)
1001			return dev_err_probe(&pdev->dev, -EINVAL,
1002						"cannot create device.");
1003	}
1004
1005	dev_info(&pdev->dev, "AXI DAC IP core (%d.%.2d.%c) probed\n",
1006		 ADI_AXI_PCORE_VER_MAJOR(ver),
1007		 ADI_AXI_PCORE_VER_MINOR(ver),
1008		 ADI_AXI_PCORE_VER_PATCH(ver));
1009
1010	return 0;
1011}
1012
1013static const struct axi_dac_info dac_generic = {
1014	.version = ADI_AXI_PCORE_VER(9, 1, 'b'),
1015	.backend_info = &axi_dac_generic,
1016};
1017
1018static const struct axi_dac_info dac_ad3552r = {
1019	.version = ADI_AXI_PCORE_VER(9, 1, 'b'),
1020	.backend_info = &axi_ad3552r,
1021	.has_dac_clk = true,
1022	.has_child_nodes = true,
1023};
1024
1025static const struct of_device_id axi_dac_of_match[] = {
1026	{ .compatible = "adi,axi-dac-9.1.b", .data = &dac_generic },
1027	{ .compatible = "adi,axi-ad3552r", .data = &dac_ad3552r },
1028	{ }
1029};
1030MODULE_DEVICE_TABLE(of, axi_dac_of_match);
1031
1032static struct platform_driver axi_dac_driver = {
1033	.driver = {
1034		.name = "adi-axi-dac",
1035		.of_match_table = axi_dac_of_match,
1036	},
1037	.probe = axi_dac_probe,
1038};
1039module_platform_driver(axi_dac_driver);
1040
1041MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>");
1042MODULE_DESCRIPTION("Analog Devices Generic AXI DAC IP core driver");
1043MODULE_LICENSE("GPL");
1044MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER");
1045MODULE_IMPORT_NS("IIO_BACKEND");