ad8460.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * AD8460 Waveform generator DAC Driver
  4 *
  5 * Copyright (C) 2024 Analog Devices, Inc.
  6 */
  7
  8#include <linux/bitfield.h>
  9#include <linux/cleanup.h>
 10#include <linux/clk.h>
 11#include <linux/debugfs.h>
 12#include <linux/delay.h>
 13#include <linux/dmaengine.h>
 14#include <linux/gpio/consumer.h>
 15#include <linux/kernel.h>
 16#include <linux/module.h>
 17#include <linux/mod_devicetable.h>
 18#include <linux/regmap.h>
 19#include <linux/regulator/consumer.h>
 20#include <linux/spi/spi.h>
 21
 22#include <linux/iio/buffer.h>
 23#include <linux/iio/buffer-dma.h>
 24#include <linux/iio/buffer-dmaengine.h>
 25#include <linux/iio/consumer.h>
 26#include <linux/iio/events.h>
 27#include <linux/iio/iio.h>
 28
 29#define AD8460_CTRL_REG(x)			(x)
 30#define AD8460_HVDAC_DATA_WORD(x)		(0x60 + (2 * (x)))
 31
 32#define AD8460_HV_RESET_MSK			BIT(7)
 33#define AD8460_HV_SLEEP_MSK			BIT(4)
 34#define AD8460_WAVE_GEN_MODE_MSK		BIT(0)
 35
 36#define AD8460_HVDAC_SLEEP_MSK			BIT(3)
 37
 38#define AD8460_FAULT_ARM_MSK			BIT(7)
 39#define AD8460_FAULT_LIMIT_MSK			GENMASK(6, 0)
 40
 41#define AD8460_APG_MODE_ENABLE_MSK		BIT(5)
 42#define AD8460_PATTERN_DEPTH_MSK		GENMASK(3, 0)
 43
 44#define AD8460_QUIESCENT_CURRENT_MSK		GENMASK(7, 0)
 45
 46#define AD8460_SHUTDOWN_FLAG_MSK		BIT(7)
 47
 48#define AD8460_DATA_BYTE_LOW_MSK		GENMASK(7, 0)
 49#define AD8460_DATA_BYTE_HIGH_MSK		GENMASK(5, 0)
 50#define AD8460_DATA_BYTE_FULL_MSK		GENMASK(13, 0)
 51
 52#define AD8460_DEFAULT_FAULT_PROTECT		0x00
 53#define AD8460_DATA_BYTE_WORD_LENGTH		2
 54#define AD8460_NUM_DATA_WORDS			16
 55#define AD8460_NOMINAL_VOLTAGE_SPAN		80
 56#define AD8460_MIN_EXT_RESISTOR_OHMS		2000
 57#define AD8460_MAX_EXT_RESISTOR_OHMS		20000
 58#define AD8460_MIN_VREFIO_UV			120000
 59#define AD8460_MAX_VREFIO_UV			1200000
 60#define AD8460_ABS_MAX_OVERVOLTAGE_UV		55000000
 61#define AD8460_ABS_MAX_OVERCURRENT_UA		1000000
 62#define AD8460_MAX_OVERTEMPERATURE_MC		150000
 63#define AD8460_MIN_OVERTEMPERATURE_MC		20000
 64#define AD8460_CURRENT_LIMIT_CONV(x)		((x) / 15625)
 65#define AD8460_VOLTAGE_LIMIT_CONV(x)		((x) / 1953000)
 66#define AD8460_TEMP_LIMIT_CONV(x)		(((x) + 266640) / 6510)
 67
 68enum ad8460_fault_type {
 69	AD8460_OVERCURRENT_SRC,
 70	AD8460_OVERCURRENT_SNK,
 71	AD8460_OVERVOLTAGE_POS,
 72	AD8460_OVERVOLTAGE_NEG,
 73	AD8460_OVERTEMPERATURE,
 74};
 75
 76struct ad8460_state {
 77	struct spi_device *spi;
 78	struct regmap *regmap;
 79	struct iio_channel *tmp_adc_channel;
 80	struct clk *sync_clk;
 81	/* lock to protect against multiple access to the device and shared data */
 82	struct mutex lock;
 83	int refio_1p2v_mv;
 84	u32 ext_resistor_ohms;
 85	/*
 86	 * DMA (thus cache coherency maintenance) requires the
 87	 * transfer buffers to live in their own cache lines.
 88	 */
 89	__le16 spi_tx_buf __aligned(IIO_DMA_MINALIGN);
 90};
 91
 92static int ad8460_hv_reset(struct ad8460_state *state)
 93{
 94	int ret;
 95
 96	ret = regmap_set_bits(state->regmap, AD8460_CTRL_REG(0x00),
 97			      AD8460_HV_RESET_MSK);
 98	if (ret)
 99		return ret;
100
101	fsleep(20);
102
103	return regmap_clear_bits(state->regmap, AD8460_CTRL_REG(0x00),
104				 AD8460_HV_RESET_MSK);
105}
106
107static int ad8460_reset(const struct ad8460_state *state)
108{
109	struct device *dev = &state->spi->dev;
110	struct gpio_desc *reset;
111
112	reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
113	if (IS_ERR(reset))
114		return dev_err_probe(dev, PTR_ERR(reset),
115				     "Failed to get reset gpio");
116	if (reset) {
117		/* minimum duration of 10ns */
118		ndelay(10);
119		gpiod_set_value_cansleep(reset, 1);
120		return 0;
121	}
122
123	/* bring all registers to their default state */
124	return regmap_write(state->regmap, AD8460_CTRL_REG(0x03), 1);
125}
126
127static int ad8460_enable_apg_mode(struct ad8460_state *state, int val)
128{
129	int ret;
130
131	ret = regmap_update_bits(state->regmap, AD8460_CTRL_REG(0x02),
132				 AD8460_APG_MODE_ENABLE_MSK,
133				 FIELD_PREP(AD8460_APG_MODE_ENABLE_MSK, val));
134	if (ret)
135		return ret;
136
137	return regmap_update_bits(state->regmap, AD8460_CTRL_REG(0x00),
138				  AD8460_WAVE_GEN_MODE_MSK,
139				  FIELD_PREP(AD8460_WAVE_GEN_MODE_MSK, val));
140}
141
142static int ad8460_read_shutdown_flag(struct ad8460_state *state, u64 *flag)
143{
144	int ret, val;
145
146	ret = regmap_read(state->regmap, AD8460_CTRL_REG(0x0E), &val);
147	if (ret)
148		return ret;
149
150	*flag = FIELD_GET(AD8460_SHUTDOWN_FLAG_MSK, val);
151	return 0;
152}
153
154static int ad8460_get_hvdac_word(struct ad8460_state *state, int index, int *val)
155{
156	int ret;
157
158	ret = regmap_bulk_read(state->regmap, AD8460_HVDAC_DATA_WORD(index),
159			       &state->spi_tx_buf, AD8460_DATA_BYTE_WORD_LENGTH);
160	if (ret)
161		return ret;
162
163	*val = le16_to_cpu(state->spi_tx_buf);
164
165	return ret;
166}
167
168static int ad8460_set_hvdac_word(struct ad8460_state *state, int index, int val)
169{
170	state->spi_tx_buf = cpu_to_le16(FIELD_PREP(AD8460_DATA_BYTE_FULL_MSK, val));
171
172	return regmap_bulk_write(state->regmap, AD8460_HVDAC_DATA_WORD(index),
173				 &state->spi_tx_buf, AD8460_DATA_BYTE_WORD_LENGTH);
174}
175
176static ssize_t ad8460_dac_input_read(struct iio_dev *indio_dev, uintptr_t private,
177				     const struct iio_chan_spec *chan, char *buf)
178{
179	struct ad8460_state *state = iio_priv(indio_dev);
180	unsigned int reg;
181	int ret;
182
183	ret = ad8460_get_hvdac_word(state, private, &reg);
184	if (ret)
185		return ret;
186
187	return sysfs_emit(buf, "%u\n", reg);
188}
189
190static ssize_t ad8460_dac_input_write(struct iio_dev *indio_dev, uintptr_t private,
191				      const struct iio_chan_spec *chan,
192				      const char *buf, size_t len)
193{
194	struct ad8460_state *state = iio_priv(indio_dev);
195	unsigned int reg;
196	int ret;
197
198	ret = kstrtou32(buf, 10, &reg);
199	if (ret)
200		return ret;
201
202	guard(mutex)(&state->lock);
203
204	return ad8460_set_hvdac_word(state, private, reg);
205}
206
207static ssize_t ad8460_read_symbol(struct iio_dev *indio_dev, uintptr_t private,
208				  const struct iio_chan_spec *chan, char *buf)
209{
210	struct ad8460_state *state = iio_priv(indio_dev);
211	unsigned int reg;
212	int ret;
213
214	ret = regmap_read(state->regmap, AD8460_CTRL_REG(0x02), &reg);
215	if (ret)
216		return ret;
217
218	return sysfs_emit(buf, "%lu\n", FIELD_GET(AD8460_PATTERN_DEPTH_MSK, reg));
219}
220
221static ssize_t ad8460_write_symbol(struct iio_dev *indio_dev, uintptr_t private,
222				   const struct iio_chan_spec *chan,
223				   const char *buf, size_t len)
224{
225	struct ad8460_state *state = iio_priv(indio_dev);
226	uint16_t sym;
227	int ret;
228
229	ret = kstrtou16(buf, 10, &sym);
230	if (ret)
231		return ret;
232
233	guard(mutex)(&state->lock);
234
235	return regmap_update_bits(state->regmap,
236				  AD8460_CTRL_REG(0x02),
237				  AD8460_PATTERN_DEPTH_MSK,
238				  FIELD_PREP(AD8460_PATTERN_DEPTH_MSK, sym));
239}
240
241static ssize_t ad8460_read_toggle_en(struct iio_dev *indio_dev, uintptr_t private,
242				     const struct iio_chan_spec *chan, char *buf)
243{
244	struct ad8460_state *state = iio_priv(indio_dev);
245	unsigned int reg;
246	int ret;
247
248	ret = regmap_read(state->regmap, AD8460_CTRL_REG(0x02), &reg);
249	if (ret)
250		return ret;
251
252	return sysfs_emit(buf, "%ld\n", FIELD_GET(AD8460_APG_MODE_ENABLE_MSK, reg));
253}
254
255static ssize_t ad8460_write_toggle_en(struct iio_dev *indio_dev, uintptr_t private,
256				      const struct iio_chan_spec *chan,
257				      const char *buf, size_t len)
258{
259	struct ad8460_state *state = iio_priv(indio_dev);
260	bool toggle_en;
261	int ret;
262
263	ret = kstrtobool(buf, &toggle_en);
264	if (ret)
265		return ret;
266
267	if (!iio_device_claim_direct(indio_dev))
268		return -EBUSY;
269
270	ret = ad8460_enable_apg_mode(state, toggle_en);
271	iio_device_release_direct(indio_dev);
272	return ret;
273}
274
275static ssize_t ad8460_read_powerdown(struct iio_dev *indio_dev, uintptr_t private,
276				     const struct iio_chan_spec *chan, char *buf)
277{
278	struct ad8460_state *state = iio_priv(indio_dev);
279	unsigned int reg;
280	int ret;
281
282	ret = regmap_read(state->regmap, AD8460_CTRL_REG(0x01), &reg);
283	if (ret)
284		return ret;
285
286	return sysfs_emit(buf, "%ld\n", FIELD_GET(AD8460_HVDAC_SLEEP_MSK, reg));
287}
288
289static ssize_t ad8460_write_powerdown(struct iio_dev *indio_dev, uintptr_t private,
290				      const struct iio_chan_spec *chan,
291				      const char *buf, size_t len)
292{
293	struct ad8460_state *state = iio_priv(indio_dev);
294	bool pwr_down;
295	u64 sdn_flag;
296	int ret;
297
298	ret = kstrtobool(buf, &pwr_down);
299	if (ret)
300		return ret;
301
302	guard(mutex)(&state->lock);
303
304	/*
305	 * If powerdown is set, HVDAC is enabled and the HV driver is
306	 * enabled via HV_RESET in case it is in shutdown mode,
307	 * If powerdown is cleared, HVDAC is set to shutdown state
308	 * as well as the HV driver. Quiescent current decreases and ouput is
309	 * floating (high impedance).
310	 */
311
312	ret = regmap_update_bits(state->regmap, AD8460_CTRL_REG(0x01),
313				 AD8460_HVDAC_SLEEP_MSK,
314				 FIELD_PREP(AD8460_HVDAC_SLEEP_MSK, pwr_down));
315	if (ret)
316		return ret;
317
318	if (!pwr_down) {
319		ret = ad8460_read_shutdown_flag(state, &sdn_flag);
320		if (ret)
321			return ret;
322
323		if (sdn_flag) {
324			ret = ad8460_hv_reset(state);
325			if (ret)
326				return ret;
327		}
328	}
329
330	ret = regmap_update_bits(state->regmap, AD8460_CTRL_REG(0x00),
331				 AD8460_HV_SLEEP_MSK,
332				 FIELD_PREP(AD8460_HV_SLEEP_MSK, !pwr_down));
333	if (ret)
334		return ret;
335
336	return len;
337}
338
339static const char * const ad8460_powerdown_modes[] = {
340	"three_state",
341};
342
343static int ad8460_get_powerdown_mode(struct iio_dev *indio_dev,
344				     const struct iio_chan_spec *chan)
345{
346	return 0;
347}
348
349static int ad8460_set_powerdown_mode(struct iio_dev *indio_dev,
350				     const struct iio_chan_spec *chan,
351				     unsigned int type)
352{
353	return 0;
354}
355
356static int ad8460_set_sample(struct ad8460_state *state, int val)
357{
358	int ret;
359
360	ret = ad8460_enable_apg_mode(state, 1);
361	if (ret)
362		return ret;
363
364	guard(mutex)(&state->lock);
365	ret = ad8460_set_hvdac_word(state, 0, val);
366	if (ret)
367		return ret;
368
369	return regmap_update_bits(state->regmap, AD8460_CTRL_REG(0x02),
370				  AD8460_PATTERN_DEPTH_MSK,
371				  FIELD_PREP(AD8460_PATTERN_DEPTH_MSK, 0));
372}
373
374static int ad8460_set_fault_threshold(struct ad8460_state *state,
375				      enum ad8460_fault_type fault,
376				      unsigned int threshold)
377{
378	return regmap_update_bits(state->regmap, AD8460_CTRL_REG(0x08 + fault),
379				  AD8460_FAULT_LIMIT_MSK,
380				  FIELD_PREP(AD8460_FAULT_LIMIT_MSK, threshold));
381}
382
383static int ad8460_get_fault_threshold(struct ad8460_state *state,
384				      enum ad8460_fault_type fault,
385				      unsigned int *threshold)
386{
387	unsigned int val;
388	int ret;
389
390	ret = regmap_read(state->regmap, AD8460_CTRL_REG(0x08 + fault), &val);
391	if (ret)
392		return ret;
393
394	*threshold = FIELD_GET(AD8460_FAULT_LIMIT_MSK, val);
395
396	return ret;
397}
398
399static int ad8460_set_fault_threshold_en(struct ad8460_state *state,
400					 enum ad8460_fault_type fault, bool en)
401{
402	return regmap_update_bits(state->regmap, AD8460_CTRL_REG(0x08 + fault),
403				  AD8460_FAULT_ARM_MSK,
404				  FIELD_PREP(AD8460_FAULT_ARM_MSK, en));
405}
406
407static int ad8460_get_fault_threshold_en(struct ad8460_state *state,
408					 enum ad8460_fault_type fault, bool *en)
409{
410	unsigned int val;
411	int ret;
412
413	ret = regmap_read(state->regmap, AD8460_CTRL_REG(0x08 + fault), &val);
414	if (ret)
415		return ret;
416
417	*en = FIELD_GET(AD8460_FAULT_ARM_MSK, val);
418
419	return 0;
420}
421
422static int ad8460_write_raw(struct iio_dev *indio_dev,
423			    struct iio_chan_spec const *chan, int val, int val2,
424			    long mask)
425{
426	struct ad8460_state *state = iio_priv(indio_dev);
427	int ret;
428
429	switch (mask) {
430	case IIO_CHAN_INFO_RAW:
431		switch (chan->type) {
432		case IIO_VOLTAGE:
433			if (!iio_device_claim_direct(indio_dev))
434				return -EBUSY;
435			ret = ad8460_set_sample(state, val);
436			iio_device_release_direct(indio_dev);
437			return ret;
438		case IIO_CURRENT:
439			return regmap_write(state->regmap, AD8460_CTRL_REG(0x04),
440					    FIELD_PREP(AD8460_QUIESCENT_CURRENT_MSK, val));
441		default:
442			return -EINVAL;
443		}
444	default:
445		return -EINVAL;
446	}
447}
448
449static int ad8460_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
450			   int *val, int *val2, long mask)
451{
452	struct ad8460_state *state = iio_priv(indio_dev);
453	int data, ret;
454
455	switch (mask) {
456	case IIO_CHAN_INFO_RAW:
457		switch (chan->type) {
458		case IIO_VOLTAGE:
459			scoped_guard(mutex, &state->lock) {
460				ret = ad8460_get_hvdac_word(state, 0, &data);
461				if (ret)
462					return ret;
463			}
464			*val = data;
465			return IIO_VAL_INT;
466		case IIO_CURRENT:
467			ret = regmap_read(state->regmap, AD8460_CTRL_REG(0x04),
468					  &data);
469			if (ret)
470				return ret;
471			*val = data;
472			return IIO_VAL_INT;
473		case IIO_TEMP:
474			ret = iio_read_channel_raw(state->tmp_adc_channel, &data);
475			if (ret)
476				return ret;
477			*val = data;
478			return IIO_VAL_INT;
479		default:
480			return -EINVAL;
481		}
482	case IIO_CHAN_INFO_SAMP_FREQ:
483		*val = clk_get_rate(state->sync_clk);
484		return IIO_VAL_INT;
485	case IIO_CHAN_INFO_SCALE:
486		/*
487		 * vCONV = vNOMINAL_SPAN * (DAC_CODE / 2**14) - 40V
488		 * vMAX  = vNOMINAL_SPAN * (2**14 / 2**14) - 40V
489		 * vMIN  = vNOMINAL_SPAN * (0 / 2**14) - 40V
490		 * vADJ  = vCONV * (2000 / rSET) * (vREF / 1.2)
491		 * vSPAN = vADJ_MAX - vADJ_MIN
492		 * See datasheet page 49, section FULL-SCALE REDUCTION
493		 */
494		*val = AD8460_NOMINAL_VOLTAGE_SPAN * 2000 * state->refio_1p2v_mv;
495		*val2 = state->ext_resistor_ohms * 1200;
496		return IIO_VAL_FRACTIONAL;
497	default:
498		return -EINVAL;
499	}
500}
501
502static int ad8460_select_fault_type(int chan_type, enum iio_event_direction dir)
503{
504	switch (chan_type) {
505	case IIO_VOLTAGE:
506		switch (dir) {
507		case IIO_EV_DIR_RISING:
508			return AD8460_OVERVOLTAGE_POS;
509		case IIO_EV_DIR_FALLING:
510			return AD8460_OVERVOLTAGE_NEG;
511		default:
512			return -EINVAL;
513		}
514	case IIO_CURRENT:
515		switch (dir) {
516		case IIO_EV_DIR_RISING:
517			return AD8460_OVERCURRENT_SRC;
518		case IIO_EV_DIR_FALLING:
519			return AD8460_OVERCURRENT_SNK;
520		default:
521			return -EINVAL;
522		}
523	case IIO_TEMP:
524		switch (dir) {
525		case IIO_EV_DIR_RISING:
526			return AD8460_OVERTEMPERATURE;
527		default:
528			return -EINVAL;
529		}
530	default:
531		return -EINVAL;
532	}
533}
534
535static int ad8460_write_event_value(struct iio_dev *indio_dev,
536				    const struct iio_chan_spec *chan,
537				    enum iio_event_type type,
538				    enum iio_event_direction dir,
539				    enum iio_event_info info, int val, int val2)
540{
541	struct ad8460_state *state = iio_priv(indio_dev);
542	int fault;
543
544	if (type != IIO_EV_TYPE_THRESH)
545		return -EINVAL;
546
547	if (info != IIO_EV_INFO_VALUE)
548		return -EINVAL;
549
550	fault = ad8460_select_fault_type(chan->type, dir);
551	if (fault < 0)
552		return fault;
553
554	return ad8460_set_fault_threshold(state, fault, val);
555}
556
557static int ad8460_read_event_value(struct iio_dev *indio_dev,
558				   const struct iio_chan_spec *chan,
559				   enum iio_event_type type,
560				   enum iio_event_direction dir,
561				   enum iio_event_info info, int *val, int *val2)
562{
563	struct ad8460_state *state = iio_priv(indio_dev);
564	int fault;
565
566	if (type != IIO_EV_TYPE_THRESH)
567		return -EINVAL;
568
569	if (info != IIO_EV_INFO_VALUE)
570		return -EINVAL;
571
572	fault = ad8460_select_fault_type(chan->type, dir);
573	if (fault < 0)
574		return fault;
575
576	return ad8460_get_fault_threshold(state, fault, val);
577}
578
579static int ad8460_write_event_config(struct iio_dev *indio_dev,
580				     const struct iio_chan_spec *chan,
581				     enum iio_event_type type,
582				     enum iio_event_direction dir, bool val)
583{
584	struct ad8460_state *state = iio_priv(indio_dev);
585	int fault;
586
587	if (type != IIO_EV_TYPE_THRESH)
588		return -EINVAL;
589
590	fault = ad8460_select_fault_type(chan->type, dir);
591	if (fault < 0)
592		return fault;
593
594	return ad8460_set_fault_threshold_en(state, fault, val);
595}
596
597static int ad8460_read_event_config(struct iio_dev *indio_dev,
598				    const struct iio_chan_spec *chan,
599				    enum iio_event_type type,
600				    enum iio_event_direction dir)
601{
602	struct ad8460_state *state = iio_priv(indio_dev);
603	int fault, ret;
604	bool en;
605
606	if (type != IIO_EV_TYPE_THRESH)
607		return -EINVAL;
608
609	fault = ad8460_select_fault_type(chan->type, dir);
610	if (fault < 0)
611		return fault;
612
613	ret = ad8460_get_fault_threshold_en(state, fault, &en);
614	if (ret)
615		return ret;
616
617	return en;
618}
619
620static int ad8460_reg_access(struct iio_dev *indio_dev, unsigned int reg,
621			     unsigned int writeval, unsigned int *readval)
622{
623	struct ad8460_state *state = iio_priv(indio_dev);
624
625	if (readval)
626		return regmap_read(state->regmap, reg, readval);
627
628	return regmap_write(state->regmap, reg, writeval);
629}
630
631static int ad8460_buffer_preenable(struct iio_dev *indio_dev)
632{
633	struct ad8460_state *state = iio_priv(indio_dev);
634
635	return ad8460_enable_apg_mode(state, 0);
636}
637
638static int ad8460_buffer_postdisable(struct iio_dev *indio_dev)
639{
640	struct ad8460_state *state = iio_priv(indio_dev);
641
642	return ad8460_enable_apg_mode(state, 1);
643}
644
645static const struct iio_buffer_setup_ops ad8460_buffer_setup_ops = {
646	.preenable = &ad8460_buffer_preenable,
647	.postdisable = &ad8460_buffer_postdisable,
648};
649
650static const struct iio_info ad8460_info = {
651	.read_raw = &ad8460_read_raw,
652	.write_raw = &ad8460_write_raw,
653	.write_event_value = &ad8460_write_event_value,
654	.read_event_value = &ad8460_read_event_value,
655	.write_event_config = &ad8460_write_event_config,
656	.read_event_config = &ad8460_read_event_config,
657	.debugfs_reg_access = &ad8460_reg_access,
658};
659
660static const struct iio_enum ad8460_powerdown_mode_enum = {
661	.items = ad8460_powerdown_modes,
662	.num_items = ARRAY_SIZE(ad8460_powerdown_modes),
663	.get = ad8460_get_powerdown_mode,
664	.set = ad8460_set_powerdown_mode,
665};
666
667#define AD8460_CHAN_EXT_INFO(_name, _what, _read, _write) {		\
668	.name = (_name),						\
669	.read = (_read),						\
670	.write = (_write),						\
671	.private = (_what),						\
672	.shared = IIO_SEPARATE,						\
673}
674
675static const struct iio_chan_spec_ext_info ad8460_ext_info[] = {
676	AD8460_CHAN_EXT_INFO("raw0", 0, ad8460_dac_input_read,
677			     ad8460_dac_input_write),
678	AD8460_CHAN_EXT_INFO("raw1", 1, ad8460_dac_input_read,
679			     ad8460_dac_input_write),
680	AD8460_CHAN_EXT_INFO("raw2", 2, ad8460_dac_input_read,
681			     ad8460_dac_input_write),
682	AD8460_CHAN_EXT_INFO("raw3", 3, ad8460_dac_input_read,
683			     ad8460_dac_input_write),
684	AD8460_CHAN_EXT_INFO("raw4", 4, ad8460_dac_input_read,
685			     ad8460_dac_input_write),
686	AD8460_CHAN_EXT_INFO("raw5", 5, ad8460_dac_input_read,
687			     ad8460_dac_input_write),
688	AD8460_CHAN_EXT_INFO("raw6", 6, ad8460_dac_input_read,
689			     ad8460_dac_input_write),
690	AD8460_CHAN_EXT_INFO("raw7", 7, ad8460_dac_input_read,
691			     ad8460_dac_input_write),
692	AD8460_CHAN_EXT_INFO("raw8", 8, ad8460_dac_input_read,
693			     ad8460_dac_input_write),
694	AD8460_CHAN_EXT_INFO("raw9", 9, ad8460_dac_input_read,
695			     ad8460_dac_input_write),
696	AD8460_CHAN_EXT_INFO("raw10", 10, ad8460_dac_input_read,
697			     ad8460_dac_input_write),
698	AD8460_CHAN_EXT_INFO("raw11", 11, ad8460_dac_input_read,
699			     ad8460_dac_input_write),
700	AD8460_CHAN_EXT_INFO("raw12", 12, ad8460_dac_input_read,
701			     ad8460_dac_input_write),
702	AD8460_CHAN_EXT_INFO("raw13", 13, ad8460_dac_input_read,
703			     ad8460_dac_input_write),
704	AD8460_CHAN_EXT_INFO("raw14", 14, ad8460_dac_input_read,
705			     ad8460_dac_input_write),
706	AD8460_CHAN_EXT_INFO("raw15", 15, ad8460_dac_input_read,
707			     ad8460_dac_input_write),
708	AD8460_CHAN_EXT_INFO("toggle_en", 0, ad8460_read_toggle_en,
709			     ad8460_write_toggle_en),
710	AD8460_CHAN_EXT_INFO("symbol", 0, ad8460_read_symbol,
711			     ad8460_write_symbol),
712	AD8460_CHAN_EXT_INFO("powerdown", 0, ad8460_read_powerdown,
713			     ad8460_write_powerdown),
714	IIO_ENUM("powerdown_mode", IIO_SEPARATE, &ad8460_powerdown_mode_enum),
715	IIO_ENUM_AVAILABLE("powerdown_mode", IIO_SHARED_BY_TYPE,
716			   &ad8460_powerdown_mode_enum),
717	{ }
718};
719
720static const struct iio_event_spec ad8460_events[] = {
721	{
722		.type = IIO_EV_TYPE_THRESH,
723		.dir = IIO_EV_DIR_RISING,
724		.mask_separate = BIT(IIO_EV_INFO_VALUE) |
725				 BIT(IIO_EV_INFO_ENABLE),
726	},
727	{
728		.type = IIO_EV_TYPE_THRESH,
729		.dir = IIO_EV_DIR_FALLING,
730		.mask_separate = BIT(IIO_EV_INFO_VALUE) |
731				 BIT(IIO_EV_INFO_ENABLE),
732	},
733};
734
735#define AD8460_VOLTAGE_CHAN {					\
736	.type = IIO_VOLTAGE,					\
737	.info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ) |	\
738			      BIT(IIO_CHAN_INFO_RAW) |		\
739			      BIT(IIO_CHAN_INFO_SCALE),		\
740	.output = 1,						\
741	.indexed = 1,						\
742	.channel = 0,						\
743	.scan_index = 0,					\
744	.scan_type = {						\
745		.sign = 'u',					\
746		.realbits = 14,					\
747		.storagebits = 16,				\
748		.endianness = IIO_CPU,				\
749	},                                                      \
750	.ext_info = ad8460_ext_info,                            \
751	.event_spec = ad8460_events,				\
752	.num_event_specs = ARRAY_SIZE(ad8460_events),		\
753}
754
755#define AD8460_CURRENT_CHAN {					\
756	.type = IIO_CURRENT,					\
757	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
758	.output = 1,						\
759	.indexed = 1,						\
760	.channel = 0,						\
761	.scan_index = -1,					\
762	.event_spec = ad8460_events,				\
763	.num_event_specs = ARRAY_SIZE(ad8460_events),		\
764}
765
766#define AD8460_TEMP_CHAN {					\
767	.type = IIO_TEMP,					\
768	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
769	.indexed = 1,						\
770	.channel = 0,						\
771	.scan_index = -1,					\
772	.event_spec = ad8460_events,				\
773	.num_event_specs = 1,					\
774}
775
776static const struct iio_chan_spec ad8460_channels[] = {
777	AD8460_VOLTAGE_CHAN,
778	AD8460_CURRENT_CHAN,
779};
780
781static const struct iio_chan_spec ad8460_channels_with_tmp_adc[] = {
782	AD8460_VOLTAGE_CHAN,
783	AD8460_CURRENT_CHAN,
784	AD8460_TEMP_CHAN,
785};
786
787static const struct regmap_config ad8460_regmap_config = {
788	.reg_bits = 8,
789	.val_bits = 8,
790	.max_register = 0x7F,
791};
792
793static const char * const ad8460_supplies[] = {
794	"avdd_3p3v", "dvdd_3p3v", "vcc_5v", "hvcc", "hvee", "vref_5v"
795};
796
797static int ad8460_probe(struct spi_device *spi)
798{
799	struct device *dev  = &spi->dev;
800	struct ad8460_state *state;
801	struct iio_dev *indio_dev;
802	u32 tmp[2], temp;
803	int ret;
804
805	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*state));
806	if (!indio_dev)
807		return -ENOMEM;
808
809	state = iio_priv(indio_dev);
810
811	indio_dev->name = "ad8460";
812	indio_dev->info = &ad8460_info;
813
814	state->spi = spi;
815
816	state->regmap = devm_regmap_init_spi(spi, &ad8460_regmap_config);
817	if (IS_ERR(state->regmap))
818		return dev_err_probe(dev, PTR_ERR(state->regmap),
819				     "Failed to initialize regmap");
820
821	ret = devm_mutex_init(dev, &state->lock);
822	if (ret)
823		return ret;
824
825	state->sync_clk = devm_clk_get_enabled(dev, NULL);
826	if (IS_ERR(state->sync_clk))
827		return dev_err_probe(dev, PTR_ERR(state->sync_clk),
828				     "Failed to get sync clk\n");
829
830	state->tmp_adc_channel = devm_iio_channel_get(dev, "ad8460-tmp");
831	if (IS_ERR(state->tmp_adc_channel)) {
832		if (PTR_ERR(state->tmp_adc_channel) == -EPROBE_DEFER)
833			return -EPROBE_DEFER;
834		indio_dev->channels = ad8460_channels;
835		indio_dev->num_channels = ARRAY_SIZE(ad8460_channels);
836	} else {
837		indio_dev->channels = ad8460_channels_with_tmp_adc;
838		indio_dev->num_channels = ARRAY_SIZE(ad8460_channels_with_tmp_adc);
839	}
840
841	ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ad8460_supplies),
842					     ad8460_supplies);
843	if (ret)
844		return dev_err_probe(dev, ret,
845				     "Failed to enable power supplies\n");
846
847	ret = devm_regulator_get_enable_read_voltage(dev, "refio_1p2v");
848	if (ret < 0 && ret != -ENODEV)
849		return dev_err_probe(dev, ret, "Failed to get reference voltage\n");
850
851	state->refio_1p2v_mv = ret == -ENODEV ? 1200 : ret / 1000;
852
853	if (!in_range(state->refio_1p2v_mv, AD8460_MIN_VREFIO_UV / 1000,
854		      AD8460_MAX_VREFIO_UV / 1000))
855		return dev_err_probe(dev, -EINVAL,
856				     "Invalid ref voltage range(%u mV) [%u mV, %u mV]\n",
857				     state->refio_1p2v_mv,
858				     AD8460_MIN_VREFIO_UV / 1000,
859				     AD8460_MAX_VREFIO_UV / 1000);
860
861	ret = device_property_read_u32(dev, "adi,external-resistor-ohms",
862				       &state->ext_resistor_ohms);
863	if (ret)
864		state->ext_resistor_ohms = 2000;
865	else if (!in_range(state->ext_resistor_ohms, AD8460_MIN_EXT_RESISTOR_OHMS,
866			   AD8460_MAX_EXT_RESISTOR_OHMS))
867		return dev_err_probe(dev, -EINVAL,
868				     "Invalid resistor set range(%u) [%u, %u]\n",
869				     state->ext_resistor_ohms,
870				     AD8460_MIN_EXT_RESISTOR_OHMS,
871				     AD8460_MAX_EXT_RESISTOR_OHMS);
872
873	ret = device_property_read_u32_array(dev, "adi,range-microamp",
874					     tmp, ARRAY_SIZE(tmp));
875	if (!ret) {
876		if (in_range(tmp[1], 0, AD8460_ABS_MAX_OVERCURRENT_UA))
877			regmap_write(state->regmap, AD8460_CTRL_REG(0x08),
878				     FIELD_PREP(AD8460_FAULT_ARM_MSK, 1) |
879				     AD8460_CURRENT_LIMIT_CONV(tmp[1]));
880
881		if (in_range(tmp[0], -AD8460_ABS_MAX_OVERCURRENT_UA, 0))
882			regmap_write(state->regmap, AD8460_CTRL_REG(0x09),
883				     FIELD_PREP(AD8460_FAULT_ARM_MSK, 1) |
884				     AD8460_CURRENT_LIMIT_CONV(abs(tmp[0])));
885	}
886
887	ret = device_property_read_u32_array(dev, "adi,range-microvolt",
888					     tmp, ARRAY_SIZE(tmp));
889	if (!ret) {
890		if (in_range(tmp[1], 0, AD8460_ABS_MAX_OVERVOLTAGE_UV))
891			regmap_write(state->regmap, AD8460_CTRL_REG(0x0A),
892				     FIELD_PREP(AD8460_FAULT_ARM_MSK, 1) |
893				     AD8460_VOLTAGE_LIMIT_CONV(tmp[1]));
894
895		if (in_range(tmp[0], -AD8460_ABS_MAX_OVERVOLTAGE_UV, 0))
896			regmap_write(state->regmap, AD8460_CTRL_REG(0x0B),
897				     FIELD_PREP(AD8460_FAULT_ARM_MSK, 1) |
898				     AD8460_VOLTAGE_LIMIT_CONV(abs(tmp[0])));
899	}
900
901	ret = device_property_read_u32(dev, "adi,max-millicelsius", &temp);
902	if (!ret) {
903		if (in_range(temp, AD8460_MIN_OVERTEMPERATURE_MC,
904			     AD8460_MAX_OVERTEMPERATURE_MC))
905			regmap_write(state->regmap, AD8460_CTRL_REG(0x0C),
906				     FIELD_PREP(AD8460_FAULT_ARM_MSK, 1) |
907				     AD8460_TEMP_LIMIT_CONV(abs(temp)));
908	}
909
910	ret = ad8460_reset(state);
911	if (ret)
912		return ret;
913
914	/* Enables DAC by default */
915	ret = regmap_clear_bits(state->regmap, AD8460_CTRL_REG(0x01),
916				AD8460_HVDAC_SLEEP_MSK);
917	if (ret)
918		return ret;
919
920	indio_dev->modes = INDIO_DIRECT_MODE;
921	indio_dev->setup_ops = &ad8460_buffer_setup_ops;
922
923	ret = devm_iio_dmaengine_buffer_setup_ext(dev, indio_dev, "tx",
924						  IIO_BUFFER_DIRECTION_OUT);
925	if (ret)
926		return dev_err_probe(dev, ret,
927				     "Failed to get DMA buffer\n");
928
929	return devm_iio_device_register(dev, indio_dev);
930}
931
932static const struct of_device_id ad8460_of_match[] = {
933	{ .compatible = "adi,ad8460" },
934	{ }
935};
936MODULE_DEVICE_TABLE(of, ad8460_of_match);
937
938static const struct spi_device_id ad8460_spi_match[] = {
939	{ .name = "ad8460" },
940	{ }
941};
942MODULE_DEVICE_TABLE(spi, ad8460_spi_match);
943
944static struct spi_driver ad8460_driver = {
945	.driver = {
946		.name = "ad8460",
947		.of_match_table = ad8460_of_match,
948	},
949	.probe = ad8460_probe,
950	.id_table = ad8460_spi_match,
951};
952module_spi_driver(ad8460_driver);
953
954MODULE_AUTHOR("Mariel Tinaco <mariel.tinaco@analog.com");
955MODULE_DESCRIPTION("AD8460 DAC driver");
956MODULE_LICENSE("GPL");
957MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER");