ad3552r.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * AD3552R Digital <-> Analog converters common header
  4 *
  5 * Copyright 2021-2024 Analog Devices Inc.
  6 * Author: Angelo Dureghello <adureghello@baylibre.com>
  7 */
  8
  9#ifndef __DRIVERS_IIO_DAC_AD3552R_H__
 10#define __DRIVERS_IIO_DAC_AD3552R_H__
 11
 12/* Register addresses */
 13/* Primary address space */
 14#define AD3552R_REG_ADDR_INTERFACE_CONFIG_A		0x00
 15#define   AD3552R_MASK_SOFTWARE_RESET			(BIT(7) | BIT(0))
 16#define   AD3552R_MASK_ADDR_ASCENSION			BIT(5)
 17#define   AD3552R_MASK_SDO_ACTIVE			BIT(4)
 18#define AD3552R_REG_ADDR_INTERFACE_CONFIG_B		0x01
 19#define   AD3552R_MASK_SINGLE_INST			BIT(7)
 20#define   AD3552R_MASK_SHORT_INSTRUCTION		BIT(3)
 21#define AD3552R_REG_ADDR_DEVICE_CONFIG			0x02
 22#define   AD3552R_MASK_DEVICE_STATUS(n)			BIT(4 + (n))
 23#define   AD3552R_MASK_CUSTOM_MODES			GENMASK(3, 2)
 24#define   AD3552R_MASK_OPERATING_MODES			GENMASK(1, 0)
 25#define AD3552R_REG_ADDR_CHIP_TYPE			0x03
 26#define   AD3552R_MASK_CLASS				GENMASK(7, 0)
 27#define AD3552R_REG_ADDR_PRODUCT_ID_L			0x04
 28#define AD3552R_REG_ADDR_PRODUCT_ID_H			0x05
 29#define AD3552R_REG_ADDR_CHIP_GRADE			0x06
 30#define   AD3552R_MASK_GRADE				GENMASK(7, 4)
 31#define   AD3552R_MASK_DEVICE_REVISION			GENMASK(3, 0)
 32#define AD3552R_REG_ADDR_SCRATCH_PAD			0x0A
 33#define AD3552R_REG_ADDR_SPI_REVISION			0x0B
 34#define AD3552R_REG_ADDR_VENDOR_L			0x0C
 35#define AD3552R_REG_ADDR_VENDOR_H			0x0D
 36#define AD3552R_REG_ADDR_STREAM_MODE			0x0E
 37#define   AD3552R_MASK_LENGTH				GENMASK(7, 0)
 38#define AD3552R_REG_ADDR_TRANSFER_REGISTER		0x0F
 39#define   AD3552R_MASK_MULTI_IO_MODE			GENMASK(7, 6)
 40#define   AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE		BIT(2)
 41#define AD3552R_REG_ADDR_INTERFACE_CONFIG_C		0x10
 42#define   AD3552R_MASK_CRC_ENABLE \
 43		(GENMASK(7, 6) | GENMASK(1, 0))
 44#define   AD3552R_MASK_STRICT_REGISTER_ACCESS		BIT(5)
 45#define AD3552R_REG_ADDR_INTERFACE_STATUS_A		0x11
 46#define   AD3552R_MASK_INTERFACE_NOT_READY		BIT(7)
 47#define   AD3552R_MASK_CLOCK_COUNTING_ERROR		BIT(5)
 48#define   AD3552R_MASK_INVALID_OR_NO_CRC		BIT(3)
 49#define   AD3552R_MASK_WRITE_TO_READ_ONLY_REGISTER	BIT(2)
 50#define   AD3552R_MASK_PARTIAL_REGISTER_ACCESS		BIT(1)
 51#define   AD3552R_MASK_REGISTER_ADDRESS_INVALID		BIT(0)
 52#define AD3552R_REG_ADDR_INTERFACE_CONFIG_D		0x14
 53#define   AD3552R_MASK_ALERT_ENABLE_PULLUP		BIT(6)
 54#define   AD3552R_MASK_MEM_CRC_EN			BIT(4)
 55#define   AD3552R_MASK_SDO_DRIVE_STRENGTH		GENMASK(3, 2)
 56#define   AD3552R_MASK_DUAL_SPI_SYNCHROUNOUS_EN		BIT(1)
 57#define   AD3552R_MASK_SPI_CONFIG_DDR			BIT(0)
 58#define AD3552R_REG_ADDR_SH_REFERENCE_CONFIG		0x15
 59#define   AD3552R_MASK_IDUMP_FAST_MODE			BIT(6)
 60#define   AD3552R_MASK_SAMPLE_HOLD_DIFF_USER_EN		BIT(5)
 61#define   AD3552R_MASK_SAMPLE_HOLD_USER_TRIM		GENMASK(4, 3)
 62#define   AD3552R_MASK_SAMPLE_HOLD_USER_ENABLE		BIT(2)
 63#define   AD3552R_MASK_REFERENCE_VOLTAGE_SEL		GENMASK(1, 0)
 64#define AD3552R_REG_ADDR_ERR_ALARM_MASK			0x16
 65#define   AD3552R_MASK_REF_RANGE_ALARM			BIT(6)
 66#define   AD3552R_MASK_CLOCK_COUNT_ERR_ALARM		BIT(5)
 67#define   AD3552R_MASK_MEM_CRC_ERR_ALARM		BIT(4)
 68#define   AD3552R_MASK_SPI_CRC_ERR_ALARM		BIT(3)
 69#define   AD3552R_MASK_WRITE_TO_READ_ONLY_ALARM		BIT(2)
 70#define   AD3552R_MASK_PARTIAL_REGISTER_ACCESS_ALARM	BIT(1)
 71#define   AD3552R_MASK_REGISTER_ADDRESS_INVALID_ALARM	BIT(0)
 72#define AD3552R_REG_ADDR_ERR_STATUS			0x17
 73#define   AD3552R_MASK_REF_RANGE_ERR_STATUS		BIT(6)
 74#define   AD3552R_MASK_STREAM_EXCEEDS_DAC_ERR_STATUS	BIT(5)
 75#define   AD3552R_MASK_MEM_CRC_ERR_STATUS		BIT(4)
 76#define   AD3552R_MASK_RESET_STATUS			BIT(0)
 77#define AD3552R_REG_ADDR_POWERDOWN_CONFIG		0x18
 78#define   AD3552R_MASK_CH_DAC_POWERDOWN(ch)		BIT(4 + (ch))
 79#define   AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(ch)	BIT(ch)
 80#define AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE		0x19
 81#define   AD3552R_MASK_CH0_RANGE			GENMASK(2, 0)
 82#define   AD3552R_MASK_CH1_RANGE			GENMASK(6, 4)
 83#define   AD3552R_MASK_CH_OUTPUT_RANGE			GENMASK(7, 0)
 84#define   AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch) \
 85		((ch) ? GENMASK(7, 4) : GENMASK(3, 0))
 86#define AD3552R_REG_ADDR_CH_OFFSET(ch)			(0x1B + (ch) * 2)
 87#define   AD3552R_MASK_CH_OFFSET_BITS_0_7		GENMASK(7, 0)
 88#define AD3552R_REG_ADDR_CH_GAIN(ch)			(0x1C + (ch) * 2)
 89#define   AD3552R_MASK_CH_RANGE_OVERRIDE		BIT(7)
 90#define   AD3552R_MASK_CH_GAIN_SCALING_N		GENMASK(6, 5)
 91#define   AD3552R_MASK_CH_GAIN_SCALING_P		GENMASK(4, 3)
 92#define   AD3552R_MASK_CH_OFFSET_POLARITY		BIT(2)
 93#define   AD3552R_MASK_CH_OFFSET_BIT_8			BIT(8)
 94/*
 95 * Secondary region
 96 * For multibyte registers specify the highest address because the access is
 97 * done in descending order
 98 */
 99#define AD3552R_SECONDARY_REGION_START			0x28
100#define AD3552R_REG_ADDR_HW_LDAC_16B			0x28
101#define AD3552R_REG_ADDR_CH_DAC_16B(ch)			(0x2C - (1 - (ch)) * 2)
102#define AD3552R_REG_ADDR_DAC_PAGE_MASK_16B		0x2E
103#define AD3552R_REG_ADDR_CH_SELECT_16B			0x2F
104#define AD3552R_REG_ADDR_INPUT_PAGE_MASK_16B		0x31
105#define AD3552R_REG_ADDR_SW_LDAC_16B			0x32
106#define AD3552R_REG_ADDR_CH_INPUT_16B(ch)		(0x36 - (1 - (ch)) * 2)
107/* 3 bytes registers */
108#define AD3552R_REG_START_24B				0x37
109#define AD3552R_REG_ADDR_HW_LDAC_24B			0x37
110#define AD3552R_REG_ADDR_CH_DAC_24B(ch)			(0x3D - (1 - (ch)) * 3)
111#define AD3552R_REG_ADDR_DAC_PAGE_MASK_24B		0x40
112#define AD3552R_REG_ADDR_CH_SELECT_24B			0x41
113#define AD3552R_REG_ADDR_INPUT_PAGE_MASK_24B		0x44
114#define AD3552R_REG_ADDR_SW_LDAC_24B			0x45
115#define AD3552R_REG_ADDR_CH_INPUT_24B(ch)		(0x4B - (1 - (ch)) * 3)
116
117#define AD3552R_MAX_CH					2
118#define AD3552R_MASK_CH(ch)				BIT(ch)
119#define AD3552R_MASK_ALL_CH				GENMASK(1, 0)
120#define AD3552R_MAX_REG_SIZE				3
121#define AD3552R_READ_BIT				BIT(7)
122#define AD3552R_ADDR_MASK				GENMASK(6, 0)
123#define AD3552R_MASK_DAC_12B				GENMASK(15, 4)
124#define AD3552R_DEFAULT_CONFIG_B_VALUE			0x8
125#define AD3552R_SCRATCH_PAD_TEST_VAL1			0x34
126#define AD3552R_SCRATCH_PAD_TEST_VAL2			0xB2
127#define AD3552R_GAIN_SCALE				1000
128#define AD3552R_LDAC_PULSE_US				100
129
130#define AD3552R_CH0_ACTIVE				BIT(0)
131#define AD3552R_CH1_ACTIVE				BIT(1)
132
133#define AD3552R_MAX_RANGES	5
134#define AD3542R_MAX_RANGES	5
135#define AD3552R_SPI		0
136#define AD3552R_DUAL_SPI	1
137#define AD3552R_QUAD_SPI	2
138
139extern const struct ad3552r_model_data ad3541r_model_data;
140extern const struct ad3552r_model_data ad3542r_model_data;
141extern const struct ad3552r_model_data ad3551r_model_data;
142extern const struct ad3552r_model_data ad3552r_model_data;
143
144enum ad3552r_id {
145	AD3541R_ID = 0x400b,
146	AD3542R_ID = 0x4009,
147	AD3551R_ID = 0x400a,
148	AD3552R_ID = 0x4008,
149};
150
151struct ad3552r_model_data {
152	const char *model_name;
153	enum ad3552r_id chip_id;
154	unsigned int num_hw_channels;
155	const s32 (*ranges_table)[2];
156	int num_ranges;
157	bool requires_output_range;
158	int num_spi_data_lanes;
159	int max_reg_addr;
160};
161
162struct ad3552r_ch_data {
163	s32	scale_int;
164	s32	scale_dec;
165	s32	offset_int;
166	s32	offset_dec;
167	s16	gain_offset;
168	u16	rfb;
169	u8	n;
170	u8	p;
171	u8	range;
172	bool	range_override;
173};
174
175enum ad3552r_ch_gain_scaling {
176	/* Gain scaling of 1 */
177	AD3552R_CH_GAIN_SCALING_1,
178	/* Gain scaling of 0.5 */
179	AD3552R_CH_GAIN_SCALING_0_5,
180	/* Gain scaling of 0.25 */
181	AD3552R_CH_GAIN_SCALING_0_25,
182	/* Gain scaling of 0.125 */
183	AD3552R_CH_GAIN_SCALING_0_125,
184};
185
186enum ad3552r_ch_vref_select {
187	/* Internal source with Vref I/O floating */
188	AD3552R_INTERNAL_VREF_PIN_FLOATING,
189	/* Internal source with Vref I/O at 2.5V */
190	AD3552R_INTERNAL_VREF_PIN_2P5V,
191	/* External source with Vref I/O as input */
192	AD3552R_EXTERNAL_VREF_PIN_INPUT
193};
194
195enum ad3542r_ch_output_range {
196	/* Range from 0 V to 2.5 V. Requires Rfb1x connection */
197	AD3542R_CH_OUTPUT_RANGE_0__2P5V,
198	/* Range from 0 V to 5 V. Requires Rfb1x connection  */
199	AD3542R_CH_OUTPUT_RANGE_0__5V,
200	/* Range from 0 V to 10 V. Requires Rfb2x connection  */
201	AD3542R_CH_OUTPUT_RANGE_0__10V,
202	/* Range from -5 V to 5 V. Requires Rfb2x connection  */
203	AD3542R_CH_OUTPUT_RANGE_NEG_5__5V,
204	/* Range from -2.5 V to 7.5 V. Requires Rfb2x connection  */
205	AD3542R_CH_OUTPUT_RANGE_NEG_2P5__7P5V,
206};
207
208enum ad3552r_ch_output_range {
209	/* Range from 0 V to 2.5 V. Requires Rfb1x connection */
210	AD3552R_CH_OUTPUT_RANGE_0__2P5V,
211	/* Range from 0 V to 5 V. Requires Rfb1x connection  */
212	AD3552R_CH_OUTPUT_RANGE_0__5V,
213	/* Range from 0 V to 10 V. Requires Rfb2x connection  */
214	AD3552R_CH_OUTPUT_RANGE_0__10V,
215	/* Range from -5 V to 5 V. Requires Rfb2x connection  */
216	AD3552R_CH_OUTPUT_RANGE_NEG_5__5V,
217	/* Range from -10 V to 10 V. Requires Rfb4x connection  */
218	AD3552R_CH_OUTPUT_RANGE_NEG_10__10V,
219};
220
221int ad3552r_get_output_range(struct device *dev,
222			     const struct ad3552r_model_data *model_info,
223			     struct fwnode_handle *child, u32 *val);
224int ad3552r_get_custom_gain(struct device *dev, struct fwnode_handle *child,
225			    u8 *gs_p, u8 *gs_n, u16 *rfb, s16 *goffs);
226u16 ad3552r_calc_custom_gain(u8 p, u8 n, s16 goffs);
227int ad3552r_get_ref_voltage(struct device *dev, u32 *val);
228int ad3552r_get_drive_strength(struct device *dev, u32 *val);
229void ad3552r_calc_gain_and_offset(struct ad3552r_ch_data *ch_data,
230				  const struct ad3552r_model_data *model_data);
231
232#endif /* __DRIVERS_IIO_DAC_AD3552R_H__ */