ad3552r.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Analog Devices AD3552R
  4 * Digital to Analog converter driver
  5 *
  6 * Copyright 2021 Analog Devices Inc.
  7 */
  8#include <linux/unaligned.h>
  9#include <linux/bitfield.h>
 10#include <linux/device.h>
 11#include <linux/iio/triggered_buffer.h>
 12#include <linux/iio/trigger_consumer.h>
 13#include <linux/iopoll.h>
 14#include <linux/kernel.h>
 15#include <linux/spi/spi.h>
 16
 17#include "ad3552r.h"
 18
 19struct ad3552r_desc {
 20	const struct ad3552r_model_data *model_data;
 21	/* Used to look the spi bus for atomic operations where needed */
 22	struct mutex		lock;
 23	struct gpio_desc	*gpio_reset;
 24	struct gpio_desc	*gpio_ldac;
 25	struct spi_device	*spi;
 26	struct ad3552r_ch_data	ch_data[AD3552R_MAX_CH];
 27	struct iio_chan_spec	channels[AD3552R_MAX_CH + 1];
 28	unsigned long		enabled_ch;
 29	unsigned int		num_ch;
 30};
 31
 32static u8 _ad3552r_reg_len(u8 addr)
 33{
 34	switch (addr) {
 35	case AD3552R_REG_ADDR_HW_LDAC_16B:
 36	case AD3552R_REG_ADDR_CH_SELECT_16B:
 37	case AD3552R_REG_ADDR_SW_LDAC_16B:
 38	case AD3552R_REG_ADDR_HW_LDAC_24B:
 39	case AD3552R_REG_ADDR_CH_SELECT_24B:
 40	case AD3552R_REG_ADDR_SW_LDAC_24B:
 41		return 1;
 42	default:
 43		break;
 44	}
 45
 46	if (addr > AD3552R_REG_ADDR_HW_LDAC_24B)
 47		return 3;
 48	if (addr > AD3552R_REG_ADDR_HW_LDAC_16B)
 49		return 2;
 50
 51	return 1;
 52}
 53
 54/* SPI transfer to device */
 55static int ad3552r_transfer(struct ad3552r_desc *dac, u8 addr, u32 len,
 56			    u8 *data, bool is_read)
 57{
 58	/* Maximum transfer: Addr (1B) + 2 * (Data Reg (3B)) + SW LDAC(1B) */
 59	u8 buf[8];
 60
 61	buf[0] = addr & AD3552R_ADDR_MASK;
 62	buf[0] |= is_read ? AD3552R_READ_BIT : 0;
 63	if (is_read)
 64		return spi_write_then_read(dac->spi, buf, 1, data, len);
 65
 66	memcpy(buf + 1, data, len);
 67	return spi_write_then_read(dac->spi, buf, len + 1, NULL, 0);
 68}
 69
 70static int ad3552r_write_reg(struct ad3552r_desc *dac, u8 addr, u16 val)
 71{
 72	u8 reg_len;
 73	u8 buf[AD3552R_MAX_REG_SIZE] = { 0 };
 74
 75	reg_len = _ad3552r_reg_len(addr);
 76	if (reg_len == 2)
 77		/* Only DAC register are 2 bytes wide */
 78		val &= AD3552R_MASK_DAC_12B;
 79	if (reg_len == 1)
 80		buf[0] = val & 0xFF;
 81	else
 82		/* reg_len can be 2 or 3, but 3rd bytes needs to be set to 0 */
 83		put_unaligned_be16(val, buf);
 84
 85	return ad3552r_transfer(dac, addr, reg_len, buf, false);
 86}
 87
 88static int ad3552r_read_reg(struct ad3552r_desc *dac, u8 addr, u16 *val)
 89{
 90	int err;
 91	u8  reg_len, buf[AD3552R_MAX_REG_SIZE] = { 0 };
 92
 93	reg_len = _ad3552r_reg_len(addr);
 94	err = ad3552r_transfer(dac, addr, reg_len, buf, true);
 95	if (err)
 96		return err;
 97
 98	if (reg_len == 1)
 99		*val = buf[0];
100	else
101		/* reg_len can be 2 or 3, but only first 2 bytes are relevant */
102		*val = get_unaligned_be16(buf);
103
104	return 0;
105}
106
107/* Update field of a register, shift val if needed */
108static int ad3552r_update_reg_field(struct ad3552r_desc *dac, u8 addr, u16 mask,
109				    u16 val)
110{
111	int ret;
112	u16 reg;
113
114	ret = ad3552r_read_reg(dac, addr, &reg);
115	if (ret < 0)
116		return ret;
117
118	reg &= ~mask;
119	reg |= val;
120
121	return ad3552r_write_reg(dac, addr, reg);
122}
123
124#define AD3552R_CH_DAC(_idx) ((struct iio_chan_spec) {		\
125	.type = IIO_VOLTAGE,					\
126	.output = true,						\
127	.indexed = true,					\
128	.channel = _idx,					\
129	.scan_index = _idx,					\
130	.scan_type = {						\
131		.sign = 'u',					\
132		.realbits = 16,					\
133		.storagebits = 16,				\
134		.endianness = IIO_BE,				\
135	},							\
136	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |		\
137				BIT(IIO_CHAN_INFO_SCALE) |	\
138				BIT(IIO_CHAN_INFO_ENABLE) |	\
139				BIT(IIO_CHAN_INFO_OFFSET),	\
140})
141
142static int ad3552r_read_raw(struct iio_dev *indio_dev,
143			    struct iio_chan_spec const *chan,
144			    int *val,
145			    int *val2,
146			    long mask)
147{
148	struct ad3552r_desc *dac = iio_priv(indio_dev);
149	u16 tmp_val;
150	int err;
151	u8 ch = chan->channel;
152
153	switch (mask) {
154	case IIO_CHAN_INFO_RAW:
155		mutex_lock(&dac->lock);
156		err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_CH_DAC_24B(ch),
157				       &tmp_val);
158		mutex_unlock(&dac->lock);
159		if (err < 0)
160			return err;
161		*val = tmp_val;
162		return IIO_VAL_INT;
163	case IIO_CHAN_INFO_ENABLE:
164		mutex_lock(&dac->lock);
165		err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_POWERDOWN_CONFIG,
166				       &tmp_val);
167		mutex_unlock(&dac->lock);
168		if (err < 0)
169			return err;
170		*val = !((tmp_val & AD3552R_MASK_CH_DAC_POWERDOWN(ch)) >>
171			  __ffs(AD3552R_MASK_CH_DAC_POWERDOWN(ch)));
172		return IIO_VAL_INT;
173	case IIO_CHAN_INFO_SCALE:
174		*val = dac->ch_data[ch].scale_int;
175		*val2 = dac->ch_data[ch].scale_dec;
176		return IIO_VAL_INT_PLUS_MICRO;
177	case IIO_CHAN_INFO_OFFSET:
178		*val = dac->ch_data[ch].offset_int;
179		*val2 = dac->ch_data[ch].offset_dec;
180		return IIO_VAL_INT_PLUS_MICRO;
181	default:
182		return -EINVAL;
183	}
184}
185
186static int ad3552r_write_raw(struct iio_dev *indio_dev,
187			     struct iio_chan_spec const *chan,
188			     int val,
189			     int val2,
190			     long mask)
191{
192	struct ad3552r_desc *dac = iio_priv(indio_dev);
193	int err;
194
195	mutex_lock(&dac->lock);
196	switch (mask) {
197	case IIO_CHAN_INFO_RAW:
198		err = ad3552r_write_reg(dac,
199					AD3552R_REG_ADDR_CH_DAC_24B(chan->channel),
200					val);
201		break;
202	case IIO_CHAN_INFO_ENABLE:
203		if (chan->channel == 0)
204			val = FIELD_PREP(AD3552R_MASK_CH_DAC_POWERDOWN(0), !val);
205		else
206			val = FIELD_PREP(AD3552R_MASK_CH_DAC_POWERDOWN(1), !val);
207
208		err = ad3552r_update_reg_field(dac, AD3552R_REG_ADDR_POWERDOWN_CONFIG,
209					       AD3552R_MASK_CH_DAC_POWERDOWN(chan->channel),
210					       val);
211		break;
212	default:
213		err = -EINVAL;
214		break;
215	}
216	mutex_unlock(&dac->lock);
217
218	return err;
219}
220
221static const struct iio_info ad3552r_iio_info = {
222	.read_raw = ad3552r_read_raw,
223	.write_raw = ad3552r_write_raw
224};
225
226static int32_t ad3552r_trigger_hw_ldac(struct gpio_desc *ldac)
227{
228	gpiod_set_value_cansleep(ldac, 0);
229	usleep_range(AD3552R_LDAC_PULSE_US, AD3552R_LDAC_PULSE_US + 10);
230	gpiod_set_value_cansleep(ldac, 1);
231
232	return 0;
233}
234
235static int ad3552r_write_all_channels(struct ad3552r_desc *dac, u8 *data)
236{
237	int err, len;
238	u8 addr, buff[AD3552R_MAX_CH * AD3552R_MAX_REG_SIZE + 1];
239
240	addr = AD3552R_REG_ADDR_CH_INPUT_24B(1);
241	/* CH1 */
242	memcpy(buff, data + 2, 2);
243	buff[2] = 0;
244	/* CH0 */
245	memcpy(buff + 3, data, 2);
246	buff[5] = 0;
247	len = 6;
248	if (!dac->gpio_ldac) {
249		/* Software LDAC */
250		buff[6] = AD3552R_MASK_ALL_CH;
251		++len;
252	}
253	err = ad3552r_transfer(dac, addr, len, buff, false);
254	if (err)
255		return err;
256
257	if (dac->gpio_ldac)
258		return ad3552r_trigger_hw_ldac(dac->gpio_ldac);
259
260	return 0;
261}
262
263static int ad3552r_write_codes(struct ad3552r_desc *dac, u32 mask, u8 *data)
264{
265	int err;
266	u8 addr, buff[AD3552R_MAX_REG_SIZE];
267
268	if (mask == AD3552R_MASK_ALL_CH) {
269		if (memcmp(data, data + 2, 2) != 0)
270			return ad3552r_write_all_channels(dac, data);
271
272		addr = AD3552R_REG_ADDR_INPUT_PAGE_MASK_24B;
273	} else {
274		addr = AD3552R_REG_ADDR_CH_INPUT_24B(__ffs(mask));
275	}
276
277	memcpy(buff, data, 2);
278	buff[2] = 0;
279	err = ad3552r_transfer(dac, addr, 3, data, false);
280	if (err)
281		return err;
282
283	if (dac->gpio_ldac)
284		return ad3552r_trigger_hw_ldac(dac->gpio_ldac);
285
286	return ad3552r_write_reg(dac, AD3552R_REG_ADDR_SW_LDAC_24B, mask);
287}
288
289static irqreturn_t ad3552r_trigger_handler(int irq, void *p)
290{
291	struct iio_poll_func *pf = p;
292	struct iio_dev *indio_dev = pf->indio_dev;
293	struct iio_buffer *buf = indio_dev->buffer;
294	struct ad3552r_desc *dac = iio_priv(indio_dev);
295	/* Maximum size of a scan */
296	u8 buff[AD3552R_MAX_CH * AD3552R_MAX_REG_SIZE] = { };
297	int err;
298
299	err = iio_pop_from_buffer(buf, buff);
300	if (err)
301		goto end;
302
303	mutex_lock(&dac->lock);
304	ad3552r_write_codes(dac, *indio_dev->active_scan_mask, buff);
305	mutex_unlock(&dac->lock);
306end:
307	iio_trigger_notify_done(indio_dev->trig);
308
309	return IRQ_HANDLED;
310}
311
312static int ad3552r_check_scratch_pad(struct ad3552r_desc *dac)
313{
314	const u16 val1 = AD3552R_SCRATCH_PAD_TEST_VAL1;
315	const u16 val2 = AD3552R_SCRATCH_PAD_TEST_VAL2;
316	u16 val;
317	int err;
318
319	err = ad3552r_write_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, val1);
320	if (err < 0)
321		return err;
322
323	err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, &val);
324	if (err < 0)
325		return err;
326
327	if (val1 != val)
328		return -ENODEV;
329
330	err = ad3552r_write_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, val2);
331	if (err < 0)
332		return err;
333
334	err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_SCRATCH_PAD, &val);
335	if (err < 0)
336		return err;
337
338	if (val2 != val)
339		return -ENODEV;
340
341	return 0;
342}
343
344struct reg_addr_pool {
345	struct ad3552r_desc *dac;
346	u8		    addr;
347};
348
349static int ad3552r_read_reg_wrapper(struct reg_addr_pool *addr)
350{
351	int err;
352	u16 val;
353
354	err = ad3552r_read_reg(addr->dac, addr->addr, &val);
355	if (err)
356		return err;
357
358	return val;
359}
360
361static int ad3552r_reset(struct ad3552r_desc *dac)
362{
363	struct reg_addr_pool addr;
364	int ret;
365	int val;
366
367	dac->gpio_reset = devm_gpiod_get_optional(&dac->spi->dev, "reset",
368						  GPIOD_OUT_LOW);
369	if (IS_ERR(dac->gpio_reset))
370		return dev_err_probe(&dac->spi->dev, PTR_ERR(dac->gpio_reset),
371				     "Error while getting gpio reset");
372
373	if (dac->gpio_reset) {
374		/* Perform hardware reset */
375		usleep_range(10, 20);
376		gpiod_set_value_cansleep(dac->gpio_reset, 1);
377	} else {
378		/* Perform software reset if no GPIO provided */
379		ret = ad3552r_update_reg_field(dac,
380					       AD3552R_REG_ADDR_INTERFACE_CONFIG_A,
381					       AD3552R_MASK_SOFTWARE_RESET,
382					       AD3552R_MASK_SOFTWARE_RESET);
383		if (ret < 0)
384			return ret;
385
386	}
387
388	addr.dac = dac;
389	addr.addr = AD3552R_REG_ADDR_INTERFACE_CONFIG_B;
390	ret = readx_poll_timeout(ad3552r_read_reg_wrapper, &addr, val,
391				 val == AD3552R_DEFAULT_CONFIG_B_VALUE ||
392				 val < 0,
393				 5000, 50000);
394	if (val < 0)
395		ret = val;
396	if (ret) {
397		dev_err(&dac->spi->dev, "Error while resetting");
398		return ret;
399	}
400
401	ret = readx_poll_timeout(ad3552r_read_reg_wrapper, &addr, val,
402				 !(val & AD3552R_MASK_INTERFACE_NOT_READY) ||
403				 val < 0,
404				 5000, 50000);
405	if (val < 0)
406		ret = val;
407	if (ret) {
408		dev_err(&dac->spi->dev, "Error while resetting");
409		return ret;
410	}
411
412	/* Clear reset error flag, see ad3552r manual, rev B table 38. */
413	ret = ad3552r_write_reg(dac, AD3552R_REG_ADDR_ERR_STATUS,
414				AD3552R_MASK_RESET_STATUS);
415	if (ret)
416		return ret;
417
418	return ad3552r_update_reg_field(dac,
419					AD3552R_REG_ADDR_INTERFACE_CONFIG_A,
420					AD3552R_MASK_ADDR_ASCENSION,
421					FIELD_PREP(AD3552R_MASK_ADDR_ASCENSION, val));
422}
423
424static int ad3552r_configure_custom_gain(struct ad3552r_desc *dac,
425					 struct fwnode_handle *child,
426					 u32 ch)
427{
428	struct device *dev = &dac->spi->dev;
429	int err;
430	u8 addr;
431	u16 reg;
432
433	err = ad3552r_get_custom_gain(dev, child,
434				      &dac->ch_data[ch].p,
435				      &dac->ch_data[ch].n,
436				      &dac->ch_data[ch].rfb,
437				      &dac->ch_data[ch].gain_offset);
438	if (err)
439		return err;
440
441	dac->ch_data[ch].range_override = 1;
442
443	addr = AD3552R_REG_ADDR_CH_GAIN(ch);
444	err = ad3552r_write_reg(dac, addr,
445				abs((s32)dac->ch_data[ch].gain_offset) &
446				AD3552R_MASK_CH_OFFSET_BITS_0_7);
447	if (err)
448		return dev_err_probe(dev, err, "Error writing register\n");
449
450	reg = ad3552r_calc_custom_gain(dac->ch_data[ch].p, dac->ch_data[ch].n,
451				       dac->ch_data[ch].gain_offset);
452
453	err = ad3552r_write_reg(dac, addr, reg);
454	if (err)
455		return dev_err_probe(dev, err, "Error writing register\n");
456
457	return 0;
458}
459
460static int ad3552r_configure_device(struct ad3552r_desc *dac)
461{
462	struct device *dev = &dac->spi->dev;
463	int err, cnt = 0;
464	u32 val, ch;
465
466	dac->gpio_ldac = devm_gpiod_get_optional(dev, "ldac", GPIOD_OUT_HIGH);
467	if (IS_ERR(dac->gpio_ldac))
468		return dev_err_probe(dev, PTR_ERR(dac->gpio_ldac),
469				     "Error getting gpio ldac");
470
471	err = ad3552r_get_ref_voltage(dev, &val);
472	if (err < 0)
473		return err;
474
475	err = ad3552r_update_reg_field(dac,
476				       AD3552R_REG_ADDR_SH_REFERENCE_CONFIG,
477				       AD3552R_MASK_REFERENCE_VOLTAGE_SEL,
478				       FIELD_PREP(AD3552R_MASK_REFERENCE_VOLTAGE_SEL, val));
479	if (err)
480		return err;
481
482	err = ad3552r_get_drive_strength(dev, &val);
483	if (!err) {
484		err = ad3552r_update_reg_field(dac,
485					       AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
486					       AD3552R_MASK_SDO_DRIVE_STRENGTH,
487					       FIELD_PREP(AD3552R_MASK_SDO_DRIVE_STRENGTH, val));
488		if (err)
489			return err;
490	}
491
492	dac->num_ch = device_get_child_node_count(dev);
493	if (!dac->num_ch) {
494		dev_err(dev, "No channels defined\n");
495		return -ENODEV;
496	}
497
498	device_for_each_child_node_scoped(dev, child) {
499		err = fwnode_property_read_u32(child, "reg", &ch);
500		if (err)
501			return dev_err_probe(dev, err,
502					     "mandatory reg property missing\n");
503		if (ch >= dac->model_data->num_hw_channels)
504			return dev_err_probe(dev, -EINVAL,
505					     "reg must be less than %d\n",
506					     dac->model_data->num_hw_channels);
507
508		err = ad3552r_get_output_range(dev, dac->model_data,
509					       child, &val);
510		if (err && err != -ENOENT)
511			return err;
512
513		if (!err) {
514			if (ch == 0)
515				val = FIELD_PREP(AD3552R_MASK_CH_OUTPUT_RANGE_SEL(0), val);
516			else
517				val = FIELD_PREP(AD3552R_MASK_CH_OUTPUT_RANGE_SEL(1), val);
518
519			err = ad3552r_update_reg_field(dac,
520						       AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE,
521						       AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch),
522						       val);
523			if (err)
524				return err;
525
526			dac->ch_data[ch].range = val;
527		} else if (dac->model_data->requires_output_range) {
528			return dev_err_probe(dev, -EINVAL,
529					     "adi,output-range-microvolt is required for %s\n",
530					     dac->model_data->model_name);
531		} else {
532			err = ad3552r_configure_custom_gain(dac, child, ch);
533			if (err)
534				return err;
535		}
536
537		ad3552r_calc_gain_and_offset(&dac->ch_data[ch], dac->model_data);
538		dac->enabled_ch |= BIT(ch);
539
540		if (ch == 0)
541			val = FIELD_PREP(AD3552R_MASK_CH(0), 1);
542		else
543			val = FIELD_PREP(AD3552R_MASK_CH(1), 1);
544
545		err = ad3552r_update_reg_field(dac,
546					       AD3552R_REG_ADDR_CH_SELECT_16B,
547					       AD3552R_MASK_CH(ch), val);
548		if (err < 0)
549			return err;
550
551		dac->channels[cnt] = AD3552R_CH_DAC(ch);
552		++cnt;
553
554	}
555
556	/* Disable unused channels */
557	for_each_clear_bit(ch, &dac->enabled_ch,
558			   dac->model_data->num_hw_channels) {
559		if (ch == 0)
560			val = FIELD_PREP(AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(0), 1);
561		else
562			val = FIELD_PREP(AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(1), 1);
563
564		err = ad3552r_update_reg_field(dac,
565					       AD3552R_REG_ADDR_POWERDOWN_CONFIG,
566					       AD3552R_MASK_CH_AMPLIFIER_POWERDOWN(ch),
567					       val);
568		if (err)
569			return err;
570	}
571
572	dac->num_ch = cnt;
573
574	return 0;
575}
576
577static int ad3552r_init(struct ad3552r_desc *dac)
578{
579	int err;
580	u16 val, id;
581
582	err = ad3552r_reset(dac);
583	if (err) {
584		dev_err(&dac->spi->dev, "Reset failed\n");
585		return err;
586	}
587
588	err = ad3552r_check_scratch_pad(dac);
589	if (err) {
590		dev_err(&dac->spi->dev, "Scratch pad test failed\n");
591		return err;
592	}
593
594	err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_PRODUCT_ID_L, &val);
595	if (err) {
596		dev_err(&dac->spi->dev, "Fail read PRODUCT_ID_L\n");
597		return err;
598	}
599
600	id = val;
601	err = ad3552r_read_reg(dac, AD3552R_REG_ADDR_PRODUCT_ID_H, &val);
602	if (err) {
603		dev_err(&dac->spi->dev, "Fail read PRODUCT_ID_H\n");
604		return err;
605	}
606
607	id |= val << 8;
608	if (id != dac->model_data->chip_id) {
609		dev_err(&dac->spi->dev, "Product id not matching\n");
610		return -ENODEV;
611	}
612
613	return ad3552r_configure_device(dac);
614}
615
616static int ad3552r_probe(struct spi_device *spi)
617{
618	struct ad3552r_desc *dac;
619	struct iio_dev *indio_dev;
620	int err;
621
622	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*dac));
623	if (!indio_dev)
624		return -ENOMEM;
625
626	dac = iio_priv(indio_dev);
627	dac->spi = spi;
628	dac->model_data = spi_get_device_match_data(spi);
629	if (!dac->model_data)
630		return -EINVAL;
631
632	mutex_init(&dac->lock);
633
634	err = ad3552r_init(dac);
635	if (err)
636		return err;
637
638	/* Config triggered buffer device */
639	indio_dev->name = dac->model_data->model_name;
640	indio_dev->dev.parent = &spi->dev;
641	indio_dev->info = &ad3552r_iio_info;
642	indio_dev->num_channels = dac->num_ch;
643	indio_dev->channels = dac->channels;
644	indio_dev->modes = INDIO_DIRECT_MODE;
645
646	err = devm_iio_triggered_buffer_setup_ext(&indio_dev->dev, indio_dev, NULL,
647						  &ad3552r_trigger_handler,
648						  IIO_BUFFER_DIRECTION_OUT,
649						  NULL,
650						  NULL);
651	if (err)
652		return err;
653
654	return devm_iio_device_register(&spi->dev, indio_dev);
655}
656
657static const struct spi_device_id ad3552r_id[] = {
658	{
659		.name = "ad3541r",
660		.driver_data = (kernel_ulong_t)&ad3541r_model_data
661	},
662	{
663		.name = "ad3542r",
664		.driver_data = (kernel_ulong_t)&ad3542r_model_data
665	},
666	{
667		.name = "ad3551r",
668		.driver_data = (kernel_ulong_t)&ad3551r_model_data
669	},
670	{
671		.name = "ad3552r",
672		.driver_data = (kernel_ulong_t)&ad3552r_model_data
673	},
674	{ }
675};
676MODULE_DEVICE_TABLE(spi, ad3552r_id);
677
678static const struct of_device_id ad3552r_of_match[] = {
679	{ .compatible = "adi,ad3541r", .data = &ad3541r_model_data },
680	{ .compatible = "adi,ad3542r", .data = &ad3542r_model_data },
681	{ .compatible = "adi,ad3551r", .data = &ad3551r_model_data },
682	{ .compatible = "adi,ad3552r", .data = &ad3552r_model_data },
683	{ }
684};
685MODULE_DEVICE_TABLE(of, ad3552r_of_match);
686
687static struct spi_driver ad3552r_driver = {
688	.driver = {
689		.name = "ad3552r",
690		.of_match_table = ad3552r_of_match,
691	},
692	.probe = ad3552r_probe,
693	.id_table = ad3552r_id
694};
695module_spi_driver(ad3552r_driver);
696
697MODULE_AUTHOR("Mihail Chindris <mihail.chindris@analog.com>");
698MODULE_DESCRIPTION("Analog Device AD3552R DAC");
699MODULE_LICENSE("GPL v2");
700MODULE_IMPORT_NS("IIO_AD3552R");