ad3552r-hs.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Analog Devices AD3552R
  4 * Digital to Analog converter driver, High Speed version
  5 *
  6 * Copyright 2024 Analog Devices Inc.
  7 */
  8
  9#include <linux/bitfield.h>
 10#include <linux/debugfs.h>
 11#include <linux/delay.h>
 12#include <linux/gpio/consumer.h>
 13#include <linux/iio/backend.h>
 14#include <linux/iio/buffer.h>
 15#include <linux/mod_devicetable.h>
 16#include <linux/platform_device.h>
 17#include <linux/property.h>
 18#include <linux/units.h>
 19
 20#include "ad3552r.h"
 21#include "ad3552r-hs.h"
 22
 23/*
 24 * Important notes for register map access:
 25 * ========================================
 26 *
 27 * Register address space is divided in 2 regions, primary (config) and
 28 * secondary (DAC). Primary region can only be accessed in simple SPI mode,
 29 * with exception for ad355x models where setting QSPI pin high allows QSPI
 30 * access to both the regions.
 31 *
 32 * Due to the fact that ad3541/2r do not implement QSPI, for proper device
 33 * detection, HDL keeps "QSPI" pin level low at boot (see ad3552r manual, rev B
 34 * table 7, pin 31, digital input). For this reason, actually the working mode
 35 * between SPI, DSPI and QSPI must be set via software, configuring the target
 36 * DAC appropriately, together with the backend API to configure the bus mode
 37 * accordingly.
 38 *
 39 * Also, important to note that none of the three modes allow to read in DDR.
 40 *
 41 * In non-buffering operations, mode is set to simple SPI SDR for all primary
 42 * and secondary region r/w accesses, to avoid to switch the mode each time DAC
 43 * register is accessed (raw accesses, r/w), and to be able to dump registers
 44 * content (possible as non DDR only).
 45 * In buffering mode, driver sets best possible mode, D/QSPI and DDR.
 46 */
 47
 48struct ad3552r_hs_state {
 49	const struct ad3552r_model_data *model_data;
 50	struct gpio_desc *reset_gpio;
 51	struct device *dev;
 52	struct iio_backend *back;
 53	bool single_channel;
 54	struct ad3552r_ch_data ch_data[AD3552R_MAX_CH];
 55	struct ad3552r_hs_platform_data *data;
 56	/* INTERFACE_CONFIG_D register cache, in DDR we cannot read values. */
 57	u32 config_d;
 58	/* Protects backend I/O operations from concurrent accesses. */
 59	struct mutex lock;
 60};
 61
 62enum ad3552r_sources {
 63	AD3552R_SRC_NORMAL,
 64	AD3552R_SRC_RAMP_16BIT,
 65};
 66
 67static const char * const dbgfs_attr_source[] = {
 68	[AD3552R_SRC_NORMAL] = "normal",
 69	[AD3552R_SRC_RAMP_16BIT] = "ramp-16bit",
 70};
 71
 72static int ad3552r_hs_reg_read(struct ad3552r_hs_state *st, u32 reg, u32 *val,
 73			       size_t xfer_size)
 74{
 75	/* No chip in the family supports DDR read. Informing of this. */
 76	WARN_ON_ONCE(st->config_d & AD3552R_MASK_SPI_CONFIG_DDR);
 77
 78	return st->data->bus_reg_read(st->back, reg, val, xfer_size);
 79}
 80
 81static int ad3552r_hs_set_data_source(struct ad3552r_hs_state *st,
 82				      enum iio_backend_data_source type)
 83{
 84	int i, ret;
 85
 86	for (i = 0; i < st->model_data->num_hw_channels; ++i) {
 87		ret = iio_backend_data_source_set(st->back, i, type);
 88		if (ret)
 89			return ret;
 90	}
 91
 92	return 0;
 93}
 94
 95static int ad3552r_hs_update_reg_bits(struct ad3552r_hs_state *st, u32 reg,
 96				      u32 mask, u32 val, size_t xfer_size)
 97{
 98	u32 rval;
 99	int ret;
100
101	ret = ad3552r_hs_reg_read(st, reg, &rval, xfer_size);
102	if (ret)
103		return ret;
104
105	rval = (rval & ~mask) | val;
106
107	return st->data->bus_reg_write(st->back, reg, rval, xfer_size);
108}
109
110static int ad3552r_hs_read_raw(struct iio_dev *indio_dev,
111			       struct iio_chan_spec const *chan,
112			       int *val, int *val2, long mask)
113{
114	struct ad3552r_hs_state *st = iio_priv(indio_dev);
115	int ret;
116	int ch = chan->channel;
117
118	switch (mask) {
119	case IIO_CHAN_INFO_SAMP_FREQ:
120		/*
121		 * Using a "num_spi_data_lanes" variable since ad3541/2 have
122		 * only DSPI interface, while ad355x is QSPI. Then using 2 as
123		 * DDR mode is considered always on (considering buffering
124		 * mode always).
125		 */
126		*val = DIV_ROUND_CLOSEST(st->data->bus_sample_data_clock_hz *
127					 st->model_data->num_spi_data_lanes * 2,
128					 chan->scan_type.realbits);
129
130		return IIO_VAL_INT;
131
132	case IIO_CHAN_INFO_RAW:
133		/* For RAW accesses, stay always in simple-spi. */
134		ret = ad3552r_hs_reg_read(st,
135				AD3552R_REG_ADDR_CH_DAC_16B(chan->channel),
136				val, 2);
137		if (ret)
138			return ret;
139
140		return IIO_VAL_INT;
141	case IIO_CHAN_INFO_SCALE:
142		*val = st->ch_data[ch].scale_int;
143		*val2 = st->ch_data[ch].scale_dec;
144		return IIO_VAL_INT_PLUS_MICRO;
145	case IIO_CHAN_INFO_OFFSET:
146		*val = st->ch_data[ch].offset_int;
147		*val2 = st->ch_data[ch].offset_dec;
148		return IIO_VAL_INT_PLUS_MICRO;
149	default:
150		return -EINVAL;
151	}
152}
153
154static int ad3552r_hs_write_raw(struct iio_dev *indio_dev,
155				struct iio_chan_spec const *chan,
156				int val, int val2, long mask)
157{
158	struct ad3552r_hs_state *st = iio_priv(indio_dev);
159	int ret;
160
161	switch (mask) {
162	case IIO_CHAN_INFO_RAW:
163		if (!iio_device_claim_direct(indio_dev))
164			return -EBUSY;
165		/* For RAW accesses, stay always in simple-spi. */
166		ret = st->data->bus_reg_write(st->back,
167			AD3552R_REG_ADDR_CH_DAC_16B(chan->channel),
168			val, 2);
169
170		iio_device_release_direct(indio_dev);
171		return ret;
172	default:
173		return -EINVAL;
174	}
175}
176
177static int ad3552r_hs_set_bus_io_mode_hs(struct ad3552r_hs_state *st)
178{
179	int bus_mode;
180
181	if (st->model_data->num_spi_data_lanes == 4)
182		bus_mode = AD3552R_IO_MODE_QSPI;
183	else
184		bus_mode = AD3552R_IO_MODE_DSPI;
185
186	return st->data->bus_set_io_mode(st->back, bus_mode);
187}
188
189static int ad3552r_hs_set_target_io_mode_hs(struct ad3552r_hs_state *st)
190{
191	u32 mode_target;
192
193	/*
194	 * Best access for secondary reg area, QSPI where possible,
195	 * else as DSPI.
196	 */
197	if (st->model_data->num_spi_data_lanes == 4)
198		mode_target = AD3552R_QUAD_SPI;
199	else
200		mode_target = AD3552R_DUAL_SPI;
201
202	/*
203	 * Better to not use update here, since generally it is already
204	 * set as DDR mode, and it's not possible to read in DDR mode.
205	 */
206	return st->data->bus_reg_write(st->back,
207				AD3552R_REG_ADDR_TRANSFER_REGISTER,
208				FIELD_PREP(AD3552R_MASK_MULTI_IO_MODE,
209					   mode_target) |
210				AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 1);
211}
212
213static int ad3552r_hs_buffer_postenable(struct iio_dev *indio_dev)
214{
215	struct ad3552r_hs_state *st = iio_priv(indio_dev);
216	struct iio_backend_data_fmt fmt = {
217		.type = IIO_BACKEND_DATA_UNSIGNED
218	};
219	int loop_len, val, ret;
220
221	switch (*indio_dev->active_scan_mask) {
222	case AD3552R_CH0_ACTIVE:
223		st->single_channel = true;
224		loop_len = 2;
225		val = AD3552R_REG_ADDR_CH_DAC_16B(0);
226		break;
227	case AD3552R_CH1_ACTIVE:
228		st->single_channel = true;
229		loop_len = 2;
230		val = AD3552R_REG_ADDR_CH_DAC_16B(1);
231		break;
232	case AD3552R_CH0_ACTIVE | AD3552R_CH1_ACTIVE:
233		st->single_channel = false;
234		loop_len = 4;
235		val = AD3552R_REG_ADDR_CH_DAC_16B(1);
236		break;
237	default:
238		return -EINVAL;
239	}
240
241	/*
242	 * With ad3541/2r support, QSPI pin is held low at reset from HDL,
243	 * streaming start sequence must respect strictly the order below.
244	 */
245
246	/* Primary region access, set streaming mode (now in SPI + SDR). */
247	ret = ad3552r_hs_update_reg_bits(st,
248					 AD3552R_REG_ADDR_INTERFACE_CONFIG_B,
249					 AD3552R_MASK_SINGLE_INST, 0, 1);
250	if (ret)
251		return ret;
252
253	/*
254	 * Set target loop len, keeping the value: streaming writes at address
255	 * 0x2c or 0x2a, in descending loop (2 or 4 bytes), keeping loop len
256	 * value so that it's not cleared hereafter when _CS is deasserted.
257	 */
258	ret = ad3552r_hs_update_reg_bits(st, AD3552R_REG_ADDR_TRANSFER_REGISTER,
259					 AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE,
260					 AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE,
261					 1);
262	if (ret)
263		goto exit_err_streaming;
264
265	ret = st->data->bus_reg_write(st->back,
266				      AD3552R_REG_ADDR_STREAM_MODE,
267				      loop_len, 1);
268	if (ret)
269		goto exit_err_streaming;
270
271	st->config_d |= AD3552R_MASK_SPI_CONFIG_DDR;
272	ret = st->data->bus_reg_write(st->back,
273				      AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
274				      st->config_d, 1);
275	if (ret)
276		goto exit_err_streaming;
277
278	ret = iio_backend_ddr_enable(st->back);
279	if (ret)
280		goto exit_err_ddr_mode_target;
281
282	/*
283	 * From here onward mode is DDR, so reading any register is not possible
284	 * anymore, including calling "ad3552r_hs_update_reg_bits" function.
285	 */
286
287	/* Set target to best high speed mode (D or QSPI). */
288	ret = ad3552r_hs_set_target_io_mode_hs(st);
289	if (ret)
290		goto exit_err_ddr_mode;
291
292	/* Set bus to best high speed mode (D or QSPI). */
293	ret = ad3552r_hs_set_bus_io_mode_hs(st);
294	if (ret)
295		goto exit_err_bus_mode_target;
296
297	/*
298	 * Backend setup must be done now only, or related register values will
299	 * be disrupted by previous bus accesses.
300	 */
301	ret = iio_backend_data_transfer_addr(st->back, val);
302	if (ret)
303		goto exit_err_bus_mode_target;
304
305	ret = iio_backend_data_format_set(st->back, 0, &fmt);
306	if (ret)
307		goto exit_err_bus_mode_target;
308
309	ret = iio_backend_data_stream_enable(st->back);
310	if (ret)
311		goto exit_err_bus_mode_target;
312
313	return 0;
314
315exit_err_bus_mode_target:
316	/* Back to simple SPI, not using update to avoid read. */
317	st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_TRANSFER_REGISTER,
318				FIELD_PREP(AD3552R_MASK_MULTI_IO_MODE,
319					   AD3552R_SPI) |
320				AD3552R_MASK_STREAM_LENGTH_KEEP_VALUE, 1);
321
322	/*
323	 * Back bus to simple SPI, this must be executed together with above
324	 * target mode unwind, and can be done only after it.
325	 */
326	st->data->bus_set_io_mode(st->back, AD3552R_IO_MODE_SPI);
327
328exit_err_ddr_mode:
329	iio_backend_ddr_disable(st->back);
330
331exit_err_ddr_mode_target:
332	/*
333	 * Back to SDR. In DDR we cannot read, whatever the mode is, so not
334	 * using update.
335	 */
336	st->config_d &= ~AD3552R_MASK_SPI_CONFIG_DDR;
337	st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
338				st->config_d, 1);
339
340exit_err_streaming:
341	/* Back to single instruction mode, disabling loop. */
342	st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_INTERFACE_CONFIG_B,
343				AD3552R_MASK_SINGLE_INST |
344				AD3552R_MASK_SHORT_INSTRUCTION, 1);
345
346	return ret;
347}
348
349static int ad3552r_hs_buffer_predisable(struct iio_dev *indio_dev)
350{
351	struct ad3552r_hs_state *st = iio_priv(indio_dev);
352	int ret;
353
354	ret = iio_backend_data_stream_disable(st->back);
355	if (ret)
356		return ret;
357
358	/*
359	 * Set us to simple SPI, even if still in ddr, so to be able to write
360	 * in primary region.
361	 */
362	ret = st->data->bus_set_io_mode(st->back, AD3552R_IO_MODE_SPI);
363	if (ret)
364		return ret;
365
366	/*
367	 * Back to SDR (in DDR we cannot read, whatever the mode is, so not
368	 * using update).
369	 */
370	st->config_d &= ~AD3552R_MASK_SPI_CONFIG_DDR;
371	ret = st->data->bus_reg_write(st->back,
372				      AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
373				      st->config_d, 1);
374	if (ret)
375		return ret;
376
377	ret = iio_backend_ddr_disable(st->back);
378	if (ret)
379		return ret;
380
381	/*
382	 * Back to simple SPI for secondary region too now, so to be able to
383	 * dump/read registers there too if needed.
384	 */
385	ret = ad3552r_hs_update_reg_bits(st, AD3552R_REG_ADDR_TRANSFER_REGISTER,
386					 AD3552R_MASK_MULTI_IO_MODE,
387					 AD3552R_SPI, 1);
388	if (ret)
389		return ret;
390
391	/* Back to single instruction mode, disabling loop. */
392	ret = ad3552r_hs_update_reg_bits(st,
393					 AD3552R_REG_ADDR_INTERFACE_CONFIG_B,
394					 AD3552R_MASK_SINGLE_INST,
395					 AD3552R_MASK_SINGLE_INST, 1);
396	if (ret)
397		return ret;
398
399	return 0;
400}
401
402static inline int ad3552r_hs_set_output_range(struct ad3552r_hs_state *st,
403					      int ch, unsigned int mode)
404{
405	int val;
406
407	if (ch == 0)
408		val = FIELD_PREP(AD3552R_MASK_CH0_RANGE, mode);
409	else
410		val = FIELD_PREP(AD3552R_MASK_CH1_RANGE, mode);
411
412	return ad3552r_hs_update_reg_bits(st,
413					  AD3552R_REG_ADDR_CH0_CH1_OUTPUT_RANGE,
414					  AD3552R_MASK_CH_OUTPUT_RANGE_SEL(ch),
415					  val, 1);
416}
417
418static int ad3552r_hs_reset(struct ad3552r_hs_state *st)
419{
420	int ret;
421
422	st->reset_gpio = devm_gpiod_get_optional(st->dev,
423						 "reset", GPIOD_OUT_HIGH);
424	if (IS_ERR(st->reset_gpio))
425		return PTR_ERR(st->reset_gpio);
426
427	if (st->reset_gpio) {
428		fsleep(10);
429		gpiod_set_value_cansleep(st->reset_gpio, 0);
430	} else {
431		ret = ad3552r_hs_update_reg_bits(st,
432			AD3552R_REG_ADDR_INTERFACE_CONFIG_A,
433			AD3552R_MASK_SOFTWARE_RESET,
434			AD3552R_MASK_SOFTWARE_RESET, 1);
435		if (ret)
436			return ret;
437	}
438	msleep(100);
439
440	return 0;
441}
442
443static int ad3552r_hs_scratch_pad_test(struct ad3552r_hs_state *st)
444{
445	int ret, val;
446
447	ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_SCRATCH_PAD,
448				      AD3552R_SCRATCH_PAD_TEST_VAL1, 1);
449	if (ret)
450		return ret;
451
452	ret = st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_SCRATCH_PAD,
453				     &val, 1);
454	if (ret)
455		return ret;
456
457	if (val != AD3552R_SCRATCH_PAD_TEST_VAL1)
458		return dev_err_probe(st->dev, -EIO,
459			"SCRATCH_PAD_TEST mismatch. Expected 0x%x, Read 0x%x\n",
460			AD3552R_SCRATCH_PAD_TEST_VAL1, val);
461
462	ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_SCRATCH_PAD,
463				      AD3552R_SCRATCH_PAD_TEST_VAL2, 1);
464	if (ret)
465		return ret;
466
467	ret = st->data->bus_reg_read(st->back, AD3552R_REG_ADDR_SCRATCH_PAD,
468				     &val, 1);
469	if (ret)
470		return ret;
471
472	if (val != AD3552R_SCRATCH_PAD_TEST_VAL2)
473		return dev_err_probe(st->dev, -EIO,
474			"SCRATCH_PAD_TEST mismatch. Expected 0x%x, Read 0x%x\n",
475			AD3552R_SCRATCH_PAD_TEST_VAL2, val);
476
477	return 0;
478}
479
480static int ad3552r_hs_setup_custom_gain(struct ad3552r_hs_state *st,
481					int ch, u16 gain, u16 offset)
482{
483	int ret;
484
485	ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_CH_OFFSET(ch),
486				      offset, 1);
487	if (ret)
488		return ret;
489
490	return st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_CH_GAIN(ch),
491				      gain, 1);
492}
493
494static int ad3552r_hs_reg_access(struct iio_dev *indio_dev, unsigned int reg,
495				 unsigned int writeval, unsigned int *readval)
496{
497	struct ad3552r_hs_state *st = iio_priv(indio_dev);
498
499	if (reg > st->model_data->max_reg_addr)
500		return -EINVAL;
501
502	/*
503	 * There are 8, 16 or 24 bit registers, but HDL supports only reading 8
504	 * or 16 bit data, not 24. So, also to avoid to check any proper read
505	 * alignment, supporting only 8-bit readings here.
506	 */
507	if (readval)
508		return ad3552r_hs_reg_read(st, reg, readval, 1);
509
510	return st->data->bus_reg_write(st->back, reg, writeval, 1);
511}
512
513static ssize_t ad3552r_hs_show_data_source(struct file *f, char __user *userbuf,
514					   size_t count, loff_t *ppos)
515{
516	struct ad3552r_hs_state *st = file_inode(f)->i_private;
517	enum iio_backend_data_source type;
518	int idx, ret;
519
520	guard(mutex)(&st->lock);
521
522	ret = iio_backend_data_source_get(st->back, 0, &type);
523	if (ret)
524		return ret;
525
526	switch (type) {
527	case IIO_BACKEND_INTERNAL_RAMP_16BIT:
528		idx = AD3552R_SRC_RAMP_16BIT;
529		break;
530	case IIO_BACKEND_EXTERNAL:
531		idx = AD3552R_SRC_NORMAL;
532		break;
533	default:
534		return -EINVAL;
535	}
536
537	return simple_read_from_buffer(userbuf, count, ppos,
538				       dbgfs_attr_source[idx],
539				       strlen(dbgfs_attr_source[idx]));
540}
541
542static ssize_t ad3552r_hs_write_data_source(struct file *f,
543					    const char __user *userbuf,
544					    size_t count, loff_t *ppos)
545{
546	struct ad3552r_hs_state *st = file_inode(f)->i_private;
547	char buf[64];
548	int ret, source;
549
550	guard(mutex)(&st->lock);
551
552	if (count >= sizeof(buf))
553		return -ENOSPC;
554
555	ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, userbuf,
556				     count);
557	if (ret < 0)
558		return ret;
559
560	buf[ret] = '\0';
561
562	ret = match_string(dbgfs_attr_source, ARRAY_SIZE(dbgfs_attr_source),
563			   buf);
564	if (ret < 0)
565		return ret;
566
567	switch (ret) {
568	case AD3552R_SRC_RAMP_16BIT:
569		source = IIO_BACKEND_INTERNAL_RAMP_16BIT;
570		break;
571	case AD3552R_SRC_NORMAL:
572		source = IIO_BACKEND_EXTERNAL;
573		break;
574	default:
575		return -EINVAL;
576	}
577
578	ret = ad3552r_hs_set_data_source(st, source);
579	if (ret)
580		return ret;
581
582	return count;
583}
584
585static ssize_t ad3552r_hs_show_data_source_avail(struct file *f,
586						 char __user *userbuf,
587						 size_t count, loff_t *ppos)
588{
589	ssize_t len = 0;
590	char buf[128];
591	int i;
592
593	for (i = 0; i < ARRAY_SIZE(dbgfs_attr_source); i++) {
594		len += scnprintf(buf + len, PAGE_SIZE - len, "%s ",
595				 dbgfs_attr_source[i]);
596	}
597	buf[len - 1] = '\n';
598
599	return simple_read_from_buffer(userbuf, count, ppos, buf, len);
600}
601
602static const struct file_operations ad3552r_hs_data_source_fops = {
603	.owner = THIS_MODULE,
604	.write = ad3552r_hs_write_data_source,
605	.read = ad3552r_hs_show_data_source,
606};
607
608static const struct file_operations ad3552r_hs_data_source_avail_fops = {
609	.owner = THIS_MODULE,
610	.read = ad3552r_hs_show_data_source_avail,
611};
612
613static int ad3552r_hs_setup(struct ad3552r_hs_state *st)
614{
615	u16 id;
616	u16 gain = 0, offset = 0;
617	u32 ch, val, range;
618	int ret;
619
620	ret = ad3552r_hs_reset(st);
621	if (ret)
622		return ret;
623
624	/* HDL starts with DDR enabled, disabling it. */
625	ret = iio_backend_ddr_disable(st->back);
626	if (ret)
627		return ret;
628
629	ret = st->data->bus_reg_write(st->back,
630				      AD3552R_REG_ADDR_INTERFACE_CONFIG_B,
631				      AD3552R_MASK_SINGLE_INST |
632				      AD3552R_MASK_SHORT_INSTRUCTION, 1);
633	if (ret)
634		return ret;
635
636	ret = ad3552r_hs_scratch_pad_test(st);
637	if (ret)
638		return ret;
639
640	/*
641	 * Caching config_d, needed to restore it after streaming,
642	 * and also, to detect possible DDR read, that's not allowed.
643	 */
644	ret = st->data->bus_reg_read(st->back,
645				     AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
646				     &st->config_d, 1);
647	if (ret)
648		return ret;
649
650	ret = ad3552r_hs_reg_read(st, AD3552R_REG_ADDR_PRODUCT_ID_L, &val, 1);
651	if (ret)
652		return ret;
653
654	id = val;
655
656	ret = ad3552r_hs_reg_read(st, AD3552R_REG_ADDR_PRODUCT_ID_H, &val, 1);
657	if (ret)
658		return ret;
659
660	id |= val << 8;
661	if (id != st->model_data->chip_id)
662		dev_warn(st->dev,
663			 "chip ID mismatch, detected 0x%x but expected 0x%x\n",
664			 id, st->model_data->chip_id);
665
666	dev_dbg(st->dev, "chip id %s detected", st->model_data->model_name);
667
668	/* Clear reset error flag, see ad3552r manual, rev B table 38. */
669	ret = st->data->bus_reg_write(st->back, AD3552R_REG_ADDR_ERR_STATUS,
670				      AD3552R_MASK_RESET_STATUS, 1);
671	if (ret)
672		return ret;
673
674	ret = st->data->bus_reg_write(st->back,
675				      AD3552R_REG_ADDR_SH_REFERENCE_CONFIG,
676				      0, 1);
677	if (ret)
678		return ret;
679
680	ret = ad3552r_hs_set_data_source(st, IIO_BACKEND_EXTERNAL);
681	if (ret)
682		return ret;
683
684	ret = ad3552r_get_ref_voltage(st->dev, &val);
685	if (ret < 0)
686		return ret;
687
688	val = ret;
689
690	ret = ad3552r_hs_update_reg_bits(st,
691					 AD3552R_REG_ADDR_SH_REFERENCE_CONFIG,
692					 AD3552R_MASK_REFERENCE_VOLTAGE_SEL,
693					 val, 1);
694	if (ret)
695		return ret;
696
697	ret = ad3552r_get_drive_strength(st->dev, &val);
698	if (!ret) {
699		st->config_d |=
700			FIELD_PREP(AD3552R_MASK_SDO_DRIVE_STRENGTH, val);
701
702		ret = st->data->bus_reg_write(st->back,
703					AD3552R_REG_ADDR_INTERFACE_CONFIG_D,
704					st->config_d, 1);
705		if (ret)
706			return ret;
707	}
708
709	device_for_each_child_node_scoped(st->dev, child) {
710		ret = fwnode_property_read_u32(child, "reg", &ch);
711		if (ret)
712			return dev_err_probe(st->dev, ret,
713					     "reg property missing\n");
714
715		ret = ad3552r_get_output_range(st->dev, st->model_data, child,
716					       &range);
717		if (ret && ret != -ENOENT)
718			return ret;
719		if (ret == -ENOENT) {
720			ret = ad3552r_get_custom_gain(st->dev, child,
721						&st->ch_data[ch].p,
722						&st->ch_data[ch].n,
723						&st->ch_data[ch].rfb,
724						&st->ch_data[ch].gain_offset);
725			if (ret)
726				return ret;
727
728			gain = ad3552r_calc_custom_gain(st->ch_data[ch].p,
729						st->ch_data[ch].n,
730						st->ch_data[ch].gain_offset);
731			offset = abs(st->ch_data[ch].gain_offset);
732
733			st->ch_data[ch].range_override = 1;
734
735			ret = ad3552r_hs_setup_custom_gain(st, ch, gain,
736							   offset);
737			if (ret)
738				return ret;
739		} else {
740			st->ch_data[ch].range = range;
741
742			ret = ad3552r_hs_set_output_range(st, ch, range);
743			if (ret)
744				return ret;
745		}
746
747		ad3552r_calc_gain_and_offset(&st->ch_data[ch], st->model_data);
748	}
749
750	return 0;
751}
752
753static const struct iio_buffer_setup_ops ad3552r_hs_buffer_setup_ops = {
754	.postenable = ad3552r_hs_buffer_postenable,
755	.predisable = ad3552r_hs_buffer_predisable,
756};
757
758#define AD3552R_CHANNEL(ch) { \
759	.type = IIO_VOLTAGE, \
760	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
761			      BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
762			      BIT(IIO_CHAN_INFO_SCALE) | \
763			      BIT(IIO_CHAN_INFO_OFFSET), \
764	.output = 1, \
765	.indexed = 1, \
766	.channel = (ch), \
767	.scan_index = (ch), \
768	.scan_type = { \
769		.sign = 'u', \
770		.realbits = 16, \
771		.storagebits = 16, \
772		.endianness = IIO_BE, \
773	} \
774}
775
776static const struct iio_chan_spec ad3552r_hs_channels[] = {
777	AD3552R_CHANNEL(0),
778	AD3552R_CHANNEL(1),
779};
780
781static const struct iio_info ad3552r_hs_info = {
782	.read_raw = &ad3552r_hs_read_raw,
783	.write_raw = &ad3552r_hs_write_raw,
784	.debugfs_reg_access = &ad3552r_hs_reg_access,
785};
786
787static void ad3552r_hs_debugfs_init(struct iio_dev *indio_dev)
788{
789	struct ad3552r_hs_state *st = iio_priv(indio_dev);
790	struct dentry *d = iio_get_debugfs_dentry(indio_dev);
791
792	if (!IS_ENABLED(CONFIG_DEBUG_FS))
793		return;
794
795	d = iio_get_debugfs_dentry(indio_dev);
796	if (!d) {
797		dev_warn(st->dev, "can't set debugfs in driver dir\n");
798		return;
799	}
800
801	debugfs_create_file("data_source", 0600, d, st,
802			    &ad3552r_hs_data_source_fops);
803	debugfs_create_file("data_source_available", 0600, d, st,
804			    &ad3552r_hs_data_source_avail_fops);
805}
806
807static int ad3552r_hs_probe(struct platform_device *pdev)
808{
809	struct ad3552r_hs_state *st;
810	struct iio_dev *indio_dev;
811	int ret;
812
813	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
814	if (!indio_dev)
815		return -ENOMEM;
816
817	st = iio_priv(indio_dev);
818	st->dev = &pdev->dev;
819
820	st->data = dev_get_platdata(st->dev);
821	if (!st->data)
822		return dev_err_probe(st->dev, -ENODEV, "No platform data !");
823
824	st->back = devm_iio_backend_get(&pdev->dev, NULL);
825	if (IS_ERR(st->back))
826		return PTR_ERR(st->back);
827
828	ret = devm_iio_backend_enable(&pdev->dev, st->back);
829	if (ret)
830		return ret;
831
832	st->model_data = device_get_match_data(&pdev->dev);
833	if (!st->model_data)
834		return -ENODEV;
835
836	indio_dev->name = "ad3552r";
837	indio_dev->modes = INDIO_DIRECT_MODE;
838	indio_dev->setup_ops = &ad3552r_hs_buffer_setup_ops;
839	indio_dev->channels = ad3552r_hs_channels;
840	indio_dev->num_channels = ARRAY_SIZE(ad3552r_hs_channels);
841	indio_dev->info = &ad3552r_hs_info;
842
843	ret = devm_iio_backend_request_buffer(&pdev->dev, st->back, indio_dev);
844	if (ret)
845		return ret;
846
847	ret = ad3552r_hs_setup(st);
848	if (ret)
849		return ret;
850
851	ret = devm_iio_device_register(&pdev->dev, indio_dev);
852	if (ret)
853		return ret;
854
855	ret = devm_mutex_init(&pdev->dev, &st->lock);
856	if (ret)
857		return ret;
858
859	ad3552r_hs_debugfs_init(indio_dev);
860
861	return ret;
862}
863
864static const struct of_device_id ad3552r_hs_of_id[] = {
865	{ .compatible = "adi,ad3541r", .data = &ad3541r_model_data },
866	{ .compatible = "adi,ad3542r", .data = &ad3542r_model_data },
867	{ .compatible = "adi,ad3551r", .data = &ad3551r_model_data },
868	{ .compatible = "adi,ad3552r", .data = &ad3552r_model_data },
869	{ }
870};
871MODULE_DEVICE_TABLE(of, ad3552r_hs_of_id);
872
873static struct platform_driver ad3552r_hs_driver = {
874	.driver = {
875		.name = "ad3552r-hs",
876		.of_match_table = ad3552r_hs_of_id,
877	},
878	.probe = ad3552r_hs_probe,
879};
880module_platform_driver(ad3552r_hs_driver);
881
882MODULE_AUTHOR("Dragos Bogdan <dragos.bogdan@analog.com>");
883MODULE_AUTHOR("Angelo Dureghello <adueghello@baylibre.com>");
884MODULE_DESCRIPTION("AD3552R Driver - High Speed version");
885MODULE_LICENSE("GPL");
886MODULE_IMPORT_NS("IIO_BACKEND");
887MODULE_IMPORT_NS("IIO_AD3552R");