ad74413r.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (C) 2021 Analog Devices, Inc.
   4 * Author: Cosmin Tanislav <cosmin.tanislav@analog.com>
   5 */
   6
   7#include <linux/bitfield.h>
   8#include <linux/cleanup.h>
   9#include <linux/crc8.h>
  10#include <linux/device.h>
  11#include <linux/err.h>
  12#include <linux/gpio/consumer.h>
  13#include <linux/gpio/driver.h>
  14#include <linux/iio/buffer.h>
  15#include <linux/iio/iio.h>
  16#include <linux/iio/sysfs.h>
  17#include <linux/iio/trigger.h>
  18#include <linux/iio/trigger_consumer.h>
  19#include <linux/iio/triggered_buffer.h>
  20#include <linux/interrupt.h>
  21#include <linux/mod_devicetable.h>
  22#include <linux/property.h>
  23#include <linux/regmap.h>
  24#include <linux/regulator/consumer.h>
  25#include <linux/spi/spi.h>
  26#include <linux/types.h>
  27#include <linux/unaligned.h>
  28
  29#include <dt-bindings/iio/addac/adi,ad74413r.h>
  30
  31#define AD74413R_CRC_POLYNOMIAL	0x7
  32DECLARE_CRC8_TABLE(ad74413r_crc8_table);
  33
  34#define AD74413R_CHANNEL_MAX	4
  35
  36#define AD74413R_FRAME_SIZE	4
  37
  38struct ad74413r_chip_info {
  39	const char	*name;
  40	bool		hart_support;
  41};
  42
  43struct ad74413r_channel_config {
  44	u32		func;
  45	u32		drive_strength;
  46	bool		gpo_comparator;
  47	bool		initialized;
  48};
  49
  50struct ad74413r_channels {
  51	const struct iio_chan_spec	*channels;
  52	unsigned int			num_channels;
  53};
  54
  55struct ad74413r_state {
  56	struct ad74413r_channel_config	channel_configs[AD74413R_CHANNEL_MAX];
  57	unsigned int			gpo_gpio_offsets[AD74413R_CHANNEL_MAX];
  58	unsigned int			comp_gpio_offsets[AD74413R_CHANNEL_MAX];
  59	struct gpio_chip		gpo_gpiochip;
  60	struct gpio_chip		comp_gpiochip;
  61	struct completion		adc_data_completion;
  62	unsigned int			num_gpo_gpios;
  63	unsigned int			num_comparator_gpios;
  64	u32				sense_resistor_ohms;
  65	int				refin_reg_uv;
  66	/*
  67	 * Synchronize consecutive operations when doing a one-shot
  68	 * conversion and when updating the ADC samples SPI message.
  69	 */
  70	struct mutex			lock;
  71
  72	const struct ad74413r_chip_info	*chip_info;
  73	struct spi_device		*spi;
  74	struct regmap			*regmap;
  75	struct device			*dev;
  76	struct iio_trigger		*trig;
  77
  78	size_t			adc_active_channels;
  79	struct spi_message	adc_samples_msg;
  80	struct spi_transfer	adc_samples_xfer[AD74413R_CHANNEL_MAX + 1];
  81
  82	/*
  83	 * DMA (thus cache coherency maintenance) may require the
  84	 * transfer buffers to live in their own cache lines.
  85	 */
  86	struct {
  87		u8 rx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX];
  88		aligned_s64 timestamp;
  89	} adc_samples_buf __aligned(IIO_DMA_MINALIGN);
  90
  91	u8	adc_samples_tx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX];
  92	u8	reg_tx_buf[AD74413R_FRAME_SIZE];
  93	u8	reg_rx_buf[AD74413R_FRAME_SIZE];
  94};
  95
  96#define AD74413R_REG_NOP		0x00
  97
  98#define AD74413R_REG_CH_FUNC_SETUP_X(x)	(0x01 + (x))
  99#define AD74413R_CH_FUNC_SETUP_MASK	GENMASK(3, 0)
 100
 101#define AD74413R_REG_ADC_CONFIG_X(x)		(0x05 + (x))
 102#define AD74413R_ADC_CONFIG_RANGE_MASK		GENMASK(7, 5)
 103#define AD74413R_ADC_CONFIG_REJECTION_MASK	GENMASK(4, 3)
 104#define AD74413R_ADC_CONFIG_CH_200K_TO_GND	BIT(2)
 105#define AD74413R_ADC_RANGE_10V			0b000
 106#define AD74413R_ADC_RANGE_2P5V_EXT_POW		0b001
 107#define AD74413R_ADC_RANGE_2P5V_INT_POW		0b010
 108#define AD74413R_ADC_RANGE_5V_BI_DIR		0b011
 109#define AD74413R_ADC_REJECTION_50_60		0b00
 110#define AD74413R_ADC_REJECTION_NONE		0b01
 111#define AD74413R_ADC_REJECTION_50_60_HART	0b10
 112#define AD74413R_ADC_REJECTION_HART		0b11
 113
 114#define AD74413R_REG_DIN_CONFIG_X(x)	(0x09 + (x))
 115#define AD74413R_DIN_DEBOUNCE_MASK	GENMASK(4, 0)
 116#define AD74413R_DIN_DEBOUNCE_LEN	BIT(5)
 117#define AD74413R_DIN_SINK_MASK		GENMASK(9, 6)
 118
 119#define AD74413R_REG_DAC_CODE_X(x)	(0x16 + (x))
 120#define AD74413R_DAC_CODE_MAX		GENMASK(12, 0)
 121#define AD74413R_DAC_VOLTAGE_MAX	11000
 122
 123#define AD74413R_REG_GPO_PAR_DATA		0x0d
 124#define AD74413R_REG_GPO_CONFIG_X(x)		(0x0e + (x))
 125#define AD74413R_GPO_CONFIG_DATA_MASK	BIT(3)
 126#define AD74413R_GPO_CONFIG_SELECT_MASK		GENMASK(2, 0)
 127#define AD74413R_GPO_CONFIG_100K_PULL_DOWN	0b000
 128#define AD74413R_GPO_CONFIG_LOGIC		0b001
 129#define AD74413R_GPO_CONFIG_LOGIC_PARALLEL	0b010
 130#define AD74413R_GPO_CONFIG_COMPARATOR		0b011
 131#define AD74413R_GPO_CONFIG_HIGH_IMPEDANCE	0b100
 132
 133#define AD74413R_REG_ADC_CONV_CTRL	0x23
 134#define AD74413R_CONV_SEQ_MASK		GENMASK(9, 8)
 135#define AD74413R_CONV_SEQ_ON		0b00
 136#define AD74413R_CONV_SEQ_SINGLE	0b01
 137#define AD74413R_CONV_SEQ_CONTINUOUS	0b10
 138#define AD74413R_CONV_SEQ_OFF		0b11
 139#define AD74413R_CH_EN_MASK(x)		BIT(x)
 140
 141#define AD74413R_REG_DIN_COMP_OUT		0x25
 142
 143#define AD74413R_REG_ADC_RESULT_X(x)	(0x26 + (x))
 144#define AD74413R_ADC_RESULT_MAX		GENMASK(15, 0)
 145
 146#define AD74413R_REG_READ_SELECT	0x41
 147
 148#define AD74413R_REG_CMD_KEY		0x44
 149#define AD74413R_CMD_KEY_LDAC		0x953a
 150#define AD74413R_CMD_KEY_RESET1		0x15fa
 151#define AD74413R_CMD_KEY_RESET2		0xaf51
 152
 153static const int ad74413r_adc_sampling_rates[] = {
 154	20, 4800,
 155};
 156
 157static const int ad74413r_adc_sampling_rates_hart[] = {
 158	10, 20, 1200, 4800,
 159};
 160
 161static int ad74413r_crc(u8 *buf)
 162{
 163	return crc8(ad74413r_crc8_table, buf, 3, 0);
 164}
 165
 166static void ad74413r_format_reg_write(u8 reg, u16 val, u8 *buf)
 167{
 168	buf[0] = reg;
 169	put_unaligned_be16(val, &buf[1]);
 170	buf[3] = ad74413r_crc(buf);
 171}
 172
 173static int ad74413r_reg_write(void *context, unsigned int reg, unsigned int val)
 174{
 175	struct ad74413r_state *st = context;
 176
 177	ad74413r_format_reg_write(reg, val, st->reg_tx_buf);
 178
 179	return spi_write(st->spi, st->reg_tx_buf, AD74413R_FRAME_SIZE);
 180}
 181
 182static int ad74413r_crc_check(struct ad74413r_state *st, u8 *buf)
 183{
 184	u8 expected_crc = ad74413r_crc(buf);
 185
 186	if (buf[3] != expected_crc) {
 187		dev_err(st->dev, "Bad CRC %02x for %02x%02x%02x\n",
 188			buf[3], buf[0], buf[1], buf[2]);
 189		return -EINVAL;
 190	}
 191
 192	return 0;
 193}
 194
 195static int ad74413r_reg_read(void *context, unsigned int reg, unsigned int *val)
 196{
 197	struct ad74413r_state *st = context;
 198	struct spi_transfer reg_read_xfer[] = {
 199		{
 200			.tx_buf = st->reg_tx_buf,
 201			.len = AD74413R_FRAME_SIZE,
 202			.cs_change = 1,
 203		},
 204		{
 205			.rx_buf = st->reg_rx_buf,
 206			.len = AD74413R_FRAME_SIZE,
 207		},
 208	};
 209	int ret;
 210
 211	ad74413r_format_reg_write(AD74413R_REG_READ_SELECT, reg,
 212				  st->reg_tx_buf);
 213
 214	ret = spi_sync_transfer(st->spi, reg_read_xfer,
 215				ARRAY_SIZE(reg_read_xfer));
 216	if (ret)
 217		return ret;
 218
 219	ret = ad74413r_crc_check(st, st->reg_rx_buf);
 220	if (ret)
 221		return ret;
 222
 223	*val = get_unaligned_be16(&st->reg_rx_buf[1]);
 224
 225	return 0;
 226}
 227
 228static const struct regmap_config ad74413r_regmap_config = {
 229	.reg_bits = 8,
 230	.val_bits = 16,
 231	.reg_read = ad74413r_reg_read,
 232	.reg_write = ad74413r_reg_write,
 233};
 234
 235static int ad74413r_set_gpo_config(struct ad74413r_state *st,
 236				   unsigned int offset, u8 mode)
 237{
 238	return regmap_update_bits(st->regmap, AD74413R_REG_GPO_CONFIG_X(offset),
 239				  AD74413R_GPO_CONFIG_SELECT_MASK, mode);
 240}
 241
 242static const unsigned int ad74413r_debounce_map[AD74413R_DIN_DEBOUNCE_LEN] = {
 243	0,     13,    18,    24,    32,    42,    56,    75,
 244	100,   130,   180,   240,   320,   420,   560,   750,
 245	1000,  1300,  1800,  2400,  3200,  4200,  5600,  7500,
 246	10000, 13000, 18000, 24000, 32000, 42000, 56000, 75000,
 247};
 248
 249static int ad74413r_set_comp_debounce(struct ad74413r_state *st,
 250				      unsigned int offset,
 251				      unsigned int debounce)
 252{
 253	unsigned int val = AD74413R_DIN_DEBOUNCE_LEN - 1;
 254	unsigned int i;
 255
 256	for (i = 0; i < AD74413R_DIN_DEBOUNCE_LEN; i++)
 257		if (debounce <= ad74413r_debounce_map[i]) {
 258			val = i;
 259			break;
 260		}
 261
 262	return regmap_update_bits(st->regmap,
 263				  AD74413R_REG_DIN_CONFIG_X(offset),
 264				  AD74413R_DIN_DEBOUNCE_MASK,
 265				  val);
 266}
 267
 268static int ad74413r_set_comp_drive_strength(struct ad74413r_state *st,
 269					    unsigned int offset,
 270					    unsigned int strength)
 271{
 272	strength = min(strength, 1800U);
 273
 274	return regmap_update_bits(st->regmap, AD74413R_REG_DIN_CONFIG_X(offset),
 275				  AD74413R_DIN_SINK_MASK,
 276				  FIELD_PREP(AD74413R_DIN_SINK_MASK, strength / 120));
 277}
 278
 279
 280static int ad74413r_gpio_set(struct gpio_chip *chip, unsigned int offset,
 281			     int val)
 282{
 283	struct ad74413r_state *st = gpiochip_get_data(chip);
 284	unsigned int real_offset = st->gpo_gpio_offsets[offset];
 285	int ret;
 286
 287	ret = ad74413r_set_gpo_config(st, real_offset,
 288				      AD74413R_GPO_CONFIG_LOGIC);
 289	if (ret)
 290		return ret;
 291
 292	return regmap_update_bits(st->regmap,
 293				  AD74413R_REG_GPO_CONFIG_X(real_offset),
 294				  AD74413R_GPO_CONFIG_DATA_MASK,
 295				  val ? AD74413R_GPO_CONFIG_DATA_MASK : 0);
 296}
 297
 298static int ad74413r_gpio_set_multiple(struct gpio_chip *chip,
 299				      unsigned long *mask, unsigned long *bits)
 300{
 301	struct ad74413r_state *st = gpiochip_get_data(chip);
 302	unsigned long real_mask = 0;
 303	unsigned long real_bits = 0;
 304	unsigned int offset;
 305	int ret;
 306
 307	for_each_set_bit(offset, mask, chip->ngpio) {
 308		unsigned int real_offset = st->gpo_gpio_offsets[offset];
 309
 310		ret = ad74413r_set_gpo_config(st, real_offset,
 311			AD74413R_GPO_CONFIG_LOGIC_PARALLEL);
 312		if (ret)
 313			return ret;
 314
 315		real_mask |= BIT(real_offset);
 316		if (*bits & offset)
 317			real_bits |= BIT(real_offset);
 318	}
 319
 320	return regmap_update_bits(st->regmap, AD74413R_REG_GPO_PAR_DATA,
 321				  real_mask, real_bits);
 322}
 323
 324static int ad74413r_gpio_get(struct gpio_chip *chip, unsigned int offset)
 325{
 326	struct ad74413r_state *st = gpiochip_get_data(chip);
 327	unsigned int real_offset = st->comp_gpio_offsets[offset];
 328	unsigned int status;
 329	int ret;
 330
 331	ret = regmap_read(st->regmap, AD74413R_REG_DIN_COMP_OUT, &status);
 332	if (ret)
 333		return ret;
 334
 335	status &= BIT(real_offset);
 336
 337	return status ? 1 : 0;
 338}
 339
 340static int ad74413r_gpio_get_multiple(struct gpio_chip *chip,
 341				      unsigned long *mask,
 342				      unsigned long *bits)
 343{
 344	struct ad74413r_state *st = gpiochip_get_data(chip);
 345	unsigned int offset;
 346	unsigned int val;
 347	int ret;
 348
 349	ret = regmap_read(st->regmap, AD74413R_REG_DIN_COMP_OUT, &val);
 350	if (ret)
 351		return ret;
 352
 353	for_each_set_bit(offset, mask, chip->ngpio) {
 354		unsigned int real_offset = st->comp_gpio_offsets[offset];
 355
 356		__assign_bit(offset, bits, val & BIT(real_offset));
 357	}
 358
 359	return ret;
 360}
 361
 362static int ad74413r_gpio_get_gpo_direction(struct gpio_chip *chip,
 363					   unsigned int offset)
 364{
 365	return GPIO_LINE_DIRECTION_OUT;
 366}
 367
 368static int ad74413r_gpio_get_comp_direction(struct gpio_chip *chip,
 369					    unsigned int offset)
 370{
 371	return GPIO_LINE_DIRECTION_IN;
 372}
 373
 374static int ad74413r_gpio_set_gpo_config(struct gpio_chip *chip,
 375					unsigned int offset,
 376					unsigned long config)
 377{
 378	struct ad74413r_state *st = gpiochip_get_data(chip);
 379	unsigned int real_offset = st->gpo_gpio_offsets[offset];
 380
 381	switch (pinconf_to_config_param(config)) {
 382	case PIN_CONFIG_BIAS_PULL_DOWN:
 383		return ad74413r_set_gpo_config(st, real_offset,
 384			AD74413R_GPO_CONFIG_100K_PULL_DOWN);
 385	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
 386		return ad74413r_set_gpo_config(st, real_offset,
 387			AD74413R_GPO_CONFIG_HIGH_IMPEDANCE);
 388	default:
 389		return -ENOTSUPP;
 390	}
 391}
 392
 393static int ad74413r_gpio_set_comp_config(struct gpio_chip *chip,
 394					 unsigned int offset,
 395					 unsigned long config)
 396{
 397	struct ad74413r_state *st = gpiochip_get_data(chip);
 398	unsigned int real_offset = st->comp_gpio_offsets[offset];
 399
 400	switch (pinconf_to_config_param(config)) {
 401	case PIN_CONFIG_INPUT_DEBOUNCE:
 402		return ad74413r_set_comp_debounce(st, real_offset,
 403			pinconf_to_config_argument(config));
 404	default:
 405		return -ENOTSUPP;
 406	}
 407}
 408
 409static int ad74413r_reset(struct ad74413r_state *st)
 410{
 411	struct gpio_desc *reset_gpio;
 412	int ret;
 413
 414	reset_gpio = devm_gpiod_get_optional(st->dev, "reset", GPIOD_OUT_HIGH);
 415	if (IS_ERR(reset_gpio))
 416		return PTR_ERR(reset_gpio);
 417
 418	if (reset_gpio) {
 419		fsleep(50);
 420		gpiod_set_value_cansleep(reset_gpio, 0);
 421		return 0;
 422	}
 423
 424	ret = regmap_write(st->regmap, AD74413R_REG_CMD_KEY,
 425			   AD74413R_CMD_KEY_RESET1);
 426	if (ret)
 427		return ret;
 428
 429	return regmap_write(st->regmap, AD74413R_REG_CMD_KEY,
 430			    AD74413R_CMD_KEY_RESET2);
 431}
 432
 433static int ad74413r_set_channel_dac_code(struct ad74413r_state *st,
 434					 unsigned int channel, int dac_code)
 435{
 436	struct reg_sequence reg_seq[2] = {
 437		{ AD74413R_REG_DAC_CODE_X(channel), dac_code },
 438		{ AD74413R_REG_CMD_KEY, AD74413R_CMD_KEY_LDAC },
 439	};
 440
 441	return regmap_multi_reg_write(st->regmap, reg_seq, 2);
 442}
 443
 444static int ad74413r_set_channel_function(struct ad74413r_state *st,
 445					 unsigned int channel, u8 func)
 446{
 447	int ret;
 448
 449	ret = regmap_update_bits(st->regmap,
 450				 AD74413R_REG_CH_FUNC_SETUP_X(channel),
 451				 AD74413R_CH_FUNC_SETUP_MASK,
 452				 CH_FUNC_HIGH_IMPEDANCE);
 453	if (ret)
 454		return ret;
 455
 456	/* Set DAC code to 0 prior to changing channel function */
 457	ret = ad74413r_set_channel_dac_code(st, channel, 0);
 458	if (ret)
 459		return ret;
 460
 461	/* Delay required before transition to new desired mode */
 462	usleep_range(130, 150);
 463
 464	ret = regmap_update_bits(st->regmap,
 465				  AD74413R_REG_CH_FUNC_SETUP_X(channel),
 466				  AD74413R_CH_FUNC_SETUP_MASK, func);
 467	if (ret)
 468		return ret;
 469
 470	/* Delay required before updating the new DAC code */
 471	usleep_range(150, 170);
 472
 473	if (func == CH_FUNC_CURRENT_INPUT_LOOP_POWER)
 474		ret = regmap_set_bits(st->regmap,
 475				      AD74413R_REG_ADC_CONFIG_X(channel),
 476				      AD74413R_ADC_CONFIG_CH_200K_TO_GND);
 477
 478	return ret;
 479}
 480
 481static int ad74413r_set_adc_conv_seq(struct ad74413r_state *st,
 482				     unsigned int status)
 483{
 484	int ret;
 485
 486	/*
 487	 * These bits do not clear when a conversion completes.
 488	 * To enable a subsequent conversion, repeat the write.
 489	 */
 490	ret = regmap_write_bits(st->regmap, AD74413R_REG_ADC_CONV_CTRL,
 491				AD74413R_CONV_SEQ_MASK,
 492				FIELD_PREP(AD74413R_CONV_SEQ_MASK, status));
 493	if (ret)
 494		return ret;
 495
 496	/*
 497	 * Wait 100us before starting conversions.
 498	 */
 499	usleep_range(100, 120);
 500
 501	return 0;
 502}
 503
 504static int ad74413r_set_adc_channel_enable(struct ad74413r_state *st,
 505					   unsigned int channel,
 506					   bool status)
 507{
 508	return regmap_update_bits(st->regmap, AD74413R_REG_ADC_CONV_CTRL,
 509				  AD74413R_CH_EN_MASK(channel),
 510				  status ? AD74413R_CH_EN_MASK(channel) : 0);
 511}
 512
 513static int ad74413r_get_adc_range(struct ad74413r_state *st,
 514				  unsigned int channel,
 515				  unsigned int *val)
 516{
 517	int ret;
 518
 519	ret = regmap_read(st->regmap, AD74413R_REG_ADC_CONFIG_X(channel), val);
 520	if (ret)
 521		return ret;
 522
 523	*val = FIELD_GET(AD74413R_ADC_CONFIG_RANGE_MASK, *val);
 524
 525	return 0;
 526}
 527
 528static int ad74413r_get_adc_rejection(struct ad74413r_state *st,
 529				      unsigned int channel,
 530				      unsigned int *val)
 531{
 532	int ret;
 533
 534	ret = regmap_read(st->regmap, AD74413R_REG_ADC_CONFIG_X(channel), val);
 535	if (ret)
 536		return ret;
 537
 538	*val = FIELD_GET(AD74413R_ADC_CONFIG_REJECTION_MASK, *val);
 539
 540	return 0;
 541}
 542
 543static int ad74413r_set_adc_rejection(struct ad74413r_state *st,
 544				      unsigned int channel,
 545				      unsigned int val)
 546{
 547	return regmap_update_bits(st->regmap,
 548				  AD74413R_REG_ADC_CONFIG_X(channel),
 549				  AD74413R_ADC_CONFIG_REJECTION_MASK,
 550				  FIELD_PREP(AD74413R_ADC_CONFIG_REJECTION_MASK,
 551					     val));
 552}
 553
 554static int ad74413r_rejection_to_rate(struct ad74413r_state *st,
 555				      unsigned int rej, int *val)
 556{
 557	switch (rej) {
 558	case AD74413R_ADC_REJECTION_50_60:
 559		*val = 20;
 560		return 0;
 561	case AD74413R_ADC_REJECTION_NONE:
 562		*val = 4800;
 563		return 0;
 564	case AD74413R_ADC_REJECTION_50_60_HART:
 565		*val = 10;
 566		return 0;
 567	case AD74413R_ADC_REJECTION_HART:
 568		*val = 1200;
 569		return 0;
 570	default:
 571		dev_err(st->dev, "ADC rejection invalid\n");
 572		return -EINVAL;
 573	}
 574}
 575
 576static int ad74413r_rate_to_rejection(struct ad74413r_state *st,
 577				      int rate, unsigned int *val)
 578{
 579	switch (rate) {
 580	case 20:
 581		*val = AD74413R_ADC_REJECTION_50_60;
 582		return 0;
 583	case 4800:
 584		*val = AD74413R_ADC_REJECTION_NONE;
 585		return 0;
 586	case 10:
 587		*val = AD74413R_ADC_REJECTION_50_60_HART;
 588		return 0;
 589	case 1200:
 590		*val = AD74413R_ADC_REJECTION_HART;
 591		return 0;
 592	default:
 593		dev_err(st->dev, "ADC rate invalid\n");
 594		return -EINVAL;
 595	}
 596}
 597
 598static int ad74413r_range_to_voltage_range(struct ad74413r_state *st,
 599					   unsigned int range, int *val)
 600{
 601	switch (range) {
 602	case AD74413R_ADC_RANGE_10V:
 603		*val = 10000;
 604		return 0;
 605	case AD74413R_ADC_RANGE_2P5V_EXT_POW:
 606	case AD74413R_ADC_RANGE_2P5V_INT_POW:
 607		*val = 2500;
 608		return 0;
 609	case AD74413R_ADC_RANGE_5V_BI_DIR:
 610		*val = 5000;
 611		return 0;
 612	default:
 613		dev_err(st->dev, "ADC range invalid\n");
 614		return -EINVAL;
 615	}
 616}
 617
 618static int ad74413r_range_to_voltage_offset(struct ad74413r_state *st,
 619					    unsigned int range, int *val)
 620{
 621	switch (range) {
 622	case AD74413R_ADC_RANGE_10V:
 623	case AD74413R_ADC_RANGE_2P5V_EXT_POW:
 624		*val = 0;
 625		return 0;
 626	case AD74413R_ADC_RANGE_2P5V_INT_POW:
 627	case AD74413R_ADC_RANGE_5V_BI_DIR:
 628		*val = -2500;
 629		return 0;
 630	default:
 631		dev_err(st->dev, "ADC range invalid\n");
 632		return -EINVAL;
 633	}
 634}
 635
 636static int ad74413r_range_to_voltage_offset_raw(struct ad74413r_state *st,
 637						unsigned int range, int *val)
 638{
 639	switch (range) {
 640	case AD74413R_ADC_RANGE_10V:
 641	case AD74413R_ADC_RANGE_2P5V_EXT_POW:
 642		*val = 0;
 643		return 0;
 644	case AD74413R_ADC_RANGE_2P5V_INT_POW:
 645		*val = -((int)AD74413R_ADC_RESULT_MAX);
 646		return 0;
 647	case AD74413R_ADC_RANGE_5V_BI_DIR:
 648		*val = -((int)AD74413R_ADC_RESULT_MAX / 2);
 649		return 0;
 650	default:
 651		dev_err(st->dev, "ADC range invalid\n");
 652		return -EINVAL;
 653	}
 654}
 655
 656static int ad74413r_get_output_voltage_scale(struct ad74413r_state *st,
 657					     int *val, int *val2)
 658{
 659	*val = AD74413R_DAC_VOLTAGE_MAX;
 660	*val2 = AD74413R_DAC_CODE_MAX;
 661
 662	return IIO_VAL_FRACTIONAL;
 663}
 664
 665static int ad74413r_get_output_current_scale(struct ad74413r_state *st,
 666					     int *val, int *val2)
 667{
 668	*val = st->refin_reg_uv;
 669	*val2 = st->sense_resistor_ohms * AD74413R_DAC_CODE_MAX * 1000;
 670
 671	return IIO_VAL_FRACTIONAL;
 672}
 673
 674static int ad74413r_get_input_voltage_scale(struct ad74413r_state *st,
 675					    unsigned int channel,
 676					    int *val, int *val2)
 677{
 678	unsigned int range;
 679	int ret;
 680
 681	ret = ad74413r_get_adc_range(st, channel, &range);
 682	if (ret)
 683		return ret;
 684
 685	ret = ad74413r_range_to_voltage_range(st, range, val);
 686	if (ret)
 687		return ret;
 688
 689	*val2 = AD74413R_ADC_RESULT_MAX;
 690
 691	return IIO_VAL_FRACTIONAL;
 692}
 693
 694static int ad74413r_get_input_voltage_offset(struct ad74413r_state *st,
 695					     unsigned int channel, int *val)
 696{
 697	unsigned int range;
 698	int ret;
 699
 700	ret = ad74413r_get_adc_range(st, channel, &range);
 701	if (ret)
 702		return ret;
 703
 704	ret = ad74413r_range_to_voltage_offset_raw(st, range, val);
 705	if (ret)
 706		return ret;
 707
 708	return IIO_VAL_INT;
 709}
 710
 711static int ad74413r_get_input_current_scale(struct ad74413r_state *st,
 712					    unsigned int channel, int *val,
 713					    int *val2)
 714{
 715	unsigned int range;
 716	int ret;
 717
 718	ret = ad74413r_get_adc_range(st, channel, &range);
 719	if (ret)
 720		return ret;
 721
 722	ret = ad74413r_range_to_voltage_range(st, range, val);
 723	if (ret)
 724		return ret;
 725
 726	*val2 = AD74413R_ADC_RESULT_MAX * st->sense_resistor_ohms;
 727
 728	return IIO_VAL_FRACTIONAL;
 729}
 730
 731static int ad74413r_get_input_current_offset(struct ad74413r_state *st,
 732					     unsigned int channel, int *val)
 733{
 734	unsigned int range;
 735	int voltage_range;
 736	int voltage_offset;
 737	int ret;
 738
 739	ret = ad74413r_get_adc_range(st, channel, &range);
 740	if (ret)
 741		return ret;
 742
 743	ret = ad74413r_range_to_voltage_range(st, range, &voltage_range);
 744	if (ret)
 745		return ret;
 746
 747	ret = ad74413r_range_to_voltage_offset(st, range, &voltage_offset);
 748	if (ret)
 749		return ret;
 750
 751	*val = voltage_offset * (int)AD74413R_ADC_RESULT_MAX / voltage_range;
 752
 753	return IIO_VAL_INT;
 754}
 755
 756static int ad74413r_get_adc_rate(struct ad74413r_state *st,
 757				 unsigned int channel, int *val)
 758{
 759	unsigned int rejection;
 760	int ret;
 761
 762	ret = ad74413r_get_adc_rejection(st, channel, &rejection);
 763	if (ret)
 764		return ret;
 765
 766	ret = ad74413r_rejection_to_rate(st, rejection, val);
 767	if (ret)
 768		return ret;
 769
 770	return IIO_VAL_INT;
 771}
 772
 773static int ad74413r_set_adc_rate(struct ad74413r_state *st,
 774				 unsigned int channel, int val)
 775{
 776	unsigned int rejection;
 777	int ret;
 778
 779	ret = ad74413r_rate_to_rejection(st, val, &rejection);
 780	if (ret)
 781		return ret;
 782
 783	return ad74413r_set_adc_rejection(st, channel, rejection);
 784}
 785
 786static irqreturn_t ad74413r_trigger_handler(int irq, void *p)
 787{
 788	struct iio_poll_func *pf = p;
 789	struct iio_dev *indio_dev = pf->indio_dev;
 790	struct ad74413r_state *st = iio_priv(indio_dev);
 791	u8 *rx_buf = st->adc_samples_buf.rx_buf;
 792	unsigned int i;
 793	int ret;
 794
 795	ret = spi_sync(st->spi, &st->adc_samples_msg);
 796	if (ret)
 797		goto out;
 798
 799	for (i = 0; i < st->adc_active_channels; i++)
 800		ad74413r_crc_check(st, &rx_buf[i * AD74413R_FRAME_SIZE]);
 801
 802	iio_push_to_buffers_with_timestamp(indio_dev, &st->adc_samples_buf,
 803					   iio_get_time_ns(indio_dev));
 804
 805out:
 806	iio_trigger_notify_done(indio_dev->trig);
 807
 808	return IRQ_HANDLED;
 809}
 810
 811static irqreturn_t ad74413r_adc_data_interrupt(int irq, void *data)
 812{
 813	struct iio_dev *indio_dev = data;
 814	struct ad74413r_state *st = iio_priv(indio_dev);
 815
 816	if (iio_buffer_enabled(indio_dev))
 817		iio_trigger_poll(st->trig);
 818	else
 819		complete(&st->adc_data_completion);
 820
 821	return IRQ_HANDLED;
 822}
 823
 824static int _ad74413r_get_single_adc_result(struct ad74413r_state *st,
 825					   unsigned int channel, int *val)
 826{
 827	unsigned int uval;
 828	int ret;
 829
 830	guard(mutex)(&st->lock);
 831
 832	reinit_completion(&st->adc_data_completion);
 833
 834	ret = ad74413r_set_adc_channel_enable(st, channel, true);
 835	if (ret)
 836		return ret;
 837
 838	ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_SINGLE);
 839	if (ret)
 840		return ret;
 841
 842	ret = wait_for_completion_timeout(&st->adc_data_completion,
 843					  msecs_to_jiffies(1000));
 844	if (!ret) {
 845		ret = -ETIMEDOUT;
 846		return ret;
 847	}
 848
 849	ret = regmap_read(st->regmap, AD74413R_REG_ADC_RESULT_X(channel),
 850			  &uval);
 851	if (ret)
 852		return ret;
 853
 854	ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF);
 855	if (ret)
 856		return ret;
 857
 858	ret = ad74413r_set_adc_channel_enable(st, channel, false);
 859	if (ret)
 860		return ret;
 861
 862	*val = uval;
 863
 864	return IIO_VAL_INT;
 865}
 866
 867static int ad74413r_get_single_adc_result(struct iio_dev *indio_dev,
 868					  unsigned int channel, int *val)
 869{
 870	struct ad74413r_state *st = iio_priv(indio_dev);
 871	int ret;
 872
 873	if (!iio_device_claim_direct(indio_dev))
 874		return -EBUSY;
 875
 876	ret = _ad74413r_get_single_adc_result(st, channel, val);
 877	iio_device_release_direct(indio_dev);
 878	return ret;
 879}
 880
 881static void ad74413r_adc_to_resistance_result(int adc_result, int *val)
 882{
 883	if (adc_result == AD74413R_ADC_RESULT_MAX)
 884		adc_result = AD74413R_ADC_RESULT_MAX - 1;
 885
 886	*val = DIV_ROUND_CLOSEST(adc_result * 2100,
 887				 AD74413R_ADC_RESULT_MAX - adc_result);
 888}
 889
 890static int ad74413r_update_scan_mode(struct iio_dev *indio_dev,
 891				     const unsigned long *active_scan_mask)
 892{
 893	struct ad74413r_state *st = iio_priv(indio_dev);
 894	struct spi_transfer *xfer = st->adc_samples_xfer;
 895	u8 *rx_buf = st->adc_samples_buf.rx_buf;
 896	u8 *tx_buf = st->adc_samples_tx_buf;
 897	unsigned int channel;
 898	int ret = -EINVAL;
 899
 900	guard(mutex)(&st->lock);
 901
 902	spi_message_init(&st->adc_samples_msg);
 903	st->adc_active_channels = 0;
 904
 905	for_each_clear_bit(channel, active_scan_mask, AD74413R_CHANNEL_MAX) {
 906		ret = ad74413r_set_adc_channel_enable(st, channel, false);
 907		if (ret)
 908			return ret;
 909	}
 910
 911	if (*active_scan_mask == 0)
 912		return ret;
 913
 914	/*
 915	 * The read select register is used to select which register's value
 916	 * will be sent by the slave on the next SPI frame.
 917	 *
 918	 * Create an SPI message that, on each step, writes to the read select
 919	 * register to select the ADC result of the next enabled channel, and
 920	 * reads the ADC result of the previous enabled channel.
 921	 *
 922	 * Example:
 923	 * W: [WCH1] [WCH2] [WCH2] [WCH3] [    ]
 924	 * R: [    ] [RCH1] [RCH2] [RCH3] [RCH4]
 925	 */
 926
 927	for_each_set_bit(channel, active_scan_mask, AD74413R_CHANNEL_MAX) {
 928		ret = ad74413r_set_adc_channel_enable(st, channel, true);
 929		if (ret)
 930			return ret;
 931
 932		st->adc_active_channels++;
 933
 934		if (xfer == st->adc_samples_xfer)
 935			xfer->rx_buf = NULL;
 936		else
 937			xfer->rx_buf = rx_buf;
 938
 939		xfer->tx_buf = tx_buf;
 940		xfer->len = AD74413R_FRAME_SIZE;
 941		xfer->cs_change = 1;
 942
 943		ad74413r_format_reg_write(AD74413R_REG_READ_SELECT,
 944					  AD74413R_REG_ADC_RESULT_X(channel),
 945					  tx_buf);
 946
 947		spi_message_add_tail(xfer, &st->adc_samples_msg);
 948
 949		tx_buf += AD74413R_FRAME_SIZE;
 950		if (xfer != st->adc_samples_xfer)
 951			rx_buf += AD74413R_FRAME_SIZE;
 952		xfer++;
 953	}
 954
 955	xfer->rx_buf = rx_buf;
 956	xfer->tx_buf = NULL;
 957	xfer->len = AD74413R_FRAME_SIZE;
 958	xfer->cs_change = 0;
 959
 960	spi_message_add_tail(xfer, &st->adc_samples_msg);
 961	return 0;
 962}
 963
 964static int ad74413r_buffer_postenable(struct iio_dev *indio_dev)
 965{
 966	struct ad74413r_state *st = iio_priv(indio_dev);
 967
 968	return ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_CONTINUOUS);
 969}
 970
 971static int ad74413r_buffer_predisable(struct iio_dev *indio_dev)
 972{
 973	struct ad74413r_state *st = iio_priv(indio_dev);
 974
 975	return ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF);
 976}
 977
 978static int ad74413r_read_raw(struct iio_dev *indio_dev,
 979			     struct iio_chan_spec const *chan,
 980			     int *val, int *val2, long info)
 981{
 982	struct ad74413r_state *st = iio_priv(indio_dev);
 983
 984	switch (info) {
 985	case IIO_CHAN_INFO_SCALE:
 986		switch (chan->type) {
 987		case IIO_VOLTAGE:
 988			if (chan->output)
 989				return ad74413r_get_output_voltage_scale(st,
 990					val, val2);
 991			else
 992				return ad74413r_get_input_voltage_scale(st,
 993					chan->channel, val, val2);
 994		case IIO_CURRENT:
 995			if (chan->output)
 996				return ad74413r_get_output_current_scale(st,
 997					val, val2);
 998			else
 999				return ad74413r_get_input_current_scale(st,
1000					chan->channel, val, val2);
1001		default:
1002			return -EINVAL;
1003		}
1004	case IIO_CHAN_INFO_OFFSET:
1005		switch (chan->type) {
1006		case IIO_VOLTAGE:
1007			return ad74413r_get_input_voltage_offset(st,
1008				chan->channel, val);
1009		case IIO_CURRENT:
1010			return ad74413r_get_input_current_offset(st,
1011				chan->channel, val);
1012		default:
1013			return -EINVAL;
1014		}
1015	case IIO_CHAN_INFO_RAW:
1016		if (chan->output)
1017			return -EINVAL;
1018
1019		return ad74413r_get_single_adc_result(indio_dev, chan->channel,
1020						      val);
1021	case IIO_CHAN_INFO_PROCESSED: {
1022		int ret;
1023
1024		ret = ad74413r_get_single_adc_result(indio_dev, chan->channel,
1025						     val);
1026		if (ret < 0)
1027			return ret;
1028
1029		ad74413r_adc_to_resistance_result(*val, val);
1030
1031		return ret;
1032	}
1033	case IIO_CHAN_INFO_SAMP_FREQ:
1034		return ad74413r_get_adc_rate(st, chan->channel, val);
1035	default:
1036		return -EINVAL;
1037	}
1038}
1039
1040static int ad74413r_write_raw(struct iio_dev *indio_dev,
1041			      struct iio_chan_spec const *chan,
1042			      int val, int val2, long info)
1043{
1044	struct ad74413r_state *st = iio_priv(indio_dev);
1045
1046	switch (info) {
1047	case IIO_CHAN_INFO_RAW:
1048		if (!chan->output)
1049			return -EINVAL;
1050
1051		if (val < 0 || val > AD74413R_DAC_CODE_MAX) {
1052			dev_err(st->dev, "Invalid DAC code\n");
1053			return -EINVAL;
1054		}
1055
1056		return ad74413r_set_channel_dac_code(st, chan->channel, val);
1057	case IIO_CHAN_INFO_SAMP_FREQ:
1058		return ad74413r_set_adc_rate(st, chan->channel, val);
1059	default:
1060		return -EINVAL;
1061	}
1062}
1063
1064static int ad74413r_read_avail(struct iio_dev *indio_dev,
1065			       struct iio_chan_spec const *chan,
1066			       const int **vals, int *type, int *length,
1067			       long info)
1068{
1069	struct ad74413r_state *st = iio_priv(indio_dev);
1070
1071	switch (info) {
1072	case IIO_CHAN_INFO_SAMP_FREQ:
1073		if (st->chip_info->hart_support) {
1074			*vals = ad74413r_adc_sampling_rates_hart;
1075			*length = ARRAY_SIZE(ad74413r_adc_sampling_rates_hart);
1076		} else {
1077			*vals = ad74413r_adc_sampling_rates;
1078			*length = ARRAY_SIZE(ad74413r_adc_sampling_rates);
1079		}
1080		*type = IIO_VAL_INT;
1081		return IIO_AVAIL_LIST;
1082	default:
1083		return -EINVAL;
1084	}
1085}
1086
1087static const struct iio_buffer_setup_ops ad74413r_buffer_ops = {
1088	.postenable = &ad74413r_buffer_postenable,
1089	.predisable = &ad74413r_buffer_predisable,
1090};
1091
1092static const struct iio_trigger_ops ad74413r_trigger_ops = {
1093	.validate_device = iio_trigger_validate_own_device,
1094};
1095
1096static const struct iio_info ad74413r_info = {
1097	.read_raw = &ad74413r_read_raw,
1098	.write_raw = &ad74413r_write_raw,
1099	.read_avail = &ad74413r_read_avail,
1100	.update_scan_mode = &ad74413r_update_scan_mode,
1101};
1102
1103#define AD74413R_DAC_CHANNEL(_type, extra_mask_separate)		\
1104	{								\
1105		.type = (_type),					\
1106		.indexed = 1,						\
1107		.output = 1,						\
1108		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW)		\
1109				      | (extra_mask_separate),		\
1110	}
1111
1112#define AD74413R_ADC_CHANNEL(_type, extra_mask_separate)		\
1113	{								\
1114		.type = (_type),					\
1115		.indexed = 1,						\
1116		.output = 0,						\
1117		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW)		\
1118				      | BIT(IIO_CHAN_INFO_SAMP_FREQ)	\
1119				      | (extra_mask_separate),		\
1120		.info_mask_separate_available =				\
1121					BIT(IIO_CHAN_INFO_SAMP_FREQ),	\
1122		.scan_type = {						\
1123			.sign = 'u',					\
1124			.realbits = 16,					\
1125			.storagebits = 32,				\
1126			.shift = 8,					\
1127			.endianness = IIO_BE,				\
1128		},							\
1129	}
1130
1131#define AD74413R_ADC_VOLTAGE_CHANNEL					\
1132	AD74413R_ADC_CHANNEL(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE)	\
1133			     | BIT(IIO_CHAN_INFO_OFFSET))
1134
1135#define AD74413R_ADC_CURRENT_CHANNEL					\
1136	AD74413R_ADC_CHANNEL(IIO_CURRENT,  BIT(IIO_CHAN_INFO_SCALE)	\
1137			     | BIT(IIO_CHAN_INFO_OFFSET))
1138
1139static const struct iio_chan_spec ad74413r_voltage_output_channels[] = {
1140	AD74413R_DAC_CHANNEL(IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE)),
1141	AD74413R_ADC_CURRENT_CHANNEL,
1142};
1143
1144static const struct iio_chan_spec ad74413r_current_output_channels[] = {
1145	AD74413R_DAC_CHANNEL(IIO_CURRENT, BIT(IIO_CHAN_INFO_SCALE)),
1146	AD74413R_ADC_VOLTAGE_CHANNEL,
1147};
1148
1149static const struct iio_chan_spec ad74413r_voltage_input_channels[] = {
1150	AD74413R_ADC_VOLTAGE_CHANNEL,
1151};
1152
1153static const struct iio_chan_spec ad74413r_current_input_channels[] = {
1154	AD74413R_ADC_CURRENT_CHANNEL,
1155};
1156
1157static const struct iio_chan_spec ad74413r_current_input_loop_channels[] = {
1158	AD74413R_DAC_CHANNEL(IIO_CURRENT, BIT(IIO_CHAN_INFO_SCALE)),
1159	AD74413R_ADC_CURRENT_CHANNEL,
1160};
1161
1162static const struct iio_chan_spec ad74413r_resistance_input_channels[] = {
1163	AD74413R_ADC_CHANNEL(IIO_RESISTANCE, BIT(IIO_CHAN_INFO_PROCESSED)),
1164};
1165
1166static const struct iio_chan_spec ad74413r_digital_input_channels[] = {
1167	AD74413R_ADC_VOLTAGE_CHANNEL,
1168};
1169
1170#define _AD74413R_CHANNELS(_channels)			\
1171	{						\
1172		.channels = _channels,			\
1173		.num_channels = ARRAY_SIZE(_channels),	\
1174	}
1175
1176#define AD74413R_CHANNELS(name) \
1177	_AD74413R_CHANNELS(ad74413r_ ## name ## _channels)
1178
1179static const struct ad74413r_channels ad74413r_channels_map[] = {
1180	[CH_FUNC_HIGH_IMPEDANCE] = AD74413R_CHANNELS(voltage_input),
1181	[CH_FUNC_VOLTAGE_OUTPUT] = AD74413R_CHANNELS(voltage_output),
1182	[CH_FUNC_CURRENT_OUTPUT] = AD74413R_CHANNELS(current_output),
1183	[CH_FUNC_VOLTAGE_INPUT] = AD74413R_CHANNELS(voltage_input),
1184	[CH_FUNC_CURRENT_INPUT_EXT_POWER] = AD74413R_CHANNELS(current_input),
1185	[CH_FUNC_CURRENT_INPUT_LOOP_POWER] = AD74413R_CHANNELS(current_input_loop),
1186	[CH_FUNC_RESISTANCE_INPUT] = AD74413R_CHANNELS(resistance_input),
1187	[CH_FUNC_DIGITAL_INPUT_LOGIC] = AD74413R_CHANNELS(digital_input),
1188	[CH_FUNC_DIGITAL_INPUT_LOOP_POWER] = AD74413R_CHANNELS(digital_input),
1189	[CH_FUNC_CURRENT_INPUT_EXT_POWER_HART] = AD74413R_CHANNELS(current_input),
1190	[CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART] = AD74413R_CHANNELS(current_input),
1191};
1192
1193static int ad74413r_parse_channel_config(struct iio_dev *indio_dev,
1194					 struct fwnode_handle *channel_node)
1195{
1196	struct ad74413r_state *st = iio_priv(indio_dev);
1197	struct ad74413r_channel_config *config;
1198	u32 index;
1199	int ret;
1200
1201	ret = fwnode_property_read_u32(channel_node, "reg", &index);
1202	if (ret) {
1203		dev_err(st->dev, "Failed to read channel reg: %d\n", ret);
1204		return ret;
1205	}
1206
1207	if (index >= AD74413R_CHANNEL_MAX) {
1208		dev_err(st->dev, "Channel index %u is too large\n", index);
1209		return -EINVAL;
1210	}
1211
1212	config = &st->channel_configs[index];
1213	if (config->initialized) {
1214		dev_err(st->dev, "Channel %u already initialized\n", index);
1215		return -EINVAL;
1216	}
1217
1218	config->func = CH_FUNC_HIGH_IMPEDANCE;
1219	fwnode_property_read_u32(channel_node, "adi,ch-func", &config->func);
1220
1221	if (config->func < CH_FUNC_MIN || config->func > CH_FUNC_MAX) {
1222		dev_err(st->dev, "Invalid channel function %u\n", config->func);
1223		return -EINVAL;
1224	}
1225
1226	if (!st->chip_info->hart_support &&
1227	    (config->func == CH_FUNC_CURRENT_INPUT_EXT_POWER_HART ||
1228	     config->func == CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART)) {
1229		dev_err(st->dev, "Unsupported HART function %u\n", config->func);
1230		return -EINVAL;
1231	}
1232
1233	if (config->func == CH_FUNC_DIGITAL_INPUT_LOGIC ||
1234	    config->func == CH_FUNC_DIGITAL_INPUT_LOOP_POWER)
1235		st->num_comparator_gpios++;
1236
1237	config->gpo_comparator = fwnode_property_read_bool(channel_node,
1238		"adi,gpo-comparator");
1239
1240	fwnode_property_read_u32(channel_node, "drive-strength-microamp",
1241				 &config->drive_strength);
1242
1243	if (!config->gpo_comparator)
1244		st->num_gpo_gpios++;
1245
1246	indio_dev->num_channels += ad74413r_channels_map[config->func].num_channels;
1247
1248	config->initialized = true;
1249
1250	return 0;
1251}
1252
1253static int ad74413r_parse_channel_configs(struct iio_dev *indio_dev)
1254{
1255	struct ad74413r_state *st = iio_priv(indio_dev);
1256	int ret;
1257
1258	device_for_each_child_node_scoped(st->dev, channel_node) {
1259		ret = ad74413r_parse_channel_config(indio_dev, channel_node);
1260		if (ret)
1261			return ret;
1262	}
1263
1264	return 0;
1265}
1266
1267static int ad74413r_setup_channels(struct iio_dev *indio_dev)
1268{
1269	struct ad74413r_state *st = iio_priv(indio_dev);
1270	struct ad74413r_channel_config *config;
1271	const struct iio_chan_spec *chans;
1272	struct iio_chan_spec *channels;
1273	unsigned int i, num_chans, chan_i;
1274	int ret;
1275
1276	channels = devm_kcalloc(st->dev, sizeof(*channels),
1277				indio_dev->num_channels, GFP_KERNEL);
1278	if (!channels)
1279		return -ENOMEM;
1280
1281	indio_dev->channels = channels;
1282
1283	for (i = 0; i < AD74413R_CHANNEL_MAX; i++) {
1284		config = &st->channel_configs[i];
1285		chans = ad74413r_channels_map[config->func].channels;
1286		num_chans = ad74413r_channels_map[config->func].num_channels;
1287
1288		memcpy(channels, chans, num_chans * sizeof(*chans));
1289
1290		for (chan_i = 0; chan_i < num_chans; chan_i++) {
1291			struct iio_chan_spec *chan = &channels[chan_i];
1292
1293			chan->channel = i;
1294			if (chan->output)
1295				chan->scan_index = -1;
1296			else
1297				chan->scan_index = i;
1298		}
1299
1300		ret = ad74413r_set_channel_function(st, i, config->func);
1301		if (ret)
1302			return ret;
1303
1304		channels += num_chans;
1305	}
1306
1307	return 0;
1308}
1309
1310static int ad74413r_setup_gpios(struct ad74413r_state *st)
1311{
1312	struct ad74413r_channel_config *config;
1313	unsigned int comp_gpio_i = 0;
1314	unsigned int gpo_gpio_i = 0;
1315	unsigned int i;
1316	u8 gpo_config;
1317	u32 strength;
1318	int ret;
1319
1320	for (i = 0; i < AD74413R_CHANNEL_MAX; i++) {
1321		config = &st->channel_configs[i];
1322
1323		if (config->gpo_comparator) {
1324			gpo_config = AD74413R_GPO_CONFIG_COMPARATOR;
1325		} else {
1326			gpo_config = AD74413R_GPO_CONFIG_LOGIC;
1327			st->gpo_gpio_offsets[gpo_gpio_i++] = i;
1328		}
1329
1330		if (config->func == CH_FUNC_DIGITAL_INPUT_LOGIC ||
1331		    config->func == CH_FUNC_DIGITAL_INPUT_LOOP_POWER) {
1332			st->comp_gpio_offsets[comp_gpio_i++] = i;
1333
1334			strength = config->drive_strength;
1335			ret = ad74413r_set_comp_drive_strength(st, i, strength);
1336			if (ret)
1337				return ret;
1338		}
1339
1340		ret = ad74413r_set_gpo_config(st, i, gpo_config);
1341		if (ret)
1342			return ret;
1343	}
1344
1345	return 0;
1346}
1347
1348static int ad74413r_probe(struct spi_device *spi)
1349{
1350	struct ad74413r_state *st;
1351	struct iio_dev *indio_dev;
1352	int ret;
1353
1354	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
1355	if (!indio_dev)
1356		return -ENOMEM;
1357
1358	st = iio_priv(indio_dev);
1359
1360	st->spi = spi;
1361	st->dev = &spi->dev;
1362	st->chip_info = spi_get_device_match_data(spi);
1363	if (!st->chip_info)
1364		return -EINVAL;
1365
1366	ret = devm_mutex_init(st->dev, &st->lock);
1367	if (ret)
1368		return ret;
1369
1370	init_completion(&st->adc_data_completion);
1371
1372	st->regmap = devm_regmap_init(st->dev, NULL, st,
1373				      &ad74413r_regmap_config);
1374	if (IS_ERR(st->regmap))
1375		return PTR_ERR(st->regmap);
1376
1377	ret = devm_regulator_get_enable_read_voltage(st->dev, "refin");
1378	if (ret < 0)
1379		return dev_err_probe(st->dev, ret,
1380				     "Failed to get refin regulator voltage\n");
1381	st->refin_reg_uv = ret;
1382
1383	st->sense_resistor_ohms = 100000000;
1384	device_property_read_u32(st->dev, "shunt-resistor-micro-ohms",
1385				 &st->sense_resistor_ohms);
1386	st->sense_resistor_ohms /= 1000000;
1387
1388	st->trig = devm_iio_trigger_alloc(st->dev, "%s-dev%d",
1389					  st->chip_info->name, iio_device_id(indio_dev));
1390	if (!st->trig)
1391		return -ENOMEM;
1392
1393	st->trig->ops = &ad74413r_trigger_ops;
1394	iio_trigger_set_drvdata(st->trig, st);
1395
1396	ret = devm_iio_trigger_register(st->dev, st->trig);
1397	if (ret)
1398		return ret;
1399
1400	indio_dev->name = st->chip_info->name;
1401	indio_dev->modes = INDIO_DIRECT_MODE;
1402	indio_dev->info = &ad74413r_info;
1403	indio_dev->trig = iio_trigger_get(st->trig);
1404
1405	ret = ad74413r_reset(st);
1406	if (ret)
1407		return ret;
1408
1409	ret = ad74413r_parse_channel_configs(indio_dev);
1410	if (ret)
1411		return ret;
1412
1413	ret = ad74413r_setup_channels(indio_dev);
1414	if (ret)
1415		return ret;
1416
1417	ret = ad74413r_setup_gpios(st);
1418	if (ret)
1419		return ret;
1420
1421	if (st->num_gpo_gpios) {
1422		st->gpo_gpiochip.owner = THIS_MODULE;
1423		st->gpo_gpiochip.label = st->chip_info->name;
1424		st->gpo_gpiochip.base = -1;
1425		st->gpo_gpiochip.ngpio = st->num_gpo_gpios;
1426		st->gpo_gpiochip.parent = st->dev;
1427		st->gpo_gpiochip.can_sleep = true;
1428		st->gpo_gpiochip.set = ad74413r_gpio_set;
1429		st->gpo_gpiochip.set_multiple = ad74413r_gpio_set_multiple;
1430		st->gpo_gpiochip.set_config = ad74413r_gpio_set_gpo_config;
1431		st->gpo_gpiochip.get_direction =
1432			ad74413r_gpio_get_gpo_direction;
1433
1434		ret = devm_gpiochip_add_data(st->dev, &st->gpo_gpiochip, st);
1435		if (ret)
1436			return ret;
1437	}
1438
1439	if (st->num_comparator_gpios) {
1440		st->comp_gpiochip.owner = THIS_MODULE;
1441		st->comp_gpiochip.label = st->chip_info->name;
1442		st->comp_gpiochip.base = -1;
1443		st->comp_gpiochip.ngpio = st->num_comparator_gpios;
1444		st->comp_gpiochip.parent = st->dev;
1445		st->comp_gpiochip.can_sleep = true;
1446		st->comp_gpiochip.get = ad74413r_gpio_get;
1447		st->comp_gpiochip.get_multiple = ad74413r_gpio_get_multiple;
1448		st->comp_gpiochip.set_config = ad74413r_gpio_set_comp_config;
1449		st->comp_gpiochip.get_direction =
1450			ad74413r_gpio_get_comp_direction;
1451
1452		ret = devm_gpiochip_add_data(st->dev, &st->comp_gpiochip, st);
1453		if (ret)
1454			return ret;
1455	}
1456
1457	ret = ad74413r_set_adc_conv_seq(st, AD74413R_CONV_SEQ_OFF);
1458	if (ret)
1459		return ret;
1460
1461	ret = devm_request_irq(st->dev, spi->irq, ad74413r_adc_data_interrupt,
1462			       0, st->chip_info->name, indio_dev);
1463	if (ret)
1464		return dev_err_probe(st->dev, ret, "Failed to request irq\n");
1465
1466	ret = devm_iio_triggered_buffer_setup(st->dev, indio_dev,
1467					      &iio_pollfunc_store_time,
1468					      &ad74413r_trigger_handler,
1469					      &ad74413r_buffer_ops);
1470	if (ret)
1471		return ret;
1472
1473	return devm_iio_device_register(st->dev, indio_dev);
1474}
1475
1476static int ad74413r_unregister_driver(struct spi_driver *spi)
1477{
1478	spi_unregister_driver(spi);
1479
1480	return 0;
1481}
1482
1483static int __init ad74413r_register_driver(struct spi_driver *spi)
1484{
1485	crc8_populate_msb(ad74413r_crc8_table, AD74413R_CRC_POLYNOMIAL);
1486
1487	return spi_register_driver(spi);
1488}
1489
1490static const struct ad74413r_chip_info ad74412r_chip_info_data = {
1491	.hart_support = false,
1492	.name = "ad74412r",
1493};
1494
1495static const struct ad74413r_chip_info ad74413r_chip_info_data = {
1496	.hart_support = true,
1497	.name = "ad74413r",
1498};
1499
1500static const struct of_device_id ad74413r_dt_id[] = {
1501	{
1502		.compatible = "adi,ad74412r",
1503		.data = &ad74412r_chip_info_data,
1504	},
1505	{
1506		.compatible = "adi,ad74413r",
1507		.data = &ad74413r_chip_info_data,
1508	},
1509	{ }
1510};
1511MODULE_DEVICE_TABLE(of, ad74413r_dt_id);
1512
1513static const struct spi_device_id ad74413r_spi_id[] = {
1514	{ .name = "ad74412r", .driver_data = (kernel_ulong_t)&ad74412r_chip_info_data },
1515	{ .name = "ad74413r", .driver_data = (kernel_ulong_t)&ad74413r_chip_info_data },
1516	{ }
1517};
1518MODULE_DEVICE_TABLE(spi, ad74413r_spi_id);
1519
1520static struct spi_driver ad74413r_driver = {
1521	.driver = {
1522		   .name = "ad74413r",
1523		   .of_match_table = ad74413r_dt_id,
1524	},
1525	.probe = ad74413r_probe,
1526	.id_table = ad74413r_spi_id,
1527};
1528
1529module_driver(ad74413r_driver,
1530	      ad74413r_register_driver,
1531	      ad74413r_unregister_driver);
1532
1533MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>");
1534MODULE_DESCRIPTION("Analog Devices AD74413R ADDAC");
1535MODULE_LICENSE("GPL v2");