ad74115.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (C) 2022 Analog Devices, Inc.
   4 * Author: Cosmin Tanislav <cosmin.tanislav@analog.com>
   5 */
   6
   7#include <linux/bitfield.h>
   8#include <linux/bitops.h>
   9#include <linux/crc8.h>
  10#include <linux/device.h>
  11#include <linux/gpio/driver.h>
  12#include <linux/interrupt.h>
  13#include <linux/module.h>
  14#include <linux/regmap.h>
  15#include <linux/regulator/consumer.h>
  16#include <linux/spi/spi.h>
  17#include <linux/units.h>
  18
  19#include <linux/unaligned.h>
  20
  21#include <linux/iio/buffer.h>
  22#include <linux/iio/iio.h>
  23#include <linux/iio/trigger.h>
  24#include <linux/iio/trigger_consumer.h>
  25#include <linux/iio/triggered_buffer.h>
  26
  27#define AD74115_NAME				"ad74115"
  28
  29#define AD74115_CH_FUNC_SETUP_REG		0x01
  30
  31#define AD74115_ADC_CONFIG_REG			0x02
  32#define AD74115_ADC_CONFIG_CONV2_RATE_MASK	GENMASK(15, 13)
  33#define AD74115_ADC_CONFIG_CONV1_RATE_MASK	GENMASK(12, 10)
  34#define AD74115_ADC_CONFIG_CONV2_RANGE_MASK	GENMASK(9, 7)
  35#define AD74115_ADC_CONFIG_CONV1_RANGE_MASK	GENMASK(6, 4)
  36
  37#define AD74115_PWR_OPTIM_CONFIG_REG		0x03
  38
  39#define AD74115_DIN_CONFIG1_REG			0x04
  40#define AD74115_DIN_COMPARATOR_EN_MASK		BIT(13)
  41#define AD74115_DIN_SINK_MASK			GENMASK(11, 7)
  42#define AD74115_DIN_DEBOUNCE_MASK		GENMASK(4, 0)
  43
  44#define AD74115_DIN_CONFIG2_REG			0x05
  45#define AD74115_COMP_THRESH_MASK		GENMASK(6, 0)
  46
  47#define AD74115_OUTPUT_CONFIG_REG		0x06
  48#define AD74115_OUTPUT_SLEW_EN_MASK		GENMASK(6, 5)
  49#define AD74115_OUTPUT_SLEW_LIN_STEP_MASK	GENMASK(4, 3)
  50#define AD74115_OUTPUT_SLEW_LIN_RATE_MASK	GENMASK(2, 1)
  51
  52#define AD74115_RTD3W4W_CONFIG_REG		0x07
  53
  54#define AD74115_BURNOUT_CONFIG_REG		0x0a
  55#define AD74115_BURNOUT_EXT2_EN_MASK		BIT(10)
  56#define AD74115_BURNOUT_EXT1_EN_MASK		BIT(5)
  57#define AD74115_BURNOUT_VIOUT_EN_MASK		BIT(0)
  58
  59#define AD74115_DAC_CODE_REG			0x0b
  60
  61#define AD74115_DAC_ACTIVE_REG			0x0d
  62
  63#define AD74115_GPIO_CONFIG_X_REG(x)		(0x35 + (x))
  64#define AD74115_GPIO_CONFIG_GPI_DATA		BIT(5)
  65#define AD74115_GPIO_CONFIG_GPO_DATA		BIT(4)
  66#define AD74115_GPIO_CONFIG_SELECT_MASK		GENMASK(2, 0)
  67
  68#define AD74115_CHARGE_PUMP_REG			0x3a
  69
  70#define AD74115_ADC_CONV_CTRL_REG		0x3b
  71#define AD74115_ADC_CONV_SEQ_MASK		GENMASK(13, 12)
  72
  73#define AD74115_DIN_COMP_OUT_REG		0x40
  74
  75#define AD74115_LIVE_STATUS_REG			0x42
  76#define AD74115_ADC_DATA_RDY_MASK		BIT(3)
  77
  78#define AD74115_READ_SELECT_REG			0x64
  79
  80#define AD74115_CMD_KEY_REG			0x78
  81#define AD74115_CMD_KEY_RESET1			0x15fa
  82#define AD74115_CMD_KEY_RESET2			0xaf51
  83
  84#define AD74115_CRC_POLYNOMIAL			0x7
  85DECLARE_CRC8_TABLE(ad74115_crc8_table);
  86
  87#define AD74115_ADC_CODE_MAX			((int)GENMASK(15, 0))
  88#define AD74115_ADC_CODE_HALF			(AD74115_ADC_CODE_MAX / 2)
  89
  90#define AD74115_DAC_VOLTAGE_MAX			12000
  91#define AD74115_DAC_CURRENT_MAX			25
  92#define AD74115_DAC_CODE_MAX			((int)GENMASK(13, 0))
  93#define AD74115_DAC_CODE_HALF			(AD74115_DAC_CODE_MAX / 2)
  94
  95#define AD74115_COMP_THRESH_MAX			98
  96
  97#define AD74115_SENSE_RESISTOR_OHMS		100
  98#define AD74115_REF_RESISTOR_OHMS		2100
  99
 100#define AD74115_DIN_SINK_LOW_STEP		120
 101#define AD74115_DIN_SINK_HIGH_STEP		240
 102#define AD74115_DIN_SINK_MAX			31
 103
 104#define AD74115_FRAME_SIZE			4
 105#define AD74115_GPIO_NUM			4
 106
 107#define AD74115_CONV_TIME_US			1000000
 108
 109enum ad74115_dac_ch {
 110	AD74115_DAC_CH_MAIN,
 111	AD74115_DAC_CH_COMPARATOR,
 112};
 113
 114enum ad74115_adc_ch {
 115	AD74115_ADC_CH_CONV1,
 116	AD74115_ADC_CH_CONV2,
 117	AD74115_ADC_CH_NUM
 118};
 119
 120enum ad74115_ch_func {
 121	AD74115_CH_FUNC_HIGH_IMPEDANCE,
 122	AD74115_CH_FUNC_VOLTAGE_OUTPUT,
 123	AD74115_CH_FUNC_CURRENT_OUTPUT,
 124	AD74115_CH_FUNC_VOLTAGE_INPUT,
 125	AD74115_CH_FUNC_CURRENT_INPUT_EXT_POWER,
 126	AD74115_CH_FUNC_CURRENT_INPUT_LOOP_POWER,
 127	AD74115_CH_FUNC_2_WIRE_RESISTANCE_INPUT,
 128	AD74115_CH_FUNC_3_4_WIRE_RESISTANCE_INPUT,
 129	AD74115_CH_FUNC_DIGITAL_INPUT_LOGIC,
 130	AD74115_CH_FUNC_DIGITAL_INPUT_LOOP_POWER,
 131	AD74115_CH_FUNC_CURRENT_OUTPUT_HART,
 132	AD74115_CH_FUNC_CURRENT_INPUT_EXT_POWER_HART,
 133	AD74115_CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART,
 134	AD74115_CH_FUNC_MAX = AD74115_CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART,
 135	AD74115_CH_FUNC_NUM
 136};
 137
 138enum ad74115_adc_range {
 139	AD74115_ADC_RANGE_12V,
 140	AD74115_ADC_RANGE_12V_BIPOLAR,
 141	AD74115_ADC_RANGE_2_5V_BIPOLAR,
 142	AD74115_ADC_RANGE_2_5V_NEG,
 143	AD74115_ADC_RANGE_2_5V,
 144	AD74115_ADC_RANGE_0_625V,
 145	AD74115_ADC_RANGE_104MV_BIPOLAR,
 146	AD74115_ADC_RANGE_12V_OTHER,
 147	AD74115_ADC_RANGE_MAX = AD74115_ADC_RANGE_12V_OTHER,
 148	AD74115_ADC_RANGE_NUM
 149};
 150
 151enum ad74115_adc_conv_seq {
 152	AD74115_ADC_CONV_SEQ_STANDBY = 0b00,
 153	AD74115_ADC_CONV_SEQ_SINGLE = 0b01,
 154	AD74115_ADC_CONV_SEQ_CONTINUOUS = 0b10,
 155};
 156
 157enum ad74115_din_threshold_mode {
 158	AD74115_DIN_THRESHOLD_MODE_AVDD,
 159	AD74115_DIN_THRESHOLD_MODE_FIXED,
 160	AD74115_DIN_THRESHOLD_MODE_MAX = AD74115_DIN_THRESHOLD_MODE_FIXED,
 161};
 162
 163enum ad74115_slew_mode {
 164	AD74115_SLEW_MODE_DISABLED,
 165	AD74115_SLEW_MODE_LINEAR,
 166	AD74115_SLEW_MODE_HART,
 167};
 168
 169enum ad74115_slew_step {
 170	AD74115_SLEW_STEP_0_8_PERCENT,
 171	AD74115_SLEW_STEP_1_5_PERCENT,
 172	AD74115_SLEW_STEP_6_1_PERCENT,
 173	AD74115_SLEW_STEP_22_2_PERCENT,
 174};
 175
 176enum ad74115_slew_rate {
 177	AD74115_SLEW_RATE_4KHZ,
 178	AD74115_SLEW_RATE_64KHZ,
 179	AD74115_SLEW_RATE_150KHZ,
 180	AD74115_SLEW_RATE_240KHZ,
 181};
 182
 183enum ad74115_gpio_config {
 184	AD74115_GPIO_CONFIG_OUTPUT_BUFFERED = 0b010,
 185	AD74115_GPIO_CONFIG_INPUT = 0b011,
 186};
 187
 188enum ad74115_gpio_mode {
 189	AD74115_GPIO_MODE_LOGIC = 1,
 190	AD74115_GPIO_MODE_SPECIAL = 2,
 191};
 192
 193struct ad74115_channels {
 194	const struct iio_chan_spec	*channels;
 195	unsigned int			num_channels;
 196};
 197
 198struct ad74115_state {
 199	struct spi_device		*spi;
 200	struct regmap			*regmap;
 201	struct iio_trigger		*trig;
 202
 203	/*
 204	 * Synchronize consecutive operations when doing a one-shot
 205	 * conversion and when updating the ADC samples SPI message.
 206	 */
 207	struct mutex			lock;
 208	struct gpio_chip		gc;
 209	struct gpio_chip		comp_gc;
 210	int				irq;
 211
 212	unsigned int			avdd_mv;
 213	unsigned long			gpio_valid_mask;
 214	bool				dac_bipolar;
 215	bool				dac_hart_slew;
 216	bool				rtd_mode_4_wire;
 217	enum ad74115_ch_func		ch_func;
 218	enum ad74115_din_threshold_mode	din_threshold_mode;
 219
 220	struct completion		adc_data_completion;
 221	struct spi_message		adc_samples_msg;
 222	struct spi_transfer		adc_samples_xfer[AD74115_ADC_CH_NUM + 1];
 223
 224	/*
 225	 * DMA (thus cache coherency maintenance) requires the
 226	 * transfer buffers to live in their own cache lines.
 227	 */
 228	u8				reg_tx_buf[AD74115_FRAME_SIZE] __aligned(IIO_DMA_MINALIGN);
 229	u8				reg_rx_buf[AD74115_FRAME_SIZE];
 230	u8				adc_samples_tx_buf[AD74115_FRAME_SIZE * AD74115_ADC_CH_NUM];
 231	u8				adc_samples_rx_buf[AD74115_FRAME_SIZE * AD74115_ADC_CH_NUM];
 232};
 233
 234struct ad74115_fw_prop {
 235	const char			*name;
 236	bool				is_boolean;
 237	bool				negate;
 238	unsigned int			max;
 239	unsigned int			reg;
 240	unsigned int			mask;
 241	const unsigned int		*lookup_tbl;
 242	unsigned int			lookup_tbl_len;
 243};
 244
 245#define AD74115_FW_PROP(_name, _max, _reg, _mask)		\
 246{								\
 247	.name = (_name),					\
 248	.max = (_max),						\
 249	.reg = (_reg),						\
 250	.mask = (_mask),					\
 251}
 252
 253#define AD74115_FW_PROP_TBL(_name, _tbl, _reg, _mask)		\
 254{								\
 255	.name = (_name),					\
 256	.reg = (_reg),						\
 257	.mask = (_mask),					\
 258	.lookup_tbl = (_tbl),					\
 259	.lookup_tbl_len = ARRAY_SIZE(_tbl),			\
 260}
 261
 262#define AD74115_FW_PROP_BOOL(_name, _reg, _mask)		\
 263{								\
 264	.name = (_name),					\
 265	.is_boolean = true,					\
 266	.reg = (_reg),						\
 267	.mask = (_mask),					\
 268}
 269
 270#define AD74115_FW_PROP_BOOL_NEG(_name, _reg, _mask)		\
 271{								\
 272	.name = (_name),					\
 273	.is_boolean = true,					\
 274	.negate = true,						\
 275	.reg = (_reg),						\
 276	.mask = (_mask),					\
 277}
 278
 279static const int ad74115_dac_rate_tbl[] = {
 280	0,
 281	4 * 8,
 282	4 * 15,
 283	4 * 61,
 284	4 * 222,
 285	64 * 8,
 286	64 * 15,
 287	64 * 61,
 288	64 * 222,
 289	150 * 8,
 290	150 * 15,
 291	150 * 61,
 292	150 * 222,
 293	240 * 8,
 294	240 * 15,
 295	240 * 61,
 296	240 * 222,
 297};
 298
 299static const unsigned int ad74115_dac_rate_step_tbl[][3] = {
 300	{ AD74115_SLEW_MODE_DISABLED },
 301	{ AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_0_8_PERCENT, AD74115_SLEW_RATE_4KHZ },
 302	{ AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_1_5_PERCENT, AD74115_SLEW_RATE_4KHZ },
 303	{ AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_6_1_PERCENT, AD74115_SLEW_RATE_4KHZ },
 304	{ AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_22_2_PERCENT, AD74115_SLEW_RATE_4KHZ },
 305	{ AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_0_8_PERCENT, AD74115_SLEW_RATE_64KHZ },
 306	{ AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_1_5_PERCENT, AD74115_SLEW_RATE_64KHZ },
 307	{ AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_6_1_PERCENT, AD74115_SLEW_RATE_64KHZ },
 308	{ AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_22_2_PERCENT, AD74115_SLEW_RATE_64KHZ },
 309	{ AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_0_8_PERCENT, AD74115_SLEW_RATE_150KHZ },
 310	{ AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_1_5_PERCENT, AD74115_SLEW_RATE_150KHZ },
 311	{ AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_6_1_PERCENT, AD74115_SLEW_RATE_150KHZ },
 312	{ AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_22_2_PERCENT, AD74115_SLEW_RATE_150KHZ },
 313	{ AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_0_8_PERCENT, AD74115_SLEW_RATE_240KHZ },
 314	{ AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_1_5_PERCENT, AD74115_SLEW_RATE_240KHZ },
 315	{ AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_6_1_PERCENT, AD74115_SLEW_RATE_240KHZ },
 316	{ AD74115_SLEW_MODE_LINEAR, AD74115_SLEW_STEP_22_2_PERCENT, AD74115_SLEW_RATE_240KHZ },
 317};
 318
 319static const unsigned int ad74115_rtd_excitation_current_ua_tbl[] = {
 320	250, 500, 750, 1000
 321};
 322
 323static const unsigned int ad74115_burnout_current_na_tbl[] = {
 324	0, 50, 0, 500, 1000, 0, 10000, 0
 325};
 326
 327static const unsigned int ad74115_viout_burnout_current_na_tbl[] = {
 328	0, 0, 0, 0, 1000, 0, 10000, 0
 329};
 330
 331static const unsigned int ad74115_gpio_mode_tbl[] = {
 332	0, 0, 0, 1, 2, 3, 4, 5
 333};
 334
 335static const unsigned int ad74115_adc_conv_rate_tbl[] = {
 336	10, 20, 1200, 4800, 9600
 337};
 338
 339static const unsigned int ad74115_debounce_tbl[] = {
 340	0,     13,    18,    24,    32,    42,    56,    75,
 341	100,   130,   180,   240,   320,   420,   560,   750,
 342	1000,  1300,  1800,  2400,  3200,  4200,  5600,  7500,
 343	10000, 13000, 18000, 24000, 32000, 42000, 56000, 75000,
 344};
 345
 346static const unsigned int ad74115_adc_ch_data_regs_tbl[] = {
 347	[AD74115_ADC_CH_CONV1] = 0x44,
 348	[AD74115_ADC_CH_CONV2] = 0x46,
 349};
 350
 351static const unsigned int ad74115_adc_ch_en_bit_tbl[] = {
 352	[AD74115_ADC_CH_CONV1] = BIT(0),
 353	[AD74115_ADC_CH_CONV2] = BIT(1),
 354};
 355
 356static const bool ad74115_adc_bipolar_tbl[AD74115_ADC_RANGE_NUM] = {
 357	[AD74115_ADC_RANGE_12V_BIPOLAR]		= true,
 358	[AD74115_ADC_RANGE_2_5V_BIPOLAR]	= true,
 359	[AD74115_ADC_RANGE_104MV_BIPOLAR]	= true,
 360};
 361
 362static const unsigned int ad74115_adc_conv_mul_tbl[AD74115_ADC_RANGE_NUM] = {
 363	[AD74115_ADC_RANGE_12V]			= 12000,
 364	[AD74115_ADC_RANGE_12V_BIPOLAR]		= 24000,
 365	[AD74115_ADC_RANGE_2_5V_BIPOLAR]	= 5000,
 366	[AD74115_ADC_RANGE_2_5V_NEG]		= 2500,
 367	[AD74115_ADC_RANGE_2_5V]		= 2500,
 368	[AD74115_ADC_RANGE_0_625V]		= 625,
 369	[AD74115_ADC_RANGE_104MV_BIPOLAR]	= 208,
 370	[AD74115_ADC_RANGE_12V_OTHER]		= 12000,
 371};
 372
 373static const unsigned int ad74115_adc_gain_tbl[AD74115_ADC_RANGE_NUM][2] = {
 374	[AD74115_ADC_RANGE_12V]			= { 5, 24 },
 375	[AD74115_ADC_RANGE_12V_BIPOLAR]		= { 5, 24 },
 376	[AD74115_ADC_RANGE_2_5V_BIPOLAR]	= { 1, 1 },
 377	[AD74115_ADC_RANGE_2_5V_NEG]		= { 1, 1 },
 378	[AD74115_ADC_RANGE_2_5V]		= { 1, 1 },
 379	[AD74115_ADC_RANGE_0_625V]		= { 4, 1 },
 380	[AD74115_ADC_RANGE_104MV_BIPOLAR]	= { 24, 1 },
 381	[AD74115_ADC_RANGE_12V_OTHER]		= { 5, 24 },
 382};
 383
 384static const int ad74115_adc_range_tbl[AD74115_ADC_RANGE_NUM][2] = {
 385	[AD74115_ADC_RANGE_12V]			= { 0,         12000000 },
 386	[AD74115_ADC_RANGE_12V_BIPOLAR]		= { -12000000, 12000000 },
 387	[AD74115_ADC_RANGE_2_5V_BIPOLAR]	= { -2500000,  2500000 },
 388	[AD74115_ADC_RANGE_2_5V_NEG]		= { -2500000,  0 },
 389	[AD74115_ADC_RANGE_2_5V]		= { 0,         2500000 },
 390	[AD74115_ADC_RANGE_0_625V]		= { 0,         625000 },
 391	[AD74115_ADC_RANGE_104MV_BIPOLAR]	= { -104000,   104000 },
 392	[AD74115_ADC_RANGE_12V_OTHER]		= { 0,         12000000 },
 393};
 394
 395static int _ad74115_find_tbl_index(const unsigned int *tbl, unsigned int tbl_len,
 396				   unsigned int val, unsigned int *index)
 397{
 398	unsigned int i;
 399
 400	for (i = 0; i < tbl_len; i++)
 401		if (val == tbl[i]) {
 402			*index = i;
 403			return 0;
 404		}
 405
 406	return -EINVAL;
 407}
 408
 409#define ad74115_find_tbl_index(tbl, val, index)	\
 410	_ad74115_find_tbl_index(tbl, ARRAY_SIZE(tbl), val, index)
 411
 412static int ad74115_crc(u8 *buf)
 413{
 414	return crc8(ad74115_crc8_table, buf, 3, 0);
 415}
 416
 417static void ad74115_format_reg_write(u8 reg, u16 val, u8 *buf)
 418{
 419	buf[0] = reg;
 420	put_unaligned_be16(val, &buf[1]);
 421	buf[3] = ad74115_crc(buf);
 422}
 423
 424static int ad74115_reg_write(void *context, unsigned int reg, unsigned int val)
 425{
 426	struct ad74115_state *st = context;
 427
 428	ad74115_format_reg_write(reg, val, st->reg_tx_buf);
 429
 430	return spi_write(st->spi, st->reg_tx_buf, AD74115_FRAME_SIZE);
 431}
 432
 433static int ad74115_crc_check(struct ad74115_state *st, u8 *buf)
 434{
 435	struct device *dev = &st->spi->dev;
 436	u8 expected_crc = ad74115_crc(buf);
 437
 438	if (buf[3] != expected_crc) {
 439		dev_err(dev, "Bad CRC %02x for %02x%02x%02x, expected %02x\n",
 440			buf[3], buf[0], buf[1], buf[2], expected_crc);
 441		return -EINVAL;
 442	}
 443
 444	return 0;
 445}
 446
 447static int ad74115_reg_read(void *context, unsigned int reg, unsigned int *val)
 448{
 449	struct ad74115_state *st = context;
 450	struct spi_transfer reg_read_xfer[] = {
 451		{
 452			.tx_buf = st->reg_tx_buf,
 453			.len = sizeof(st->reg_tx_buf),
 454			.cs_change = 1,
 455		},
 456		{
 457			.rx_buf = st->reg_rx_buf,
 458			.len = sizeof(st->reg_rx_buf),
 459		},
 460	};
 461	int ret;
 462
 463	ad74115_format_reg_write(AD74115_READ_SELECT_REG, reg, st->reg_tx_buf);
 464
 465	ret = spi_sync_transfer(st->spi, reg_read_xfer, ARRAY_SIZE(reg_read_xfer));
 466	if (ret)
 467		return ret;
 468
 469	ret = ad74115_crc_check(st, st->reg_rx_buf);
 470	if (ret)
 471		return ret;
 472
 473	*val = get_unaligned_be16(&st->reg_rx_buf[1]);
 474
 475	return 0;
 476}
 477
 478static const struct regmap_config ad74115_regmap_config = {
 479	.reg_bits = 8,
 480	.val_bits = 16,
 481	.reg_read = ad74115_reg_read,
 482	.reg_write = ad74115_reg_write,
 483};
 484
 485static int ad74115_gpio_config_set(struct ad74115_state *st, unsigned int offset,
 486				   enum ad74115_gpio_config cfg)
 487{
 488	return regmap_update_bits(st->regmap, AD74115_GPIO_CONFIG_X_REG(offset),
 489				  AD74115_GPIO_CONFIG_SELECT_MASK,
 490				  FIELD_PREP(AD74115_GPIO_CONFIG_SELECT_MASK, cfg));
 491}
 492
 493static int ad74115_gpio_init_valid_mask(struct gpio_chip *gc,
 494					unsigned long *valid_mask,
 495					unsigned int ngpios)
 496{
 497	struct ad74115_state *st = gpiochip_get_data(gc);
 498
 499	*valid_mask = st->gpio_valid_mask;
 500
 501	return 0;
 502}
 503
 504static int ad74115_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
 505{
 506	struct ad74115_state *st = gpiochip_get_data(gc);
 507	unsigned int val;
 508	int ret;
 509
 510	ret = regmap_read(st->regmap, AD74115_GPIO_CONFIG_X_REG(offset), &val);
 511	if (ret)
 512		return ret;
 513
 514	return FIELD_GET(AD74115_GPIO_CONFIG_SELECT_MASK, val) == AD74115_GPIO_CONFIG_INPUT;
 515}
 516
 517static int ad74115_gpio_direction_input(struct gpio_chip *gc, unsigned int offset)
 518{
 519	struct ad74115_state *st = gpiochip_get_data(gc);
 520
 521	return ad74115_gpio_config_set(st, offset, AD74115_GPIO_CONFIG_INPUT);
 522}
 523
 524static int ad74115_gpio_direction_output(struct gpio_chip *gc, unsigned int offset,
 525					 int value)
 526{
 527	struct ad74115_state *st = gpiochip_get_data(gc);
 528
 529	return ad74115_gpio_config_set(st, offset, AD74115_GPIO_CONFIG_OUTPUT_BUFFERED);
 530}
 531
 532static int ad74115_gpio_get(struct gpio_chip *gc, unsigned int offset)
 533{
 534	struct ad74115_state *st = gpiochip_get_data(gc);
 535	unsigned int val;
 536	int ret;
 537
 538	ret = regmap_read(st->regmap, AD74115_GPIO_CONFIG_X_REG(offset), &val);
 539	if (ret)
 540		return ret;
 541
 542	return FIELD_GET(AD74115_GPIO_CONFIG_GPI_DATA, val);
 543}
 544
 545static int ad74115_gpio_set(struct gpio_chip *gc, unsigned int offset,
 546			    int value)
 547{
 548	struct ad74115_state *st = gpiochip_get_data(gc);
 549
 550	return regmap_update_bits(st->regmap,
 551				  AD74115_GPIO_CONFIG_X_REG(offset),
 552				  AD74115_GPIO_CONFIG_GPO_DATA,
 553				  FIELD_PREP(AD74115_GPIO_CONFIG_GPO_DATA,
 554					     value));
 555}
 556
 557static int ad74115_set_comp_debounce(struct ad74115_state *st, unsigned int val)
 558{
 559	unsigned int len = ARRAY_SIZE(ad74115_debounce_tbl);
 560	unsigned int i;
 561
 562	for (i = 0; i < len; i++)
 563		if (val <= ad74115_debounce_tbl[i])
 564			break;
 565
 566	if (i == len)
 567		i = len - 1;
 568
 569	return regmap_update_bits(st->regmap, AD74115_DIN_CONFIG1_REG,
 570				  AD74115_DIN_DEBOUNCE_MASK,
 571				  FIELD_PREP(AD74115_DIN_DEBOUNCE_MASK, val));
 572}
 573
 574static int ad74115_comp_gpio_get_direction(struct gpio_chip *chip,
 575					   unsigned int offset)
 576{
 577	return GPIO_LINE_DIRECTION_IN;
 578}
 579
 580static int ad74115_comp_gpio_set_config(struct gpio_chip *chip,
 581					unsigned int offset,
 582					unsigned long config)
 583{
 584	struct ad74115_state *st = gpiochip_get_data(chip);
 585	u32 param = pinconf_to_config_param(config);
 586	u32 arg = pinconf_to_config_argument(config);
 587
 588	switch (param) {
 589	case PIN_CONFIG_INPUT_DEBOUNCE:
 590		return ad74115_set_comp_debounce(st, arg);
 591	default:
 592		return -ENOTSUPP;
 593	}
 594}
 595
 596static int ad74115_comp_gpio_get(struct gpio_chip *chip, unsigned int offset)
 597{
 598	struct ad74115_state *st = gpiochip_get_data(chip);
 599	unsigned int val;
 600	int ret;
 601
 602	ret = regmap_read(st->regmap, AD74115_DIN_COMP_OUT_REG, &val);
 603	if (ret)
 604		return ret;
 605
 606	return !!val;
 607}
 608
 609static irqreturn_t ad74115_trigger_handler(int irq, void *p)
 610{
 611	struct iio_poll_func *pf = p;
 612	struct iio_dev *indio_dev = pf->indio_dev;
 613	struct ad74115_state *st = iio_priv(indio_dev);
 614	int ret;
 615
 616	ret = spi_sync(st->spi, &st->adc_samples_msg);
 617	if (ret)
 618		goto out;
 619
 620	iio_push_to_buffers(indio_dev, st->adc_samples_rx_buf);
 621
 622out:
 623	iio_trigger_notify_done(indio_dev->trig);
 624
 625	return IRQ_HANDLED;
 626}
 627
 628static irqreturn_t ad74115_adc_data_interrupt(int irq, void *data)
 629{
 630	struct iio_dev *indio_dev = data;
 631	struct ad74115_state *st = iio_priv(indio_dev);
 632
 633	if (iio_buffer_enabled(indio_dev))
 634		iio_trigger_poll(st->trig);
 635	else
 636		complete(&st->adc_data_completion);
 637
 638	return IRQ_HANDLED;
 639}
 640
 641static int ad74115_set_adc_ch_en(struct ad74115_state *st,
 642				 enum ad74115_adc_ch channel, bool status)
 643{
 644	unsigned int mask = ad74115_adc_ch_en_bit_tbl[channel];
 645
 646	return regmap_update_bits(st->regmap, AD74115_ADC_CONV_CTRL_REG, mask,
 647				  status ? mask : 0);
 648}
 649
 650static int ad74115_set_adc_conv_seq(struct ad74115_state *st,
 651				    enum ad74115_adc_conv_seq conv_seq)
 652{
 653	return regmap_update_bits(st->regmap, AD74115_ADC_CONV_CTRL_REG,
 654				  AD74115_ADC_CONV_SEQ_MASK,
 655				  FIELD_PREP(AD74115_ADC_CONV_SEQ_MASK, conv_seq));
 656}
 657
 658static int ad74115_update_scan_mode(struct iio_dev *indio_dev,
 659				    const unsigned long *active_scan_mask)
 660{
 661	struct ad74115_state *st = iio_priv(indio_dev);
 662	struct spi_transfer *xfer = st->adc_samples_xfer;
 663	u8 *rx_buf = st->adc_samples_rx_buf;
 664	u8 *tx_buf = st->adc_samples_tx_buf;
 665	unsigned int i;
 666	int ret = 0;
 667
 668	mutex_lock(&st->lock);
 669
 670	spi_message_init(&st->adc_samples_msg);
 671
 672	for_each_clear_bit(i, active_scan_mask, AD74115_ADC_CH_NUM) {
 673		ret = ad74115_set_adc_ch_en(st, i, false);
 674		if (ret)
 675			goto out;
 676	}
 677
 678	/*
 679	 * The read select register is used to select which register's value
 680	 * will be sent by the slave on the next SPI frame.
 681	 *
 682	 * Create an SPI message that, on each step, writes to the read select
 683	 * register to select the ADC result of the next enabled channel, and
 684	 * reads the ADC result of the previous enabled channel.
 685	 *
 686	 * Example:
 687	 * W: [WCH1] [WCH2] [WCH2] [WCH3] [    ]
 688	 * R: [    ] [RCH1] [RCH2] [RCH3] [RCH4]
 689	 */
 690	for_each_set_bit(i, active_scan_mask, AD74115_ADC_CH_NUM) {
 691		ret = ad74115_set_adc_ch_en(st, i, true);
 692		if (ret)
 693			goto out;
 694
 695		if (xfer == st->adc_samples_xfer)
 696			xfer->rx_buf = NULL;
 697		else
 698			xfer->rx_buf = rx_buf;
 699
 700		xfer->tx_buf = tx_buf;
 701		xfer->len = AD74115_FRAME_SIZE;
 702		xfer->cs_change = 1;
 703
 704		ad74115_format_reg_write(AD74115_READ_SELECT_REG,
 705					 ad74115_adc_ch_data_regs_tbl[i], tx_buf);
 706
 707		spi_message_add_tail(xfer, &st->adc_samples_msg);
 708
 709		tx_buf += AD74115_FRAME_SIZE;
 710		if (xfer != st->adc_samples_xfer)
 711			rx_buf += AD74115_FRAME_SIZE;
 712		xfer++;
 713	}
 714
 715	xfer->rx_buf = rx_buf;
 716	xfer->tx_buf = NULL;
 717	xfer->len = AD74115_FRAME_SIZE;
 718	xfer->cs_change = 0;
 719
 720	spi_message_add_tail(xfer, &st->adc_samples_msg);
 721
 722out:
 723	mutex_unlock(&st->lock);
 724
 725	return ret;
 726}
 727
 728static int ad74115_buffer_postenable(struct iio_dev *indio_dev)
 729{
 730	struct ad74115_state *st = iio_priv(indio_dev);
 731
 732	return ad74115_set_adc_conv_seq(st, AD74115_ADC_CONV_SEQ_CONTINUOUS);
 733}
 734
 735static int ad74115_buffer_predisable(struct iio_dev *indio_dev)
 736{
 737	struct ad74115_state *st = iio_priv(indio_dev);
 738	unsigned int i;
 739	int ret;
 740
 741	mutex_lock(&st->lock);
 742
 743	ret = ad74115_set_adc_conv_seq(st, AD74115_ADC_CONV_SEQ_STANDBY);
 744	if (ret)
 745		goto out;
 746
 747	/*
 748	 * update_scan_mode() is not called in the disable path, disable all
 749	 * channels here.
 750	 */
 751	for (i = 0; i < AD74115_ADC_CH_NUM; i++) {
 752		ret = ad74115_set_adc_ch_en(st, i, false);
 753		if (ret)
 754			goto out;
 755	}
 756
 757out:
 758	mutex_unlock(&st->lock);
 759
 760	return ret;
 761}
 762
 763static const struct iio_buffer_setup_ops ad74115_buffer_ops = {
 764	.postenable = &ad74115_buffer_postenable,
 765	.predisable = &ad74115_buffer_predisable,
 766};
 767
 768static const struct iio_trigger_ops ad74115_trigger_ops = {
 769	.validate_device = iio_trigger_validate_own_device,
 770};
 771
 772static int ad74115_get_adc_rate(struct ad74115_state *st,
 773				enum ad74115_adc_ch channel, int *val)
 774{
 775	unsigned int i;
 776	int ret;
 777
 778	ret = regmap_read(st->regmap, AD74115_ADC_CONFIG_REG, &i);
 779	if (ret)
 780		return ret;
 781
 782	if (channel == AD74115_ADC_CH_CONV1)
 783		i = FIELD_GET(AD74115_ADC_CONFIG_CONV1_RATE_MASK, i);
 784	else
 785		i = FIELD_GET(AD74115_ADC_CONFIG_CONV2_RATE_MASK, i);
 786
 787	*val = ad74115_adc_conv_rate_tbl[i];
 788
 789	return IIO_VAL_INT;
 790}
 791
 792static int _ad74115_get_adc_code(struct ad74115_state *st,
 793				 enum ad74115_adc_ch channel, int *val)
 794{
 795	unsigned int uval;
 796	int ret;
 797
 798	reinit_completion(&st->adc_data_completion);
 799
 800	ret = ad74115_set_adc_ch_en(st, channel, true);
 801	if (ret)
 802		return ret;
 803
 804	ret = ad74115_set_adc_conv_seq(st, AD74115_ADC_CONV_SEQ_SINGLE);
 805	if (ret)
 806		return ret;
 807
 808	if (st->irq) {
 809		ret = wait_for_completion_timeout(&st->adc_data_completion,
 810						  msecs_to_jiffies(1000));
 811		if (!ret)
 812			return -ETIMEDOUT;
 813	} else {
 814		unsigned int regval, wait_time;
 815		int rate;
 816
 817		ret = ad74115_get_adc_rate(st, channel, &rate);
 818		if (ret < 0)
 819			return ret;
 820
 821		wait_time = DIV_ROUND_CLOSEST(AD74115_CONV_TIME_US, rate);
 822
 823		ret = regmap_read_poll_timeout(st->regmap, AD74115_LIVE_STATUS_REG,
 824					       regval, regval & AD74115_ADC_DATA_RDY_MASK,
 825					       wait_time, 5 * wait_time);
 826		if (ret)
 827			return ret;
 828
 829		/*
 830		 * The ADC_DATA_RDY bit is W1C.
 831		 * See datasheet page 98, Table 62. Bit Descriptions for
 832		 * LIVE_STATUS.
 833		 * Although the datasheet mentions that the bit will auto-clear
 834		 * when writing to the ADC_CONV_CTRL register, this does not
 835		 * seem to happen.
 836		 */
 837		ret = regmap_write_bits(st->regmap, AD74115_LIVE_STATUS_REG,
 838					AD74115_ADC_DATA_RDY_MASK,
 839					FIELD_PREP(AD74115_ADC_DATA_RDY_MASK, 1));
 840		if (ret)
 841			return ret;
 842	}
 843
 844	ret = regmap_read(st->regmap, ad74115_adc_ch_data_regs_tbl[channel], &uval);
 845	if (ret)
 846		return ret;
 847
 848	ret = ad74115_set_adc_conv_seq(st, AD74115_ADC_CONV_SEQ_STANDBY);
 849	if (ret)
 850		return ret;
 851
 852	ret = ad74115_set_adc_ch_en(st, channel, false);
 853	if (ret)
 854		return ret;
 855
 856	*val = uval;
 857
 858	return IIO_VAL_INT;
 859}
 860
 861static int ad74115_get_adc_code(struct iio_dev *indio_dev,
 862				enum ad74115_adc_ch channel, int *val)
 863{
 864	struct ad74115_state *st = iio_priv(indio_dev);
 865	int ret;
 866
 867	if (!iio_device_claim_direct(indio_dev))
 868		return -EBUSY;
 869
 870	mutex_lock(&st->lock);
 871	ret = _ad74115_get_adc_code(st, channel, val);
 872	mutex_unlock(&st->lock);
 873
 874	iio_device_release_direct(indio_dev);
 875
 876	return ret;
 877}
 878
 879static int ad74115_adc_code_to_resistance(int code, int *val, int *val2)
 880{
 881	if (code == AD74115_ADC_CODE_MAX)
 882		code--;
 883
 884	*val = code * AD74115_REF_RESISTOR_OHMS;
 885	*val2 = AD74115_ADC_CODE_MAX - code;
 886
 887	return IIO_VAL_FRACTIONAL;
 888}
 889
 890static int ad74115_set_dac_code(struct ad74115_state *st,
 891				enum ad74115_dac_ch channel, int val)
 892{
 893	if (val < 0)
 894		return -EINVAL;
 895
 896	if (channel == AD74115_DAC_CH_COMPARATOR) {
 897		if (val > AD74115_COMP_THRESH_MAX)
 898			return -EINVAL;
 899
 900		return regmap_update_bits(st->regmap, AD74115_DIN_CONFIG2_REG,
 901					  AD74115_COMP_THRESH_MASK,
 902					  FIELD_PREP(AD74115_COMP_THRESH_MASK, val));
 903	}
 904
 905	if (val > AD74115_DAC_CODE_MAX)
 906		return -EINVAL;
 907
 908	return regmap_write(st->regmap, AD74115_DAC_CODE_REG, val);
 909}
 910
 911static int ad74115_get_dac_code(struct ad74115_state *st,
 912				enum ad74115_dac_ch channel, int *val)
 913{
 914	unsigned int uval;
 915	int ret;
 916
 917	if (channel == AD74115_DAC_CH_COMPARATOR)
 918		return -EINVAL;
 919
 920	ret = regmap_read(st->regmap, AD74115_DAC_ACTIVE_REG, &uval);
 921	if (ret)
 922		return ret;
 923
 924	*val = uval;
 925
 926	return IIO_VAL_INT;
 927}
 928
 929static int ad74115_set_adc_rate(struct ad74115_state *st,
 930				enum ad74115_adc_ch channel, int val)
 931{
 932	unsigned int i;
 933	int ret;
 934
 935	ret = ad74115_find_tbl_index(ad74115_adc_conv_rate_tbl, val, &i);
 936	if (ret)
 937		return ret;
 938
 939	if (channel == AD74115_ADC_CH_CONV1)
 940		return regmap_update_bits(st->regmap, AD74115_ADC_CONFIG_REG,
 941					  AD74115_ADC_CONFIG_CONV1_RATE_MASK,
 942					  FIELD_PREP(AD74115_ADC_CONFIG_CONV1_RATE_MASK, i));
 943
 944	return regmap_update_bits(st->regmap, AD74115_ADC_CONFIG_REG,
 945				  AD74115_ADC_CONFIG_CONV2_RATE_MASK,
 946				  FIELD_PREP(AD74115_ADC_CONFIG_CONV2_RATE_MASK, i));
 947}
 948
 949static int ad74115_get_dac_rate(struct ad74115_state *st, int *val)
 950{
 951	unsigned int i, en_val, step_val, rate_val, tmp;
 952	int ret;
 953
 954	ret = regmap_read(st->regmap, AD74115_OUTPUT_CONFIG_REG, &tmp);
 955	if (ret)
 956		return ret;
 957
 958	en_val = FIELD_GET(AD74115_OUTPUT_SLEW_EN_MASK, tmp);
 959	step_val = FIELD_GET(AD74115_OUTPUT_SLEW_LIN_STEP_MASK, tmp);
 960	rate_val = FIELD_GET(AD74115_OUTPUT_SLEW_LIN_RATE_MASK, tmp);
 961
 962	for (i = 0; i < ARRAY_SIZE(ad74115_dac_rate_step_tbl); i++)
 963		if (en_val == ad74115_dac_rate_step_tbl[i][0] &&
 964		    step_val == ad74115_dac_rate_step_tbl[i][1] &&
 965		    rate_val == ad74115_dac_rate_step_tbl[i][2])
 966			break;
 967
 968	if (i == ARRAY_SIZE(ad74115_dac_rate_step_tbl))
 969		return -EINVAL;
 970
 971	*val = ad74115_dac_rate_tbl[i];
 972
 973	return IIO_VAL_INT;
 974}
 975
 976static int ad74115_set_dac_rate(struct ad74115_state *st, int val)
 977{
 978	unsigned int i, en_val, step_val, rate_val, mask, tmp;
 979	int ret;
 980
 981	ret = ad74115_find_tbl_index(ad74115_dac_rate_tbl, val, &i);
 982	if (ret)
 983		return ret;
 984
 985	en_val = ad74115_dac_rate_step_tbl[i][0];
 986	step_val = ad74115_dac_rate_step_tbl[i][1];
 987	rate_val = ad74115_dac_rate_step_tbl[i][2];
 988
 989	mask = AD74115_OUTPUT_SLEW_EN_MASK;
 990	mask |= AD74115_OUTPUT_SLEW_LIN_STEP_MASK;
 991	mask |= AD74115_OUTPUT_SLEW_LIN_RATE_MASK;
 992
 993	tmp = FIELD_PREP(AD74115_OUTPUT_SLEW_EN_MASK, en_val);
 994	tmp |= FIELD_PREP(AD74115_OUTPUT_SLEW_LIN_STEP_MASK, step_val);
 995	tmp |= FIELD_PREP(AD74115_OUTPUT_SLEW_LIN_RATE_MASK, rate_val);
 996
 997	return regmap_update_bits(st->regmap, AD74115_OUTPUT_CONFIG_REG, mask, tmp);
 998}
 999
1000static int ad74115_get_dac_scale(struct ad74115_state *st,
1001				 struct iio_chan_spec const *chan,
1002				 int *val, int *val2)
1003{
1004	if (chan->channel == AD74115_DAC_CH_MAIN) {
1005		if (chan->type == IIO_VOLTAGE) {
1006			*val = AD74115_DAC_VOLTAGE_MAX;
1007
1008			if (st->dac_bipolar)
1009				*val *= 2;
1010
1011		} else {
1012			*val = AD74115_DAC_CURRENT_MAX;
1013		}
1014
1015		*val2 = AD74115_DAC_CODE_MAX;
1016	} else {
1017		if (st->din_threshold_mode == AD74115_DIN_THRESHOLD_MODE_AVDD) {
1018			*val = 196 * st->avdd_mv;
1019			*val2 = 10 * AD74115_COMP_THRESH_MAX;
1020		} else {
1021			*val = 49000;
1022			*val2 = AD74115_COMP_THRESH_MAX;
1023		}
1024	}
1025
1026	return IIO_VAL_FRACTIONAL;
1027}
1028
1029static int ad74115_get_dac_offset(struct ad74115_state *st,
1030				  struct iio_chan_spec const *chan, int *val)
1031{
1032	if (chan->channel == AD74115_DAC_CH_MAIN) {
1033		if (chan->type == IIO_VOLTAGE && st->dac_bipolar)
1034			*val = -AD74115_DAC_CODE_HALF;
1035		else
1036			*val = 0;
1037	} else {
1038		if (st->din_threshold_mode == AD74115_DIN_THRESHOLD_MODE_AVDD)
1039			*val = -48;
1040		else
1041			*val = -38;
1042	}
1043
1044	return IIO_VAL_INT;
1045}
1046
1047static int ad74115_get_adc_range(struct ad74115_state *st,
1048				 enum ad74115_adc_ch channel, unsigned int *val)
1049{
1050	int ret;
1051
1052	ret = regmap_read(st->regmap, AD74115_ADC_CONFIG_REG, val);
1053	if (ret)
1054		return ret;
1055
1056	if (channel == AD74115_ADC_CH_CONV1)
1057		*val = FIELD_GET(AD74115_ADC_CONFIG_CONV1_RANGE_MASK, *val);
1058	else
1059		*val = FIELD_GET(AD74115_ADC_CONFIG_CONV2_RANGE_MASK, *val);
1060
1061	return 0;
1062}
1063
1064static int ad74115_get_adc_resistance_scale(struct ad74115_state *st,
1065					    unsigned int range,
1066					    int *val, int *val2)
1067{
1068	*val = ad74115_adc_gain_tbl[range][1] * AD74115_REF_RESISTOR_OHMS;
1069	*val2 = ad74115_adc_gain_tbl[range][0];
1070
1071	if (ad74115_adc_bipolar_tbl[range])
1072		*val2 *= AD74115_ADC_CODE_HALF;
1073	else
1074		*val2 *= AD74115_ADC_CODE_MAX;
1075
1076	return IIO_VAL_FRACTIONAL;
1077}
1078
1079static int ad74115_get_adc_scale(struct ad74115_state *st,
1080				 struct iio_chan_spec const *chan,
1081				 int *val, int *val2)
1082{
1083	unsigned int range;
1084	int ret;
1085
1086	ret = ad74115_get_adc_range(st, chan->channel, &range);
1087	if (ret)
1088		return ret;
1089
1090	if (chan->type == IIO_RESISTANCE)
1091		return ad74115_get_adc_resistance_scale(st, range, val, val2);
1092
1093	*val = ad74115_adc_conv_mul_tbl[range];
1094	*val2 = AD74115_ADC_CODE_MAX;
1095
1096	if (chan->type == IIO_CURRENT)
1097		*val2 *= AD74115_SENSE_RESISTOR_OHMS;
1098
1099	return IIO_VAL_FRACTIONAL;
1100}
1101
1102static int ad74115_get_adc_resistance_offset(struct ad74115_state *st,
1103					     unsigned int range,
1104					     int *val, int *val2)
1105{
1106	unsigned int d = 10 * AD74115_REF_RESISTOR_OHMS
1107			 * ad74115_adc_gain_tbl[range][1];
1108
1109	*val = 5;
1110
1111	if (ad74115_adc_bipolar_tbl[range])
1112		*val -= AD74115_ADC_CODE_HALF;
1113
1114	*val *= d;
1115
1116	if (!st->rtd_mode_4_wire) {
1117		/* Add 0.2 Ohm to the final result for 3-wire RTD. */
1118		unsigned int v = 2 * ad74115_adc_gain_tbl[range][0];
1119
1120		if (ad74115_adc_bipolar_tbl[range])
1121			v *= AD74115_ADC_CODE_HALF;
1122		else
1123			v *= AD74115_ADC_CODE_MAX;
1124
1125		*val += v;
1126	}
1127
1128	*val2 = d;
1129
1130	return IIO_VAL_FRACTIONAL;
1131}
1132
1133static int ad74115_get_adc_offset(struct ad74115_state *st,
1134				  struct iio_chan_spec const *chan,
1135				  int *val, int *val2)
1136{
1137	unsigned int range;
1138	int ret;
1139
1140	ret = ad74115_get_adc_range(st, chan->channel, &range);
1141	if (ret)
1142		return ret;
1143
1144	if (chan->type == IIO_RESISTANCE)
1145		return ad74115_get_adc_resistance_offset(st, range, val, val2);
1146
1147	if (ad74115_adc_bipolar_tbl[range])
1148		*val = -AD74115_ADC_CODE_HALF;
1149	else if (range == AD74115_ADC_RANGE_2_5V_NEG)
1150		*val = -AD74115_ADC_CODE_MAX;
1151	else
1152		*val = 0;
1153
1154	return IIO_VAL_INT;
1155}
1156
1157static int ad74115_read_raw(struct iio_dev *indio_dev,
1158			    struct iio_chan_spec const *chan,
1159			    int *val, int *val2, long info)
1160{
1161	struct ad74115_state *st = iio_priv(indio_dev);
1162	int ret;
1163
1164	switch (info) {
1165	case IIO_CHAN_INFO_RAW:
1166		if (chan->output)
1167			return ad74115_get_dac_code(st, chan->channel, val);
1168
1169		return ad74115_get_adc_code(indio_dev, chan->channel, val);
1170	case IIO_CHAN_INFO_PROCESSED:
1171		ret = ad74115_get_adc_code(indio_dev, chan->channel, val);
1172		if (ret)
1173			return ret;
1174
1175		return ad74115_adc_code_to_resistance(*val, val, val2);
1176	case IIO_CHAN_INFO_SCALE:
1177		if (chan->output)
1178			return ad74115_get_dac_scale(st, chan, val, val2);
1179
1180		return ad74115_get_adc_scale(st, chan, val, val2);
1181	case IIO_CHAN_INFO_OFFSET:
1182		if (chan->output)
1183			return ad74115_get_dac_offset(st, chan, val);
1184
1185		return ad74115_get_adc_offset(st, chan, val, val2);
1186	case IIO_CHAN_INFO_SAMP_FREQ:
1187		if (chan->output)
1188			return ad74115_get_dac_rate(st, val);
1189
1190		return ad74115_get_adc_rate(st, chan->channel, val);
1191	default:
1192		return -EINVAL;
1193	}
1194}
1195
1196static int ad74115_write_raw(struct iio_dev *indio_dev,
1197			     struct iio_chan_spec const *chan, int val, int val2,
1198			     long info)
1199{
1200	struct ad74115_state *st = iio_priv(indio_dev);
1201
1202	switch (info) {
1203	case IIO_CHAN_INFO_RAW:
1204		if (!chan->output)
1205			return -EINVAL;
1206
1207		return ad74115_set_dac_code(st, chan->channel, val);
1208	case IIO_CHAN_INFO_SAMP_FREQ:
1209		if (chan->output)
1210			return ad74115_set_dac_rate(st, val);
1211
1212		return ad74115_set_adc_rate(st, chan->channel, val);
1213	default:
1214		return -EINVAL;
1215	}
1216}
1217
1218static int ad74115_read_avail(struct iio_dev *indio_dev,
1219			      struct iio_chan_spec const *chan,
1220			      const int **vals, int *type, int *length, long info)
1221{
1222	switch (info) {
1223	case IIO_CHAN_INFO_SAMP_FREQ:
1224		if (chan->output) {
1225			*vals = ad74115_dac_rate_tbl;
1226			*length = ARRAY_SIZE(ad74115_dac_rate_tbl);
1227		} else {
1228			*vals = ad74115_adc_conv_rate_tbl;
1229			*length = ARRAY_SIZE(ad74115_adc_conv_rate_tbl);
1230		}
1231
1232		*type = IIO_VAL_INT;
1233
1234		return IIO_AVAIL_LIST;
1235	default:
1236		return -EINVAL;
1237	}
1238}
1239
1240static int ad74115_reg_access(struct iio_dev *indio_dev, unsigned int reg,
1241			      unsigned int writeval, unsigned int *readval)
1242{
1243	struct ad74115_state *st = iio_priv(indio_dev);
1244
1245	if (readval)
1246		return regmap_read(st->regmap, reg, readval);
1247
1248	return regmap_write(st->regmap, reg, writeval);
1249}
1250
1251static const struct iio_info ad74115_info = {
1252	.read_raw = ad74115_read_raw,
1253	.write_raw = ad74115_write_raw,
1254	.read_avail = ad74115_read_avail,
1255	.update_scan_mode = ad74115_update_scan_mode,
1256	.debugfs_reg_access = ad74115_reg_access,
1257};
1258
1259#define AD74115_DAC_CHANNEL(_type, index)				\
1260	{								\
1261		.type = (_type),					\
1262		.channel = (index),					\
1263		.indexed = 1,						\
1264		.output = 1,						\
1265		.scan_index = -1,					\
1266		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW)		\
1267				      | BIT(IIO_CHAN_INFO_SCALE)	\
1268				      | BIT(IIO_CHAN_INFO_OFFSET),	\
1269	}
1270
1271#define _AD74115_ADC_CHANNEL(_type, index, extra_mask_separate)		\
1272	{								\
1273		.type = (_type),					\
1274		.channel = (index),					\
1275		.indexed = 1,						\
1276		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW)		\
1277				      | BIT(IIO_CHAN_INFO_SAMP_FREQ)	\
1278				      | (extra_mask_separate),		\
1279		.info_mask_separate_available =				\
1280					BIT(IIO_CHAN_INFO_SAMP_FREQ),	\
1281		.scan_index = index,					\
1282		.scan_type = {						\
1283			.sign = 'u',					\
1284			.realbits = 16,					\
1285			.storagebits = 32,				\
1286			.shift = 8,					\
1287			.endianness = IIO_BE,				\
1288		},							\
1289	}
1290
1291#define AD74115_ADC_CHANNEL(_type, index)				\
1292	_AD74115_ADC_CHANNEL(_type, index, BIT(IIO_CHAN_INFO_SCALE)	\
1293					   | BIT(IIO_CHAN_INFO_OFFSET))
1294
1295static const struct iio_chan_spec ad74115_voltage_input_channels[] = {
1296	AD74115_ADC_CHANNEL(IIO_VOLTAGE, AD74115_ADC_CH_CONV1),
1297	AD74115_ADC_CHANNEL(IIO_VOLTAGE, AD74115_ADC_CH_CONV2),
1298};
1299
1300static const struct iio_chan_spec ad74115_voltage_output_channels[] = {
1301	AD74115_DAC_CHANNEL(IIO_VOLTAGE, AD74115_DAC_CH_MAIN),
1302	AD74115_ADC_CHANNEL(IIO_CURRENT, AD74115_ADC_CH_CONV1),
1303	AD74115_ADC_CHANNEL(IIO_VOLTAGE, AD74115_ADC_CH_CONV2),
1304};
1305
1306static const struct iio_chan_spec ad74115_current_input_channels[] = {
1307	AD74115_ADC_CHANNEL(IIO_CURRENT, AD74115_ADC_CH_CONV1),
1308	AD74115_ADC_CHANNEL(IIO_VOLTAGE, AD74115_ADC_CH_CONV2),
1309};
1310
1311static const struct iio_chan_spec ad74115_current_output_channels[] = {
1312	AD74115_DAC_CHANNEL(IIO_CURRENT, AD74115_DAC_CH_MAIN),
1313	AD74115_ADC_CHANNEL(IIO_VOLTAGE, AD74115_ADC_CH_CONV1),
1314	AD74115_ADC_CHANNEL(IIO_VOLTAGE, AD74115_ADC_CH_CONV2),
1315};
1316
1317static const struct iio_chan_spec ad74115_2_wire_resistance_input_channels[] = {
1318	_AD74115_ADC_CHANNEL(IIO_RESISTANCE, AD74115_ADC_CH_CONV1,
1319			     BIT(IIO_CHAN_INFO_PROCESSED)),
1320	AD74115_ADC_CHANNEL(IIO_VOLTAGE, AD74115_ADC_CH_CONV2),
1321};
1322
1323static const struct iio_chan_spec ad74115_3_4_wire_resistance_input_channels[] = {
1324	AD74115_ADC_CHANNEL(IIO_RESISTANCE, AD74115_ADC_CH_CONV1),
1325	AD74115_ADC_CHANNEL(IIO_VOLTAGE, AD74115_ADC_CH_CONV2),
1326};
1327
1328static const struct iio_chan_spec ad74115_digital_input_logic_channels[] = {
1329	AD74115_DAC_CHANNEL(IIO_VOLTAGE, AD74115_DAC_CH_COMPARATOR),
1330	AD74115_ADC_CHANNEL(IIO_VOLTAGE, AD74115_ADC_CH_CONV1),
1331	AD74115_ADC_CHANNEL(IIO_VOLTAGE, AD74115_ADC_CH_CONV2),
1332};
1333
1334static const struct iio_chan_spec ad74115_digital_input_loop_channels[] = {
1335	AD74115_DAC_CHANNEL(IIO_CURRENT, AD74115_DAC_CH_MAIN),
1336	AD74115_DAC_CHANNEL(IIO_VOLTAGE, AD74115_DAC_CH_COMPARATOR),
1337	AD74115_ADC_CHANNEL(IIO_VOLTAGE, AD74115_ADC_CH_CONV1),
1338	AD74115_ADC_CHANNEL(IIO_VOLTAGE, AD74115_ADC_CH_CONV2),
1339};
1340
1341#define _AD74115_CHANNELS(_channels)			\
1342	{						\
1343		.channels = _channels,			\
1344		.num_channels = ARRAY_SIZE(_channels),	\
1345	}
1346
1347#define AD74115_CHANNELS(name) \
1348	_AD74115_CHANNELS(ad74115_ ## name ## _channels)
1349
1350static const struct ad74115_channels ad74115_channels_map[AD74115_CH_FUNC_NUM] = {
1351	[AD74115_CH_FUNC_HIGH_IMPEDANCE] = AD74115_CHANNELS(voltage_input),
1352	[AD74115_CH_FUNC_VOLTAGE_INPUT] = AD74115_CHANNELS(voltage_input),
1353
1354	[AD74115_CH_FUNC_VOLTAGE_OUTPUT] = AD74115_CHANNELS(voltage_output),
1355
1356	[AD74115_CH_FUNC_CURRENT_INPUT_EXT_POWER] = AD74115_CHANNELS(current_input),
1357	[AD74115_CH_FUNC_CURRENT_INPUT_LOOP_POWER] = AD74115_CHANNELS(current_input),
1358	[AD74115_CH_FUNC_CURRENT_INPUT_EXT_POWER_HART] = AD74115_CHANNELS(current_input),
1359	[AD74115_CH_FUNC_CURRENT_INPUT_LOOP_POWER_HART] = AD74115_CHANNELS(current_input),
1360
1361	[AD74115_CH_FUNC_CURRENT_OUTPUT] = AD74115_CHANNELS(current_output),
1362	[AD74115_CH_FUNC_CURRENT_OUTPUT_HART] = AD74115_CHANNELS(current_output),
1363
1364	[AD74115_CH_FUNC_2_WIRE_RESISTANCE_INPUT] = AD74115_CHANNELS(2_wire_resistance_input),
1365	[AD74115_CH_FUNC_3_4_WIRE_RESISTANCE_INPUT] = AD74115_CHANNELS(3_4_wire_resistance_input),
1366
1367	[AD74115_CH_FUNC_DIGITAL_INPUT_LOGIC] = AD74115_CHANNELS(digital_input_logic),
1368
1369	[AD74115_CH_FUNC_DIGITAL_INPUT_LOOP_POWER] = AD74115_CHANNELS(digital_input_loop),
1370};
1371
1372#define AD74115_GPIO_MODE_FW_PROP(i)					\
1373{									\
1374	.name = "adi,gpio" __stringify(i) "-mode",			\
1375	.reg = AD74115_GPIO_CONFIG_X_REG(i),				\
1376	.mask = AD74115_GPIO_CONFIG_SELECT_MASK,			\
1377	.lookup_tbl = ad74115_gpio_mode_tbl,				\
1378	.lookup_tbl_len = ARRAY_SIZE(ad74115_gpio_mode_tbl),		\
1379}
1380
1381static const struct ad74115_fw_prop ad74115_gpio_mode_fw_props[] = {
1382	AD74115_GPIO_MODE_FW_PROP(0),
1383	AD74115_GPIO_MODE_FW_PROP(1),
1384	AD74115_GPIO_MODE_FW_PROP(2),
1385	AD74115_GPIO_MODE_FW_PROP(3),
1386};
1387
1388static const struct ad74115_fw_prop ad74115_din_threshold_mode_fw_prop =
1389	AD74115_FW_PROP_BOOL("adi,digital-input-threshold-mode-fixed",
1390			     AD74115_DIN_CONFIG2_REG, BIT(7));
1391
1392static const struct ad74115_fw_prop ad74115_dac_bipolar_fw_prop =
1393	AD74115_FW_PROP_BOOL("adi,dac-bipolar", AD74115_OUTPUT_CONFIG_REG, BIT(7));
1394
1395static const struct ad74115_fw_prop ad74115_ch_func_fw_prop =
1396	AD74115_FW_PROP("adi,ch-func", AD74115_CH_FUNC_MAX,
1397			AD74115_CH_FUNC_SETUP_REG, GENMASK(3, 0));
1398
1399static const struct ad74115_fw_prop ad74115_rtd_mode_fw_prop =
1400	AD74115_FW_PROP_BOOL("adi,4-wire-rtd", AD74115_RTD3W4W_CONFIG_REG, BIT(3));
1401
1402static const struct ad74115_fw_prop ad74115_din_range_fw_prop =
1403	AD74115_FW_PROP_BOOL("adi,digital-input-sink-range-high",
1404			     AD74115_DIN_CONFIG1_REG, BIT(12));
1405
1406static const struct ad74115_fw_prop ad74115_ext2_burnout_current_fw_prop =
1407	AD74115_FW_PROP_TBL("adi,ext2-burnout-current-nanoamp",
1408			    ad74115_burnout_current_na_tbl,
1409			    AD74115_BURNOUT_CONFIG_REG, GENMASK(14, 12));
1410
1411static const struct ad74115_fw_prop ad74115_ext1_burnout_current_fw_prop =
1412	AD74115_FW_PROP_TBL("adi,ext1-burnout-current-nanoamp",
1413			    ad74115_burnout_current_na_tbl,
1414			    AD74115_BURNOUT_CONFIG_REG, GENMASK(9, 7));
1415
1416static const struct ad74115_fw_prop ad74115_viout_burnout_current_fw_prop =
1417	AD74115_FW_PROP_TBL("adi,viout-burnout-current-nanoamp",
1418			    ad74115_viout_burnout_current_na_tbl,
1419			    AD74115_BURNOUT_CONFIG_REG, GENMASK(4, 2));
1420
1421static const struct ad74115_fw_prop ad74115_fw_props[] = {
1422	AD74115_FW_PROP("adi,conv2-mux", 3,
1423			AD74115_ADC_CONFIG_REG, GENMASK(3, 2)),
1424
1425	AD74115_FW_PROP_BOOL_NEG("adi,sense-agnd-buffer-low-power",
1426				 AD74115_PWR_OPTIM_CONFIG_REG, BIT(4)),
1427	AD74115_FW_PROP_BOOL_NEG("adi,lf-buffer-low-power",
1428				 AD74115_PWR_OPTIM_CONFIG_REG, BIT(3)),
1429	AD74115_FW_PROP_BOOL_NEG("adi,hf-buffer-low-power",
1430				 AD74115_PWR_OPTIM_CONFIG_REG, BIT(2)),
1431	AD74115_FW_PROP_BOOL_NEG("adi,ext2-buffer-low-power",
1432				 AD74115_PWR_OPTIM_CONFIG_REG, BIT(1)),
1433	AD74115_FW_PROP_BOOL_NEG("adi,ext1-buffer-low-power",
1434				 AD74115_PWR_OPTIM_CONFIG_REG, BIT(0)),
1435
1436	AD74115_FW_PROP_BOOL("adi,comparator-invert",
1437			     AD74115_DIN_CONFIG1_REG, BIT(14)),
1438	AD74115_FW_PROP_BOOL("adi,digital-input-debounce-mode-counter-reset",
1439			     AD74115_DIN_CONFIG1_REG, BIT(6)),
1440
1441	AD74115_FW_PROP_BOOL("adi,digital-input-unbuffered",
1442			     AD74115_DIN_CONFIG2_REG, BIT(10)),
1443	AD74115_FW_PROP_BOOL("adi,digital-input-short-circuit-detection",
1444			     AD74115_DIN_CONFIG2_REG, BIT(9)),
1445	AD74115_FW_PROP_BOOL("adi,digital-input-open-circuit-detection",
1446			     AD74115_DIN_CONFIG2_REG, BIT(8)),
1447
1448	AD74115_FW_PROP_BOOL("adi,dac-current-limit-low",
1449			     AD74115_OUTPUT_CONFIG_REG, BIT(0)),
1450
1451	AD74115_FW_PROP_BOOL("adi,3-wire-rtd-excitation-swap",
1452			     AD74115_RTD3W4W_CONFIG_REG, BIT(2)),
1453	AD74115_FW_PROP_TBL("adi,rtd-excitation-current-microamp",
1454			    ad74115_rtd_excitation_current_ua_tbl,
1455			    AD74115_RTD3W4W_CONFIG_REG, GENMASK(1, 0)),
1456
1457	AD74115_FW_PROP_BOOL("adi,ext2-burnout-current-polarity-sourcing",
1458			     AD74115_BURNOUT_CONFIG_REG, BIT(11)),
1459	AD74115_FW_PROP_BOOL("adi,ext1-burnout-current-polarity-sourcing",
1460			     AD74115_BURNOUT_CONFIG_REG, BIT(6)),
1461	AD74115_FW_PROP_BOOL("adi,viout-burnout-current-polarity-sourcing",
1462			     AD74115_BURNOUT_CONFIG_REG, BIT(1)),
1463
1464	AD74115_FW_PROP_BOOL("adi,charge-pump",
1465			     AD74115_CHARGE_PUMP_REG, BIT(0)),
1466};
1467
1468static int ad74115_apply_fw_prop(struct ad74115_state *st,
1469				 const struct ad74115_fw_prop *prop, u32 *retval)
1470{
1471	struct device *dev = &st->spi->dev;
1472	u32 val = 0;
1473	int ret;
1474
1475	if (prop->is_boolean) {
1476		val = device_property_read_bool(dev, prop->name);
1477	} else {
1478		ret = device_property_read_u32(dev, prop->name, &val);
1479		if (ret && prop->lookup_tbl)
1480			val = prop->lookup_tbl[0];
1481	}
1482
1483	*retval = val;
1484
1485	if (prop->negate)
1486		val = !val;
1487
1488	if (prop->lookup_tbl)
1489		ret = _ad74115_find_tbl_index(prop->lookup_tbl,
1490					      prop->lookup_tbl_len, val, &val);
1491	else if (prop->max && val > prop->max)
1492		ret = -EINVAL;
1493	else
1494		ret = 0;
1495
1496	if (ret)
1497		return dev_err_probe(dev, -EINVAL,
1498				     "Invalid value %u for prop %s\n",
1499				     val, prop->name);
1500
1501	WARN(!prop->mask, "Prop %s mask is empty\n", prop->name);
1502
1503	val = (val << __ffs(prop->mask)) & prop->mask;
1504
1505	return regmap_update_bits(st->regmap, prop->reg, prop->mask, val);
1506}
1507
1508static int ad74115_setup_adc_conv2_range(struct ad74115_state *st)
1509{
1510	unsigned int tbl_len = ARRAY_SIZE(ad74115_adc_range_tbl);
1511	const char *prop_name = "adi,conv2-range-microvolt";
1512	s32 vals[2] = {
1513		ad74115_adc_range_tbl[0][0],
1514		ad74115_adc_range_tbl[0][1],
1515	};
1516	struct device *dev = &st->spi->dev;
1517	unsigned int i;
1518
1519	device_property_read_u32_array(dev, prop_name, vals, 2);
1520
1521	for (i = 0; i < tbl_len; i++)
1522		if (vals[0] == ad74115_adc_range_tbl[i][0] &&
1523		    vals[1] == ad74115_adc_range_tbl[i][1])
1524			break;
1525
1526	if (i == tbl_len)
1527		return dev_err_probe(dev, -EINVAL,
1528				     "Invalid value %d, %d for prop %s\n",
1529				     vals[0], vals[1], prop_name);
1530
1531	return regmap_update_bits(st->regmap, AD74115_ADC_CONFIG_REG,
1532				  AD74115_ADC_CONFIG_CONV2_RANGE_MASK,
1533				  FIELD_PREP(AD74115_ADC_CONFIG_CONV2_RANGE_MASK, i));
1534}
1535
1536static int ad74115_setup_iio_channels(struct iio_dev *indio_dev)
1537{
1538	struct ad74115_state *st = iio_priv(indio_dev);
1539	struct device *dev = &st->spi->dev;
1540	struct iio_chan_spec *channels;
1541
1542	channels = devm_kcalloc(dev, sizeof(*channels),
1543				indio_dev->num_channels, GFP_KERNEL);
1544	if (!channels)
1545		return -ENOMEM;
1546
1547	indio_dev->channels = channels;
1548
1549	memcpy(channels, ad74115_channels_map[st->ch_func].channels,
1550	       sizeof(*channels) * ad74115_channels_map[st->ch_func].num_channels);
1551
1552	if (channels[0].output && channels[0].channel == AD74115_DAC_CH_MAIN &&
1553	    channels[0].type == IIO_VOLTAGE && !st->dac_hart_slew) {
1554		channels[0].info_mask_separate |= BIT(IIO_CHAN_INFO_SAMP_FREQ);
1555		channels[0].info_mask_separate_available |= BIT(IIO_CHAN_INFO_SAMP_FREQ);
1556	}
1557
1558	return 0;
1559}
1560
1561static int ad74115_setup_gpio_chip(struct ad74115_state *st)
1562{
1563	struct device *dev = &st->spi->dev;
1564
1565	if (!st->gpio_valid_mask)
1566		return 0;
1567
1568	st->gc = (struct gpio_chip) {
1569		.owner = THIS_MODULE,
1570		.label = AD74115_NAME,
1571		.base = -1,
1572		.ngpio = AD74115_GPIO_NUM,
1573		.parent = dev,
1574		.can_sleep = true,
1575		.init_valid_mask = ad74115_gpio_init_valid_mask,
1576		.get_direction = ad74115_gpio_get_direction,
1577		.direction_input = ad74115_gpio_direction_input,
1578		.direction_output = ad74115_gpio_direction_output,
1579		.get = ad74115_gpio_get,
1580		.set = ad74115_gpio_set,
1581	};
1582
1583	return devm_gpiochip_add_data(dev, &st->gc, st);
1584}
1585
1586static int ad74115_setup_comp_gpio_chip(struct ad74115_state *st)
1587{
1588	struct device *dev = &st->spi->dev;
1589	u32 val;
1590	int ret;
1591
1592	ret = regmap_read(st->regmap, AD74115_DIN_CONFIG1_REG, &val);
1593	if (ret)
1594		return ret;
1595
1596	if (!(val & AD74115_DIN_COMPARATOR_EN_MASK))
1597		return 0;
1598
1599	st->comp_gc = (struct gpio_chip) {
1600		.owner = THIS_MODULE,
1601		.label = AD74115_NAME,
1602		.base = -1,
1603		.ngpio = 1,
1604		.parent = dev,
1605		.can_sleep = true,
1606		.get_direction = ad74115_comp_gpio_get_direction,
1607		.get = ad74115_comp_gpio_get,
1608		.set_config = ad74115_comp_gpio_set_config,
1609	};
1610
1611	return devm_gpiochip_add_data(dev, &st->comp_gc, st);
1612}
1613
1614static int ad74115_setup(struct iio_dev *indio_dev)
1615{
1616	struct ad74115_state *st = iio_priv(indio_dev);
1617	struct device *dev = &st->spi->dev;
1618	u32 val, din_range_high;
1619	unsigned int i;
1620	int ret;
1621
1622	ret = ad74115_apply_fw_prop(st, &ad74115_ch_func_fw_prop, &val);
1623	if (ret)
1624		return ret;
1625
1626	indio_dev->num_channels += ad74115_channels_map[val].num_channels;
1627	st->ch_func = val;
1628
1629	ret = ad74115_setup_adc_conv2_range(st);
1630	if (ret)
1631		return ret;
1632
1633	val = device_property_read_bool(dev, "adi,dac-hart-slew");
1634	if (val) {
1635		st->dac_hart_slew = val;
1636
1637		ret = regmap_update_bits(st->regmap, AD74115_OUTPUT_CONFIG_REG,
1638					 AD74115_OUTPUT_SLEW_EN_MASK,
1639					 FIELD_PREP(AD74115_OUTPUT_SLEW_EN_MASK,
1640						    AD74115_SLEW_MODE_HART));
1641		if (ret)
1642			return ret;
1643	}
1644
1645	ret = ad74115_apply_fw_prop(st, &ad74115_din_range_fw_prop,
1646				    &din_range_high);
1647	if (ret)
1648		return ret;
1649
1650	ret = device_property_read_u32(dev, "adi,digital-input-sink-microamp", &val);
1651	if (!ret) {
1652		if (din_range_high)
1653			val = DIV_ROUND_CLOSEST(val, AD74115_DIN_SINK_LOW_STEP);
1654		else
1655			val = DIV_ROUND_CLOSEST(val, AD74115_DIN_SINK_HIGH_STEP);
1656
1657		if (val > AD74115_DIN_SINK_MAX)
1658			val = AD74115_DIN_SINK_MAX;
1659
1660		ret = regmap_update_bits(st->regmap, AD74115_DIN_CONFIG1_REG,
1661					 AD74115_DIN_SINK_MASK,
1662					 FIELD_PREP(AD74115_DIN_SINK_MASK, val));
1663		if (ret)
1664			return ret;
1665	}
1666
1667	ret = ad74115_apply_fw_prop(st, &ad74115_din_threshold_mode_fw_prop, &val);
1668	if (ret)
1669		return ret;
1670
1671	if (val == AD74115_DIN_THRESHOLD_MODE_AVDD && !st->avdd_mv)
1672		return dev_err_probe(dev, -EINVAL,
1673				     "AVDD voltage is required for digital input threshold mode AVDD\n");
1674
1675	st->din_threshold_mode = val;
1676
1677	ret = ad74115_apply_fw_prop(st, &ad74115_dac_bipolar_fw_prop, &val);
1678	if (ret)
1679		return ret;
1680
1681	st->dac_bipolar = val;
1682
1683	ret = ad74115_apply_fw_prop(st, &ad74115_rtd_mode_fw_prop, &val);
1684	if (ret)
1685		return ret;
1686
1687	st->rtd_mode_4_wire = val;
1688
1689	ret = ad74115_apply_fw_prop(st, &ad74115_ext2_burnout_current_fw_prop, &val);
1690	if (ret)
1691		return ret;
1692
1693	if (val) {
1694		ret = regmap_update_bits(st->regmap, AD74115_BURNOUT_CONFIG_REG,
1695					 AD74115_BURNOUT_EXT2_EN_MASK,
1696					 FIELD_PREP(AD74115_BURNOUT_EXT2_EN_MASK, 1));
1697		if (ret)
1698			return ret;
1699	}
1700
1701	ret = ad74115_apply_fw_prop(st, &ad74115_ext1_burnout_current_fw_prop, &val);
1702	if (ret)
1703		return ret;
1704
1705	if (val) {
1706		ret = regmap_update_bits(st->regmap, AD74115_BURNOUT_CONFIG_REG,
1707					 AD74115_BURNOUT_EXT1_EN_MASK,
1708					 FIELD_PREP(AD74115_BURNOUT_EXT1_EN_MASK, 1));
1709		if (ret)
1710			return ret;
1711	}
1712
1713	ret = ad74115_apply_fw_prop(st, &ad74115_viout_burnout_current_fw_prop, &val);
1714	if (ret)
1715		return ret;
1716
1717	if (val) {
1718		ret = regmap_update_bits(st->regmap, AD74115_BURNOUT_CONFIG_REG,
1719					 AD74115_BURNOUT_VIOUT_EN_MASK,
1720					 FIELD_PREP(AD74115_BURNOUT_VIOUT_EN_MASK, 1));
1721		if (ret)
1722			return ret;
1723	}
1724
1725	for (i = 0; i < AD74115_GPIO_NUM; i++) {
1726		ret = ad74115_apply_fw_prop(st, &ad74115_gpio_mode_fw_props[i], &val);
1727		if (ret)
1728			return ret;
1729
1730		if (val == AD74115_GPIO_MODE_LOGIC)
1731			st->gpio_valid_mask |= BIT(i);
1732	}
1733
1734	for (i = 0; i < ARRAY_SIZE(ad74115_fw_props); i++) {
1735		ret = ad74115_apply_fw_prop(st, &ad74115_fw_props[i], &val);
1736		if (ret)
1737			return ret;
1738	}
1739
1740	ret = ad74115_setup_gpio_chip(st);
1741	if (ret)
1742		return ret;
1743
1744	ret = ad74115_setup_comp_gpio_chip(st);
1745	if (ret)
1746		return ret;
1747
1748	return ad74115_setup_iio_channels(indio_dev);
1749}
1750
1751static int ad74115_reset(struct ad74115_state *st)
1752{
1753	struct device *dev = &st->spi->dev;
1754	struct gpio_desc *reset_gpio;
1755	int ret;
1756
1757	reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
1758	if (IS_ERR(reset_gpio))
1759		return dev_err_probe(dev, PTR_ERR(reset_gpio),
1760				     "Failed to find reset GPIO\n");
1761
1762	if (reset_gpio) {
1763		fsleep(100);
1764
1765		gpiod_set_value_cansleep(reset_gpio, 0);
1766	} else {
1767		ret = regmap_write(st->regmap, AD74115_CMD_KEY_REG,
1768				   AD74115_CMD_KEY_RESET1);
1769		if (ret)
1770			return ret;
1771
1772		ret = regmap_write(st->regmap, AD74115_CMD_KEY_REG,
1773				   AD74115_CMD_KEY_RESET2);
1774		if (ret)
1775			return ret;
1776	}
1777
1778	fsleep(1000);
1779
1780	return 0;
1781}
1782
1783static int ad74115_setup_trigger(struct iio_dev *indio_dev)
1784{
1785	struct ad74115_state *st = iio_priv(indio_dev);
1786	struct device *dev = &st->spi->dev;
1787	int ret;
1788
1789	st->irq = fwnode_irq_get_byname(dev_fwnode(dev), "adc_rdy");
1790
1791	if (st->irq == -EPROBE_DEFER)
1792		return -EPROBE_DEFER;
1793
1794	if (st->irq < 0) {
1795		st->irq = 0;
1796		return 0;
1797	}
1798
1799	ret = devm_request_irq(dev, st->irq, ad74115_adc_data_interrupt,
1800			       0, AD74115_NAME, indio_dev);
1801	if (ret)
1802		return ret;
1803
1804	st->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", AD74115_NAME,
1805					  iio_device_id(indio_dev));
1806	if (!st->trig)
1807		return -ENOMEM;
1808
1809	st->trig->ops = &ad74115_trigger_ops;
1810	iio_trigger_set_drvdata(st->trig, st);
1811
1812	ret = devm_iio_trigger_register(dev, st->trig);
1813	if (ret)
1814		return ret;
1815
1816	indio_dev->trig = iio_trigger_get(st->trig);
1817
1818	return 0;
1819}
1820
1821static int ad74115_probe(struct spi_device *spi)
1822{
1823	static const char * const regulator_names[] = {
1824		"avcc", "dvcc", "dovdd", "refin",
1825	};
1826	struct device *dev = &spi->dev;
1827	struct ad74115_state *st;
1828	struct iio_dev *indio_dev;
1829	int ret;
1830
1831	indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1832	if (!indio_dev)
1833		return -ENOMEM;
1834
1835	st = iio_priv(indio_dev);
1836
1837	st->spi = spi;
1838	mutex_init(&st->lock);
1839	init_completion(&st->adc_data_completion);
1840
1841	indio_dev->name = AD74115_NAME;
1842	indio_dev->modes = INDIO_DIRECT_MODE;
1843	indio_dev->info = &ad74115_info;
1844
1845	ret = devm_regulator_get_enable_read_voltage(dev, "avdd");
1846	if (ret < 0) {
1847		/*
1848		 * Since this is both a power supply and only optionally a
1849		 * reference voltage, make sure to enable it even when the
1850		 * voltage is not available.
1851		 */
1852		ret = devm_regulator_get_enable(dev, "avdd");
1853		if (ret)
1854			return dev_err_probe(dev, ret, "failed to enable avdd\n");
1855	} else {
1856		st->avdd_mv = ret / 1000;
1857	}
1858
1859	ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulator_names),
1860					     regulator_names);
1861	if (ret)
1862		return ret;
1863
1864	st->regmap = devm_regmap_init(dev, NULL, st, &ad74115_regmap_config);
1865	if (IS_ERR(st->regmap))
1866		return PTR_ERR(st->regmap);
1867
1868	ret = ad74115_reset(st);
1869	if (ret)
1870		return ret;
1871
1872	ret = ad74115_setup(indio_dev);
1873	if (ret)
1874		return ret;
1875
1876	ret = ad74115_setup_trigger(indio_dev);
1877	if (ret)
1878		return ret;
1879
1880	ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
1881					      ad74115_trigger_handler,
1882					      &ad74115_buffer_ops);
1883	if (ret)
1884		return ret;
1885
1886	return devm_iio_device_register(dev, indio_dev);
1887}
1888
1889static int ad74115_unregister_driver(struct spi_driver *spi)
1890{
1891	spi_unregister_driver(spi);
1892
1893	return 0;
1894}
1895
1896static int __init ad74115_register_driver(struct spi_driver *spi)
1897{
1898	crc8_populate_msb(ad74115_crc8_table, AD74115_CRC_POLYNOMIAL);
1899
1900	return spi_register_driver(spi);
1901}
1902
1903static const struct spi_device_id ad74115_spi_id[] = {
1904	{ "ad74115h" },
1905	{ }
1906};
1907
1908MODULE_DEVICE_TABLE(spi, ad74115_spi_id);
1909
1910static const struct of_device_id ad74115_dt_id[] = {
1911	{ .compatible = "adi,ad74115h" },
1912	{ }
1913};
1914MODULE_DEVICE_TABLE(of, ad74115_dt_id);
1915
1916static struct spi_driver ad74115_driver = {
1917	.driver = {
1918		   .name = "ad74115",
1919		   .of_match_table = ad74115_dt_id,
1920	},
1921	.probe = ad74115_probe,
1922	.id_table = ad74115_spi_id,
1923};
1924
1925module_driver(ad74115_driver,
1926	      ad74115_register_driver, ad74115_unregister_driver);
1927
1928MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>");
1929MODULE_DESCRIPTION("Analog Devices AD74115 ADDAC");
1930MODULE_LICENSE("GPL");