xilinx-ams.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Xilinx AMS driver
   4 *
   5 *  Copyright (C) 2021 Xilinx, Inc.
   6 *
   7 *  Manish Narani <mnarani@xilinx.com>
   8 *  Rajnikant Bhojani <rajnikant.bhojani@xilinx.com>
   9 */
  10
  11#include <linux/bits.h>
  12#include <linux/bitfield.h>
  13#include <linux/clk.h>
  14#include <linux/delay.h>
  15#include <linux/devm-helpers.h>
  16#include <linux/interrupt.h>
  17#include <linux/io.h>
  18#include <linux/iopoll.h>
  19#include <linux/kernel.h>
  20#include <linux/module.h>
  21#include <linux/mod_devicetable.h>
  22#include <linux/overflow.h>
  23#include <linux/platform_device.h>
  24#include <linux/property.h>
  25#include <linux/slab.h>
  26
  27#include <linux/iio/events.h>
  28#include <linux/iio/iio.h>
  29
  30/* AMS registers definitions */
  31#define AMS_ISR_0			0x010
  32#define AMS_ISR_1			0x014
  33#define AMS_IER_0			0x020
  34#define AMS_IER_1			0x024
  35#define AMS_IDR_0			0x028
  36#define AMS_IDR_1			0x02C
  37#define AMS_PS_CSTS			0x040
  38#define AMS_PL_CSTS			0x044
  39
  40#define AMS_VCC_PSPLL0			0x060
  41#define AMS_VCC_PSPLL3			0x06C
  42#define AMS_VCCINT			0x078
  43#define AMS_VCCBRAM			0x07C
  44#define AMS_VCCAUX			0x080
  45#define AMS_PSDDRPLL			0x084
  46#define AMS_PSINTFPDDR			0x09C
  47
  48#define AMS_VCC_PSPLL0_CH		48
  49#define AMS_VCC_PSPLL3_CH		51
  50#define AMS_VCCINT_CH			54
  51#define AMS_VCCBRAM_CH			55
  52#define AMS_VCCAUX_CH			56
  53#define AMS_PSDDRPLL_CH			57
  54#define AMS_PSINTFPDDR_CH		63
  55
  56#define AMS_REG_CONFIG0			0x100
  57#define AMS_REG_CONFIG1			0x104
  58#define AMS_REG_CONFIG3			0x10C
  59#define AMS_REG_CONFIG4			0x110
  60#define AMS_REG_SEQ_CH0			0x120
  61#define AMS_REG_SEQ_CH1			0x124
  62#define AMS_REG_SEQ_CH2			0x118
  63
  64#define AMS_VUSER0_MASK			BIT(0)
  65#define AMS_VUSER1_MASK			BIT(1)
  66#define AMS_VUSER2_MASK			BIT(2)
  67#define AMS_VUSER3_MASK			BIT(3)
  68
  69#define AMS_TEMP			0x000
  70#define AMS_SUPPLY1			0x004
  71#define AMS_SUPPLY2			0x008
  72#define AMS_VP_VN			0x00C
  73#define AMS_VREFP			0x010
  74#define AMS_VREFN			0x014
  75#define AMS_SUPPLY3			0x018
  76#define AMS_SUPPLY4			0x034
  77#define AMS_SUPPLY5			0x038
  78#define AMS_SUPPLY6			0x03C
  79#define AMS_SUPPLY7			0x200
  80#define AMS_SUPPLY8			0x204
  81#define AMS_SUPPLY9			0x208
  82#define AMS_SUPPLY10			0x20C
  83#define AMS_VCCAMS			0x210
  84#define AMS_TEMP_REMOTE			0x214
  85
  86#define AMS_REG_VAUX(x)			(0x40 + 4 * (x))
  87
  88#define AMS_PS_RESET_VALUE		0xFFFF
  89#define AMS_PL_RESET_VALUE		0xFFFF
  90
  91#define AMS_CONF0_CHANNEL_NUM_MASK	GENMASK(6, 0)
  92
  93#define AMS_CONF1_SEQ_MASK		GENMASK(15, 12)
  94#define AMS_CONF1_SEQ_DEFAULT		FIELD_PREP(AMS_CONF1_SEQ_MASK, 0)
  95#define AMS_CONF1_SEQ_CONTINUOUS	FIELD_PREP(AMS_CONF1_SEQ_MASK, 2)
  96#define AMS_CONF1_SEQ_SINGLE_CHANNEL	FIELD_PREP(AMS_CONF1_SEQ_MASK, 3)
  97
  98#define AMS_REG_SEQ0_MASK		GENMASK(15, 0)
  99#define AMS_REG_SEQ2_MASK		GENMASK(21, 16)
 100#define AMS_REG_SEQ1_MASK		GENMASK_ULL(37, 22)
 101
 102#define AMS_PS_SEQ_MASK			GENMASK(21, 0)
 103#define AMS_PL_SEQ_MASK			GENMASK_ULL(59, 22)
 104
 105#define AMS_ALARM_TEMP			0x140
 106#define AMS_ALARM_SUPPLY1		0x144
 107#define AMS_ALARM_SUPPLY2		0x148
 108#define AMS_ALARM_SUPPLY3		0x160
 109#define AMS_ALARM_SUPPLY4		0x164
 110#define AMS_ALARM_SUPPLY5		0x168
 111#define AMS_ALARM_SUPPLY6		0x16C
 112#define AMS_ALARM_SUPPLY7		0x180
 113#define AMS_ALARM_SUPPLY8		0x184
 114#define AMS_ALARM_SUPPLY9		0x188
 115#define AMS_ALARM_SUPPLY10		0x18C
 116#define AMS_ALARM_VCCAMS		0x190
 117#define AMS_ALARM_TEMP_REMOTE		0x194
 118#define AMS_ALARM_THRESHOLD_OFF_10	0x10
 119#define AMS_ALARM_THRESHOLD_OFF_20	0x20
 120
 121#define AMS_ALARM_THR_DIRECT_MASK	BIT(0)
 122#define AMS_ALARM_THR_MIN		0x0000
 123#define AMS_ALARM_THR_MAX		(BIT(16) - 1)
 124
 125#define AMS_ALARM_MASK			GENMASK_ULL(63, 0)
 126#define AMS_NO_OF_ALARMS		32
 127#define AMS_PL_ALARM_START		16
 128#define AMS_PL_ALARM_MASK		GENMASK(31, 16)
 129#define AMS_ISR0_ALARM_MASK		GENMASK(31, 0)
 130#define AMS_ISR1_ALARM_MASK		(GENMASK(31, 29) | GENMASK(4, 0))
 131#define AMS_ISR1_EOC_MASK		BIT(3)
 132#define AMS_ISR1_INTR_MASK		GENMASK_ULL(63, 32)
 133#define AMS_ISR0_ALARM_2_TO_0_MASK	GENMASK(2, 0)
 134#define AMS_ISR0_ALARM_6_TO_3_MASK	GENMASK(6, 3)
 135#define AMS_ISR0_ALARM_12_TO_7_MASK	GENMASK(13, 8)
 136#define AMS_CONF1_ALARM_2_TO_0_MASK	GENMASK(3, 1)
 137#define AMS_CONF1_ALARM_6_TO_3_MASK	GENMASK(11, 8)
 138#define AMS_CONF1_ALARM_12_TO_7_MASK	GENMASK(5, 0)
 139#define AMS_REGCFG1_ALARM_MASK  \
 140	(AMS_CONF1_ALARM_2_TO_0_MASK | AMS_CONF1_ALARM_6_TO_3_MASK | BIT(0))
 141#define AMS_REGCFG3_ALARM_MASK		AMS_CONF1_ALARM_12_TO_7_MASK
 142
 143#define AMS_PS_CSTS_PS_READY		(BIT(27) | BIT(16))
 144#define AMS_PL_CSTS_ACCESS_MASK		BIT(1)
 145
 146#define AMS_PL_MAX_FIXED_CHANNEL	10
 147#define AMS_PL_MAX_EXT_CHANNEL		20
 148
 149#define AMS_INIT_POLL_TIME_US		200
 150#define AMS_INIT_TIMEOUT_US		10000
 151#define AMS_UNMASK_TIMEOUT_MS		500
 152
 153/*
 154 * Following scale and offset value is derived from
 155 * UG580 (v1.7) December 20, 2016
 156 */
 157#define AMS_SUPPLY_SCALE_1VOLT_mV		1000
 158#define AMS_SUPPLY_SCALE_3VOLT_mV		3000
 159#define AMS_SUPPLY_SCALE_6VOLT_mV		6000
 160#define AMS_SUPPLY_SCALE_DIV_BIT	16
 161
 162#define AMS_TEMP_SCALE			509314
 163#define AMS_TEMP_SCALE_DIV_BIT		16
 164#define AMS_TEMP_OFFSET			-((280230LL << 16) / 509314)
 165
 166enum ams_alarm_bit {
 167	AMS_ALARM_BIT_TEMP = 0,
 168	AMS_ALARM_BIT_SUPPLY1 = 1,
 169	AMS_ALARM_BIT_SUPPLY2 = 2,
 170	AMS_ALARM_BIT_SUPPLY3 = 3,
 171	AMS_ALARM_BIT_SUPPLY4 = 4,
 172	AMS_ALARM_BIT_SUPPLY5 = 5,
 173	AMS_ALARM_BIT_SUPPLY6 = 6,
 174	AMS_ALARM_BIT_RESERVED = 7,
 175	AMS_ALARM_BIT_SUPPLY7 = 8,
 176	AMS_ALARM_BIT_SUPPLY8 = 9,
 177	AMS_ALARM_BIT_SUPPLY9 = 10,
 178	AMS_ALARM_BIT_SUPPLY10 = 11,
 179	AMS_ALARM_BIT_VCCAMS = 12,
 180	AMS_ALARM_BIT_TEMP_REMOTE = 13,
 181};
 182
 183enum ams_seq {
 184	AMS_SEQ_VCC_PSPLL = 0,
 185	AMS_SEQ_VCC_PSBATT = 1,
 186	AMS_SEQ_VCCINT = 2,
 187	AMS_SEQ_VCCBRAM = 3,
 188	AMS_SEQ_VCCAUX = 4,
 189	AMS_SEQ_PSDDRPLL = 5,
 190	AMS_SEQ_INTDDR = 6,
 191};
 192
 193enum ams_ps_pl_seq {
 194	AMS_SEQ_CALIB = 0,
 195	AMS_SEQ_RSVD_1 = 1,
 196	AMS_SEQ_RSVD_2 = 2,
 197	AMS_SEQ_TEST = 3,
 198	AMS_SEQ_RSVD_4 = 4,
 199	AMS_SEQ_SUPPLY4 = 5,
 200	AMS_SEQ_SUPPLY5 = 6,
 201	AMS_SEQ_SUPPLY6 = 7,
 202	AMS_SEQ_TEMP = 8,
 203	AMS_SEQ_SUPPLY2 = 9,
 204	AMS_SEQ_SUPPLY1 = 10,
 205	AMS_SEQ_VP_VN = 11,
 206	AMS_SEQ_VREFP = 12,
 207	AMS_SEQ_VREFN = 13,
 208	AMS_SEQ_SUPPLY3 = 14,
 209	AMS_SEQ_CURRENT_MON = 15,
 210	AMS_SEQ_SUPPLY7 = 16,
 211	AMS_SEQ_SUPPLY8 = 17,
 212	AMS_SEQ_SUPPLY9 = 18,
 213	AMS_SEQ_SUPPLY10 = 19,
 214	AMS_SEQ_VCCAMS = 20,
 215	AMS_SEQ_TEMP_REMOTE = 21,
 216	AMS_SEQ_MAX = 22
 217};
 218
 219#define AMS_PS_SEQ_MAX		AMS_SEQ_MAX
 220#define AMS_SEQ(x)		(AMS_SEQ_MAX + (x))
 221#define PS_SEQ(x)		(x)
 222#define PL_SEQ(x)		(AMS_PS_SEQ_MAX + (x))
 223#define AMS_CTRL_SEQ_BASE	(AMS_PS_SEQ_MAX * 3)
 224
 225#define AMS_CHAN_TEMP(_scan_index, _addr, _name) { \
 226	.type = IIO_TEMP, \
 227	.indexed = 1, \
 228	.address = (_addr), \
 229	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
 230		BIT(IIO_CHAN_INFO_SCALE) | \
 231		BIT(IIO_CHAN_INFO_OFFSET), \
 232	.event_spec = ams_temp_events, \
 233	.scan_index = _scan_index, \
 234	.num_event_specs = ARRAY_SIZE(ams_temp_events), \
 235	.datasheet_name = _name, \
 236}
 237
 238#define AMS_CHAN_VOLTAGE(_scan_index, _addr, _alarm, _name) { \
 239	.type = IIO_VOLTAGE, \
 240	.indexed = 1, \
 241	.address = (_addr), \
 242	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
 243		BIT(IIO_CHAN_INFO_SCALE), \
 244	.event_spec = (_alarm) ? ams_voltage_events : NULL, \
 245	.scan_index = _scan_index, \
 246	.num_event_specs = (_alarm) ? ARRAY_SIZE(ams_voltage_events) : 0, \
 247	.datasheet_name = _name, \
 248}
 249
 250#define AMS_PS_CHAN_TEMP(_scan_index, _addr, _name) \
 251	AMS_CHAN_TEMP(PS_SEQ(_scan_index), _addr, _name)
 252#define AMS_PS_CHAN_VOLTAGE(_scan_index, _addr, _name) \
 253	AMS_CHAN_VOLTAGE(PS_SEQ(_scan_index), _addr, true, _name)
 254
 255#define AMS_PL_CHAN_TEMP(_scan_index, _addr, _name) \
 256	AMS_CHAN_TEMP(PL_SEQ(_scan_index), _addr, _name)
 257#define AMS_PL_CHAN_VOLTAGE(_scan_index, _addr, _alarm, _name) \
 258	AMS_CHAN_VOLTAGE(PL_SEQ(_scan_index), _addr, _alarm, _name)
 259#define AMS_PL_AUX_CHAN_VOLTAGE(_auxno) \
 260	AMS_CHAN_VOLTAGE(PL_SEQ(AMS_SEQ(_auxno)), AMS_REG_VAUX(_auxno), false, \
 261			 "VAUX" #_auxno)
 262#define AMS_CTRL_CHAN_VOLTAGE(_scan_index, _addr, _name) \
 263	AMS_CHAN_VOLTAGE(PL_SEQ(AMS_SEQ(AMS_SEQ(_scan_index))), _addr, false, \
 264			 _name)
 265
 266/**
 267 * struct ams - This structure contains necessary state for xilinx-ams to operate
 268 * @base: physical base address of device
 269 * @ps_base: physical base address of PS device
 270 * @pl_base: physical base address of PL device
 271 * @clk: clocks associated with the device
 272 * @dev: pointer to device struct
 273 * @lock: to handle multiple user interaction
 274 * @intr_lock: to protect interrupt mask values
 275 * @alarm_mask: alarm configuration
 276 * @current_masked_alarm: currently masked due to alarm
 277 * @intr_mask: interrupt configuration
 278 * @ams_unmask_work: re-enables event once the event condition disappears
 279 *
 280 */
 281struct ams {
 282	void __iomem *base;
 283	void __iomem *ps_base;
 284	void __iomem *pl_base;
 285	struct clk *clk;
 286	struct device *dev;
 287	struct mutex lock;
 288	spinlock_t intr_lock;
 289	unsigned int alarm_mask;
 290	unsigned int current_masked_alarm;
 291	u64 intr_mask;
 292	struct delayed_work ams_unmask_work;
 293};
 294
 295static inline void ams_ps_update_reg(struct ams *ams, unsigned int offset,
 296				     u32 mask, u32 data)
 297{
 298	u32 val, regval;
 299
 300	val = readl(ams->ps_base + offset);
 301	regval = (val & ~mask) | (data & mask);
 302	writel(regval, ams->ps_base + offset);
 303}
 304
 305static inline void ams_pl_update_reg(struct ams *ams, unsigned int offset,
 306				     u32 mask, u32 data)
 307{
 308	u32 val, regval;
 309
 310	val = readl(ams->pl_base + offset);
 311	regval = (val & ~mask) | (data & mask);
 312	writel(regval, ams->pl_base + offset);
 313}
 314
 315static void ams_update_intrmask(struct ams *ams, u64 mask, u64 val)
 316{
 317	u32 regval;
 318
 319	ams->intr_mask = (ams->intr_mask & ~mask) | (val & mask);
 320
 321	regval = ~(ams->intr_mask | ams->current_masked_alarm);
 322	writel(regval, ams->base + AMS_IER_0);
 323
 324	regval = ~(FIELD_GET(AMS_ISR1_INTR_MASK, ams->intr_mask));
 325	writel(regval, ams->base + AMS_IER_1);
 326
 327	regval = ams->intr_mask | ams->current_masked_alarm;
 328	writel(regval, ams->base + AMS_IDR_0);
 329
 330	regval = FIELD_GET(AMS_ISR1_INTR_MASK, ams->intr_mask);
 331	writel(regval, ams->base + AMS_IDR_1);
 332}
 333
 334static void ams_disable_all_alarms(struct ams *ams)
 335{
 336	/* disable PS module alarm */
 337	if (ams->ps_base) {
 338		ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK,
 339				  AMS_REGCFG1_ALARM_MASK);
 340		ams_ps_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK,
 341				  AMS_REGCFG3_ALARM_MASK);
 342	}
 343
 344	/* disable PL module alarm */
 345	if (ams->pl_base) {
 346		ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK,
 347				  AMS_REGCFG1_ALARM_MASK);
 348		ams_pl_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK,
 349				  AMS_REGCFG3_ALARM_MASK);
 350	}
 351}
 352
 353static void ams_update_ps_alarm(struct ams *ams, unsigned long alarm_mask)
 354{
 355	u32 cfg;
 356	u32 val;
 357
 358	val = FIELD_GET(AMS_ISR0_ALARM_2_TO_0_MASK, alarm_mask);
 359	cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_2_TO_0_MASK, val));
 360
 361	val = FIELD_GET(AMS_ISR0_ALARM_6_TO_3_MASK, alarm_mask);
 362	cfg &= ~(FIELD_PREP(AMS_CONF1_ALARM_6_TO_3_MASK, val));
 363
 364	ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, cfg);
 365
 366	val = FIELD_GET(AMS_ISR0_ALARM_12_TO_7_MASK, alarm_mask);
 367	cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_12_TO_7_MASK, val));
 368	ams_ps_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, cfg);
 369}
 370
 371static void ams_update_pl_alarm(struct ams *ams, unsigned long alarm_mask)
 372{
 373	unsigned long pl_alarm_mask;
 374	u32 cfg;
 375	u32 val;
 376
 377	pl_alarm_mask = FIELD_GET(AMS_PL_ALARM_MASK, alarm_mask);
 378
 379	val = FIELD_GET(AMS_ISR0_ALARM_2_TO_0_MASK, pl_alarm_mask);
 380	cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_2_TO_0_MASK, val));
 381
 382	val = FIELD_GET(AMS_ISR0_ALARM_6_TO_3_MASK, pl_alarm_mask);
 383	cfg &= ~(FIELD_PREP(AMS_CONF1_ALARM_6_TO_3_MASK, val));
 384
 385	ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_REGCFG1_ALARM_MASK, cfg);
 386
 387	val = FIELD_GET(AMS_ISR0_ALARM_12_TO_7_MASK, pl_alarm_mask);
 388	cfg = ~(FIELD_PREP(AMS_CONF1_ALARM_12_TO_7_MASK, val));
 389	ams_pl_update_reg(ams, AMS_REG_CONFIG3, AMS_REGCFG3_ALARM_MASK, cfg);
 390}
 391
 392static void ams_unmask(struct ams *ams)
 393{
 394	unsigned int status, unmask;
 395
 396	status = readl(ams->base + AMS_ISR_0);
 397
 398	/* Clear those bits which are not active anymore */
 399	unmask = (ams->current_masked_alarm ^ status) & ams->current_masked_alarm;
 400
 401	/* Clear status of disabled alarm */
 402	unmask |= ams->intr_mask;
 403
 404	ams->current_masked_alarm &= status;
 405
 406	/* Also clear those which are masked out anyway */
 407	ams->current_masked_alarm &= ~ams->intr_mask;
 408
 409	/* Clear the interrupts before we unmask them */
 410	writel(unmask, ams->base + AMS_ISR_0);
 411
 412	ams_update_intrmask(ams, ~AMS_ALARM_MASK, ~AMS_ALARM_MASK);
 413}
 414
 415static void ams_update_alarm(struct ams *ams, unsigned long alarm_mask)
 416{
 417	unsigned long flags;
 418
 419	if (ams->ps_base)
 420		ams_update_ps_alarm(ams, alarm_mask);
 421
 422	if (ams->pl_base)
 423		ams_update_pl_alarm(ams, alarm_mask);
 424
 425	spin_lock_irqsave(&ams->intr_lock, flags);
 426	ams_update_intrmask(ams, AMS_ISR0_ALARM_MASK, ~alarm_mask);
 427	ams_unmask(ams);
 428	spin_unlock_irqrestore(&ams->intr_lock, flags);
 429}
 430
 431static void ams_enable_channel_sequence(struct iio_dev *indio_dev)
 432{
 433	struct ams *ams = iio_priv(indio_dev);
 434	unsigned long long scan_mask;
 435	int i;
 436	u32 regval;
 437
 438	/*
 439	 * Enable channel sequence. First 22 bits of scan_mask represent
 440	 * PS channels, and next remaining bits represent PL channels.
 441	 */
 442
 443	/* Run calibration of PS & PL as part of the sequence */
 444	scan_mask = BIT(0) | BIT(AMS_PS_SEQ_MAX);
 445	for (i = 0; i < indio_dev->num_channels; i++) {
 446		const struct iio_chan_spec *chan = &indio_dev->channels[i];
 447
 448		if (chan->scan_index < AMS_CTRL_SEQ_BASE)
 449			scan_mask |= BIT_ULL(chan->scan_index);
 450	}
 451
 452	if (ams->ps_base) {
 453		/* put sysmon in a soft reset to change the sequence */
 454		ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
 455				  AMS_CONF1_SEQ_DEFAULT);
 456
 457		/* configure basic channels */
 458		regval = FIELD_GET(AMS_REG_SEQ0_MASK, scan_mask);
 459		writel(regval, ams->ps_base + AMS_REG_SEQ_CH0);
 460
 461		regval = FIELD_GET(AMS_REG_SEQ2_MASK, scan_mask);
 462		writel(regval, ams->ps_base + AMS_REG_SEQ_CH2);
 463
 464		/* set continuous sequence mode */
 465		ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
 466				  AMS_CONF1_SEQ_CONTINUOUS);
 467	}
 468
 469	if (ams->pl_base) {
 470		/* put sysmon in a soft reset to change the sequence */
 471		ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
 472				  AMS_CONF1_SEQ_DEFAULT);
 473
 474		/* configure basic channels */
 475		scan_mask = FIELD_GET(AMS_PL_SEQ_MASK, scan_mask);
 476
 477		regval = FIELD_GET(AMS_REG_SEQ0_MASK, scan_mask);
 478		writel(regval, ams->pl_base + AMS_REG_SEQ_CH0);
 479
 480		regval = FIELD_GET(AMS_REG_SEQ1_MASK, scan_mask);
 481		writel(regval, ams->pl_base + AMS_REG_SEQ_CH1);
 482
 483		regval = FIELD_GET(AMS_REG_SEQ2_MASK, scan_mask);
 484		writel(regval, ams->pl_base + AMS_REG_SEQ_CH2);
 485
 486		/* set continuous sequence mode */
 487		ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
 488				  AMS_CONF1_SEQ_CONTINUOUS);
 489	}
 490}
 491
 492static int ams_init_device(struct ams *ams)
 493{
 494	u32 expect = AMS_PS_CSTS_PS_READY;
 495	u32 reg, value;
 496	int ret;
 497
 498	/* reset AMS */
 499	if (ams->ps_base) {
 500		writel(AMS_PS_RESET_VALUE, ams->ps_base + AMS_VP_VN);
 501
 502		ret = readl_poll_timeout(ams->base + AMS_PS_CSTS, reg, (reg & expect),
 503					 AMS_INIT_POLL_TIME_US, AMS_INIT_TIMEOUT_US);
 504		if (ret)
 505			return ret;
 506
 507		/* put sysmon in a default state */
 508		ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
 509				  AMS_CONF1_SEQ_DEFAULT);
 510	}
 511
 512	if (ams->pl_base) {
 513		value = readl(ams->base + AMS_PL_CSTS);
 514		if (value == 0)
 515			return 0;
 516
 517		writel(AMS_PL_RESET_VALUE, ams->pl_base + AMS_VP_VN);
 518
 519		/* put sysmon in a default state */
 520		ams_pl_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
 521				  AMS_CONF1_SEQ_DEFAULT);
 522	}
 523
 524	ams_disable_all_alarms(ams);
 525
 526	/* Disable interrupt */
 527	ams_update_intrmask(ams, AMS_ALARM_MASK, AMS_ALARM_MASK);
 528
 529	/* Clear any pending interrupt */
 530	writel(AMS_ISR0_ALARM_MASK, ams->base + AMS_ISR_0);
 531	writel(AMS_ISR1_ALARM_MASK, ams->base + AMS_ISR_1);
 532
 533	return 0;
 534}
 535
 536static int ams_read_label(struct iio_dev *indio_dev,
 537			  struct iio_chan_spec const *chan, char *label)
 538{
 539	return sysfs_emit(label, "%s\n", chan->datasheet_name);
 540}
 541
 542static int ams_enable_single_channel(struct ams *ams, unsigned int offset)
 543{
 544	u8 channel_num;
 545
 546	switch (offset) {
 547	case AMS_VCC_PSPLL0:
 548		channel_num = AMS_VCC_PSPLL0_CH;
 549		break;
 550	case AMS_VCC_PSPLL3:
 551		channel_num = AMS_VCC_PSPLL3_CH;
 552		break;
 553	case AMS_VCCINT:
 554		channel_num = AMS_VCCINT_CH;
 555		break;
 556	case AMS_VCCBRAM:
 557		channel_num = AMS_VCCBRAM_CH;
 558		break;
 559	case AMS_VCCAUX:
 560		channel_num = AMS_VCCAUX_CH;
 561		break;
 562	case AMS_PSDDRPLL:
 563		channel_num = AMS_PSDDRPLL_CH;
 564		break;
 565	case AMS_PSINTFPDDR:
 566		channel_num = AMS_PSINTFPDDR_CH;
 567		break;
 568	default:
 569		return -EINVAL;
 570	}
 571
 572	/* put sysmon in a soft reset to change the sequence */
 573	ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
 574			  AMS_CONF1_SEQ_DEFAULT);
 575
 576	/* write the channel number */
 577	ams_ps_update_reg(ams, AMS_REG_CONFIG0, AMS_CONF0_CHANNEL_NUM_MASK,
 578			  channel_num);
 579
 580	/* set single channel, sequencer off mode */
 581	ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
 582			  AMS_CONF1_SEQ_SINGLE_CHANNEL);
 583
 584	return 0;
 585}
 586
 587static int ams_read_vcc_reg(struct ams *ams, unsigned int offset, u32 *data)
 588{
 589	u32 expect = AMS_ISR1_EOC_MASK;
 590	u32 reg;
 591	int ret;
 592
 593	ret = ams_enable_single_channel(ams, offset);
 594	if (ret)
 595		return ret;
 596
 597	/* clear end-of-conversion flag, wait for next conversion to complete */
 598	writel(expect, ams->base + AMS_ISR_1);
 599	ret = readl_poll_timeout(ams->base + AMS_ISR_1, reg, (reg & expect),
 600				 AMS_INIT_POLL_TIME_US, AMS_INIT_TIMEOUT_US);
 601	if (ret)
 602		return ret;
 603
 604	*data = readl(ams->base + offset);
 605
 606	return 0;
 607}
 608
 609static int ams_get_ps_scale(int address)
 610{
 611	int val;
 612
 613	switch (address) {
 614	case AMS_SUPPLY1:
 615	case AMS_SUPPLY2:
 616	case AMS_SUPPLY3:
 617	case AMS_SUPPLY4:
 618	case AMS_SUPPLY9:
 619	case AMS_SUPPLY10:
 620	case AMS_VCCAMS:
 621		val = AMS_SUPPLY_SCALE_3VOLT_mV;
 622		break;
 623	case AMS_SUPPLY5:
 624	case AMS_SUPPLY6:
 625	case AMS_SUPPLY7:
 626	case AMS_SUPPLY8:
 627		val = AMS_SUPPLY_SCALE_6VOLT_mV;
 628		break;
 629	default:
 630		val = AMS_SUPPLY_SCALE_1VOLT_mV;
 631		break;
 632	}
 633
 634	return val;
 635}
 636
 637static int ams_get_pl_scale(struct ams *ams, int address)
 638{
 639	int val, regval;
 640
 641	switch (address) {
 642	case AMS_SUPPLY1:
 643	case AMS_SUPPLY2:
 644	case AMS_SUPPLY3:
 645	case AMS_SUPPLY4:
 646	case AMS_SUPPLY5:
 647	case AMS_SUPPLY6:
 648	case AMS_VCCAMS:
 649	case AMS_VREFP:
 650	case AMS_VREFN:
 651		val = AMS_SUPPLY_SCALE_3VOLT_mV;
 652		break;
 653	case AMS_SUPPLY7:
 654		regval = readl(ams->pl_base + AMS_REG_CONFIG4);
 655		if (FIELD_GET(AMS_VUSER0_MASK, regval))
 656			val = AMS_SUPPLY_SCALE_6VOLT_mV;
 657		else
 658			val = AMS_SUPPLY_SCALE_3VOLT_mV;
 659		break;
 660	case AMS_SUPPLY8:
 661		regval = readl(ams->pl_base + AMS_REG_CONFIG4);
 662		if (FIELD_GET(AMS_VUSER1_MASK, regval))
 663			val = AMS_SUPPLY_SCALE_6VOLT_mV;
 664		else
 665			val = AMS_SUPPLY_SCALE_3VOLT_mV;
 666		break;
 667	case AMS_SUPPLY9:
 668		regval = readl(ams->pl_base + AMS_REG_CONFIG4);
 669		if (FIELD_GET(AMS_VUSER2_MASK, regval))
 670			val = AMS_SUPPLY_SCALE_6VOLT_mV;
 671		else
 672			val = AMS_SUPPLY_SCALE_3VOLT_mV;
 673		break;
 674	case AMS_SUPPLY10:
 675		regval = readl(ams->pl_base + AMS_REG_CONFIG4);
 676		if (FIELD_GET(AMS_VUSER3_MASK, regval))
 677			val = AMS_SUPPLY_SCALE_6VOLT_mV;
 678		else
 679			val = AMS_SUPPLY_SCALE_3VOLT_mV;
 680		break;
 681	case AMS_VP_VN:
 682	case AMS_REG_VAUX(0) ... AMS_REG_VAUX(15):
 683		val = AMS_SUPPLY_SCALE_1VOLT_mV;
 684		break;
 685	default:
 686		val = AMS_SUPPLY_SCALE_1VOLT_mV;
 687		break;
 688	}
 689
 690	return val;
 691}
 692
 693static int ams_get_ctrl_scale(int address)
 694{
 695	int val;
 696
 697	switch (address) {
 698	case AMS_VCC_PSPLL0:
 699	case AMS_VCC_PSPLL3:
 700	case AMS_VCCINT:
 701	case AMS_VCCBRAM:
 702	case AMS_VCCAUX:
 703	case AMS_PSDDRPLL:
 704	case AMS_PSINTFPDDR:
 705		val = AMS_SUPPLY_SCALE_3VOLT_mV;
 706		break;
 707	default:
 708		val = AMS_SUPPLY_SCALE_1VOLT_mV;
 709		break;
 710	}
 711
 712	return val;
 713}
 714
 715static int ams_read_raw(struct iio_dev *indio_dev,
 716			struct iio_chan_spec const *chan,
 717			int *val, int *val2, long mask)
 718{
 719	struct ams *ams = iio_priv(indio_dev);
 720	int ret;
 721
 722	switch (mask) {
 723	case IIO_CHAN_INFO_RAW:
 724		mutex_lock(&ams->lock);
 725		if (chan->scan_index >= AMS_CTRL_SEQ_BASE) {
 726			ret = ams_read_vcc_reg(ams, chan->address, val);
 727			if (ret)
 728				goto unlock_mutex;
 729			ams_enable_channel_sequence(indio_dev);
 730		} else if (chan->scan_index >= AMS_PS_SEQ_MAX)
 731			*val = readl(ams->pl_base + chan->address);
 732		else
 733			*val = readl(ams->ps_base + chan->address);
 734
 735		ret = IIO_VAL_INT;
 736unlock_mutex:
 737		mutex_unlock(&ams->lock);
 738		return ret;
 739	case IIO_CHAN_INFO_SCALE:
 740		switch (chan->type) {
 741		case IIO_VOLTAGE:
 742			if (chan->scan_index < AMS_PS_SEQ_MAX)
 743				*val = ams_get_ps_scale(chan->address);
 744			else if (chan->scan_index >= AMS_PS_SEQ_MAX &&
 745				 chan->scan_index < AMS_CTRL_SEQ_BASE)
 746				*val = ams_get_pl_scale(ams, chan->address);
 747			else
 748				*val = ams_get_ctrl_scale(chan->address);
 749
 750			*val2 = AMS_SUPPLY_SCALE_DIV_BIT;
 751			return IIO_VAL_FRACTIONAL_LOG2;
 752		case IIO_TEMP:
 753			*val = AMS_TEMP_SCALE;
 754			*val2 = AMS_TEMP_SCALE_DIV_BIT;
 755			return IIO_VAL_FRACTIONAL_LOG2;
 756		default:
 757			return -EINVAL;
 758		}
 759	case IIO_CHAN_INFO_OFFSET:
 760		/* Only the temperature channel has an offset */
 761		*val = AMS_TEMP_OFFSET;
 762		return IIO_VAL_INT;
 763	default:
 764		return -EINVAL;
 765	}
 766}
 767
 768static int ams_get_alarm_offset(int scan_index, enum iio_event_direction dir)
 769{
 770	int offset;
 771
 772	if (scan_index >= AMS_PS_SEQ_MAX)
 773		scan_index -= AMS_PS_SEQ_MAX;
 774
 775	if (dir == IIO_EV_DIR_FALLING) {
 776		if (scan_index < AMS_SEQ_SUPPLY7)
 777			offset = AMS_ALARM_THRESHOLD_OFF_10;
 778		else
 779			offset = AMS_ALARM_THRESHOLD_OFF_20;
 780	} else {
 781		offset = 0;
 782	}
 783
 784	switch (scan_index) {
 785	case AMS_SEQ_TEMP:
 786		return AMS_ALARM_TEMP + offset;
 787	case AMS_SEQ_SUPPLY1:
 788		return AMS_ALARM_SUPPLY1 + offset;
 789	case AMS_SEQ_SUPPLY2:
 790		return AMS_ALARM_SUPPLY2 + offset;
 791	case AMS_SEQ_SUPPLY3:
 792		return AMS_ALARM_SUPPLY3 + offset;
 793	case AMS_SEQ_SUPPLY4:
 794		return AMS_ALARM_SUPPLY4 + offset;
 795	case AMS_SEQ_SUPPLY5:
 796		return AMS_ALARM_SUPPLY5 + offset;
 797	case AMS_SEQ_SUPPLY6:
 798		return AMS_ALARM_SUPPLY6 + offset;
 799	case AMS_SEQ_SUPPLY7:
 800		return AMS_ALARM_SUPPLY7 + offset;
 801	case AMS_SEQ_SUPPLY8:
 802		return AMS_ALARM_SUPPLY8 + offset;
 803	case AMS_SEQ_SUPPLY9:
 804		return AMS_ALARM_SUPPLY9 + offset;
 805	case AMS_SEQ_SUPPLY10:
 806		return AMS_ALARM_SUPPLY10 + offset;
 807	case AMS_SEQ_VCCAMS:
 808		return AMS_ALARM_VCCAMS + offset;
 809	case AMS_SEQ_TEMP_REMOTE:
 810		return AMS_ALARM_TEMP_REMOTE + offset;
 811	default:
 812		return 0;
 813	}
 814}
 815
 816static const struct iio_chan_spec *ams_event_to_channel(struct iio_dev *dev,
 817							u32 event)
 818{
 819	int scan_index = 0, i;
 820
 821	if (event >= AMS_PL_ALARM_START) {
 822		event -= AMS_PL_ALARM_START;
 823		scan_index = AMS_PS_SEQ_MAX;
 824	}
 825
 826	switch (event) {
 827	case AMS_ALARM_BIT_TEMP:
 828		scan_index += AMS_SEQ_TEMP;
 829		break;
 830	case AMS_ALARM_BIT_SUPPLY1:
 831		scan_index += AMS_SEQ_SUPPLY1;
 832		break;
 833	case AMS_ALARM_BIT_SUPPLY2:
 834		scan_index += AMS_SEQ_SUPPLY2;
 835		break;
 836	case AMS_ALARM_BIT_SUPPLY3:
 837		scan_index += AMS_SEQ_SUPPLY3;
 838		break;
 839	case AMS_ALARM_BIT_SUPPLY4:
 840		scan_index += AMS_SEQ_SUPPLY4;
 841		break;
 842	case AMS_ALARM_BIT_SUPPLY5:
 843		scan_index += AMS_SEQ_SUPPLY5;
 844		break;
 845	case AMS_ALARM_BIT_SUPPLY6:
 846		scan_index += AMS_SEQ_SUPPLY6;
 847		break;
 848	case AMS_ALARM_BIT_SUPPLY7:
 849		scan_index += AMS_SEQ_SUPPLY7;
 850		break;
 851	case AMS_ALARM_BIT_SUPPLY8:
 852		scan_index += AMS_SEQ_SUPPLY8;
 853		break;
 854	case AMS_ALARM_BIT_SUPPLY9:
 855		scan_index += AMS_SEQ_SUPPLY9;
 856		break;
 857	case AMS_ALARM_BIT_SUPPLY10:
 858		scan_index += AMS_SEQ_SUPPLY10;
 859		break;
 860	case AMS_ALARM_BIT_VCCAMS:
 861		scan_index += AMS_SEQ_VCCAMS;
 862		break;
 863	case AMS_ALARM_BIT_TEMP_REMOTE:
 864		scan_index += AMS_SEQ_TEMP_REMOTE;
 865		break;
 866	default:
 867		break;
 868	}
 869
 870	for (i = 0; i < dev->num_channels; i++)
 871		if (dev->channels[i].scan_index == scan_index)
 872			break;
 873
 874	return &dev->channels[i];
 875}
 876
 877static int ams_get_alarm_mask(int scan_index)
 878{
 879	int bit = 0;
 880
 881	if (scan_index >= AMS_PS_SEQ_MAX) {
 882		bit = AMS_PL_ALARM_START;
 883		scan_index -= AMS_PS_SEQ_MAX;
 884	}
 885
 886	switch (scan_index) {
 887	case AMS_SEQ_TEMP:
 888		return BIT(AMS_ALARM_BIT_TEMP + bit);
 889	case AMS_SEQ_SUPPLY1:
 890		return BIT(AMS_ALARM_BIT_SUPPLY1 + bit);
 891	case AMS_SEQ_SUPPLY2:
 892		return BIT(AMS_ALARM_BIT_SUPPLY2 + bit);
 893	case AMS_SEQ_SUPPLY3:
 894		return BIT(AMS_ALARM_BIT_SUPPLY3 + bit);
 895	case AMS_SEQ_SUPPLY4:
 896		return BIT(AMS_ALARM_BIT_SUPPLY4 + bit);
 897	case AMS_SEQ_SUPPLY5:
 898		return BIT(AMS_ALARM_BIT_SUPPLY5 + bit);
 899	case AMS_SEQ_SUPPLY6:
 900		return BIT(AMS_ALARM_BIT_SUPPLY6 + bit);
 901	case AMS_SEQ_SUPPLY7:
 902		return BIT(AMS_ALARM_BIT_SUPPLY7 + bit);
 903	case AMS_SEQ_SUPPLY8:
 904		return BIT(AMS_ALARM_BIT_SUPPLY8 + bit);
 905	case AMS_SEQ_SUPPLY9:
 906		return BIT(AMS_ALARM_BIT_SUPPLY9 + bit);
 907	case AMS_SEQ_SUPPLY10:
 908		return BIT(AMS_ALARM_BIT_SUPPLY10 + bit);
 909	case AMS_SEQ_VCCAMS:
 910		return BIT(AMS_ALARM_BIT_VCCAMS + bit);
 911	case AMS_SEQ_TEMP_REMOTE:
 912		return BIT(AMS_ALARM_BIT_TEMP_REMOTE + bit);
 913	default:
 914		return 0;
 915	}
 916}
 917
 918static int ams_read_event_config(struct iio_dev *indio_dev,
 919				 const struct iio_chan_spec *chan,
 920				 enum iio_event_type type,
 921				 enum iio_event_direction dir)
 922{
 923	struct ams *ams = iio_priv(indio_dev);
 924
 925	return !!(ams->alarm_mask & ams_get_alarm_mask(chan->scan_index));
 926}
 927
 928static int ams_write_event_config(struct iio_dev *indio_dev,
 929				  const struct iio_chan_spec *chan,
 930				  enum iio_event_type type,
 931				  enum iio_event_direction dir,
 932				  bool state)
 933{
 934	struct ams *ams = iio_priv(indio_dev);
 935	unsigned int alarm;
 936
 937	alarm = ams_get_alarm_mask(chan->scan_index);
 938
 939	mutex_lock(&ams->lock);
 940
 941	if (state)
 942		ams->alarm_mask |= alarm;
 943	else
 944		ams->alarm_mask &= ~alarm;
 945
 946	ams_update_alarm(ams, ams->alarm_mask);
 947
 948	mutex_unlock(&ams->lock);
 949
 950	return 0;
 951}
 952
 953static int ams_read_event_value(struct iio_dev *indio_dev,
 954				const struct iio_chan_spec *chan,
 955				enum iio_event_type type,
 956				enum iio_event_direction dir,
 957				enum iio_event_info info, int *val, int *val2)
 958{
 959	struct ams *ams = iio_priv(indio_dev);
 960	unsigned int offset = ams_get_alarm_offset(chan->scan_index, dir);
 961
 962	mutex_lock(&ams->lock);
 963
 964	if (chan->scan_index >= AMS_PS_SEQ_MAX)
 965		*val = readl(ams->pl_base + offset);
 966	else
 967		*val = readl(ams->ps_base + offset);
 968
 969	mutex_unlock(&ams->lock);
 970
 971	return IIO_VAL_INT;
 972}
 973
 974static int ams_write_event_value(struct iio_dev *indio_dev,
 975				 const struct iio_chan_spec *chan,
 976				 enum iio_event_type type,
 977				 enum iio_event_direction dir,
 978				 enum iio_event_info info, int val, int val2)
 979{
 980	struct ams *ams = iio_priv(indio_dev);
 981	unsigned int offset;
 982
 983	mutex_lock(&ams->lock);
 984
 985	/* Set temperature channel threshold to direct threshold */
 986	if (chan->type == IIO_TEMP) {
 987		offset = ams_get_alarm_offset(chan->scan_index, IIO_EV_DIR_FALLING);
 988
 989		if (chan->scan_index >= AMS_PS_SEQ_MAX)
 990			ams_pl_update_reg(ams, offset,
 991					  AMS_ALARM_THR_DIRECT_MASK,
 992					  AMS_ALARM_THR_DIRECT_MASK);
 993		else
 994			ams_ps_update_reg(ams, offset,
 995					  AMS_ALARM_THR_DIRECT_MASK,
 996					  AMS_ALARM_THR_DIRECT_MASK);
 997	}
 998
 999	offset = ams_get_alarm_offset(chan->scan_index, dir);
1000	if (chan->scan_index >= AMS_PS_SEQ_MAX)
1001		writel(val, ams->pl_base + offset);
1002	else
1003		writel(val, ams->ps_base + offset);
1004
1005	mutex_unlock(&ams->lock);
1006
1007	return 0;
1008}
1009
1010static void ams_handle_event(struct iio_dev *indio_dev, u32 event)
1011{
1012	const struct iio_chan_spec *chan;
1013
1014	chan = ams_event_to_channel(indio_dev, event);
1015
1016	if (chan->type == IIO_TEMP) {
1017		/*
1018		 * The temperature channel only supports over-temperature
1019		 * events.
1020		 */
1021		iio_push_event(indio_dev,
1022			       IIO_UNMOD_EVENT_CODE(chan->type, chan->channel,
1023						    IIO_EV_TYPE_THRESH,
1024						    IIO_EV_DIR_RISING),
1025			       iio_get_time_ns(indio_dev));
1026	} else {
1027		/*
1028		 * For other channels we don't know whether it is a upper or
1029		 * lower threshold event. Userspace will have to check the
1030		 * channel value if it wants to know.
1031		 */
1032		iio_push_event(indio_dev,
1033			       IIO_UNMOD_EVENT_CODE(chan->type, chan->channel,
1034						    IIO_EV_TYPE_THRESH,
1035						    IIO_EV_DIR_EITHER),
1036			       iio_get_time_ns(indio_dev));
1037	}
1038}
1039
1040static void ams_handle_events(struct iio_dev *indio_dev, unsigned long events)
1041{
1042	unsigned int bit;
1043
1044	for_each_set_bit(bit, &events, AMS_NO_OF_ALARMS)
1045		ams_handle_event(indio_dev, bit);
1046}
1047
1048/**
1049 * ams_unmask_worker - ams alarm interrupt unmask worker
1050 * @work: work to be done
1051 *
1052 * The ZynqMP threshold interrupts are level sensitive. Since we can't make the
1053 * threshold condition go way from within the interrupt handler, this means as
1054 * soon as a threshold condition is present we would enter the interrupt handler
1055 * again and again. To work around this we mask all active threshold interrupts
1056 * in the interrupt handler and start a timer. In this timer we poll the
1057 * interrupt status and only if the interrupt is inactive we unmask it again.
1058 */
1059static void ams_unmask_worker(struct work_struct *work)
1060{
1061	struct ams *ams = container_of(work, struct ams, ams_unmask_work.work);
1062
1063	spin_lock_irq(&ams->intr_lock);
1064	ams_unmask(ams);
1065	spin_unlock_irq(&ams->intr_lock);
1066
1067	/* If still pending some alarm re-trigger the timer */
1068	if (ams->current_masked_alarm)
1069		schedule_delayed_work(&ams->ams_unmask_work,
1070				      msecs_to_jiffies(AMS_UNMASK_TIMEOUT_MS));
1071}
1072
1073static irqreturn_t ams_irq(int irq, void *data)
1074{
1075	struct iio_dev *indio_dev = data;
1076	struct ams *ams = iio_priv(indio_dev);
1077	u32 isr0;
1078
1079	spin_lock(&ams->intr_lock);
1080
1081	isr0 = readl(ams->base + AMS_ISR_0);
1082
1083	/* Only process alarms that are not masked */
1084	isr0 &= ~((ams->intr_mask & AMS_ISR0_ALARM_MASK) | ams->current_masked_alarm);
1085	if (!isr0) {
1086		spin_unlock(&ams->intr_lock);
1087		return IRQ_NONE;
1088	}
1089
1090	/* Clear interrupt */
1091	writel(isr0, ams->base + AMS_ISR_0);
1092
1093	/* Mask the alarm interrupts until cleared */
1094	ams->current_masked_alarm |= isr0;
1095	ams_update_intrmask(ams, ~AMS_ALARM_MASK, ~AMS_ALARM_MASK);
1096
1097	ams_handle_events(indio_dev, isr0);
1098
1099	schedule_delayed_work(&ams->ams_unmask_work,
1100			      msecs_to_jiffies(AMS_UNMASK_TIMEOUT_MS));
1101
1102	spin_unlock(&ams->intr_lock);
1103
1104	return IRQ_HANDLED;
1105}
1106
1107static const struct iio_event_spec ams_temp_events[] = {
1108	{
1109		.type = IIO_EV_TYPE_THRESH,
1110		.dir = IIO_EV_DIR_RISING,
1111		.mask_separate = BIT(IIO_EV_INFO_ENABLE) | BIT(IIO_EV_INFO_VALUE),
1112	},
1113};
1114
1115static const struct iio_event_spec ams_voltage_events[] = {
1116	{
1117		.type = IIO_EV_TYPE_THRESH,
1118		.dir = IIO_EV_DIR_RISING,
1119		.mask_separate = BIT(IIO_EV_INFO_VALUE),
1120	},
1121	{
1122		.type = IIO_EV_TYPE_THRESH,
1123		.dir = IIO_EV_DIR_FALLING,
1124		.mask_separate = BIT(IIO_EV_INFO_VALUE),
1125	},
1126	{
1127		.type = IIO_EV_TYPE_THRESH,
1128		.dir = IIO_EV_DIR_EITHER,
1129		.mask_separate = BIT(IIO_EV_INFO_ENABLE),
1130	},
1131};
1132
1133static const struct iio_chan_spec ams_ps_channels[] = {
1134	AMS_PS_CHAN_TEMP(AMS_SEQ_TEMP, AMS_TEMP, "Temp_LPD"),
1135	AMS_PS_CHAN_TEMP(AMS_SEQ_TEMP_REMOTE, AMS_TEMP_REMOTE, "Temp_FPD"),
1136	AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY1, AMS_SUPPLY1, "VCC_PSINTLP"),
1137	AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY2, AMS_SUPPLY2, "VCC_PSINTFP"),
1138	AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY3, AMS_SUPPLY3, "VCC_PSAUX"),
1139	AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY4, AMS_SUPPLY4, "VCC_PSDDR"),
1140	AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY5, AMS_SUPPLY5, "VCC_PSIO3"),
1141	AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY6, AMS_SUPPLY6, "VCC_PSIO0"),
1142	AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY7, AMS_SUPPLY7, "VCC_PSIO1"),
1143	AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY8, AMS_SUPPLY8, "VCC_PSIO2"),
1144	AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY9, AMS_SUPPLY9, "PS_MGTRAVCC"),
1145	AMS_PS_CHAN_VOLTAGE(AMS_SEQ_SUPPLY10, AMS_SUPPLY10, "PS_MGTRAVTT"),
1146	AMS_PS_CHAN_VOLTAGE(AMS_SEQ_VCCAMS, AMS_VCCAMS, "VCC_PSADC"),
1147};
1148
1149static const struct iio_chan_spec ams_pl_channels[] = {
1150	AMS_PL_CHAN_TEMP(AMS_SEQ_TEMP, AMS_TEMP, "Temp_PL"),
1151	AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY1, AMS_SUPPLY1, true, "VCCINT"),
1152	AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY2, AMS_SUPPLY2, true, "VCCAUX"),
1153	AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VREFP, AMS_VREFP, false, "VREFP"),
1154	AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VREFN, AMS_VREFN, false, "VREFN"),
1155	AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY3, AMS_SUPPLY3, true, "VCCBRAM"),
1156	AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY4, AMS_SUPPLY4, true, "VCC_PSINTLP"),
1157	AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY5, AMS_SUPPLY5, true, "VCC_PSINTFP"),
1158	AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY6, AMS_SUPPLY6, true, "VCC_PSAUX"),
1159	AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VCCAMS, AMS_VCCAMS, true, "VCCAMS"),
1160	AMS_PL_CHAN_VOLTAGE(AMS_SEQ_VP_VN, AMS_VP_VN, false, "VP_VN"),
1161	AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY7, AMS_SUPPLY7, true, "VUser0"),
1162	AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY8, AMS_SUPPLY8, true, "VUser1"),
1163	AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY9, AMS_SUPPLY9, true, "VUser2"),
1164	AMS_PL_CHAN_VOLTAGE(AMS_SEQ_SUPPLY10, AMS_SUPPLY10, true, "VUser3"),
1165	AMS_PL_AUX_CHAN_VOLTAGE(0),
1166	AMS_PL_AUX_CHAN_VOLTAGE(1),
1167	AMS_PL_AUX_CHAN_VOLTAGE(2),
1168	AMS_PL_AUX_CHAN_VOLTAGE(3),
1169	AMS_PL_AUX_CHAN_VOLTAGE(4),
1170	AMS_PL_AUX_CHAN_VOLTAGE(5),
1171	AMS_PL_AUX_CHAN_VOLTAGE(6),
1172	AMS_PL_AUX_CHAN_VOLTAGE(7),
1173	AMS_PL_AUX_CHAN_VOLTAGE(8),
1174	AMS_PL_AUX_CHAN_VOLTAGE(9),
1175	AMS_PL_AUX_CHAN_VOLTAGE(10),
1176	AMS_PL_AUX_CHAN_VOLTAGE(11),
1177	AMS_PL_AUX_CHAN_VOLTAGE(12),
1178	AMS_PL_AUX_CHAN_VOLTAGE(13),
1179	AMS_PL_AUX_CHAN_VOLTAGE(14),
1180	AMS_PL_AUX_CHAN_VOLTAGE(15),
1181};
1182
1183static const struct iio_chan_spec ams_ctrl_channels[] = {
1184	AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCC_PSPLL, AMS_VCC_PSPLL0, "VCC_PSPLL"),
1185	AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCC_PSBATT, AMS_VCC_PSPLL3, "VCC_PSBATT"),
1186	AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCCINT, AMS_VCCINT, "VCCINT"),
1187	AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCCBRAM, AMS_VCCBRAM, "VCCBRAM"),
1188	AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_VCCAUX, AMS_VCCAUX, "VCCAUX"),
1189	AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_PSDDRPLL, AMS_PSDDRPLL, "VCC_PSDDR_PLL"),
1190	AMS_CTRL_CHAN_VOLTAGE(AMS_SEQ_INTDDR, AMS_PSINTFPDDR, "VCC_PSINTFP_DDR"),
1191};
1192
1193static int ams_get_ext_chan(struct fwnode_handle *chan_node,
1194			    struct iio_chan_spec *channels, int num_channels)
1195{
1196	struct iio_chan_spec *chan;
1197	struct fwnode_handle *child;
1198	unsigned int reg, ext_chan;
1199	int ret;
1200
1201	fwnode_for_each_child_node(chan_node, child) {
1202		ret = fwnode_property_read_u32(child, "reg", &reg);
1203		if (ret || reg > AMS_PL_MAX_EXT_CHANNEL + 30)
1204			continue;
1205
1206		chan = &channels[num_channels];
1207		ext_chan = reg + AMS_PL_MAX_FIXED_CHANNEL - 30;
1208		memcpy(chan, &ams_pl_channels[ext_chan], sizeof(*channels));
1209
1210		if (fwnode_property_read_bool(child, "xlnx,bipolar"))
1211			chan->scan_type.sign = 's';
1212
1213		num_channels++;
1214	}
1215
1216	return num_channels;
1217}
1218
1219static void ams_iounmap_ps(void *data)
1220{
1221	struct ams *ams = data;
1222
1223	iounmap(ams->ps_base);
1224}
1225
1226static void ams_iounmap_pl(void *data)
1227{
1228	struct ams *ams = data;
1229
1230	iounmap(ams->pl_base);
1231}
1232
1233static int ams_init_module(struct iio_dev *indio_dev,
1234			   struct fwnode_handle *fwnode,
1235			   struct iio_chan_spec *channels)
1236{
1237	struct device *dev = indio_dev->dev.parent;
1238	struct ams *ams = iio_priv(indio_dev);
1239	int num_channels = 0;
1240	int ret;
1241
1242	if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams-ps")) {
1243		ams->ps_base = fwnode_iomap(fwnode, 0);
1244		if (!ams->ps_base)
1245			return -ENXIO;
1246		ret = devm_add_action_or_reset(dev, ams_iounmap_ps, ams);
1247		if (ret < 0)
1248			return ret;
1249
1250		/* add PS channels to iio device channels */
1251		memcpy(channels, ams_ps_channels, sizeof(ams_ps_channels));
1252		num_channels = ARRAY_SIZE(ams_ps_channels);
1253	} else if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams-pl")) {
1254		ams->pl_base = fwnode_iomap(fwnode, 0);
1255		if (!ams->pl_base)
1256			return -ENXIO;
1257
1258		ret = devm_add_action_or_reset(dev, ams_iounmap_pl, ams);
1259		if (ret < 0)
1260			return ret;
1261
1262		/* Copy only first 10 fix channels */
1263		memcpy(channels, ams_pl_channels, AMS_PL_MAX_FIXED_CHANNEL * sizeof(*channels));
1264		num_channels += AMS_PL_MAX_FIXED_CHANNEL;
1265		num_channels = ams_get_ext_chan(fwnode, channels,
1266						num_channels);
1267	} else if (fwnode_device_is_compatible(fwnode, "xlnx,zynqmp-ams")) {
1268		/* add AMS channels to iio device channels */
1269		memcpy(channels, ams_ctrl_channels, sizeof(ams_ctrl_channels));
1270		num_channels += ARRAY_SIZE(ams_ctrl_channels);
1271	} else {
1272		return -EINVAL;
1273	}
1274
1275	return num_channels;
1276}
1277
1278static int ams_parse_firmware(struct iio_dev *indio_dev)
1279{
1280	struct ams *ams = iio_priv(indio_dev);
1281	struct iio_chan_spec *ams_channels, *dev_channels;
1282	struct device *dev = indio_dev->dev.parent;
1283	struct fwnode_handle *fwnode = dev_fwnode(dev);
1284	size_t ams_size;
1285	int ret, ch_cnt = 0, i, rising_off, falling_off;
1286	unsigned int num_channels = 0;
1287
1288	ams_size = ARRAY_SIZE(ams_ps_channels) + ARRAY_SIZE(ams_pl_channels) +
1289		ARRAY_SIZE(ams_ctrl_channels);
1290
1291	/* Initialize buffer for channel specification */
1292	ams_channels = devm_kcalloc(dev, ams_size, sizeof(*ams_channels), GFP_KERNEL);
1293	if (!ams_channels)
1294		return -ENOMEM;
1295
1296	if (fwnode_device_is_available(fwnode)) {
1297		ret = ams_init_module(indio_dev, fwnode, ams_channels);
1298		if (ret < 0)
1299			return ret;
1300
1301		num_channels += ret;
1302	}
1303
1304	device_for_each_child_node_scoped(dev, child) {
1305		ret = ams_init_module(indio_dev, child, ams_channels + num_channels);
1306		if (ret < 0)
1307			return ret;
1308
1309		num_channels += ret;
1310	}
1311
1312	for (i = 0; i < num_channels; i++) {
1313		ams_channels[i].channel = ch_cnt++;
1314
1315		if (ams_channels[i].scan_index < AMS_CTRL_SEQ_BASE) {
1316			/* set threshold to max and min for each channel */
1317			falling_off =
1318				ams_get_alarm_offset(ams_channels[i].scan_index,
1319						     IIO_EV_DIR_FALLING);
1320			rising_off =
1321				ams_get_alarm_offset(ams_channels[i].scan_index,
1322						     IIO_EV_DIR_RISING);
1323			if (ams_channels[i].scan_index >= AMS_PS_SEQ_MAX) {
1324				writel(AMS_ALARM_THR_MIN,
1325				       ams->pl_base + falling_off);
1326				writel(AMS_ALARM_THR_MAX,
1327				       ams->pl_base + rising_off);
1328			} else {
1329				writel(AMS_ALARM_THR_MIN,
1330				       ams->ps_base + falling_off);
1331				writel(AMS_ALARM_THR_MAX,
1332				       ams->ps_base + rising_off);
1333			}
1334		}
1335	}
1336
1337	dev_channels = devm_krealloc_array(dev, ams_channels, num_channels,
1338					   sizeof(*dev_channels), GFP_KERNEL);
1339	if (!dev_channels)
1340		return -ENOMEM;
1341
1342	indio_dev->channels = dev_channels;
1343	indio_dev->num_channels = num_channels;
1344
1345	return 0;
1346}
1347
1348static const struct iio_info iio_ams_info = {
1349	.read_label = ams_read_label,
1350	.read_raw = &ams_read_raw,
1351	.read_event_config = &ams_read_event_config,
1352	.write_event_config = &ams_write_event_config,
1353	.read_event_value = &ams_read_event_value,
1354	.write_event_value = &ams_write_event_value,
1355};
1356
1357static const struct of_device_id ams_of_match_table[] = {
1358	{ .compatible = "xlnx,zynqmp-ams" },
1359	{ }
1360};
1361MODULE_DEVICE_TABLE(of, ams_of_match_table);
1362
1363static int ams_probe(struct platform_device *pdev)
1364{
1365	struct iio_dev *indio_dev;
1366	struct ams *ams;
1367	int ret;
1368	int irq;
1369
1370	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*ams));
1371	if (!indio_dev)
1372		return -ENOMEM;
1373
1374	ams = iio_priv(indio_dev);
1375	mutex_init(&ams->lock);
1376	spin_lock_init(&ams->intr_lock);
1377
1378	indio_dev->name = "xilinx-ams";
1379
1380	indio_dev->info = &iio_ams_info;
1381	indio_dev->modes = INDIO_DIRECT_MODE;
1382
1383	ams->base = devm_platform_ioremap_resource(pdev, 0);
1384	if (IS_ERR(ams->base))
1385		return PTR_ERR(ams->base);
1386
1387	ams->clk = devm_clk_get_enabled(&pdev->dev, NULL);
1388	if (IS_ERR(ams->clk))
1389		return PTR_ERR(ams->clk);
1390
1391	ret = devm_delayed_work_autocancel(&pdev->dev, &ams->ams_unmask_work,
1392					   ams_unmask_worker);
1393	if (ret < 0)
1394		return ret;
1395
1396	ret = ams_parse_firmware(indio_dev);
1397	if (ret)
1398		return dev_err_probe(&pdev->dev, ret, "failure in parsing DT\n");
1399
1400	ret = ams_init_device(ams);
1401	if (ret)
1402		return dev_err_probe(&pdev->dev, ret, "failed to initialize AMS\n");
1403
1404	ams_enable_channel_sequence(indio_dev);
1405
1406	irq = platform_get_irq(pdev, 0);
1407	if (irq < 0)
1408		return irq;
1409
1410	ret = devm_request_irq(&pdev->dev, irq, &ams_irq, 0, "ams-irq",
1411			       indio_dev);
1412	if (ret < 0)
1413		return dev_err_probe(&pdev->dev, ret, "failed to register interrupt\n");
1414
1415	platform_set_drvdata(pdev, indio_dev);
1416
1417	return devm_iio_device_register(&pdev->dev, indio_dev);
1418}
1419
1420static int ams_suspend(struct device *dev)
1421{
1422	struct ams *ams = iio_priv(dev_get_drvdata(dev));
1423
1424	clk_disable_unprepare(ams->clk);
1425
1426	return 0;
1427}
1428
1429static int ams_resume(struct device *dev)
1430{
1431	struct ams *ams = iio_priv(dev_get_drvdata(dev));
1432
1433	return clk_prepare_enable(ams->clk);
1434}
1435
1436static DEFINE_SIMPLE_DEV_PM_OPS(ams_pm_ops, ams_suspend, ams_resume);
1437
1438static struct platform_driver ams_driver = {
1439	.probe = ams_probe,
1440	.driver = {
1441		.name = "xilinx-ams",
1442		.pm = pm_sleep_ptr(&ams_pm_ops),
1443		.of_match_table = ams_of_match_table,
1444	},
1445};
1446module_platform_driver(ams_driver);
1447
1448MODULE_DESCRIPTION("Xilinx AMS driver");
1449MODULE_LICENSE("GPL v2");
1450MODULE_AUTHOR("Xilinx, Inc.");