ti-ads8688.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (C) 2015 Prevas A/S
  4 */
  5
  6#include <linux/device.h>
  7#include <linux/kernel.h>
  8#include <linux/slab.h>
  9#include <linux/sysfs.h>
 10#include <linux/spi/spi.h>
 11#include <linux/regulator/consumer.h>
 12#include <linux/err.h>
 13#include <linux/module.h>
 14#include <linux/mod_devicetable.h>
 15
 16#include <linux/iio/iio.h>
 17#include <linux/iio/buffer.h>
 18#include <linux/iio/trigger_consumer.h>
 19#include <linux/iio/triggered_buffer.h>
 20#include <linux/iio/sysfs.h>
 21
 22#define ADS8688_CMD_REG(x)		(x << 8)
 23#define ADS8688_CMD_REG_NOOP		0x00
 24#define ADS8688_CMD_REG_RST		0x85
 25#define ADS8688_CMD_REG_MAN_CH(chan)	(0xC0 | (4 * chan))
 26#define ADS8688_CMD_DONT_CARE_BITS	16
 27
 28#define ADS8688_PROG_REG(x)		(x << 9)
 29#define ADS8688_PROG_REG_RANGE_CH(chan)	(0x05 + chan)
 30#define ADS8688_PROG_WR_BIT		BIT(8)
 31#define ADS8688_PROG_DONT_CARE_BITS	8
 32
 33#define ADS8688_REG_PLUSMINUS25VREF	0
 34#define ADS8688_REG_PLUSMINUS125VREF	1
 35#define ADS8688_REG_PLUSMINUS0625VREF	2
 36#define ADS8688_REG_PLUS25VREF		5
 37#define ADS8688_REG_PLUS125VREF		6
 38
 39#define ADS8688_VREF_MV			4096
 40#define ADS8688_REALBITS		16
 41#define ADS8688_MAX_CHANNELS		8
 42
 43/*
 44 * enum ads8688_range - ADS8688 reference voltage range
 45 * @ADS8688_PLUSMINUS25VREF: Device is configured for input range ±2.5 * VREF
 46 * @ADS8688_PLUSMINUS125VREF: Device is configured for input range ±1.25 * VREF
 47 * @ADS8688_PLUSMINUS0625VREF: Device is configured for input range ±0.625 * VREF
 48 * @ADS8688_PLUS25VREF: Device is configured for input range 0 - 2.5 * VREF
 49 * @ADS8688_PLUS125VREF: Device is configured for input range 0 - 1.25 * VREF
 50 */
 51enum ads8688_range {
 52	ADS8688_PLUSMINUS25VREF,
 53	ADS8688_PLUSMINUS125VREF,
 54	ADS8688_PLUSMINUS0625VREF,
 55	ADS8688_PLUS25VREF,
 56	ADS8688_PLUS125VREF,
 57};
 58
 59struct ads8688_chip_info {
 60	const struct iio_chan_spec *channels;
 61	unsigned int num_channels;
 62};
 63
 64struct ads8688_state {
 65	struct mutex			lock;
 66	const struct ads8688_chip_info	*chip_info;
 67	struct spi_device		*spi;
 68	unsigned int			vref_mv;
 69	enum ads8688_range		range[8];
 70	union {
 71		__be32 d32;
 72		u8 d8[4];
 73	} data[2] __aligned(IIO_DMA_MINALIGN);
 74};
 75
 76enum ads8688_id {
 77	ID_ADS8684,
 78	ID_ADS8688,
 79};
 80
 81struct ads8688_ranges {
 82	enum ads8688_range range;
 83	unsigned int scale;
 84	int offset;
 85	u8 reg;
 86};
 87
 88static const struct ads8688_ranges ads8688_range_def[5] = {
 89	{
 90		.range = ADS8688_PLUSMINUS25VREF,
 91		.scale = 76295,
 92		.offset = -(1 << (ADS8688_REALBITS - 1)),
 93		.reg = ADS8688_REG_PLUSMINUS25VREF,
 94	}, {
 95		.range = ADS8688_PLUSMINUS125VREF,
 96		.scale = 38148,
 97		.offset = -(1 << (ADS8688_REALBITS - 1)),
 98		.reg = ADS8688_REG_PLUSMINUS125VREF,
 99	}, {
100		.range = ADS8688_PLUSMINUS0625VREF,
101		.scale = 19074,
102		.offset = -(1 << (ADS8688_REALBITS - 1)),
103		.reg = ADS8688_REG_PLUSMINUS0625VREF,
104	}, {
105		.range = ADS8688_PLUS25VREF,
106		.scale = 38148,
107		.offset = 0,
108		.reg = ADS8688_REG_PLUS25VREF,
109	}, {
110		.range = ADS8688_PLUS125VREF,
111		.scale = 19074,
112		.offset = 0,
113		.reg = ADS8688_REG_PLUS125VREF,
114	}
115};
116
117static ssize_t ads8688_show_scales(struct device *dev,
118				   struct device_attribute *attr, char *buf)
119{
120	struct ads8688_state *st = iio_priv(dev_to_iio_dev(dev));
121
122	return sprintf(buf, "0.%09u 0.%09u 0.%09u\n",
123		       ads8688_range_def[0].scale * st->vref_mv,
124		       ads8688_range_def[1].scale * st->vref_mv,
125		       ads8688_range_def[2].scale * st->vref_mv);
126}
127
128static ssize_t ads8688_show_offsets(struct device *dev,
129				    struct device_attribute *attr, char *buf)
130{
131	return sprintf(buf, "%d %d\n", ads8688_range_def[0].offset,
132		       ads8688_range_def[3].offset);
133}
134
135static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO,
136		       ads8688_show_scales, NULL, 0);
137static IIO_DEVICE_ATTR(in_voltage_offset_available, S_IRUGO,
138		       ads8688_show_offsets, NULL, 0);
139
140static struct attribute *ads8688_attributes[] = {
141	&iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
142	&iio_dev_attr_in_voltage_offset_available.dev_attr.attr,
143	NULL,
144};
145
146static const struct attribute_group ads8688_attribute_group = {
147	.attrs = ads8688_attributes,
148};
149
150#define ADS8688_CHAN(index)					\
151{								\
152	.type = IIO_VOLTAGE,					\
153	.indexed = 1,						\
154	.channel = index,					\
155	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW)		\
156			      | BIT(IIO_CHAN_INFO_SCALE)	\
157			      | BIT(IIO_CHAN_INFO_OFFSET),	\
158	.scan_index = index,					\
159	.scan_type = {						\
160		.sign = 'u',					\
161		.realbits = 16,					\
162		.storagebits = 16,				\
163		.endianness = IIO_BE,				\
164	},							\
165}
166
167static const struct iio_chan_spec ads8684_channels[] = {
168	ADS8688_CHAN(0),
169	ADS8688_CHAN(1),
170	ADS8688_CHAN(2),
171	ADS8688_CHAN(3),
172};
173
174static const struct iio_chan_spec ads8688_channels[] = {
175	ADS8688_CHAN(0),
176	ADS8688_CHAN(1),
177	ADS8688_CHAN(2),
178	ADS8688_CHAN(3),
179	ADS8688_CHAN(4),
180	ADS8688_CHAN(5),
181	ADS8688_CHAN(6),
182	ADS8688_CHAN(7),
183};
184
185static int ads8688_prog_write(struct iio_dev *indio_dev, unsigned int addr,
186			      unsigned int val)
187{
188	struct ads8688_state *st = iio_priv(indio_dev);
189	u32 tmp;
190
191	tmp = ADS8688_PROG_REG(addr) | ADS8688_PROG_WR_BIT | val;
192	tmp <<= ADS8688_PROG_DONT_CARE_BITS;
193	st->data[0].d32 = cpu_to_be32(tmp);
194
195	return spi_write(st->spi, &st->data[0].d8[1], 3);
196}
197
198static int ads8688_reset(struct iio_dev *indio_dev)
199{
200	struct ads8688_state *st = iio_priv(indio_dev);
201	u32 tmp;
202
203	tmp = ADS8688_CMD_REG(ADS8688_CMD_REG_RST);
204	tmp <<= ADS8688_CMD_DONT_CARE_BITS;
205	st->data[0].d32 = cpu_to_be32(tmp);
206
207	return spi_write(st->spi, &st->data[0].d8[0], 4);
208}
209
210static int ads8688_read(struct iio_dev *indio_dev, unsigned int chan)
211{
212	struct ads8688_state *st = iio_priv(indio_dev);
213	int ret;
214	u32 tmp;
215	struct spi_transfer t[] = {
216		{
217			.tx_buf = &st->data[0].d8[0],
218			.len = 4,
219			.cs_change = 1,
220		}, {
221			.tx_buf = &st->data[1].d8[0],
222			.rx_buf = &st->data[1].d8[0],
223			.len = 4,
224		},
225	};
226
227	tmp = ADS8688_CMD_REG(ADS8688_CMD_REG_MAN_CH(chan));
228	tmp <<= ADS8688_CMD_DONT_CARE_BITS;
229	st->data[0].d32 = cpu_to_be32(tmp);
230
231	tmp = ADS8688_CMD_REG(ADS8688_CMD_REG_NOOP);
232	tmp <<= ADS8688_CMD_DONT_CARE_BITS;
233	st->data[1].d32 = cpu_to_be32(tmp);
234
235	ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t));
236	if (ret < 0)
237		return ret;
238
239	return be32_to_cpu(st->data[1].d32) & 0xffff;
240}
241
242static int ads8688_read_raw(struct iio_dev *indio_dev,
243			    struct iio_chan_spec const *chan,
244			    int *val, int *val2, long m)
245{
246	int ret, offset;
247	unsigned long scale_mv;
248
249	struct ads8688_state *st = iio_priv(indio_dev);
250
251	mutex_lock(&st->lock);
252	switch (m) {
253	case IIO_CHAN_INFO_RAW:
254		ret = ads8688_read(indio_dev, chan->channel);
255		mutex_unlock(&st->lock);
256		if (ret < 0)
257			return ret;
258		*val = ret;
259		return IIO_VAL_INT;
260	case IIO_CHAN_INFO_SCALE:
261		scale_mv = st->vref_mv;
262		scale_mv *= ads8688_range_def[st->range[chan->channel]].scale;
263		*val = 0;
264		*val2 = scale_mv;
265		mutex_unlock(&st->lock);
266		return IIO_VAL_INT_PLUS_NANO;
267	case IIO_CHAN_INFO_OFFSET:
268		offset = ads8688_range_def[st->range[chan->channel]].offset;
269		*val = offset;
270		mutex_unlock(&st->lock);
271		return IIO_VAL_INT;
272	}
273	mutex_unlock(&st->lock);
274
275	return -EINVAL;
276}
277
278static int ads8688_write_reg_range(struct iio_dev *indio_dev,
279				   struct iio_chan_spec const *chan,
280				   enum ads8688_range range)
281{
282	unsigned int tmp;
283
284	tmp = ADS8688_PROG_REG_RANGE_CH(chan->channel);
285
286	return ads8688_prog_write(indio_dev, tmp, range);
287}
288
289static int ads8688_write_raw(struct iio_dev *indio_dev,
290			     struct iio_chan_spec const *chan,
291			     int val, int val2, long mask)
292{
293	struct ads8688_state *st = iio_priv(indio_dev);
294	unsigned int scale = 0;
295	int ret = -EINVAL, i, offset = 0;
296
297	mutex_lock(&st->lock);
298	switch (mask) {
299	case IIO_CHAN_INFO_SCALE:
300		/* If the offset is 0 the ±2.5 * VREF mode is not available */
301		offset = ads8688_range_def[st->range[chan->channel]].offset;
302		if (offset == 0 && val2 == ads8688_range_def[0].scale * st->vref_mv) {
303			mutex_unlock(&st->lock);
304			return -EINVAL;
305		}
306
307		/* Lookup new mode */
308		for (i = 0; i < ARRAY_SIZE(ads8688_range_def); i++)
309			if (val2 == ads8688_range_def[i].scale * st->vref_mv &&
310			    offset == ads8688_range_def[i].offset) {
311				ret = ads8688_write_reg_range(indio_dev, chan,
312					ads8688_range_def[i].reg);
313				break;
314			}
315		break;
316	case IIO_CHAN_INFO_OFFSET:
317		/*
318		 * There are only two available offsets:
319		 * 0 and -(1 << (ADS8688_REALBITS - 1))
320		 */
321		if (!(ads8688_range_def[0].offset == val ||
322		    ads8688_range_def[3].offset == val)) {
323			mutex_unlock(&st->lock);
324			return -EINVAL;
325		}
326
327		/*
328		 * If the device are in ±2.5 * VREF mode, it's not allowed to
329		 * switch to a mode where the offset is 0
330		 */
331		if (val == 0 &&
332		    st->range[chan->channel] == ADS8688_PLUSMINUS25VREF) {
333			mutex_unlock(&st->lock);
334			return -EINVAL;
335		}
336
337		scale = ads8688_range_def[st->range[chan->channel]].scale;
338
339		/* Lookup new mode */
340		for (i = 0; i < ARRAY_SIZE(ads8688_range_def); i++)
341			if (val == ads8688_range_def[i].offset &&
342			    scale == ads8688_range_def[i].scale) {
343				ret = ads8688_write_reg_range(indio_dev, chan,
344					ads8688_range_def[i].reg);
345				break;
346			}
347		break;
348	}
349
350	if (!ret)
351		st->range[chan->channel] = ads8688_range_def[i].range;
352
353	mutex_unlock(&st->lock);
354
355	return ret;
356}
357
358static int ads8688_write_raw_get_fmt(struct iio_dev *indio_dev,
359				     struct iio_chan_spec const *chan,
360				     long mask)
361{
362	switch (mask) {
363	case IIO_CHAN_INFO_SCALE:
364		return IIO_VAL_INT_PLUS_NANO;
365	case IIO_CHAN_INFO_OFFSET:
366		return IIO_VAL_INT;
367	}
368
369	return -EINVAL;
370}
371
372static const struct iio_info ads8688_info = {
373	.read_raw = &ads8688_read_raw,
374	.write_raw = &ads8688_write_raw,
375	.write_raw_get_fmt = &ads8688_write_raw_get_fmt,
376	.attrs = &ads8688_attribute_group,
377};
378
379static irqreturn_t ads8688_trigger_handler(int irq, void *p)
380{
381	struct iio_poll_func *pf = p;
382	struct iio_dev *indio_dev = pf->indio_dev;
383	/* Ensure naturally aligned timestamp */
384	u16 buffer[ADS8688_MAX_CHANNELS + sizeof(s64)/sizeof(u16)] __aligned(8) = { };
385	int i, j = 0;
386
387	iio_for_each_active_channel(indio_dev, i) {
388		buffer[j] = ads8688_read(indio_dev, i);
389		j++;
390	}
391
392	iio_push_to_buffers_with_ts(indio_dev, buffer, sizeof(buffer),
393				    iio_get_time_ns(indio_dev));
394
395	iio_trigger_notify_done(indio_dev->trig);
396
397	return IRQ_HANDLED;
398}
399
400static const struct ads8688_chip_info ads8688_chip_info_tbl[] = {
401	[ID_ADS8684] = {
402		.channels = ads8684_channels,
403		.num_channels = ARRAY_SIZE(ads8684_channels),
404	},
405	[ID_ADS8688] = {
406		.channels = ads8688_channels,
407		.num_channels = ARRAY_SIZE(ads8688_channels),
408	},
409};
410
411static int ads8688_probe(struct spi_device *spi)
412{
413	struct ads8688_state *st;
414	struct iio_dev *indio_dev;
415	int ret;
416
417	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
418	if (indio_dev == NULL)
419		return -ENOMEM;
420
421	st = iio_priv(indio_dev);
422
423	ret = devm_regulator_get_enable_read_voltage(&spi->dev, "vref");
424	if (ret < 0 && ret != -ENODEV)
425		return ret;
426
427	st->vref_mv = ret == -ENODEV ? ADS8688_VREF_MV : ret / 1000;
428
429	st->chip_info =	&ads8688_chip_info_tbl[spi_get_device_id(spi)->driver_data];
430
431	spi->mode = SPI_MODE_1;
432
433	st->spi = spi;
434
435	indio_dev->name = spi_get_device_id(spi)->name;
436	indio_dev->modes = INDIO_DIRECT_MODE;
437	indio_dev->channels = st->chip_info->channels;
438	indio_dev->num_channels = st->chip_info->num_channels;
439	indio_dev->info = &ads8688_info;
440
441	ads8688_reset(indio_dev);
442
443	mutex_init(&st->lock);
444
445	ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
446					      ads8688_trigger_handler, NULL);
447	if (ret < 0)
448		return dev_err_probe(&spi->dev, ret,
449				     "iio triggered buffer setup failed\n");
450
451	return devm_iio_device_register(&spi->dev, indio_dev);
452}
453
454static const struct spi_device_id ads8688_id[] = {
455	{ "ads8684", ID_ADS8684 },
456	{ "ads8688", ID_ADS8688 },
457	{ }
458};
459MODULE_DEVICE_TABLE(spi, ads8688_id);
460
461static const struct of_device_id ads8688_of_match[] = {
462	{ .compatible = "ti,ads8684" },
463	{ .compatible = "ti,ads8688" },
464	{ }
465};
466MODULE_DEVICE_TABLE(of, ads8688_of_match);
467
468static struct spi_driver ads8688_driver = {
469	.driver = {
470		.name	= "ads8688",
471		.of_match_table = ads8688_of_match,
472	},
473	.probe		= ads8688_probe,
474	.id_table	= ads8688_id,
475};
476module_spi_driver(ads8688_driver);
477
478MODULE_AUTHOR("Sean Nyekjaer <sean@geanix.dk>");
479MODULE_DESCRIPTION("Texas Instruments ADS8688 driver");
480MODULE_LICENSE("GPL v2");