ti-ads7950.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Texas Instruments ADS7950 SPI ADC driver
  4 *
  5 * Copyright 2016 David Lechner <david@lechnology.com>
  6 *
  7 * Based on iio/ad7923.c:
  8 * Copyright 2011 Analog Devices Inc
  9 * Copyright 2012 CS Systemes d'Information
 10 *
 11 * And also on hwmon/ads79xx.c
 12 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
 13 *	Nishanth Menon
 14 */
 15
 16#include <linux/acpi.h>
 17#include <linux/bitops.h>
 18#include <linux/device.h>
 19#include <linux/err.h>
 20#include <linux/gpio/driver.h>
 21#include <linux/interrupt.h>
 22#include <linux/kernel.h>
 23#include <linux/module.h>
 24#include <linux/regulator/consumer.h>
 25#include <linux/slab.h>
 26#include <linux/spi/spi.h>
 27
 28#include <linux/iio/buffer.h>
 29#include <linux/iio/iio.h>
 30#include <linux/iio/sysfs.h>
 31#include <linux/iio/trigger_consumer.h>
 32#include <linux/iio/triggered_buffer.h>
 33
 34/*
 35 * In case of ACPI, we use the 5000 mV as default for the reference pin.
 36 * Device tree users encode that via the vref-supply regulator.
 37 */
 38#define TI_ADS7950_VA_MV_ACPI_DEFAULT	5000
 39
 40#define TI_ADS7950_CR_GPIO	BIT(14)
 41#define TI_ADS7950_CR_MANUAL	BIT(12)
 42#define TI_ADS7950_CR_WRITE	BIT(11)
 43#define TI_ADS7950_CR_CHAN(ch)	((ch) << 7)
 44#define TI_ADS7950_CR_RANGE_5V	BIT(6)
 45#define TI_ADS7950_CR_GPIO_DATA	BIT(4)
 46
 47#define TI_ADS7950_MAX_CHAN	16
 48#define TI_ADS7950_NUM_GPIOS	4
 49
 50#define TI_ADS7950_TIMESTAMP_SIZE (sizeof(int64_t) / sizeof(__be16))
 51
 52/* val = value, dec = left shift, bits = number of bits of the mask */
 53#define TI_ADS7950_EXTRACT(val, dec, bits) \
 54	(((val) >> (dec)) & ((1 << (bits)) - 1))
 55
 56#define TI_ADS7950_MAN_CMD(cmd)         (TI_ADS7950_CR_MANUAL | (cmd))
 57#define TI_ADS7950_GPIO_CMD(cmd)        (TI_ADS7950_CR_GPIO | (cmd))
 58
 59/* Manual mode configuration */
 60#define TI_ADS7950_MAN_CMD_SETTINGS(st) \
 61	(TI_ADS7950_MAN_CMD(TI_ADS7950_CR_WRITE | st->cmd_settings_bitmask))
 62/* GPIO mode configuration */
 63#define TI_ADS7950_GPIO_CMD_SETTINGS(st) \
 64	(TI_ADS7950_GPIO_CMD(st->gpio_cmd_settings_bitmask))
 65
 66struct ti_ads7950_state {
 67	struct spi_device	*spi;
 68	struct spi_transfer	ring_xfer;
 69	struct spi_transfer	scan_single_xfer[3];
 70	struct spi_message	ring_msg;
 71	struct spi_message	scan_single_msg;
 72
 73	/* Lock to protect the spi xfer buffers */
 74	struct mutex		slock;
 75	struct gpio_chip	chip;
 76
 77	struct regulator	*reg;
 78	unsigned int		vref_mv;
 79
 80	/*
 81	 * Bitmask of lower 7 bits used for configuration
 82	 * These bits only can be written when TI_ADS7950_CR_WRITE
 83	 * is set, otherwise it retains its original state.
 84	 * [0-3] GPIO signal
 85	 * [4]   Set following frame to return GPIO signal values
 86	 * [5]   Powers down device
 87	 * [6]   Sets Vref range1(2.5v) or range2(5v)
 88	 *
 89	 * Bits present on Manual/Auto1/Auto2 commands
 90	 */
 91	unsigned int		cmd_settings_bitmask;
 92
 93	/*
 94	 * Bitmask of GPIO command
 95	 * [0-3] GPIO direction
 96	 * [4-6] Different GPIO alarm mode configurations
 97	 * [7]   GPIO 2 as device range input
 98	 * [8]   GPIO 3 as device power down input
 99	 * [9]   Reset all registers
100	 * [10-11] N/A
101	 */
102	unsigned int		gpio_cmd_settings_bitmask;
103
104	/*
105	 * DMA (thus cache coherency maintenance) may require the
106	 * transfer buffers to live in their own cache lines.
107	 */
108	u16 rx_buf[TI_ADS7950_MAX_CHAN + 2 + TI_ADS7950_TIMESTAMP_SIZE]
109		__aligned(IIO_DMA_MINALIGN);
110	u16 tx_buf[TI_ADS7950_MAX_CHAN + 2];
111	u16 single_tx;
112	u16 single_rx;
113
114};
115
116struct ti_ads7950_chip_info {
117	const struct iio_chan_spec *channels;
118	unsigned int num_channels;
119};
120
121enum ti_ads7950_id {
122	TI_ADS7950,
123	TI_ADS7951,
124	TI_ADS7952,
125	TI_ADS7953,
126	TI_ADS7954,
127	TI_ADS7955,
128	TI_ADS7956,
129	TI_ADS7957,
130	TI_ADS7958,
131	TI_ADS7959,
132	TI_ADS7960,
133	TI_ADS7961,
134};
135
136#define TI_ADS7950_V_CHAN(index, bits)				\
137{								\
138	.type = IIO_VOLTAGE,					\
139	.indexed = 1,						\
140	.channel = index,					\
141	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
142	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
143	.address = index,					\
144	.datasheet_name = "CH##index",				\
145	.scan_index = index,					\
146	.scan_type = {						\
147		.sign = 'u',					\
148		.realbits = bits,				\
149		.storagebits = 16,				\
150		.shift = 12 - (bits),				\
151		.endianness = IIO_CPU,				\
152	},							\
153}
154
155#define DECLARE_TI_ADS7950_4_CHANNELS(name, bits) \
156const struct iio_chan_spec name ## _channels[] = { \
157	TI_ADS7950_V_CHAN(0, bits), \
158	TI_ADS7950_V_CHAN(1, bits), \
159	TI_ADS7950_V_CHAN(2, bits), \
160	TI_ADS7950_V_CHAN(3, bits), \
161	IIO_CHAN_SOFT_TIMESTAMP(4), \
162}
163
164#define DECLARE_TI_ADS7950_8_CHANNELS(name, bits) \
165const struct iio_chan_spec name ## _channels[] = { \
166	TI_ADS7950_V_CHAN(0, bits), \
167	TI_ADS7950_V_CHAN(1, bits), \
168	TI_ADS7950_V_CHAN(2, bits), \
169	TI_ADS7950_V_CHAN(3, bits), \
170	TI_ADS7950_V_CHAN(4, bits), \
171	TI_ADS7950_V_CHAN(5, bits), \
172	TI_ADS7950_V_CHAN(6, bits), \
173	TI_ADS7950_V_CHAN(7, bits), \
174	IIO_CHAN_SOFT_TIMESTAMP(8), \
175}
176
177#define DECLARE_TI_ADS7950_12_CHANNELS(name, bits) \
178const struct iio_chan_spec name ## _channels[] = { \
179	TI_ADS7950_V_CHAN(0, bits), \
180	TI_ADS7950_V_CHAN(1, bits), \
181	TI_ADS7950_V_CHAN(2, bits), \
182	TI_ADS7950_V_CHAN(3, bits), \
183	TI_ADS7950_V_CHAN(4, bits), \
184	TI_ADS7950_V_CHAN(5, bits), \
185	TI_ADS7950_V_CHAN(6, bits), \
186	TI_ADS7950_V_CHAN(7, bits), \
187	TI_ADS7950_V_CHAN(8, bits), \
188	TI_ADS7950_V_CHAN(9, bits), \
189	TI_ADS7950_V_CHAN(10, bits), \
190	TI_ADS7950_V_CHAN(11, bits), \
191	IIO_CHAN_SOFT_TIMESTAMP(12), \
192}
193
194#define DECLARE_TI_ADS7950_16_CHANNELS(name, bits) \
195const struct iio_chan_spec name ## _channels[] = { \
196	TI_ADS7950_V_CHAN(0, bits), \
197	TI_ADS7950_V_CHAN(1, bits), \
198	TI_ADS7950_V_CHAN(2, bits), \
199	TI_ADS7950_V_CHAN(3, bits), \
200	TI_ADS7950_V_CHAN(4, bits), \
201	TI_ADS7950_V_CHAN(5, bits), \
202	TI_ADS7950_V_CHAN(6, bits), \
203	TI_ADS7950_V_CHAN(7, bits), \
204	TI_ADS7950_V_CHAN(8, bits), \
205	TI_ADS7950_V_CHAN(9, bits), \
206	TI_ADS7950_V_CHAN(10, bits), \
207	TI_ADS7950_V_CHAN(11, bits), \
208	TI_ADS7950_V_CHAN(12, bits), \
209	TI_ADS7950_V_CHAN(13, bits), \
210	TI_ADS7950_V_CHAN(14, bits), \
211	TI_ADS7950_V_CHAN(15, bits), \
212	IIO_CHAN_SOFT_TIMESTAMP(16), \
213}
214
215static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7950, 12);
216static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7951, 12);
217static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7952, 12);
218static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7953, 12);
219static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7954, 10);
220static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7955, 10);
221static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7956, 10);
222static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7957, 10);
223static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7958, 8);
224static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7959, 8);
225static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7960, 8);
226static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7961, 8);
227
228static const struct ti_ads7950_chip_info ti_ads7950_chip_info[] = {
229	[TI_ADS7950] = {
230		.channels	= ti_ads7950_channels,
231		.num_channels	= ARRAY_SIZE(ti_ads7950_channels),
232	},
233	[TI_ADS7951] = {
234		.channels	= ti_ads7951_channels,
235		.num_channels	= ARRAY_SIZE(ti_ads7951_channels),
236	},
237	[TI_ADS7952] = {
238		.channels	= ti_ads7952_channels,
239		.num_channels	= ARRAY_SIZE(ti_ads7952_channels),
240	},
241	[TI_ADS7953] = {
242		.channels	= ti_ads7953_channels,
243		.num_channels	= ARRAY_SIZE(ti_ads7953_channels),
244	},
245	[TI_ADS7954] = {
246		.channels	= ti_ads7954_channels,
247		.num_channels	= ARRAY_SIZE(ti_ads7954_channels),
248	},
249	[TI_ADS7955] = {
250		.channels	= ti_ads7955_channels,
251		.num_channels	= ARRAY_SIZE(ti_ads7955_channels),
252	},
253	[TI_ADS7956] = {
254		.channels	= ti_ads7956_channels,
255		.num_channels	= ARRAY_SIZE(ti_ads7956_channels),
256	},
257	[TI_ADS7957] = {
258		.channels	= ti_ads7957_channels,
259		.num_channels	= ARRAY_SIZE(ti_ads7957_channels),
260	},
261	[TI_ADS7958] = {
262		.channels	= ti_ads7958_channels,
263		.num_channels	= ARRAY_SIZE(ti_ads7958_channels),
264	},
265	[TI_ADS7959] = {
266		.channels	= ti_ads7959_channels,
267		.num_channels	= ARRAY_SIZE(ti_ads7959_channels),
268	},
269	[TI_ADS7960] = {
270		.channels	= ti_ads7960_channels,
271		.num_channels	= ARRAY_SIZE(ti_ads7960_channels),
272	},
273	[TI_ADS7961] = {
274		.channels	= ti_ads7961_channels,
275		.num_channels	= ARRAY_SIZE(ti_ads7961_channels),
276	},
277};
278
279/*
280 * ti_ads7950_update_scan_mode() setup the spi transfer buffer for the new
281 * scan mask
282 */
283static int ti_ads7950_update_scan_mode(struct iio_dev *indio_dev,
284				       const unsigned long *active_scan_mask)
285{
286	struct ti_ads7950_state *st = iio_priv(indio_dev);
287	int i, cmd, len;
288
289	len = 0;
290	for_each_set_bit(i, active_scan_mask, indio_dev->num_channels) {
291		cmd = TI_ADS7950_MAN_CMD(TI_ADS7950_CR_CHAN(i));
292		st->tx_buf[len++] = cmd;
293	}
294
295	/* Data for the 1st channel is not returned until the 3rd transfer */
296	st->tx_buf[len++] = 0;
297	st->tx_buf[len++] = 0;
298
299	st->ring_xfer.len = len * 2;
300
301	return 0;
302}
303
304static irqreturn_t ti_ads7950_trigger_handler(int irq, void *p)
305{
306	struct iio_poll_func *pf = p;
307	struct iio_dev *indio_dev = pf->indio_dev;
308	struct ti_ads7950_state *st = iio_priv(indio_dev);
309	int ret;
310
311	mutex_lock(&st->slock);
312	ret = spi_sync(st->spi, &st->ring_msg);
313	if (ret < 0)
314		goto out;
315
316	iio_push_to_buffers_with_timestamp(indio_dev, &st->rx_buf[2],
317					   iio_get_time_ns(indio_dev));
318
319out:
320	mutex_unlock(&st->slock);
321	iio_trigger_notify_done(indio_dev->trig);
322
323	return IRQ_HANDLED;
324}
325
326static int ti_ads7950_scan_direct(struct iio_dev *indio_dev, unsigned int ch)
327{
328	struct ti_ads7950_state *st = iio_priv(indio_dev);
329	int ret, cmd;
330
331	mutex_lock(&st->slock);
332	cmd = TI_ADS7950_MAN_CMD(TI_ADS7950_CR_CHAN(ch));
333	st->single_tx = cmd;
334
335	ret = spi_sync(st->spi, &st->scan_single_msg);
336	if (ret)
337		goto out;
338
339	ret = st->single_rx;
340
341out:
342	mutex_unlock(&st->slock);
343
344	return ret;
345}
346
347static int ti_ads7950_get_range(struct ti_ads7950_state *st)
348{
349	int vref;
350
351	if (st->vref_mv) {
352		vref = st->vref_mv;
353	} else {
354		vref = regulator_get_voltage(st->reg);
355		if (vref < 0)
356			return vref;
357
358		vref /= 1000;
359	}
360
361	if (st->cmd_settings_bitmask & TI_ADS7950_CR_RANGE_5V)
362		vref *= 2;
363
364	return vref;
365}
366
367static int ti_ads7950_read_raw(struct iio_dev *indio_dev,
368			       struct iio_chan_spec const *chan,
369			       int *val, int *val2, long m)
370{
371	struct ti_ads7950_state *st = iio_priv(indio_dev);
372	int ret;
373
374	switch (m) {
375	case IIO_CHAN_INFO_RAW:
376		ret = ti_ads7950_scan_direct(indio_dev, chan->address);
377		if (ret < 0)
378			return ret;
379
380		if (chan->address != TI_ADS7950_EXTRACT(ret, 12, 4))
381			return -EIO;
382
383		*val = TI_ADS7950_EXTRACT(ret, chan->scan_type.shift,
384					  chan->scan_type.realbits);
385
386		return IIO_VAL_INT;
387	case IIO_CHAN_INFO_SCALE:
388		ret = ti_ads7950_get_range(st);
389		if (ret < 0)
390			return ret;
391
392		*val = ret;
393		*val2 = (1 << chan->scan_type.realbits) - 1;
394
395		return IIO_VAL_FRACTIONAL;
396	}
397
398	return -EINVAL;
399}
400
401static const struct iio_info ti_ads7950_info = {
402	.read_raw		= &ti_ads7950_read_raw,
403	.update_scan_mode	= ti_ads7950_update_scan_mode,
404};
405
406static int ti_ads7950_set(struct gpio_chip *chip, unsigned int offset,
407			  int value)
408{
409	struct ti_ads7950_state *st = gpiochip_get_data(chip);
410	int ret;
411
412	mutex_lock(&st->slock);
413
414	if (value)
415		st->cmd_settings_bitmask |= BIT(offset);
416	else
417		st->cmd_settings_bitmask &= ~BIT(offset);
418
419	st->single_tx = TI_ADS7950_MAN_CMD_SETTINGS(st);
420	ret = spi_sync(st->spi, &st->scan_single_msg);
421
422	mutex_unlock(&st->slock);
423
424	return ret;
425}
426
427static int ti_ads7950_get(struct gpio_chip *chip, unsigned int offset)
428{
429	struct ti_ads7950_state *st = gpiochip_get_data(chip);
430	bool state;
431	int ret;
432
433	mutex_lock(&st->slock);
434
435	/* If set as output, return the output */
436	if (st->gpio_cmd_settings_bitmask & BIT(offset)) {
437		state = st->cmd_settings_bitmask & BIT(offset);
438		ret = 0;
439		goto out;
440	}
441
442	/* GPIO data bit sets SDO bits 12-15 to GPIO input */
443	st->cmd_settings_bitmask |= TI_ADS7950_CR_GPIO_DATA;
444	st->single_tx = TI_ADS7950_MAN_CMD_SETTINGS(st);
445	ret = spi_sync(st->spi, &st->scan_single_msg);
446	if (ret)
447		goto out;
448
449	state = (st->single_rx >> 12) & BIT(offset);
450
451	/* Revert back to original settings */
452	st->cmd_settings_bitmask &= ~TI_ADS7950_CR_GPIO_DATA;
453	st->single_tx = TI_ADS7950_MAN_CMD_SETTINGS(st);
454	ret = spi_sync(st->spi, &st->scan_single_msg);
455	if (ret)
456		goto out;
457
458out:
459	mutex_unlock(&st->slock);
460
461	return ret ?: state;
462}
463
464static int ti_ads7950_get_direction(struct gpio_chip *chip,
465				    unsigned int offset)
466{
467	struct ti_ads7950_state *st = gpiochip_get_data(chip);
468
469	/* Bitmask is inverted from GPIO framework 0=input/1=output */
470	return !(st->gpio_cmd_settings_bitmask & BIT(offset));
471}
472
473static int _ti_ads7950_set_direction(struct gpio_chip *chip, int offset,
474				     int input)
475{
476	struct ti_ads7950_state *st = gpiochip_get_data(chip);
477	int ret = 0;
478
479	mutex_lock(&st->slock);
480
481	/* Only change direction if needed */
482	if (input && (st->gpio_cmd_settings_bitmask & BIT(offset)))
483		st->gpio_cmd_settings_bitmask &= ~BIT(offset);
484	else if (!input && !(st->gpio_cmd_settings_bitmask & BIT(offset)))
485		st->gpio_cmd_settings_bitmask |= BIT(offset);
486	else
487		goto out;
488
489	st->single_tx = TI_ADS7950_GPIO_CMD_SETTINGS(st);
490	ret = spi_sync(st->spi, &st->scan_single_msg);
491
492out:
493	mutex_unlock(&st->slock);
494
495	return ret;
496}
497
498static int ti_ads7950_direction_input(struct gpio_chip *chip,
499				      unsigned int offset)
500{
501	return _ti_ads7950_set_direction(chip, offset, 1);
502}
503
504static int ti_ads7950_direction_output(struct gpio_chip *chip,
505				       unsigned int offset, int value)
506{
507	int ret;
508
509	ret = ti_ads7950_set(chip, offset, value);
510	if (ret)
511		return ret;
512
513	return _ti_ads7950_set_direction(chip, offset, 0);
514}
515
516static int ti_ads7950_init_hw(struct ti_ads7950_state *st)
517{
518	int ret = 0;
519
520	mutex_lock(&st->slock);
521
522	/* Settings for Manual/Auto1/Auto2 commands */
523	/* Default to 5v ref */
524	st->cmd_settings_bitmask = TI_ADS7950_CR_RANGE_5V;
525	st->single_tx = TI_ADS7950_MAN_CMD_SETTINGS(st);
526	ret = spi_sync(st->spi, &st->scan_single_msg);
527	if (ret)
528		goto out;
529
530	/* Settings for GPIO command */
531	st->gpio_cmd_settings_bitmask = 0x0;
532	st->single_tx = TI_ADS7950_GPIO_CMD_SETTINGS(st);
533	ret = spi_sync(st->spi, &st->scan_single_msg);
534
535out:
536	mutex_unlock(&st->slock);
537
538	return ret;
539}
540
541static int ti_ads7950_probe(struct spi_device *spi)
542{
543	struct ti_ads7950_state *st;
544	struct iio_dev *indio_dev;
545	const struct ti_ads7950_chip_info *info;
546	int ret;
547
548	spi->bits_per_word = 16;
549	spi->mode |= SPI_CS_WORD;
550	ret = spi_setup(spi);
551	if (ret < 0) {
552		dev_err(&spi->dev, "Error in spi setup\n");
553		return ret;
554	}
555
556	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
557	if (!indio_dev)
558		return -ENOMEM;
559
560	st = iio_priv(indio_dev);
561
562	spi_set_drvdata(spi, indio_dev);
563
564	st->spi = spi;
565
566	info = &ti_ads7950_chip_info[spi_get_device_id(spi)->driver_data];
567
568	indio_dev->name = spi_get_device_id(spi)->name;
569	indio_dev->modes = INDIO_DIRECT_MODE;
570	indio_dev->channels = info->channels;
571	indio_dev->num_channels = info->num_channels;
572	indio_dev->info = &ti_ads7950_info;
573
574	/* build spi ring message */
575	spi_message_init(&st->ring_msg);
576
577	st->ring_xfer.tx_buf = &st->tx_buf[0];
578	st->ring_xfer.rx_buf = &st->rx_buf[0];
579	/* len will be set later */
580
581	spi_message_add_tail(&st->ring_xfer, &st->ring_msg);
582
583	/*
584	 * Setup default message. The sample is read at the end of the first
585	 * transfer, then it takes one full cycle to convert the sample and one
586	 * more cycle to send the value. The conversion process is driven by
587	 * the SPI clock, which is why we have 3 transfers. The middle one is
588	 * just dummy data sent while the chip is converting the sample that
589	 * was read at the end of the first transfer.
590	 */
591
592	st->scan_single_xfer[0].tx_buf = &st->single_tx;
593	st->scan_single_xfer[0].len = 2;
594	st->scan_single_xfer[0].cs_change = 1;
595	st->scan_single_xfer[1].tx_buf = &st->single_tx;
596	st->scan_single_xfer[1].len = 2;
597	st->scan_single_xfer[1].cs_change = 1;
598	st->scan_single_xfer[2].rx_buf = &st->single_rx;
599	st->scan_single_xfer[2].len = 2;
600
601	spi_message_init_with_transfers(&st->scan_single_msg,
602					st->scan_single_xfer, 3);
603
604	/* Use hard coded value for reference voltage in ACPI case */
605	if (ACPI_COMPANION(&spi->dev))
606		st->vref_mv = TI_ADS7950_VA_MV_ACPI_DEFAULT;
607
608	mutex_init(&st->slock);
609
610	st->reg = devm_regulator_get(&spi->dev, "vref");
611	if (IS_ERR(st->reg)) {
612		ret = dev_err_probe(&spi->dev, PTR_ERR(st->reg),
613				     "Failed to get regulator \"vref\"\n");
614		goto error_destroy_mutex;
615	}
616
617	ret = regulator_enable(st->reg);
618	if (ret) {
619		dev_err(&spi->dev, "Failed to enable regulator \"vref\"\n");
620		goto error_destroy_mutex;
621	}
622
623	ret = iio_triggered_buffer_setup(indio_dev, NULL,
624					 &ti_ads7950_trigger_handler, NULL);
625	if (ret) {
626		dev_err(&spi->dev, "Failed to setup triggered buffer\n");
627		goto error_disable_reg;
628	}
629
630	ret = ti_ads7950_init_hw(st);
631	if (ret) {
632		dev_err(&spi->dev, "Failed to init adc chip\n");
633		goto error_cleanup_ring;
634	}
635
636	ret = iio_device_register(indio_dev);
637	if (ret) {
638		dev_err(&spi->dev, "Failed to register iio device\n");
639		goto error_cleanup_ring;
640	}
641
642	/* Add GPIO chip */
643	st->chip.label = dev_name(&st->spi->dev);
644	st->chip.parent = &st->spi->dev;
645	st->chip.owner = THIS_MODULE;
646	st->chip.can_sleep = true;
647	st->chip.base = -1;
648	st->chip.ngpio = TI_ADS7950_NUM_GPIOS;
649	st->chip.get_direction = ti_ads7950_get_direction;
650	st->chip.direction_input = ti_ads7950_direction_input;
651	st->chip.direction_output = ti_ads7950_direction_output;
652	st->chip.get = ti_ads7950_get;
653	st->chip.set = ti_ads7950_set;
654
655	ret = gpiochip_add_data(&st->chip, st);
656	if (ret) {
657		dev_err(&spi->dev, "Failed to init GPIOs\n");
658		goto error_iio_device;
659	}
660
661	return 0;
662
663error_iio_device:
664	iio_device_unregister(indio_dev);
665error_cleanup_ring:
666	iio_triggered_buffer_cleanup(indio_dev);
667error_disable_reg:
668	regulator_disable(st->reg);
669error_destroy_mutex:
670	mutex_destroy(&st->slock);
671
672	return ret;
673}
674
675static void ti_ads7950_remove(struct spi_device *spi)
676{
677	struct iio_dev *indio_dev = spi_get_drvdata(spi);
678	struct ti_ads7950_state *st = iio_priv(indio_dev);
679
680	gpiochip_remove(&st->chip);
681	iio_device_unregister(indio_dev);
682	iio_triggered_buffer_cleanup(indio_dev);
683	regulator_disable(st->reg);
684	mutex_destroy(&st->slock);
685}
686
687static const struct spi_device_id ti_ads7950_id[] = {
688	{ "ads7950", TI_ADS7950 },
689	{ "ads7951", TI_ADS7951 },
690	{ "ads7952", TI_ADS7952 },
691	{ "ads7953", TI_ADS7953 },
692	{ "ads7954", TI_ADS7954 },
693	{ "ads7955", TI_ADS7955 },
694	{ "ads7956", TI_ADS7956 },
695	{ "ads7957", TI_ADS7957 },
696	{ "ads7958", TI_ADS7958 },
697	{ "ads7959", TI_ADS7959 },
698	{ "ads7960", TI_ADS7960 },
699	{ "ads7961", TI_ADS7961 },
700	{ }
701};
702MODULE_DEVICE_TABLE(spi, ti_ads7950_id);
703
704static const struct of_device_id ads7950_of_table[] = {
705	{ .compatible = "ti,ads7950", .data = &ti_ads7950_chip_info[TI_ADS7950] },
706	{ .compatible = "ti,ads7951", .data = &ti_ads7950_chip_info[TI_ADS7951] },
707	{ .compatible = "ti,ads7952", .data = &ti_ads7950_chip_info[TI_ADS7952] },
708	{ .compatible = "ti,ads7953", .data = &ti_ads7950_chip_info[TI_ADS7953] },
709	{ .compatible = "ti,ads7954", .data = &ti_ads7950_chip_info[TI_ADS7954] },
710	{ .compatible = "ti,ads7955", .data = &ti_ads7950_chip_info[TI_ADS7955] },
711	{ .compatible = "ti,ads7956", .data = &ti_ads7950_chip_info[TI_ADS7956] },
712	{ .compatible = "ti,ads7957", .data = &ti_ads7950_chip_info[TI_ADS7957] },
713	{ .compatible = "ti,ads7958", .data = &ti_ads7950_chip_info[TI_ADS7958] },
714	{ .compatible = "ti,ads7959", .data = &ti_ads7950_chip_info[TI_ADS7959] },
715	{ .compatible = "ti,ads7960", .data = &ti_ads7950_chip_info[TI_ADS7960] },
716	{ .compatible = "ti,ads7961", .data = &ti_ads7950_chip_info[TI_ADS7961] },
717	{ }
718};
719MODULE_DEVICE_TABLE(of, ads7950_of_table);
720
721static struct spi_driver ti_ads7950_driver = {
722	.driver = {
723		.name	= "ads7950",
724		.of_match_table = ads7950_of_table,
725	},
726	.probe		= ti_ads7950_probe,
727	.remove		= ti_ads7950_remove,
728	.id_table	= ti_ads7950_id,
729};
730module_spi_driver(ti_ads7950_driver);
731
732MODULE_AUTHOR("David Lechner <david@lechnology.com>");
733MODULE_DESCRIPTION("TI TI_ADS7950 ADC");
734MODULE_LICENSE("GPL v2");