ti-ads7924.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * IIO driver for Texas Instruments ADS7924 ADC, 12-bit, 4-Channels, I2C
  4 *
  5 * Author: Hugo Villeneuve <hvilleneuve@dimonoff.com>
  6 * Copyright 2022 DimOnOff
  7 *
  8 * based on iio/adc/ti-ads1015.c
  9 * Copyright (c) 2016, Intel Corporation.
 10 *
 11 * Datasheet: https://www.ti.com/lit/gpn/ads7924
 12 */
 13
 14#include <linux/bitfield.h>
 15#include <linux/delay.h>
 16#include <linux/gpio/consumer.h>
 17#include <linux/init.h>
 18#include <linux/irq.h>
 19#include <linux/i2c.h>
 20#include <linux/module.h>
 21#include <linux/mutex.h>
 22#include <linux/regmap.h>
 23#include <linux/regulator/consumer.h>
 24
 25#include <linux/iio/iio.h>
 26#include <linux/iio/types.h>
 27
 28#define ADS7924_CHANNELS	 4
 29#define ADS7924_BITS		12
 30#define ADS7924_DATA_SHIFT	 4
 31
 32/* Registers. */
 33#define ADS7924_MODECNTRL_REG	0x00
 34#define ADS7924_INTCNTRL_REG	0x01
 35#define ADS7924_DATA0_U_REG	0x02
 36#define ADS7924_DATA0_L_REG	0x03
 37#define ADS7924_DATA1_U_REG	0x04
 38#define ADS7924_DATA1_L_REG	0x05
 39#define ADS7924_DATA2_U_REG	0x06
 40#define ADS7924_DATA2_L_REG	0x07
 41#define ADS7924_DATA3_U_REG	0x08
 42#define ADS7924_DATA3_L_REG	0x09
 43#define ADS7924_ULR0_REG	0x0A
 44#define ADS7924_LLR0_REG	0x0B
 45#define ADS7924_ULR1_REG	0x0C
 46#define ADS7924_LLR1_REG	0x0D
 47#define ADS7924_ULR2_REG	0x0E
 48#define ADS7924_LLR2_REG	0x0F
 49#define ADS7924_ULR3_REG	0x10
 50#define ADS7924_LLR3_REG	0x11
 51#define ADS7924_INTCONFIG_REG	0x12
 52#define ADS7924_SLPCONFIG_REG	0x13
 53#define ADS7924_ACQCONFIG_REG	0x14
 54#define ADS7924_PWRCONFIG_REG	0x15
 55#define ADS7924_RESET_REG	0x16
 56
 57/*
 58 * Register address INC bit: when set to '1', the register address is
 59 * automatically incremented after every register read which allows convenient
 60 * reading of multiple registers. Set INC to '0' when reading a single register.
 61 */
 62#define ADS7924_AUTO_INCREMENT_BIT	BIT(7)
 63
 64#define ADS7924_MODECNTRL_MODE_MASK	GENMASK(7, 2)
 65
 66#define ADS7924_MODECNTRL_SEL_MASK	GENMASK(1, 0)
 67
 68#define ADS7924_CFG_INTPOL_BIT		1
 69#define ADS7924_CFG_INTTRIG_BIT		0
 70
 71#define ADS7924_CFG_INTPOL_MASK		BIT(ADS7924_CFG_INTPOL_BIT)
 72#define ADS7924_CFG_INTTRIG_MASK	BIT(ADS7924_CFG_INTTRIG_BIT)
 73
 74/* Interrupt pin polarity */
 75#define ADS7924_CFG_INTPOL_LOW		0
 76#define ADS7924_CFG_INTPOL_HIGH		1
 77
 78/* Interrupt pin signaling */
 79#define ADS7924_CFG_INTTRIG_LEVEL	0
 80#define ADS7924_CFG_INTTRIG_EDGE	1
 81
 82/* Mode control values */
 83#define ADS7924_MODECNTRL_IDLE			0x00
 84#define ADS7924_MODECNTRL_AWAKE			0x20
 85#define ADS7924_MODECNTRL_MANUAL_SINGLE		0x30
 86#define ADS7924_MODECNTRL_MANUAL_SCAN		0x32
 87#define ADS7924_MODECNTRL_AUTO_SINGLE		0x31
 88#define ADS7924_MODECNTRL_AUTO_SCAN		0x33
 89#define ADS7924_MODECNTRL_AUTO_SINGLE_SLEEP	0x39
 90#define ADS7924_MODECNTRL_AUTO_SCAN_SLEEP	0x3B
 91#define ADS7924_MODECNTRL_AUTO_BURST_SLEEP	0x3F
 92
 93#define ADS7924_ACQTIME_MASK	GENMASK(4, 0)
 94
 95#define ADS7924_PWRUPTIME_MASK	GENMASK(4, 0)
 96
 97/*
 98 * The power-up time is allowed to elapse whenever the device has been shutdown
 99 * in idle mode. Power-up time can allow external circuits, such as an
100 * operational amplifier, between the MUXOUT and ADCIN pins to turn on.
101 * The nominal time programmed by the PUTIME[4:0] register bits is given by:
102 *     t PU = PWRUPTIME[4:0] × 2 μs
103 * If a power-up time is not required, set the bits to '0' to effectively bypass.
104 */
105#define ADS7924_PWRUPTIME_US 0 /* Bypass (0us). */
106
107/*
108 * Acquisition Time according to ACQTIME[4:0] register bits.
109 * The Acquisition Time is given by:
110 *     t ACQ = (ACQTIME[4:0] × 2 μs) + 6 μs
111 * Using default value of 0 for ACQTIME[4:0] results in a minimum acquisition
112 * time of 6us.
113 */
114#define ADS7924_ACQTIME_US 6
115
116/* The conversion time is always 4μs and cannot be programmed by the user. */
117#define ADS7924_CONVTIME_US 4
118
119#define ADS7924_TOTAL_CONVTIME_US (ADS7924_PWRUPTIME_US + ADS7924_ACQTIME_US + \
120				   ADS7924_CONVTIME_US)
121
122#define ADS7924_V_CHAN(_chan, _addr) {				\
123	.type = IIO_VOLTAGE,					\
124	.indexed = 1,						\
125	.channel = _chan,					\
126	.address = _addr,					\
127	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 		\
128	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
129	.datasheet_name = "AIN"#_chan,				\
130}
131
132struct ads7924_data {
133	struct device *dev;
134	struct regmap *regmap;
135	struct regulator *vref_reg;
136
137	/* GPIO descriptor for device hard-reset pin. */
138	struct gpio_desc *reset_gpio;
139
140	/*
141	 * Protects ADC ops, e.g: concurrent sysfs/buffered
142	 * data reads, configuration updates
143	 */
144	struct mutex lock;
145
146	/*
147	 * Set to true when the ADC is switched to the continuous-conversion
148	 * mode and exits from a power-down state. This flag is used to avoid
149	 * getting the stale result from the conversion register.
150	 */
151	bool conv_invalid;
152};
153
154static bool ads7924_is_writeable_reg(struct device *dev, unsigned int reg)
155{
156	switch (reg) {
157	case ADS7924_MODECNTRL_REG:
158	case ADS7924_INTCNTRL_REG:
159	case ADS7924_ULR0_REG:
160	case ADS7924_LLR0_REG:
161	case ADS7924_ULR1_REG:
162	case ADS7924_LLR1_REG:
163	case ADS7924_ULR2_REG:
164	case ADS7924_LLR2_REG:
165	case ADS7924_ULR3_REG:
166	case ADS7924_LLR3_REG:
167	case ADS7924_INTCONFIG_REG:
168	case ADS7924_SLPCONFIG_REG:
169	case ADS7924_ACQCONFIG_REG:
170	case ADS7924_PWRCONFIG_REG:
171	case ADS7924_RESET_REG:
172		return true;
173	default:
174		return false;
175	}
176}
177
178static const struct regmap_config ads7924_regmap_config = {
179	.reg_bits = 8,
180	.val_bits = 8,
181	.max_register = ADS7924_RESET_REG,
182	.writeable_reg = ads7924_is_writeable_reg,
183};
184
185static const struct iio_chan_spec ads7924_channels[] = {
186	ADS7924_V_CHAN(0, ADS7924_DATA0_U_REG),
187	ADS7924_V_CHAN(1, ADS7924_DATA1_U_REG),
188	ADS7924_V_CHAN(2, ADS7924_DATA2_U_REG),
189	ADS7924_V_CHAN(3, ADS7924_DATA3_U_REG),
190};
191
192static int ads7924_get_adc_result(struct ads7924_data *data,
193				  struct iio_chan_spec const *chan, int *val)
194{
195	int ret;
196	__be16 be_val;
197
198	if (chan->channel < 0 || chan->channel >= ADS7924_CHANNELS)
199		return -EINVAL;
200
201	if (data->conv_invalid) {
202		int conv_time;
203
204		conv_time = ADS7924_TOTAL_CONVTIME_US;
205		/* Allow 10% for internal clock inaccuracy. */
206		conv_time += conv_time / 10;
207		usleep_range(conv_time, conv_time + 1);
208		data->conv_invalid = false;
209	}
210
211	ret = regmap_raw_read(data->regmap, ADS7924_AUTO_INCREMENT_BIT |
212			      chan->address, &be_val, sizeof(be_val));
213	if (ret)
214		return ret;
215
216	*val = be16_to_cpu(be_val) >> ADS7924_DATA_SHIFT;
217
218	return 0;
219}
220
221static int ads7924_read_raw(struct iio_dev *indio_dev,
222			    struct iio_chan_spec const *chan, int *val,
223			    int *val2, long mask)
224{
225	int ret, vref_uv;
226	struct ads7924_data *data = iio_priv(indio_dev);
227
228	switch (mask) {
229	case IIO_CHAN_INFO_RAW:
230		mutex_lock(&data->lock);
231		ret = ads7924_get_adc_result(data, chan, val);
232		mutex_unlock(&data->lock);
233		if (ret < 0)
234			return ret;
235
236		return IIO_VAL_INT;
237	case IIO_CHAN_INFO_SCALE:
238		vref_uv = regulator_get_voltage(data->vref_reg);
239		if (vref_uv < 0)
240			return vref_uv;
241
242		*val =  vref_uv / 1000; /* Convert reg voltage to mV */
243		*val2 = ADS7924_BITS;
244		return IIO_VAL_FRACTIONAL_LOG2;
245	default:
246		return -EINVAL;
247	}
248}
249
250static const struct iio_info ads7924_info = {
251	.read_raw = ads7924_read_raw,
252};
253
254static int ads7924_get_channels_config(struct device *dev)
255{
256	struct fwnode_handle *node;
257	int num_channels = 0;
258
259	device_for_each_child_node(dev, node) {
260		u32 pval;
261		unsigned int channel;
262
263		if (fwnode_property_read_u32(node, "reg", &pval)) {
264			dev_err(dev, "invalid reg on %pfw\n", node);
265			continue;
266		}
267
268		channel = pval;
269		if (channel >= ADS7924_CHANNELS) {
270			dev_err(dev, "invalid channel index %d on %pfw\n",
271				channel, node);
272			continue;
273		}
274
275		num_channels++;
276	}
277
278	if (!num_channels)
279		return -EINVAL;
280
281	return 0;
282}
283
284static int ads7924_set_conv_mode(struct ads7924_data *data, int mode)
285{
286	int ret;
287	unsigned int mode_field;
288	struct device *dev = data->dev;
289
290	/*
291	 * When switching between modes, be sure to first select the Awake mode
292	 * and then switch to the desired mode. This procedure ensures the
293	 * internal control logic is properly synchronized.
294	 */
295	if (mode != ADS7924_MODECNTRL_IDLE) {
296		mode_field = FIELD_PREP(ADS7924_MODECNTRL_MODE_MASK,
297					ADS7924_MODECNTRL_AWAKE);
298
299		ret = regmap_update_bits(data->regmap, ADS7924_MODECNTRL_REG,
300					 ADS7924_MODECNTRL_MODE_MASK,
301					 mode_field);
302		if (ret) {
303			dev_err(dev, "failed to set awake mode (%pe)\n",
304				ERR_PTR(ret));
305			return ret;
306		}
307	}
308
309	mode_field = FIELD_PREP(ADS7924_MODECNTRL_MODE_MASK, mode);
310
311	ret = regmap_update_bits(data->regmap, ADS7924_MODECNTRL_REG,
312				 ADS7924_MODECNTRL_MODE_MASK, mode_field);
313	if (ret)
314		dev_err(dev, "failed to set mode %d (%pe)\n", mode,
315			ERR_PTR(ret));
316
317	return ret;
318}
319
320static int ads7924_reset(struct iio_dev *indio_dev)
321{
322	struct ads7924_data *data = iio_priv(indio_dev);
323
324	if (data->reset_gpio) {
325		gpiod_set_value(data->reset_gpio, 1); /* Assert. */
326		/* Educated guess: assert time not specified in datasheet... */
327		mdelay(100);
328		gpiod_set_value(data->reset_gpio, 0); /* Deassert. */
329		return 0;
330	}
331
332	/*
333	 * A write of 10101010 to this register will generate a
334	 * software reset of the ADS7924.
335	 */
336	return regmap_write(data->regmap, ADS7924_RESET_REG, 0b10101010);
337};
338
339static void ads7924_reg_disable(void *data)
340{
341	regulator_disable(data);
342}
343
344static void ads7924_set_idle_mode(void *data)
345{
346	ads7924_set_conv_mode(data, ADS7924_MODECNTRL_IDLE);
347}
348
349static int ads7924_probe(struct i2c_client *client)
350{
351	struct iio_dev *indio_dev;
352	struct ads7924_data *data;
353	struct device *dev = &client->dev;
354	int ret;
355
356	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
357	if (!indio_dev)
358		return -ENOMEM;
359
360	data = iio_priv(indio_dev);
361
362	data->dev = dev;
363
364	/* Initialize the reset GPIO as output with an initial value of 0. */
365	data->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
366	if (IS_ERR(data->reset_gpio))
367		return dev_err_probe(dev, PTR_ERR(data->reset_gpio),
368				     "failed to get request reset GPIO\n");
369
370	mutex_init(&data->lock);
371
372	indio_dev->name = "ads7924";
373	indio_dev->modes = INDIO_DIRECT_MODE;
374
375	indio_dev->channels = ads7924_channels;
376	indio_dev->num_channels = ARRAY_SIZE(ads7924_channels);
377	indio_dev->info = &ads7924_info;
378
379	ret = ads7924_get_channels_config(dev);
380	if (ret < 0)
381		return dev_err_probe(dev, ret,
382				     "failed to get channels configuration\n");
383
384	data->regmap = devm_regmap_init_i2c(client, &ads7924_regmap_config);
385	if (IS_ERR(data->regmap))
386		return dev_err_probe(dev, PTR_ERR(data->regmap),
387				     "failed to init regmap\n");
388
389	data->vref_reg = devm_regulator_get(dev, "vref");
390	if (IS_ERR(data->vref_reg))
391		return dev_err_probe(dev, PTR_ERR(data->vref_reg),
392				     "failed to get vref regulator\n");
393
394	ret = regulator_enable(data->vref_reg);
395	if (ret)
396		return dev_err_probe(dev, ret,
397				     "failed to enable regulator\n");
398
399	ret = devm_add_action_or_reset(dev, ads7924_reg_disable, data->vref_reg);
400	if (ret)
401		return ret;
402
403	ret = ads7924_reset(indio_dev);
404	if (ret < 0)
405		return dev_err_probe(dev, ret,
406				     "failed to reset device\n");
407
408	ret = ads7924_set_conv_mode(data, ADS7924_MODECNTRL_AUTO_SCAN);
409	if (ret)
410		return dev_err_probe(dev, ret,
411				     "failed to set conversion mode\n");
412
413	ret = devm_add_action_or_reset(dev, ads7924_set_idle_mode, data);
414	if (ret)
415		return ret;
416
417	/* Use minimum signal acquire time. */
418	ret = regmap_update_bits(data->regmap, ADS7924_ACQCONFIG_REG,
419				 ADS7924_ACQTIME_MASK,
420				 FIELD_PREP(ADS7924_ACQTIME_MASK, 0));
421	if (ret < 0)
422		return dev_err_probe(dev, ret,
423				     "failed to configure signal acquire time\n");
424
425	/* Disable power-up time. */
426	ret = regmap_update_bits(data->regmap, ADS7924_PWRCONFIG_REG,
427				 ADS7924_PWRUPTIME_MASK,
428				 FIELD_PREP(ADS7924_PWRUPTIME_MASK, 0));
429	if (ret < 0)
430		return dev_err_probe(dev, ret,
431				     "failed to configure power-up time\n");
432
433	data->conv_invalid = true;
434
435	ret = devm_iio_device_register(dev, indio_dev);
436	if (ret < 0)
437		return dev_err_probe(dev, ret,
438				     "failed to register IIO device\n");
439
440	return 0;
441}
442
443static const struct i2c_device_id ads7924_id[] = {
444	{ "ads7924" },
445	{ }
446};
447MODULE_DEVICE_TABLE(i2c, ads7924_id);
448
449static const struct of_device_id ads7924_of_match[] = {
450	{ .compatible = "ti,ads7924", },
451	{ }
452};
453MODULE_DEVICE_TABLE(of, ads7924_of_match);
454
455static struct i2c_driver ads7924_driver = {
456	.driver = {
457		.name = "ads7924",
458		.of_match_table = ads7924_of_match,
459	},
460	.probe		= ads7924_probe,
461	.id_table	= ads7924_id,
462};
463
464module_i2c_driver(ads7924_driver);
465
466MODULE_AUTHOR("Hugo Villeneuve <hvilleneuve@dimonoff.com>");
467MODULE_DESCRIPTION("Texas Instruments ADS7924 ADC I2C driver");
468MODULE_LICENSE("GPL");