ti-ads131e08.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Texas Instruments ADS131E0x 4-, 6- and 8-Channel ADCs
  4 *
  5 * Copyright (c) 2020 AVL DiTEST GmbH
  6 *   Tomislav Denis <tomislav.denis@avl.com>
  7 *
  8 * Datasheet: https://www.ti.com/lit/ds/symlink/ads131e08.pdf
  9 */
 10
 11#include <linux/bitfield.h>
 12#include <linux/clk.h>
 13#include <linux/delay.h>
 14#include <linux/module.h>
 15
 16#include <linux/iio/buffer.h>
 17#include <linux/iio/iio.h>
 18#include <linux/iio/sysfs.h>
 19#include <linux/iio/trigger.h>
 20#include <linux/iio/trigger_consumer.h>
 21#include <linux/iio/triggered_buffer.h>
 22
 23#include <linux/regulator/consumer.h>
 24#include <linux/spi/spi.h>
 25
 26#include <linux/unaligned.h>
 27
 28/* Commands */
 29#define ADS131E08_CMD_RESET		0x06
 30#define ADS131E08_CMD_START		0x08
 31#define ADS131E08_CMD_STOP		0x0A
 32#define ADS131E08_CMD_OFFSETCAL		0x1A
 33#define ADS131E08_CMD_SDATAC		0x11
 34#define ADS131E08_CMD_RDATA		0x12
 35#define ADS131E08_CMD_RREG(r)		(BIT(5) | (r & GENMASK(4, 0)))
 36#define ADS131E08_CMD_WREG(r)		(BIT(6) | (r & GENMASK(4, 0)))
 37
 38/* Registers */
 39#define ADS131E08_ADR_CFG1R		0x01
 40#define ADS131E08_ADR_CFG3R		0x03
 41#define ADS131E08_ADR_CH0R		0x05
 42
 43/* Configuration register 1 */
 44#define ADS131E08_CFG1R_DR_MASK		GENMASK(2, 0)
 45
 46/* Configuration register 3 */
 47#define ADS131E08_CFG3R_PDB_REFBUF_MASK	BIT(7)
 48#define ADS131E08_CFG3R_VREF_4V_MASK	BIT(5)
 49
 50/* Channel settings register */
 51#define ADS131E08_CHR_GAIN_MASK		GENMASK(6, 4)
 52#define ADS131E08_CHR_MUX_MASK		GENMASK(2, 0)
 53#define ADS131E08_CHR_PWD_MASK		BIT(7)
 54
 55/* ADC  misc */
 56#define ADS131E08_DEFAULT_DATA_RATE	1
 57#define ADS131E08_DEFAULT_PGA_GAIN	1
 58#define ADS131E08_DEFAULT_MUX		0
 59
 60#define ADS131E08_VREF_2V4_mV		2400
 61#define ADS131E08_VREF_4V_mV		4000
 62
 63#define ADS131E08_WAIT_RESET_CYCLES	18
 64#define ADS131E08_WAIT_SDECODE_CYCLES	4
 65#define ADS131E08_WAIT_OFFSETCAL_MS	153
 66#define ADS131E08_MAX_SETTLING_TIME_MS	6
 67
 68#define ADS131E08_NUM_STATUS_BYTES	3
 69#define ADS131E08_NUM_DATA_BYTES_MAX	24
 70#define ADS131E08_NUM_DATA_BYTES(dr)	(((dr) >= 32) ? 2 : 3)
 71#define ADS131E08_NUM_DATA_BITS(dr)	(ADS131E08_NUM_DATA_BYTES(dr) * 8)
 72#define ADS131E08_NUM_STORAGE_BYTES	4
 73
 74enum ads131e08_ids {
 75	ads131e04,
 76	ads131e06,
 77	ads131e08,
 78};
 79
 80struct ads131e08_info {
 81	unsigned int max_channels;
 82	const char *name;
 83};
 84
 85struct ads131e08_channel_config {
 86	unsigned int pga_gain;
 87	unsigned int mux;
 88};
 89
 90struct ads131e08_state {
 91	const struct ads131e08_info *info;
 92	struct spi_device *spi;
 93	struct iio_trigger *trig;
 94	struct clk *adc_clk;
 95	struct regulator *vref_reg;
 96	struct ads131e08_channel_config *channel_config;
 97	unsigned int data_rate;
 98	unsigned int vref_mv;
 99	unsigned int sdecode_delay_us;
100	unsigned int reset_delay_us;
101	unsigned int readback_len;
102	struct completion completion;
103	struct {
104		u8 data[ADS131E08_NUM_DATA_BYTES_MAX];
105		aligned_s64 ts;
106	} tmp_buf;
107
108	u8 tx_buf[3] __aligned(IIO_DMA_MINALIGN);
109	/*
110	 * Add extra one padding byte to be able to access the last channel
111	 * value using u32 pointer
112	 */
113	u8 rx_buf[ADS131E08_NUM_STATUS_BYTES +
114		ADS131E08_NUM_DATA_BYTES_MAX + 1];
115};
116
117static const struct ads131e08_info ads131e08_info_tbl[] = {
118	[ads131e04] = {
119		.max_channels = 4,
120		.name = "ads131e04",
121	},
122	[ads131e06] = {
123		.max_channels = 6,
124		.name = "ads131e06",
125	},
126	[ads131e08] = {
127		.max_channels = 8,
128		.name = "ads131e08",
129	},
130};
131
132struct ads131e08_data_rate_desc {
133	unsigned int rate;  /* data rate in kSPS */
134	u8 reg;             /* reg value */
135};
136
137static const struct ads131e08_data_rate_desc ads131e08_data_rate_tbl[] = {
138	{ .rate = 64,   .reg = 0x00 },
139	{ .rate = 32,   .reg = 0x01 },
140	{ .rate = 16,   .reg = 0x02 },
141	{ .rate = 8,    .reg = 0x03 },
142	{ .rate = 4,    .reg = 0x04 },
143	{ .rate = 2,    .reg = 0x05 },
144	{ .rate = 1,    .reg = 0x06 },
145};
146
147struct ads131e08_pga_gain_desc {
148	unsigned int gain;  /* PGA gain value */
149	u8 reg;             /* field value */
150};
151
152static const struct ads131e08_pga_gain_desc ads131e08_pga_gain_tbl[] = {
153	{ .gain = 1,   .reg = 0x01 },
154	{ .gain = 2,   .reg = 0x02 },
155	{ .gain = 4,   .reg = 0x04 },
156	{ .gain = 8,   .reg = 0x05 },
157	{ .gain = 12,  .reg = 0x06 },
158};
159
160static const u8 ads131e08_valid_channel_mux_values[] = { 0, 1, 3, 4 };
161
162static int ads131e08_exec_cmd(struct ads131e08_state *st, u8 cmd)
163{
164	int ret;
165
166	ret = spi_write_then_read(st->spi, &cmd, 1, NULL, 0);
167	if (ret)
168		dev_err(&st->spi->dev, "Exec cmd(%02x) failed\n", cmd);
169
170	return ret;
171}
172
173static int ads131e08_read_reg(struct ads131e08_state *st, u8 reg)
174{
175	int ret;
176	struct spi_transfer transfer[] = {
177		{
178			.tx_buf = &st->tx_buf,
179			.len = 2,
180			.delay = {
181				.value = st->sdecode_delay_us,
182				.unit = SPI_DELAY_UNIT_USECS,
183			},
184		}, {
185			.rx_buf = &st->rx_buf,
186			.len = 1,
187		},
188	};
189
190	st->tx_buf[0] = ADS131E08_CMD_RREG(reg);
191	st->tx_buf[1] = 0;
192
193	ret = spi_sync_transfer(st->spi, transfer, ARRAY_SIZE(transfer));
194	if (ret) {
195		dev_err(&st->spi->dev, "Read register failed\n");
196		return ret;
197	}
198
199	return st->rx_buf[0];
200}
201
202static int ads131e08_write_reg(struct ads131e08_state *st, u8 reg, u8 value)
203{
204	int ret;
205	struct spi_transfer transfer[] = {
206		{
207			.tx_buf = &st->tx_buf,
208			.len = 3,
209			.delay = {
210				.value = st->sdecode_delay_us,
211				.unit = SPI_DELAY_UNIT_USECS,
212			},
213		}
214	};
215
216	st->tx_buf[0] = ADS131E08_CMD_WREG(reg);
217	st->tx_buf[1] = 0;
218	st->tx_buf[2] = value;
219
220	ret = spi_sync_transfer(st->spi, transfer, ARRAY_SIZE(transfer));
221	if (ret)
222		dev_err(&st->spi->dev, "Write register failed\n");
223
224	return ret;
225}
226
227static int ads131e08_read_data(struct ads131e08_state *st, int rx_len)
228{
229	int ret;
230	struct spi_transfer transfer[] = {
231		{
232			.tx_buf = &st->tx_buf,
233			.len = 1,
234		}, {
235			.rx_buf = &st->rx_buf,
236			.len = rx_len,
237		},
238	};
239
240	st->tx_buf[0] = ADS131E08_CMD_RDATA;
241
242	ret = spi_sync_transfer(st->spi, transfer, ARRAY_SIZE(transfer));
243	if (ret)
244		dev_err(&st->spi->dev, "Read data failed\n");
245
246	return ret;
247}
248
249static int ads131e08_set_data_rate(struct ads131e08_state *st, int data_rate)
250{
251	int i, reg, ret;
252
253	for (i = 0; i < ARRAY_SIZE(ads131e08_data_rate_tbl); i++) {
254		if (ads131e08_data_rate_tbl[i].rate == data_rate)
255			break;
256	}
257
258	if (i == ARRAY_SIZE(ads131e08_data_rate_tbl)) {
259		dev_err(&st->spi->dev, "invalid data rate value\n");
260		return -EINVAL;
261	}
262
263	reg = ads131e08_read_reg(st, ADS131E08_ADR_CFG1R);
264	if (reg < 0)
265		return reg;
266
267	reg &= ~ADS131E08_CFG1R_DR_MASK;
268	reg |= FIELD_PREP(ADS131E08_CFG1R_DR_MASK,
269		ads131e08_data_rate_tbl[i].reg);
270
271	ret = ads131e08_write_reg(st, ADS131E08_ADR_CFG1R, reg);
272	if (ret)
273		return ret;
274
275	st->data_rate = data_rate;
276	st->readback_len = ADS131E08_NUM_STATUS_BYTES +
277		ADS131E08_NUM_DATA_BYTES(st->data_rate) *
278		st->info->max_channels;
279
280	return 0;
281}
282
283static int ads131e08_pga_gain_to_field_value(struct ads131e08_state *st,
284	unsigned int pga_gain)
285{
286	int i;
287
288	for (i = 0; i < ARRAY_SIZE(ads131e08_pga_gain_tbl); i++) {
289		if (ads131e08_pga_gain_tbl[i].gain == pga_gain)
290			break;
291	}
292
293	if (i == ARRAY_SIZE(ads131e08_pga_gain_tbl)) {
294		dev_err(&st->spi->dev, "invalid PGA gain value\n");
295		return -EINVAL;
296	}
297
298	return ads131e08_pga_gain_tbl[i].reg;
299}
300
301static int ads131e08_set_pga_gain(struct ads131e08_state *st,
302	unsigned int channel, unsigned int pga_gain)
303{
304	int field_value, reg;
305
306	field_value = ads131e08_pga_gain_to_field_value(st, pga_gain);
307	if (field_value < 0)
308		return field_value;
309
310	reg = ads131e08_read_reg(st, ADS131E08_ADR_CH0R + channel);
311	if (reg < 0)
312		return reg;
313
314	reg &= ~ADS131E08_CHR_GAIN_MASK;
315	reg |= FIELD_PREP(ADS131E08_CHR_GAIN_MASK, field_value);
316
317	return ads131e08_write_reg(st, ADS131E08_ADR_CH0R + channel, reg);
318}
319
320static int ads131e08_validate_channel_mux(struct ads131e08_state *st,
321	unsigned int mux)
322{
323	int i;
324
325	for (i = 0; i < ARRAY_SIZE(ads131e08_valid_channel_mux_values); i++) {
326		if (ads131e08_valid_channel_mux_values[i] == mux)
327			break;
328	}
329
330	if (i == ARRAY_SIZE(ads131e08_valid_channel_mux_values)) {
331		dev_err(&st->spi->dev, "invalid channel mux value\n");
332		return -EINVAL;
333	}
334
335	return 0;
336}
337
338static int ads131e08_set_channel_mux(struct ads131e08_state *st,
339	unsigned int channel, unsigned int mux)
340{
341	int reg;
342
343	reg = ads131e08_read_reg(st, ADS131E08_ADR_CH0R + channel);
344	if (reg < 0)
345		return reg;
346
347	reg &= ~ADS131E08_CHR_MUX_MASK;
348	reg |= FIELD_PREP(ADS131E08_CHR_MUX_MASK, mux);
349
350	return ads131e08_write_reg(st, ADS131E08_ADR_CH0R + channel, reg);
351}
352
353static int ads131e08_power_down_channel(struct ads131e08_state *st,
354	unsigned int channel, bool value)
355{
356	int reg;
357
358	reg = ads131e08_read_reg(st, ADS131E08_ADR_CH0R + channel);
359	if (reg < 0)
360		return reg;
361
362	reg &= ~ADS131E08_CHR_PWD_MASK;
363	reg |= FIELD_PREP(ADS131E08_CHR_PWD_MASK, value);
364
365	return ads131e08_write_reg(st, ADS131E08_ADR_CH0R + channel, reg);
366}
367
368static int ads131e08_config_reference_voltage(struct ads131e08_state *st)
369{
370	int reg;
371
372	reg = ads131e08_read_reg(st, ADS131E08_ADR_CFG3R);
373	if (reg < 0)
374		return reg;
375
376	reg &= ~ADS131E08_CFG3R_PDB_REFBUF_MASK;
377	if (!st->vref_reg) {
378		reg |= FIELD_PREP(ADS131E08_CFG3R_PDB_REFBUF_MASK, 1);
379		reg &= ~ADS131E08_CFG3R_VREF_4V_MASK;
380		reg |= FIELD_PREP(ADS131E08_CFG3R_VREF_4V_MASK,
381			st->vref_mv == ADS131E08_VREF_4V_mV);
382	}
383
384	return ads131e08_write_reg(st, ADS131E08_ADR_CFG3R, reg);
385}
386
387static int ads131e08_initial_config(struct iio_dev *indio_dev)
388{
389	const struct iio_chan_spec *channel = indio_dev->channels;
390	struct ads131e08_state *st = iio_priv(indio_dev);
391	unsigned long active_channels = 0;
392	int ret, i;
393
394	ret = ads131e08_exec_cmd(st, ADS131E08_CMD_RESET);
395	if (ret)
396		return ret;
397
398	udelay(st->reset_delay_us);
399
400	/* Disable read data in continuous mode (enabled by default) */
401	ret = ads131e08_exec_cmd(st, ADS131E08_CMD_SDATAC);
402	if (ret)
403		return ret;
404
405	ret = ads131e08_set_data_rate(st, ADS131E08_DEFAULT_DATA_RATE);
406	if (ret)
407		return ret;
408
409	ret = ads131e08_config_reference_voltage(st);
410	if (ret)
411		return ret;
412
413	for (i = 0;  i < indio_dev->num_channels; i++) {
414		ret = ads131e08_set_pga_gain(st, channel->channel,
415			st->channel_config[i].pga_gain);
416		if (ret)
417			return ret;
418
419		ret = ads131e08_set_channel_mux(st, channel->channel,
420			st->channel_config[i].mux);
421		if (ret)
422			return ret;
423
424		active_channels |= BIT(channel->channel);
425		channel++;
426	}
427
428	/* Power down unused channels */
429	for_each_clear_bit(i, &active_channels, st->info->max_channels) {
430		ret = ads131e08_power_down_channel(st, i, true);
431		if (ret)
432			return ret;
433	}
434
435	/* Request channel offset calibration */
436	ret = ads131e08_exec_cmd(st, ADS131E08_CMD_OFFSETCAL);
437	if (ret)
438		return ret;
439
440	/*
441	 * Channel offset calibration is triggered with the first START
442	 * command. Since calibration takes more time than settling operation,
443	 * this causes timeout error when command START is sent first
444	 * time (e.g. first call of the ads131e08_read_direct method).
445	 * To avoid this problem offset calibration is triggered here.
446	 */
447	ret = ads131e08_exec_cmd(st, ADS131E08_CMD_START);
448	if (ret)
449		return ret;
450
451	msleep(ADS131E08_WAIT_OFFSETCAL_MS);
452
453	return ads131e08_exec_cmd(st, ADS131E08_CMD_STOP);
454}
455
456static int ads131e08_pool_data(struct ads131e08_state *st)
457{
458	unsigned long timeout;
459	int ret;
460
461	reinit_completion(&st->completion);
462
463	ret = ads131e08_exec_cmd(st, ADS131E08_CMD_START);
464	if (ret)
465		return ret;
466
467	timeout = msecs_to_jiffies(ADS131E08_MAX_SETTLING_TIME_MS);
468	ret = wait_for_completion_timeout(&st->completion, timeout);
469	if (!ret)
470		return -ETIMEDOUT;
471
472	ret = ads131e08_read_data(st, st->readback_len);
473	if (ret)
474		return ret;
475
476	return ads131e08_exec_cmd(st, ADS131E08_CMD_STOP);
477}
478
479static int ads131e08_read_direct(struct iio_dev *indio_dev,
480	struct iio_chan_spec const *channel, int *value)
481{
482	struct ads131e08_state *st = iio_priv(indio_dev);
483	u8 num_bits, *src;
484	int ret;
485
486	ret = ads131e08_pool_data(st);
487	if (ret)
488		return ret;
489
490	src = st->rx_buf + ADS131E08_NUM_STATUS_BYTES +
491		channel->channel * ADS131E08_NUM_DATA_BYTES(st->data_rate);
492
493	num_bits = ADS131E08_NUM_DATA_BITS(st->data_rate);
494	*value = sign_extend32(get_unaligned_be32(src) >> (32 - num_bits), num_bits - 1);
495
496	return 0;
497}
498
499static int ads131e08_read_raw(struct iio_dev *indio_dev,
500	struct iio_chan_spec const *channel, int *value,
501	int *value2, long mask)
502{
503	struct ads131e08_state *st = iio_priv(indio_dev);
504	int ret;
505
506	switch (mask) {
507	case IIO_CHAN_INFO_RAW:
508		if (!iio_device_claim_direct(indio_dev))
509			return -EBUSY;
510
511		ret = ads131e08_read_direct(indio_dev, channel, value);
512		iio_device_release_direct(indio_dev);
513		if (ret)
514			return ret;
515
516		return IIO_VAL_INT;
517
518	case IIO_CHAN_INFO_SCALE:
519		if (st->vref_reg) {
520			ret = regulator_get_voltage(st->vref_reg);
521			if (ret < 0)
522				return ret;
523
524			*value = ret / 1000;
525		} else {
526			*value = st->vref_mv;
527		}
528
529		*value /= st->channel_config[channel->address].pga_gain;
530		*value2 = ADS131E08_NUM_DATA_BITS(st->data_rate) - 1;
531
532		return IIO_VAL_FRACTIONAL_LOG2;
533
534	case IIO_CHAN_INFO_SAMP_FREQ:
535		*value = st->data_rate;
536
537		return IIO_VAL_INT;
538
539	default:
540		return -EINVAL;
541	}
542}
543
544static int ads131e08_write_raw(struct iio_dev *indio_dev,
545	struct iio_chan_spec const *channel, int value,
546	int value2, long mask)
547{
548	struct ads131e08_state *st = iio_priv(indio_dev);
549	int ret;
550
551	switch (mask) {
552	case IIO_CHAN_INFO_SAMP_FREQ:
553		if (!iio_device_claim_direct(indio_dev))
554			return -EBUSY;
555
556		ret = ads131e08_set_data_rate(st, value);
557		iio_device_release_direct(indio_dev);
558		return ret;
559
560	default:
561		return -EINVAL;
562	}
563}
564
565static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("1 2 4 8 16 32 64");
566
567static struct attribute *ads131e08_attributes[] = {
568	&iio_const_attr_sampling_frequency_available.dev_attr.attr,
569	NULL
570};
571
572static const struct attribute_group ads131e08_attribute_group = {
573	.attrs = ads131e08_attributes,
574};
575
576static int ads131e08_debugfs_reg_access(struct iio_dev *indio_dev,
577	unsigned int reg, unsigned int writeval, unsigned int *readval)
578{
579	struct ads131e08_state *st = iio_priv(indio_dev);
580
581	if (readval) {
582		int ret = ads131e08_read_reg(st, reg);
583		*readval = ret;
584		return ret;
585	}
586
587	return ads131e08_write_reg(st, reg, writeval);
588}
589
590static const struct iio_info ads131e08_iio_info = {
591	.read_raw = ads131e08_read_raw,
592	.write_raw = ads131e08_write_raw,
593	.attrs = &ads131e08_attribute_group,
594	.debugfs_reg_access = &ads131e08_debugfs_reg_access,
595};
596
597static int ads131e08_set_trigger_state(struct iio_trigger *trig, bool state)
598{
599	struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
600	struct ads131e08_state *st = iio_priv(indio_dev);
601	u8 cmd = state ? ADS131E08_CMD_START : ADS131E08_CMD_STOP;
602
603	return ads131e08_exec_cmd(st, cmd);
604}
605
606static const struct iio_trigger_ops ads131e08_trigger_ops = {
607	.set_trigger_state = &ads131e08_set_trigger_state,
608	.validate_device = &iio_trigger_validate_own_device,
609};
610
611static irqreturn_t ads131e08_trigger_handler(int irq, void *private)
612{
613	struct iio_poll_func *pf = private;
614	struct iio_dev *indio_dev = pf->indio_dev;
615	struct ads131e08_state *st = iio_priv(indio_dev);
616	unsigned int chn, i = 0;
617	u8 *src, *dest;
618	int ret;
619
620	/*
621	 * The number of data bits per channel depends on the data rate.
622	 * For 32 and 64 ksps data rates, number of data bits per channel
623	 * is 16. This case is not compliant with used (fixed) scan element
624	 * type (be:s24/32>>8). So we use a little tweak to pack properly
625	 * 16 bits of data into the buffer.
626	 */
627	unsigned int num_bytes = ADS131E08_NUM_DATA_BYTES(st->data_rate);
628	u8 tweak_offset = num_bytes == 2 ? 1 : 0;
629
630	if (iio_trigger_using_own(indio_dev))
631		ret = ads131e08_read_data(st, st->readback_len);
632	else
633		ret = ads131e08_pool_data(st);
634
635	if (ret)
636		goto out;
637
638	iio_for_each_active_channel(indio_dev, chn) {
639		src = st->rx_buf + ADS131E08_NUM_STATUS_BYTES + chn * num_bytes;
640		dest = st->tmp_buf.data + i * ADS131E08_NUM_STORAGE_BYTES;
641
642		/*
643		 * Tweak offset is 0:
644		 * +---+---+---+---+
645		 * |D0 |D1 |D2 | X | (3 data bytes)
646		 * +---+---+---+---+
647		 *  a+0 a+1 a+2 a+3
648		 *
649		 * Tweak offset is 1:
650		 * +---+---+---+---+
651		 * |P0 |D0 |D1 | X | (one padding byte and 2 data bytes)
652		 * +---+---+---+---+
653		 *  a+0 a+1 a+2 a+3
654		 */
655		memcpy(dest + tweak_offset, src, num_bytes);
656
657		/*
658		 * Data conversion from 16 bits of data to 24 bits of data
659		 * is done by sign extension (properly filling padding byte).
660		 */
661		if (tweak_offset)
662			*dest = *src & BIT(7) ? 0xff : 0x00;
663
664		i++;
665	}
666
667	iio_push_to_buffers_with_ts(indio_dev, &st->tmp_buf, sizeof(st->tmp_buf),
668				    iio_get_time_ns(indio_dev));
669
670out:
671	iio_trigger_notify_done(indio_dev->trig);
672
673	return IRQ_HANDLED;
674}
675
676static irqreturn_t ads131e08_interrupt(int irq, void *private)
677{
678	struct iio_dev *indio_dev = private;
679	struct ads131e08_state *st = iio_priv(indio_dev);
680
681	if (iio_buffer_enabled(indio_dev) && iio_trigger_using_own(indio_dev))
682		iio_trigger_poll(st->trig);
683	else
684		complete(&st->completion);
685
686	return IRQ_HANDLED;
687}
688
689static int ads131e08_alloc_channels(struct iio_dev *indio_dev)
690{
691	struct ads131e08_state *st = iio_priv(indio_dev);
692	struct ads131e08_channel_config *channel_config;
693	struct device *dev = &st->spi->dev;
694	struct iio_chan_spec *channels;
695	unsigned int channel, tmp;
696	int num_channels, i, ret;
697
698	ret = device_property_read_u32(dev, "ti,vref-internal", &tmp);
699	if (ret)
700		tmp = 0;
701
702	switch (tmp) {
703	case 0:
704		st->vref_mv = ADS131E08_VREF_2V4_mV;
705		break;
706	case 1:
707		st->vref_mv = ADS131E08_VREF_4V_mV;
708		break;
709	default:
710		dev_err(&st->spi->dev, "invalid internal voltage reference\n");
711		return -EINVAL;
712	}
713
714	num_channels = device_get_child_node_count(dev);
715	if (num_channels == 0) {
716		dev_err(&st->spi->dev, "no channel children\n");
717		return -ENODEV;
718	}
719
720	if (num_channels > st->info->max_channels) {
721		dev_err(&st->spi->dev, "num of channel children out of range\n");
722		return -EINVAL;
723	}
724
725	channels = devm_kcalloc(&st->spi->dev, num_channels,
726		sizeof(*channels), GFP_KERNEL);
727	if (!channels)
728		return -ENOMEM;
729
730	channel_config = devm_kcalloc(&st->spi->dev, num_channels,
731		sizeof(*channel_config), GFP_KERNEL);
732	if (!channel_config)
733		return -ENOMEM;
734
735	i = 0;
736	device_for_each_child_node_scoped(dev, node) {
737		ret = fwnode_property_read_u32(node, "reg", &channel);
738		if (ret)
739			return ret;
740
741		ret = fwnode_property_read_u32(node, "ti,gain", &tmp);
742		if (ret) {
743			channel_config[i].pga_gain = ADS131E08_DEFAULT_PGA_GAIN;
744		} else {
745			ret = ads131e08_pga_gain_to_field_value(st, tmp);
746			if (ret < 0)
747				return ret;
748
749			channel_config[i].pga_gain = tmp;
750		}
751
752		ret = fwnode_property_read_u32(node, "ti,mux", &tmp);
753		if (ret) {
754			channel_config[i].mux = ADS131E08_DEFAULT_MUX;
755		} else {
756			ret = ads131e08_validate_channel_mux(st, tmp);
757			if (ret)
758				return ret;
759
760			channel_config[i].mux = tmp;
761		}
762
763		channels[i].type = IIO_VOLTAGE;
764		channels[i].indexed = 1;
765		channels[i].channel = channel;
766		channels[i].address = i;
767		channels[i].info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
768						BIT(IIO_CHAN_INFO_SCALE);
769		channels[i].info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ);
770		channels[i].scan_index = channel;
771		channels[i].scan_type.sign = 's';
772		channels[i].scan_type.realbits = 24;
773		channels[i].scan_type.storagebits = 32;
774		channels[i].scan_type.shift = 8;
775		channels[i].scan_type.endianness = IIO_BE;
776		i++;
777	}
778
779	indio_dev->channels = channels;
780	indio_dev->num_channels = num_channels;
781	st->channel_config = channel_config;
782
783	return 0;
784
785}
786
787static void ads131e08_regulator_disable(void *data)
788{
789	struct ads131e08_state *st = data;
790
791	regulator_disable(st->vref_reg);
792}
793
794static int ads131e08_probe(struct spi_device *spi)
795{
796	const struct ads131e08_info *info;
797	struct ads131e08_state *st;
798	struct iio_dev *indio_dev;
799	unsigned long adc_clk_hz;
800	unsigned long adc_clk_ns;
801	int ret;
802
803	info = spi_get_device_match_data(spi);
804	if (!info) {
805		dev_err(&spi->dev, "failed to get match data\n");
806		return -ENODEV;
807	}
808
809	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
810	if (!indio_dev)
811		return -ENOMEM;
812
813	st = iio_priv(indio_dev);
814	st->info = info;
815	st->spi = spi;
816
817	ret = ads131e08_alloc_channels(indio_dev);
818	if (ret)
819		return ret;
820
821	indio_dev->name = st->info->name;
822	indio_dev->info = &ads131e08_iio_info;
823	indio_dev->modes = INDIO_DIRECT_MODE;
824
825	init_completion(&st->completion);
826
827	if (spi->irq) {
828		ret = devm_request_irq(&spi->dev, spi->irq,
829			ads131e08_interrupt,
830			IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
831			spi->dev.driver->name, indio_dev);
832		if (ret)
833			return dev_err_probe(&spi->dev, ret,
834					     "request irq failed\n");
835	} else {
836		dev_err(&spi->dev, "data ready IRQ missing\n");
837		return -ENODEV;
838	}
839
840	st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-dev%d",
841		indio_dev->name, iio_device_id(indio_dev));
842	if (!st->trig)
843		return -ENOMEM;
844
845	st->trig->ops = &ads131e08_trigger_ops;
846	st->trig->dev.parent = &spi->dev;
847	iio_trigger_set_drvdata(st->trig, indio_dev);
848	ret = devm_iio_trigger_register(&spi->dev, st->trig);
849	if (ret) {
850		dev_err(&spi->dev, "failed to register IIO trigger\n");
851		return ret;
852	}
853
854	indio_dev->trig = iio_trigger_get(st->trig);
855
856	ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
857		NULL, &ads131e08_trigger_handler, NULL);
858	if (ret) {
859		dev_err(&spi->dev, "failed to setup IIO buffer\n");
860		return ret;
861	}
862
863	st->vref_reg = devm_regulator_get_optional(&spi->dev, "vref");
864	if (!IS_ERR(st->vref_reg)) {
865		ret = regulator_enable(st->vref_reg);
866		if (ret) {
867			dev_err(&spi->dev,
868				"failed to enable external vref supply\n");
869			return ret;
870		}
871
872		ret = devm_add_action_or_reset(&spi->dev, ads131e08_regulator_disable, st);
873		if (ret)
874			return ret;
875	} else {
876		if (PTR_ERR(st->vref_reg) != -ENODEV)
877			return PTR_ERR(st->vref_reg);
878
879		st->vref_reg = NULL;
880	}
881
882	st->adc_clk = devm_clk_get_enabled(&spi->dev, "adc-clk");
883	if (IS_ERR(st->adc_clk))
884		return dev_err_probe(&spi->dev, PTR_ERR(st->adc_clk),
885				     "failed to get the ADC clock\n");
886
887	adc_clk_hz = clk_get_rate(st->adc_clk);
888	if (!adc_clk_hz) {
889		dev_err(&spi->dev, "failed to get the ADC clock rate\n");
890		return  -EINVAL;
891	}
892
893	adc_clk_ns = NSEC_PER_SEC / adc_clk_hz;
894	st->sdecode_delay_us = DIV_ROUND_UP(
895		ADS131E08_WAIT_SDECODE_CYCLES * adc_clk_ns, NSEC_PER_USEC);
896	st->reset_delay_us = DIV_ROUND_UP(
897		ADS131E08_WAIT_RESET_CYCLES * adc_clk_ns, NSEC_PER_USEC);
898
899	ret = ads131e08_initial_config(indio_dev);
900	if (ret) {
901		dev_err(&spi->dev, "initial configuration failed\n");
902		return ret;
903	}
904
905	return devm_iio_device_register(&spi->dev, indio_dev);
906}
907
908static const struct of_device_id ads131e08_of_match[] = {
909	{ .compatible = "ti,ads131e04",
910	  .data = &ads131e08_info_tbl[ads131e04], },
911	{ .compatible = "ti,ads131e06",
912	  .data = &ads131e08_info_tbl[ads131e06], },
913	{ .compatible = "ti,ads131e08",
914	  .data = &ads131e08_info_tbl[ads131e08], },
915	{ }
916};
917MODULE_DEVICE_TABLE(of, ads131e08_of_match);
918
919static const struct spi_device_id ads131e08_ids[] = {
920	{ "ads131e04", (kernel_ulong_t)&ads131e08_info_tbl[ads131e04] },
921	{ "ads131e06", (kernel_ulong_t)&ads131e08_info_tbl[ads131e06] },
922	{ "ads131e08", (kernel_ulong_t)&ads131e08_info_tbl[ads131e08] },
923	{ }
924};
925MODULE_DEVICE_TABLE(spi, ads131e08_ids);
926
927static struct spi_driver ads131e08_driver = {
928	.driver = {
929		.name = "ads131e08",
930		.of_match_table = ads131e08_of_match,
931	},
932	.probe = ads131e08_probe,
933	.id_table = ads131e08_ids,
934};
935module_spi_driver(ads131e08_driver);
936
937MODULE_AUTHOR("Tomislav Denis <tomislav.denis@avl.com>");
938MODULE_DESCRIPTION("Driver for ADS131E0x ADC family");
939MODULE_LICENSE("GPL v2");