stm32-dfsdm-adc.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * This file is the ADC part of the STM32 DFSDM driver
   4 *
   5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
   6 * Author: Arnaud Pouliquen <arnaud.pouliquen@st.com>.
   7 */
   8
   9#include <linux/dmaengine.h>
  10#include <linux/dma-mapping.h>
  11#include <linux/export.h>
  12#include <linux/iio/adc/stm32-dfsdm-adc.h>
  13#include <linux/iio/backend.h>
  14#include <linux/iio/buffer.h>
  15#include <linux/iio/hw-consumer.h>
  16#include <linux/iio/sysfs.h>
  17#include <linux/iio/timer/stm32-lptim-trigger.h>
  18#include <linux/iio/timer/stm32-timer-trigger.h>
  19#include <linux/iio/trigger.h>
  20#include <linux/iio/trigger_consumer.h>
  21#include <linux/iio/triggered_buffer.h>
  22#include <linux/interrupt.h>
  23#include <linux/module.h>
  24#include <linux/of.h>
  25#include <linux/of_platform.h>
  26#include <linux/platform_device.h>
  27#include <linux/regmap.h>
  28#include <linux/slab.h>
  29
  30#include "stm32-dfsdm.h"
  31
  32#define DFSDM_DMA_BUFFER_SIZE (4 * PAGE_SIZE)
  33
  34/* Conversion timeout */
  35#define DFSDM_TIMEOUT_US 100000
  36#define DFSDM_TIMEOUT (msecs_to_jiffies(DFSDM_TIMEOUT_US / 1000))
  37
  38/* Oversampling attribute default */
  39#define DFSDM_DEFAULT_OVERSAMPLING  100
  40
  41/* Oversampling max values */
  42#define DFSDM_MAX_INT_OVERSAMPLING 256
  43#define DFSDM_MAX_FL_OVERSAMPLING 1024
  44
  45/* Limit filter output resolution to 31 bits. (i.e. sample range is +/-2^30) */
  46#define DFSDM_DATA_MAX BIT(30)
  47/*
  48 * Data are output as two's complement data in a 24 bit field.
  49 * Data from filters are in the range +/-2^(n-1)
  50 * 2^(n-1) maximum positive value cannot be coded in 2's complement n bits
  51 * An extra bit is required to avoid wrap-around of the binary code for 2^(n-1)
  52 * So, the resolution of samples from filter is actually limited to 23 bits
  53 */
  54#define DFSDM_DATA_RES 24
  55
  56/* Filter configuration */
  57#define DFSDM_CR1_CFG_MASK (DFSDM_CR1_RCH_MASK | DFSDM_CR1_RCONT_MASK | \
  58			    DFSDM_CR1_RSYNC_MASK | DFSDM_CR1_JSYNC_MASK | \
  59			    DFSDM_CR1_JSCAN_MASK)
  60
  61enum sd_converter_type {
  62	DFSDM_AUDIO,
  63	DFSDM_IIO,
  64};
  65
  66struct stm32_dfsdm_dev_data {
  67	int type;
  68	int (*init)(struct device *dev, struct iio_dev *indio_dev);
  69	unsigned int num_channels;
  70	const struct regmap_config *regmap_cfg;
  71};
  72
  73struct stm32_dfsdm_adc {
  74	struct stm32_dfsdm *dfsdm;
  75	const struct stm32_dfsdm_dev_data *dev_data;
  76	unsigned int fl_id;
  77	unsigned int nconv;
  78	unsigned long smask;
  79
  80	/* ADC specific */
  81	unsigned int oversamp;
  82	struct iio_hw_consumer *hwc;
  83	struct iio_backend **backend;
  84	struct completion completion;
  85	u32 *buffer;
  86
  87	/* Audio specific */
  88	unsigned int spi_freq;  /* SPI bus clock frequency */
  89	unsigned int sample_freq; /* Sample frequency after filter decimation */
  90	int (*cb)(const void *data, size_t size, void *cb_priv);
  91	void *cb_priv;
  92
  93	/* DMA */
  94	u8 *rx_buf;
  95	unsigned int bufi; /* Buffer current position */
  96	unsigned int buf_sz; /* Buffer size */
  97	struct dma_chan	*dma_chan;
  98	dma_addr_t dma_buf;
  99};
 100
 101struct stm32_dfsdm_str2field {
 102	const char	*name;
 103	unsigned int	val;
 104};
 105
 106/* DFSDM channel serial interface type */
 107static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_type[] = {
 108	{ "SPI_R", 0 }, /* SPI with data on rising edge */
 109	{ "SPI_F", 1 }, /* SPI with data on falling edge */
 110	{ "MANCH_R", 2 }, /* Manchester codec, rising edge = logic 0 */
 111	{ "MANCH_F", 3 }, /* Manchester codec, falling edge = logic 1 */
 112	{ }
 113};
 114
 115/* DFSDM channel clock source */
 116static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_src[] = {
 117	/* External SPI clock (CLKIN x) */
 118	{ "CLKIN", DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL },
 119	/* Internal SPI clock (CLKOUT) */
 120	{ "CLKOUT", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL },
 121	/* Internal SPI clock divided by 2 (falling edge) */
 122	{ "CLKOUT_F", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING },
 123	/* Internal SPI clock divided by 2 (falling edge) */
 124	{ "CLKOUT_R", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING },
 125	{ }
 126};
 127
 128static int stm32_dfsdm_str2val(const char *str,
 129			       const struct stm32_dfsdm_str2field *list)
 130{
 131	const struct stm32_dfsdm_str2field *p = list;
 132
 133	for (p = list; p && p->name; p++)
 134		if (!strcmp(p->name, str))
 135			return p->val;
 136
 137	return -EINVAL;
 138}
 139
 140/**
 141 * struct stm32_dfsdm_trig_info - DFSDM trigger info
 142 * @name:		name of the trigger, corresponding to its source
 143 * @jextsel:		trigger signal selection
 144 */
 145struct stm32_dfsdm_trig_info {
 146	const char *name;
 147	unsigned int jextsel;
 148};
 149
 150/* hardware injected trigger enable, edge selection */
 151enum stm32_dfsdm_jexten {
 152	STM32_DFSDM_JEXTEN_DISABLED,
 153	STM32_DFSDM_JEXTEN_RISING_EDGE,
 154	STM32_DFSDM_JEXTEN_FALLING_EDGE,
 155	STM32_DFSDM_EXTEN_BOTH_EDGES,
 156};
 157
 158static const struct stm32_dfsdm_trig_info stm32_dfsdm_trigs[] = {
 159	{ TIM1_TRGO, 0 },
 160	{ TIM1_TRGO2, 1 },
 161	{ TIM8_TRGO, 2 },
 162	{ TIM8_TRGO2, 3 },
 163	{ TIM3_TRGO, 4 },
 164	{ TIM4_TRGO, 5 },
 165	{ TIM16_OC1, 6 },
 166	{ TIM6_TRGO, 7 },
 167	{ TIM7_TRGO, 8 },
 168	{ LPTIM1_OUT, 26 },
 169	{ LPTIM2_OUT, 27 },
 170	{ LPTIM3_OUT, 28 },
 171	{ }
 172};
 173
 174static int stm32_dfsdm_get_jextsel(struct iio_dev *indio_dev,
 175				   struct iio_trigger *trig)
 176{
 177	int i;
 178
 179	/* lookup triggers registered by stm32 timer trigger driver */
 180	for (i = 0; stm32_dfsdm_trigs[i].name; i++) {
 181		/**
 182		 * Checking both stm32 timer trigger type and trig name
 183		 * should be safe against arbitrary trigger names.
 184		 */
 185		if ((is_stm32_timer_trigger(trig) ||
 186		     is_stm32_lptim_trigger(trig)) &&
 187		    !strcmp(stm32_dfsdm_trigs[i].name, trig->name)) {
 188			return stm32_dfsdm_trigs[i].jextsel;
 189		}
 190	}
 191
 192	return -EINVAL;
 193}
 194
 195static int stm32_dfsdm_compute_osrs(struct stm32_dfsdm_filter *fl,
 196				    unsigned int fast, unsigned int oversamp)
 197{
 198	unsigned int i, d, fosr, iosr;
 199	u64 res, max;
 200	int bits, shift;
 201	unsigned int m = 1;	/* multiplication factor */
 202	unsigned int p = fl->ford;	/* filter order (ford) */
 203	struct stm32_dfsdm_filter_osr *flo = &fl->flo[fast];
 204
 205	pr_debug("Requested oversampling: %d\n", oversamp);
 206	/*
 207	 * This function tries to compute filter oversampling and integrator
 208	 * oversampling, base on oversampling ratio requested by user.
 209	 *
 210	 * Decimation d depends on the filter order and the oversampling ratios.
 211	 * ford: filter order
 212	 * fosr: filter over sampling ratio
 213	 * iosr: integrator over sampling ratio
 214	 */
 215	if (fl->ford == DFSDM_FASTSINC_ORDER) {
 216		m = 2;
 217		p = 2;
 218	}
 219
 220	/*
 221	 * Look for filter and integrator oversampling ratios which allows
 222	 * to maximize data output resolution.
 223	 */
 224	for (fosr = 1; fosr <= DFSDM_MAX_FL_OVERSAMPLING; fosr++) {
 225		for (iosr = 1; iosr <= DFSDM_MAX_INT_OVERSAMPLING; iosr++) {
 226			if (fast)
 227				d = fosr * iosr;
 228			else if (fl->ford == DFSDM_FASTSINC_ORDER)
 229				d = fosr * (iosr + 3) + 2;
 230			else
 231				d = fosr * (iosr - 1 + p) + p;
 232
 233			if (d > oversamp)
 234				break;
 235			else if (d != oversamp)
 236				continue;
 237			/*
 238			 * Check resolution (limited to signed 32 bits)
 239			 *   res <= 2^31
 240			 * Sincx filters:
 241			 *   res = m * fosr^p x iosr (with m=1, p=ford)
 242			 * FastSinc filter
 243			 *   res = m * fosr^p x iosr (with m=2, p=2)
 244			 */
 245			res = fosr;
 246			for (i = p - 1; i > 0; i--) {
 247				res = res * (u64)fosr;
 248				if (res > DFSDM_DATA_MAX)
 249					break;
 250			}
 251			if (res > DFSDM_DATA_MAX)
 252				continue;
 253
 254			res = res * (u64)m * (u64)iosr;
 255			if (res > DFSDM_DATA_MAX)
 256				continue;
 257
 258			if (res >= flo->res) {
 259				flo->res = res;
 260				flo->fosr = fosr;
 261				flo->iosr = iosr;
 262
 263				bits = fls(flo->res);
 264				/* 8 LBSs in data register contain chan info */
 265				max = flo->res << 8;
 266
 267				/* if resolution is not a power of two */
 268				if (flo->res > BIT(bits - 1))
 269					bits++;
 270				else
 271					max--;
 272
 273				shift = DFSDM_DATA_RES - bits;
 274				/*
 275				 * Compute right/left shift
 276				 * Right shift is performed by hardware
 277				 * when transferring samples to data register.
 278				 * Left shift is done by software on buffer
 279				 */
 280				if (shift > 0) {
 281					/* Resolution is lower than 24 bits */
 282					flo->rshift = 0;
 283					flo->lshift = shift;
 284				} else {
 285					/*
 286					 * If resolution is 24 bits or more,
 287					 * max positive value may be ambiguous
 288					 * (equal to max negative value as sign
 289					 * bit is dropped).
 290					 * Reduce resolution to 23 bits (rshift)
 291					 * to keep the sign on bit 23 and treat
 292					 * saturation before rescaling on 24
 293					 * bits (lshift).
 294					 */
 295					flo->rshift = 1 - shift;
 296					flo->lshift = 1;
 297					max >>= flo->rshift;
 298				}
 299				flo->max = (s32)max;
 300				flo->bits = bits;
 301
 302				pr_debug("fast %d, fosr %d, iosr %d, res 0x%llx/%d bits, rshift %d, lshift %d\n",
 303					 fast, flo->fosr, flo->iosr,
 304					 flo->res, bits, flo->rshift,
 305					 flo->lshift);
 306			}
 307		}
 308	}
 309
 310	if (!flo->res)
 311		return -EINVAL;
 312
 313	return 0;
 314}
 315
 316static int stm32_dfsdm_compute_all_osrs(struct iio_dev *indio_dev,
 317					unsigned int oversamp)
 318{
 319	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 320	struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
 321	int ret0, ret1;
 322
 323	memset(&fl->flo[0], 0, sizeof(fl->flo[0]));
 324	memset(&fl->flo[1], 0, sizeof(fl->flo[1]));
 325
 326	ret0 = stm32_dfsdm_compute_osrs(fl, 0, oversamp);
 327	ret1 = stm32_dfsdm_compute_osrs(fl, 1, oversamp);
 328	if (ret0 < 0 && ret1 < 0) {
 329		dev_err(&indio_dev->dev,
 330			"Filter parameters not found: errors %d/%d\n",
 331			ret0, ret1);
 332		return -EINVAL;
 333	}
 334
 335	return 0;
 336}
 337
 338static int stm32_dfsdm_start_channel(struct iio_dev *indio_dev)
 339{
 340	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 341	struct regmap *regmap = adc->dfsdm->regmap;
 342	const struct iio_chan_spec *chan;
 343	unsigned int bit;
 344	int ret;
 345
 346	for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) {
 347		chan = indio_dev->channels + bit;
 348		ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(chan->channel),
 349					 DFSDM_CHCFGR1_CHEN_MASK,
 350					 DFSDM_CHCFGR1_CHEN(1));
 351		if (ret < 0)
 352			return ret;
 353	}
 354
 355	return 0;
 356}
 357
 358static void stm32_dfsdm_stop_channel(struct iio_dev *indio_dev)
 359{
 360	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 361	struct regmap *regmap = adc->dfsdm->regmap;
 362	const struct iio_chan_spec *chan;
 363	unsigned int bit;
 364
 365	for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) {
 366		chan = indio_dev->channels + bit;
 367		regmap_update_bits(regmap, DFSDM_CHCFGR1(chan->channel),
 368				   DFSDM_CHCFGR1_CHEN_MASK,
 369				   DFSDM_CHCFGR1_CHEN(0));
 370	}
 371}
 372
 373static int stm32_dfsdm_chan_configure(struct stm32_dfsdm *dfsdm,
 374				      struct stm32_dfsdm_channel *ch)
 375{
 376	unsigned int id = ch->id;
 377	struct regmap *regmap = dfsdm->regmap;
 378	int ret;
 379
 380	ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
 381				 DFSDM_CHCFGR1_SITP_MASK,
 382				 DFSDM_CHCFGR1_SITP(ch->type));
 383	if (ret < 0)
 384		return ret;
 385	ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
 386				 DFSDM_CHCFGR1_SPICKSEL_MASK,
 387				 DFSDM_CHCFGR1_SPICKSEL(ch->src));
 388	if (ret < 0)
 389		return ret;
 390	return regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
 391				  DFSDM_CHCFGR1_CHINSEL_MASK,
 392				  DFSDM_CHCFGR1_CHINSEL(ch->alt_si));
 393}
 394
 395static int stm32_dfsdm_start_filter(struct stm32_dfsdm_adc *adc,
 396				    unsigned int fl_id,
 397				    struct iio_trigger *trig)
 398{
 399	struct stm32_dfsdm *dfsdm = adc->dfsdm;
 400	int ret;
 401
 402	/* Enable filter */
 403	ret = regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
 404				 DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(1));
 405	if (ret < 0)
 406		return ret;
 407
 408	/* Nothing more to do for injected (scan mode/triggered) conversions */
 409	if (adc->nconv > 1 || trig)
 410		return 0;
 411
 412	/* Software start (single or continuous) regular conversion */
 413	return regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
 414				  DFSDM_CR1_RSWSTART_MASK,
 415				  DFSDM_CR1_RSWSTART(1));
 416}
 417
 418static void stm32_dfsdm_stop_filter(struct stm32_dfsdm *dfsdm,
 419				    unsigned int fl_id)
 420{
 421	/* Disable conversion */
 422	regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
 423			   DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(0));
 424}
 425
 426static int stm32_dfsdm_filter_set_trig(struct iio_dev *indio_dev,
 427				       unsigned int fl_id,
 428				       struct iio_trigger *trig)
 429{
 430	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 431	struct regmap *regmap = adc->dfsdm->regmap;
 432	u32 jextsel = 0, jexten = STM32_DFSDM_JEXTEN_DISABLED;
 433	int ret;
 434
 435	if (trig) {
 436		ret = stm32_dfsdm_get_jextsel(indio_dev, trig);
 437		if (ret < 0)
 438			return ret;
 439
 440		/* set trigger source and polarity (default to rising edge) */
 441		jextsel = ret;
 442		jexten = STM32_DFSDM_JEXTEN_RISING_EDGE;
 443	}
 444
 445	ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id),
 446				 DFSDM_CR1_JEXTSEL_MASK | DFSDM_CR1_JEXTEN_MASK,
 447				 DFSDM_CR1_JEXTSEL(jextsel) |
 448				 DFSDM_CR1_JEXTEN(jexten));
 449	if (ret < 0)
 450		return ret;
 451
 452	return 0;
 453}
 454
 455static int stm32_dfsdm_channels_configure(struct iio_dev *indio_dev,
 456					  unsigned int fl_id,
 457					  struct iio_trigger *trig)
 458{
 459	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 460	struct regmap *regmap = adc->dfsdm->regmap;
 461	struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[fl_id];
 462	struct stm32_dfsdm_filter_osr *flo = &fl->flo[0];
 463	const struct iio_chan_spec *chan;
 464	unsigned int bit;
 465	int ret;
 466
 467	fl->fast = 0;
 468
 469	/*
 470	 * In continuous mode, use fast mode configuration,
 471	 * if it provides a better resolution.
 472	 */
 473	if (adc->nconv == 1 && !trig && iio_buffer_enabled(indio_dev)) {
 474		if (fl->flo[1].res >= fl->flo[0].res) {
 475			fl->fast = 1;
 476			flo = &fl->flo[1];
 477		}
 478	}
 479
 480	if (!flo->res)
 481		return -EINVAL;
 482
 483	dev_dbg(&indio_dev->dev, "Samples actual resolution: %d bits",
 484		min(flo->bits, (u32)DFSDM_DATA_RES - 1));
 485
 486	for_each_set_bit(bit, &adc->smask,
 487			 sizeof(adc->smask) * BITS_PER_BYTE) {
 488		chan = indio_dev->channels + bit;
 489
 490		ret = regmap_update_bits(regmap,
 491					 DFSDM_CHCFGR2(chan->channel),
 492					 DFSDM_CHCFGR2_DTRBS_MASK,
 493					 DFSDM_CHCFGR2_DTRBS(flo->rshift));
 494		if (ret)
 495			return ret;
 496	}
 497
 498	return 0;
 499}
 500
 501static int stm32_dfsdm_filter_configure(struct iio_dev *indio_dev,
 502					unsigned int fl_id,
 503					struct iio_trigger *trig)
 504{
 505	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 506	struct regmap *regmap = adc->dfsdm->regmap;
 507	struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[fl_id];
 508	struct stm32_dfsdm_filter_osr *flo = &fl->flo[fl->fast];
 509	u32 cr1;
 510	const struct iio_chan_spec *chan;
 511	unsigned int bit, jchg = 0;
 512	int ret;
 513
 514	/* Average integrator oversampling */
 515	ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_IOSR_MASK,
 516				 DFSDM_FCR_IOSR(flo->iosr - 1));
 517	if (ret)
 518		return ret;
 519
 520	/* Filter order and Oversampling */
 521	ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FOSR_MASK,
 522				 DFSDM_FCR_FOSR(flo->fosr - 1));
 523	if (ret)
 524		return ret;
 525
 526	ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FORD_MASK,
 527				 DFSDM_FCR_FORD(fl->ford));
 528	if (ret)
 529		return ret;
 530
 531	ret = stm32_dfsdm_filter_set_trig(indio_dev, fl_id, trig);
 532	if (ret)
 533		return ret;
 534
 535	ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id),
 536				 DFSDM_CR1_FAST_MASK,
 537				 DFSDM_CR1_FAST(fl->fast));
 538	if (ret)
 539		return ret;
 540
 541	/*
 542	 * DFSDM modes configuration W.R.T audio/iio type modes
 543	 * ----------------------------------------------------------------
 544	 * Modes         | regular |  regular     | injected | injected   |
 545	 *               |         |  continuous  |          | + scan     |
 546	 * --------------|---------|--------------|----------|------------|
 547	 * single conv   |    x    |              |          |            |
 548	 * (1 chan)      |         |              |          |            |
 549	 * --------------|---------|--------------|----------|------------|
 550	 * 1 Audio chan	 |         | sample freq  |          |            |
 551	 *               |         | or sync_mode |          |            |
 552	 * --------------|---------|--------------|----------|------------|
 553	 * 1 IIO chan	 |         | sample freq  | trigger  |            |
 554	 *               |         | or sync_mode |          |            |
 555	 * --------------|---------|--------------|----------|------------|
 556	 * 2+ IIO chans  |         |              |          | trigger or |
 557	 *               |         |              |          | sync_mode  |
 558	 * ----------------------------------------------------------------
 559	 */
 560	if (adc->nconv == 1 && !trig) {
 561		bit = __ffs(adc->smask);
 562		chan = indio_dev->channels + bit;
 563
 564		/* Use regular conversion for single channel without trigger */
 565		cr1 = DFSDM_CR1_RCH(chan->channel);
 566
 567		/* Continuous conversions triggered by SPI clk in buffer mode */
 568		if (iio_buffer_enabled(indio_dev))
 569			cr1 |= DFSDM_CR1_RCONT(1);
 570
 571		cr1 |= DFSDM_CR1_RSYNC(fl->sync_mode);
 572	} else {
 573		/* Use injected conversion for multiple channels */
 574		for_each_set_bit(bit, &adc->smask,
 575				 sizeof(adc->smask) * BITS_PER_BYTE) {
 576			chan = indio_dev->channels + bit;
 577			jchg |= BIT(chan->channel);
 578		}
 579		ret = regmap_write(regmap, DFSDM_JCHGR(fl_id), jchg);
 580		if (ret < 0)
 581			return ret;
 582
 583		/* Use scan mode for multiple channels */
 584		cr1 = DFSDM_CR1_JSCAN((adc->nconv > 1) ? 1 : 0);
 585
 586		/*
 587		 * Continuous conversions not supported in injected mode,
 588		 * either use:
 589		 * - conversions in sync with filter 0
 590		 * - triggered conversions
 591		 */
 592		if (!fl->sync_mode && !trig)
 593			return -EINVAL;
 594		cr1 |= DFSDM_CR1_JSYNC(fl->sync_mode);
 595	}
 596
 597	return regmap_update_bits(regmap, DFSDM_CR1(fl_id), DFSDM_CR1_CFG_MASK,
 598				  cr1);
 599}
 600
 601static int stm32_dfsdm_channel_parse_of(struct stm32_dfsdm *dfsdm,
 602					struct iio_dev *indio_dev,
 603					struct iio_chan_spec *ch)
 604{
 605	struct stm32_dfsdm_channel *df_ch;
 606	const char *of_str;
 607	int chan_idx = ch->scan_index;
 608	int ret, val;
 609
 610	ret = of_property_read_u32_index(indio_dev->dev.of_node,
 611					 "st,adc-channels", chan_idx,
 612					 &ch->channel);
 613	if (ret < 0) {
 614		dev_err(&indio_dev->dev,
 615			" Error parsing 'st,adc-channels' for idx %d\n",
 616			chan_idx);
 617		return ret;
 618	}
 619	if (ch->channel >= dfsdm->num_chs) {
 620		dev_err(&indio_dev->dev,
 621			" Error bad channel number %d (max = %d)\n",
 622			ch->channel, dfsdm->num_chs);
 623		return -EINVAL;
 624	}
 625
 626	ret = of_property_read_string_index(indio_dev->dev.of_node,
 627					    "st,adc-channel-names", chan_idx,
 628					    &ch->datasheet_name);
 629	if (ret < 0) {
 630		dev_err(&indio_dev->dev,
 631			" Error parsing 'st,adc-channel-names' for idx %d\n",
 632			chan_idx);
 633		return ret;
 634	}
 635
 636	df_ch =  &dfsdm->ch_list[ch->channel];
 637	df_ch->id = ch->channel;
 638
 639	ret = of_property_read_string_index(indio_dev->dev.of_node,
 640					    "st,adc-channel-types", chan_idx,
 641					    &of_str);
 642	if (!ret) {
 643		val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_type);
 644		if (val < 0)
 645			return val;
 646	} else {
 647		val = 0;
 648	}
 649	df_ch->type = val;
 650
 651	ret = of_property_read_string_index(indio_dev->dev.of_node,
 652					    "st,adc-channel-clk-src", chan_idx,
 653					    &of_str);
 654	if (!ret) {
 655		val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_src);
 656		if (val < 0)
 657			return val;
 658	} else {
 659		val = 0;
 660	}
 661	df_ch->src = val;
 662
 663	ret = of_property_read_u32_index(indio_dev->dev.of_node,
 664					 "st,adc-alt-channel", chan_idx,
 665					 &df_ch->alt_si);
 666	if (ret < 0)
 667		df_ch->alt_si = 0;
 668
 669	return 0;
 670}
 671
 672static int stm32_dfsdm_generic_channel_parse_of(struct stm32_dfsdm *dfsdm,
 673						struct iio_dev *indio_dev,
 674						struct iio_chan_spec *ch,
 675						struct fwnode_handle *node)
 676{
 677	struct stm32_dfsdm_channel *df_ch;
 678	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 679	struct iio_backend *backend;
 680	const char *of_str;
 681	int ret, val;
 682
 683	ret = fwnode_property_read_u32(node, "reg", &ch->channel);
 684	if (ret < 0) {
 685		dev_err(&indio_dev->dev, "Missing channel index %d\n", ret);
 686		return ret;
 687	}
 688
 689	if (ch->channel >= dfsdm->num_chs) {
 690		dev_err(&indio_dev->dev, " Error bad channel number %d (max = %d)\n",
 691			ch->channel, dfsdm->num_chs);
 692		return -EINVAL;
 693	}
 694
 695	if (fwnode_property_present(node, "label")) {
 696		/* label is optional */
 697		ret = fwnode_property_read_string(node, "label", &ch->datasheet_name);
 698		if (ret < 0) {
 699			dev_err(&indio_dev->dev,
 700				" Error parsing 'label' for idx %d\n", ch->channel);
 701			return ret;
 702		}
 703	}
 704
 705	df_ch =  &dfsdm->ch_list[ch->channel];
 706	df_ch->id = ch->channel;
 707
 708	ret = fwnode_property_read_string(node, "st,adc-channel-type", &of_str);
 709	if (!ret) {
 710		val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_type);
 711		if (val < 0)
 712			return val;
 713	} else {
 714		val = 0;
 715	}
 716	df_ch->type = val;
 717
 718	ret = fwnode_property_read_string(node, "st,adc-channel-clk-src", &of_str);
 719	if (!ret) {
 720		val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_src);
 721		if (val < 0)
 722			return val;
 723	} else {
 724		val = 0;
 725	}
 726	df_ch->src = val;
 727
 728	if (fwnode_property_present(node, "st,adc-alt-channel"))
 729		df_ch->alt_si = 1;
 730
 731	if (adc->dev_data->type == DFSDM_IIO) {
 732		backend = devm_iio_backend_fwnode_get(&indio_dev->dev, NULL, node);
 733		if (IS_ERR(backend))
 734			return dev_err_probe(&indio_dev->dev, PTR_ERR(backend),
 735					     "Failed to get backend\n");
 736		adc->backend[ch->scan_index] = backend;
 737	}
 738
 739	return 0;
 740}
 741
 742static ssize_t dfsdm_adc_audio_get_spiclk(struct iio_dev *indio_dev,
 743					  uintptr_t priv,
 744					  const struct iio_chan_spec *chan,
 745					  char *buf)
 746{
 747	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 748
 749	return snprintf(buf, PAGE_SIZE, "%d\n", adc->spi_freq);
 750}
 751
 752static int dfsdm_adc_set_samp_freq(struct iio_dev *indio_dev,
 753				   unsigned int sample_freq,
 754				   unsigned int spi_freq)
 755{
 756	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 757	unsigned int oversamp;
 758	int ret;
 759
 760	oversamp = DIV_ROUND_CLOSEST(spi_freq, sample_freq);
 761	if (spi_freq % sample_freq)
 762		dev_dbg(&indio_dev->dev,
 763			"Rate not accurate. requested (%u), actual (%u)\n",
 764			sample_freq, spi_freq / oversamp);
 765
 766	ret = stm32_dfsdm_compute_all_osrs(indio_dev, oversamp);
 767	if (ret < 0)
 768		return ret;
 769
 770	adc->sample_freq = spi_freq / oversamp;
 771	adc->oversamp = oversamp;
 772
 773	return 0;
 774}
 775
 776static ssize_t dfsdm_adc_audio_set_spiclk(struct iio_dev *indio_dev,
 777					  uintptr_t priv,
 778					  const struct iio_chan_spec *chan,
 779					  const char *buf, size_t len)
 780{
 781	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 782	struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
 783	unsigned int sample_freq = adc->sample_freq;
 784	unsigned int spi_freq;
 785	int ret;
 786
 787	dev_err(&indio_dev->dev, "enter %s\n", __func__);
 788	/* If DFSDM is master on SPI, SPI freq can not be updated */
 789	if (ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
 790		return -EPERM;
 791
 792	ret = kstrtoint(buf, 0, &spi_freq);
 793	if (ret)
 794		return ret;
 795
 796	if (!spi_freq)
 797		return -EINVAL;
 798
 799	if (sample_freq) {
 800		ret = dfsdm_adc_set_samp_freq(indio_dev, sample_freq, spi_freq);
 801		if (ret < 0)
 802			return ret;
 803	}
 804	adc->spi_freq = spi_freq;
 805
 806	return len;
 807}
 808
 809static int stm32_dfsdm_start_conv(struct iio_dev *indio_dev,
 810				  struct iio_trigger *trig)
 811{
 812	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 813	struct regmap *regmap = adc->dfsdm->regmap;
 814	int ret;
 815
 816	ret = stm32_dfsdm_channels_configure(indio_dev, adc->fl_id, trig);
 817	if (ret < 0)
 818		return ret;
 819
 820	ret = stm32_dfsdm_start_channel(indio_dev);
 821	if (ret < 0)
 822		return ret;
 823
 824	ret = stm32_dfsdm_filter_configure(indio_dev, adc->fl_id, trig);
 825	if (ret < 0)
 826		goto stop_channels;
 827
 828	ret = stm32_dfsdm_start_filter(adc, adc->fl_id, trig);
 829	if (ret < 0)
 830		goto filter_unconfigure;
 831
 832	return 0;
 833
 834filter_unconfigure:
 835	regmap_clear_bits(regmap, DFSDM_CR1(adc->fl_id), DFSDM_CR1_CFG_MASK);
 836stop_channels:
 837	stm32_dfsdm_stop_channel(indio_dev);
 838
 839	return ret;
 840}
 841
 842static void stm32_dfsdm_stop_conv(struct iio_dev *indio_dev)
 843{
 844	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 845	struct regmap *regmap = adc->dfsdm->regmap;
 846
 847	stm32_dfsdm_stop_filter(adc->dfsdm, adc->fl_id);
 848
 849	regmap_clear_bits(regmap, DFSDM_CR1(adc->fl_id), DFSDM_CR1_CFG_MASK);
 850
 851	stm32_dfsdm_stop_channel(indio_dev);
 852}
 853
 854static int stm32_dfsdm_set_watermark(struct iio_dev *indio_dev,
 855				     unsigned int val)
 856{
 857	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 858	unsigned int watermark = DFSDM_DMA_BUFFER_SIZE / 2;
 859	unsigned int rx_buf_sz = DFSDM_DMA_BUFFER_SIZE;
 860
 861	/*
 862	 * DMA cyclic transfers are used, buffer is split into two periods.
 863	 * There should be :
 864	 * - always one buffer (period) DMA is working on
 865	 * - one buffer (period) driver pushed to ASoC side.
 866	 */
 867	watermark = min(watermark, val * (unsigned int)(sizeof(u32)));
 868	adc->buf_sz = min(rx_buf_sz, watermark * 2 * adc->nconv);
 869
 870	return 0;
 871}
 872
 873static unsigned int stm32_dfsdm_adc_dma_residue(struct stm32_dfsdm_adc *adc)
 874{
 875	struct dma_tx_state state;
 876	enum dma_status status;
 877
 878	status = dmaengine_tx_status(adc->dma_chan,
 879				     adc->dma_chan->cookie,
 880				     &state);
 881	if (status == DMA_IN_PROGRESS) {
 882		/* Residue is size in bytes from end of buffer */
 883		unsigned int i = adc->buf_sz - state.residue;
 884		unsigned int size;
 885
 886		/* Return available bytes */
 887		if (i >= adc->bufi)
 888			size = i - adc->bufi;
 889		else
 890			size = adc->buf_sz + i - adc->bufi;
 891
 892		return size;
 893	}
 894
 895	return 0;
 896}
 897
 898static inline void stm32_dfsdm_process_data(struct stm32_dfsdm_adc *adc,
 899					    s32 *buffer)
 900{
 901	struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
 902	struct stm32_dfsdm_filter_osr *flo = &fl->flo[fl->fast];
 903	unsigned int i = adc->nconv;
 904	s32 *ptr = buffer;
 905
 906	while (i--) {
 907		/* Mask 8 LSB that contains the channel ID */
 908		*ptr &= 0xFFFFFF00;
 909		/* Convert 2^(n-1) sample to 2^(n-1)-1 to avoid wrap-around */
 910		if (*ptr > flo->max)
 911			*ptr -= 1;
 912		/*
 913		 * Samples from filter are retrieved with 23 bits resolution
 914		 * or less. Shift left to align MSB on 24 bits.
 915		 */
 916		*ptr <<= flo->lshift;
 917
 918		ptr++;
 919	}
 920}
 921
 922static void stm32_dfsdm_dma_buffer_done(void *data)
 923{
 924	struct iio_dev *indio_dev = data;
 925	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 926	int available = stm32_dfsdm_adc_dma_residue(adc);
 927	size_t old_pos;
 928
 929	/*
 930	 * FIXME: In Kernel interface does not support cyclic DMA buffer,and
 931	 * offers only an interface to push data samples per samples.
 932	 * For this reason IIO buffer interface is not used and interface is
 933	 * bypassed using a private callback registered by ASoC.
 934	 * This should be a temporary solution waiting a cyclic DMA engine
 935	 * support in IIO.
 936	 */
 937
 938	dev_dbg(&indio_dev->dev, "pos = %d, available = %d\n",
 939		adc->bufi, available);
 940	old_pos = adc->bufi;
 941
 942	while (available >= indio_dev->scan_bytes) {
 943		s32 *buffer = (s32 *)&adc->rx_buf[adc->bufi];
 944
 945		stm32_dfsdm_process_data(adc, buffer);
 946
 947		available -= indio_dev->scan_bytes;
 948		adc->bufi += indio_dev->scan_bytes;
 949		if (adc->bufi >= adc->buf_sz) {
 950			if (adc->cb)
 951				adc->cb(&adc->rx_buf[old_pos],
 952					 adc->buf_sz - old_pos, adc->cb_priv);
 953			adc->bufi = 0;
 954			old_pos = 0;
 955		}
 956		/*
 957		 * In DMA mode the trigger services of IIO are not used
 958		 * (e.g. no call to iio_trigger_poll).
 959		 * Calling irq handler associated to the hardware trigger is not
 960		 * relevant as the conversions have already been done. Data
 961		 * transfers are performed directly in DMA callback instead.
 962		 * This implementation avoids to call trigger irq handler that
 963		 * may sleep, in an atomic context (DMA irq handler context).
 964		 */
 965		if (adc->dev_data->type == DFSDM_IIO)
 966			iio_push_to_buffers(indio_dev, buffer);
 967	}
 968	if (adc->cb)
 969		adc->cb(&adc->rx_buf[old_pos], adc->bufi - old_pos,
 970			adc->cb_priv);
 971}
 972
 973static int stm32_dfsdm_adc_dma_start(struct iio_dev *indio_dev)
 974{
 975	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
 976	/*
 977	 * The DFSDM supports half-word transfers. However, for 16 bits record,
 978	 * 4 bytes buswidth is kept, to avoid losing samples LSBs when left
 979	 * shift is required.
 980	 */
 981	struct dma_slave_config config = {
 982		.src_addr = (dma_addr_t)adc->dfsdm->phys_base,
 983		.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
 984	};
 985	struct dma_async_tx_descriptor *desc;
 986	dma_cookie_t cookie;
 987	int ret;
 988
 989	if (!adc->dma_chan)
 990		return -EINVAL;
 991
 992	dev_dbg(&indio_dev->dev, "size=%d watermark=%d\n",
 993		adc->buf_sz, adc->buf_sz / 2);
 994
 995	if (adc->nconv == 1 && !indio_dev->trig)
 996		config.src_addr += DFSDM_RDATAR(adc->fl_id);
 997	else
 998		config.src_addr += DFSDM_JDATAR(adc->fl_id);
 999	ret = dmaengine_slave_config(adc->dma_chan, &config);
1000	if (ret)
1001		return ret;
1002
1003	/* Prepare a DMA cyclic transaction */
1004	desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
1005					 adc->dma_buf,
1006					 adc->buf_sz, adc->buf_sz / 2,
1007					 DMA_DEV_TO_MEM,
1008					 DMA_PREP_INTERRUPT);
1009	if (!desc)
1010		return -EBUSY;
1011
1012	desc->callback = stm32_dfsdm_dma_buffer_done;
1013	desc->callback_param = indio_dev;
1014
1015	cookie = dmaengine_submit(desc);
1016	ret = dma_submit_error(cookie);
1017	if (ret)
1018		goto err_stop_dma;
1019
1020	/* Issue pending DMA requests */
1021	dma_async_issue_pending(adc->dma_chan);
1022
1023	if (adc->nconv == 1 && !indio_dev->trig) {
1024		/* Enable regular DMA transfer*/
1025		ret = regmap_set_bits(adc->dfsdm->regmap,
1026				      DFSDM_CR1(adc->fl_id),
1027				      DFSDM_CR1_RDMAEN_MASK);
1028	} else {
1029		/* Enable injected DMA transfer*/
1030		ret = regmap_set_bits(adc->dfsdm->regmap,
1031				      DFSDM_CR1(adc->fl_id),
1032				      DFSDM_CR1_JDMAEN_MASK);
1033	}
1034
1035	if (ret < 0)
1036		goto err_stop_dma;
1037
1038	return 0;
1039
1040err_stop_dma:
1041	dmaengine_terminate_all(adc->dma_chan);
1042
1043	return ret;
1044}
1045
1046static void stm32_dfsdm_adc_dma_stop(struct iio_dev *indio_dev)
1047{
1048	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1049
1050	if (!adc->dma_chan)
1051		return;
1052
1053	regmap_clear_bits(adc->dfsdm->regmap, DFSDM_CR1(adc->fl_id),
1054			  DFSDM_CR1_RDMAEN_MASK | DFSDM_CR1_JDMAEN_MASK);
1055	dmaengine_terminate_all(adc->dma_chan);
1056}
1057
1058static int stm32_dfsdm_update_scan_mode(struct iio_dev *indio_dev,
1059					const unsigned long *scan_mask)
1060{
1061	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1062
1063	adc->nconv = bitmap_weight(scan_mask, iio_get_masklength(indio_dev));
1064	adc->smask = *scan_mask;
1065
1066	dev_dbg(&indio_dev->dev, "nconv=%d mask=%lx\n", adc->nconv, *scan_mask);
1067
1068	return 0;
1069}
1070
1071static int stm32_dfsdm_postenable(struct iio_dev *indio_dev)
1072{
1073	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1074	int i = 0;
1075	int ret;
1076
1077	/* Reset adc buffer index */
1078	adc->bufi = 0;
1079
1080	if (adc->hwc) {
1081		ret = iio_hw_consumer_enable(adc->hwc);
1082		if (ret < 0)
1083			return ret;
1084	}
1085
1086	if (adc->backend) {
1087		while (adc->backend[i]) {
1088			ret = iio_backend_enable(adc->backend[i]);
1089			if (ret < 0)
1090				return ret;
1091			i++;
1092		}
1093	}
1094
1095	ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
1096	if (ret < 0)
1097		goto err_stop_hwc;
1098
1099	ret = stm32_dfsdm_adc_dma_start(indio_dev);
1100	if (ret) {
1101		dev_err(&indio_dev->dev, "Can't start DMA\n");
1102		goto stop_dfsdm;
1103	}
1104
1105	ret = stm32_dfsdm_start_conv(indio_dev, indio_dev->trig);
1106	if (ret) {
1107		dev_err(&indio_dev->dev, "Can't start conversion\n");
1108		goto err_stop_dma;
1109	}
1110
1111	return 0;
1112
1113err_stop_dma:
1114	stm32_dfsdm_adc_dma_stop(indio_dev);
1115stop_dfsdm:
1116	stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1117err_stop_hwc:
1118	if (adc->hwc)
1119		iio_hw_consumer_disable(adc->hwc);
1120
1121	return ret;
1122}
1123
1124static int stm32_dfsdm_predisable(struct iio_dev *indio_dev)
1125{
1126	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1127	int i = 0;
1128
1129	stm32_dfsdm_stop_conv(indio_dev);
1130
1131	stm32_dfsdm_adc_dma_stop(indio_dev);
1132
1133	stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1134
1135	if (adc->backend) {
1136		while (adc->backend[i]) {
1137			iio_backend_disable(adc->backend[i]);
1138			i++;
1139		}
1140	}
1141
1142	if (adc->hwc)
1143		iio_hw_consumer_disable(adc->hwc);
1144
1145	return 0;
1146}
1147
1148static const struct iio_buffer_setup_ops stm32_dfsdm_buffer_setup_ops = {
1149	.postenable = &stm32_dfsdm_postenable,
1150	.predisable = &stm32_dfsdm_predisable,
1151};
1152
1153/**
1154 * stm32_dfsdm_get_buff_cb() - register a callback that will be called when
1155 *                             DMA transfer period is achieved.
1156 *
1157 * @iio_dev: Handle to IIO device.
1158 * @cb: Pointer to callback function:
1159 *      - data: pointer to data buffer
1160 *      - size: size in byte of the data buffer
1161 *      - private: pointer to consumer private structure.
1162 * @private: Pointer to consumer private structure.
1163 */
1164int stm32_dfsdm_get_buff_cb(struct iio_dev *iio_dev,
1165			    int (*cb)(const void *data, size_t size,
1166				      void *private),
1167			    void *private)
1168{
1169	struct stm32_dfsdm_adc *adc;
1170
1171	if (!iio_dev)
1172		return -EINVAL;
1173	adc = iio_priv(iio_dev);
1174
1175	adc->cb = cb;
1176	adc->cb_priv = private;
1177
1178	return 0;
1179}
1180EXPORT_SYMBOL_GPL(stm32_dfsdm_get_buff_cb);
1181
1182/**
1183 * stm32_dfsdm_release_buff_cb - unregister buffer callback
1184 *
1185 * @iio_dev: Handle to IIO device.
1186 */
1187int stm32_dfsdm_release_buff_cb(struct iio_dev *iio_dev)
1188{
1189	struct stm32_dfsdm_adc *adc;
1190
1191	if (!iio_dev)
1192		return -EINVAL;
1193	adc = iio_priv(iio_dev);
1194
1195	adc->cb = NULL;
1196	adc->cb_priv = NULL;
1197
1198	return 0;
1199}
1200EXPORT_SYMBOL_GPL(stm32_dfsdm_release_buff_cb);
1201
1202static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev,
1203				   const struct iio_chan_spec *chan, int *res)
1204{
1205	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1206	long time_left;
1207	int ret;
1208
1209	reinit_completion(&adc->completion);
1210
1211	adc->buffer = res;
1212
1213	ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
1214	if (ret < 0)
1215		return ret;
1216
1217	ret = regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1218				 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(1));
1219	if (ret < 0)
1220		goto stop_dfsdm;
1221
1222	adc->nconv = 1;
1223	adc->smask = BIT(chan->scan_index);
1224	ret = stm32_dfsdm_start_conv(indio_dev, NULL);
1225	if (ret < 0) {
1226		regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1227				   DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
1228		goto stop_dfsdm;
1229	}
1230
1231	time_left = wait_for_completion_interruptible_timeout(&adc->completion,
1232							      DFSDM_TIMEOUT);
1233
1234	/* Mask IRQ for regular conversion achievement*/
1235	regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1236			   DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
1237
1238	if (time_left == 0)
1239		ret = -ETIMEDOUT;
1240	else if (time_left < 0)
1241		ret = time_left;
1242	else
1243		ret = IIO_VAL_INT;
1244
1245	stm32_dfsdm_stop_conv(indio_dev);
1246
1247	stm32_dfsdm_process_data(adc, res);
1248
1249stop_dfsdm:
1250	stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1251
1252	return ret;
1253}
1254
1255static int stm32_dfsdm_write_raw(struct iio_dev *indio_dev,
1256				 struct iio_chan_spec const *chan,
1257				 int val, int val2, long mask)
1258{
1259	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1260	struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
1261	unsigned int spi_freq;
1262	int ret = -EINVAL;
1263
1264	switch (ch->src) {
1265	case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL:
1266		spi_freq = adc->dfsdm->spi_master_freq;
1267		break;
1268	case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING:
1269	case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING:
1270		spi_freq = adc->dfsdm->spi_master_freq / 2;
1271		break;
1272	default:
1273		spi_freq = adc->spi_freq;
1274	}
1275
1276	switch (mask) {
1277	case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1278		if (!iio_device_claim_direct(indio_dev))
1279			return -EBUSY;
1280
1281		ret = stm32_dfsdm_compute_all_osrs(indio_dev, val);
1282		if (!ret) {
1283			dev_dbg(&indio_dev->dev,
1284				"Sampling rate changed from (%u) to (%u)\n",
1285				adc->sample_freq, spi_freq / val);
1286			adc->oversamp = val;
1287			adc->sample_freq = spi_freq / val;
1288		}
1289		iio_device_release_direct(indio_dev);
1290		return ret;
1291
1292	case IIO_CHAN_INFO_SAMP_FREQ:
1293		if (!val)
1294			return -EINVAL;
1295
1296		if (!iio_device_claim_direct(indio_dev))
1297			return -EBUSY;
1298
1299		ret = dfsdm_adc_set_samp_freq(indio_dev, val, spi_freq);
1300		iio_device_release_direct(indio_dev);
1301		return ret;
1302	}
1303
1304	return -EINVAL;
1305}
1306
1307static int __stm32_dfsdm_read_info_raw(struct iio_dev *indio_dev,
1308				       struct iio_chan_spec const *chan,
1309				       int *val)
1310{
1311	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1312	int ret = 0;
1313
1314	if (adc->hwc)
1315		ret = iio_hw_consumer_enable(adc->hwc);
1316	if (adc->backend)
1317		ret = iio_backend_enable(adc->backend[chan->scan_index]);
1318	if (ret < 0) {
1319		dev_err(&indio_dev->dev,
1320			"%s: IIO enable failed (channel %d)\n",
1321			__func__, chan->channel);
1322		return ret;
1323	}
1324	ret = stm32_dfsdm_single_conv(indio_dev, chan, val);
1325	if (adc->hwc)
1326		iio_hw_consumer_disable(adc->hwc);
1327	if (adc->backend)
1328		iio_backend_disable(adc->backend[chan->scan_index]);
1329	if (ret < 0) {
1330		dev_err(&indio_dev->dev,
1331			"%s: Conversion failed (channel %d)\n",
1332			__func__, chan->channel);
1333		return ret;
1334	}
1335
1336	return 0;
1337}
1338
1339static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev,
1340				struct iio_chan_spec const *chan, int *val,
1341				int *val2, long mask)
1342{
1343	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1344
1345	struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
1346	struct stm32_dfsdm_filter_osr *flo = &fl->flo[fl->fast];
1347	u32 max = flo->max << (flo->lshift - chan->scan_type.shift);
1348	int idx = chan->scan_index;
1349	int ret;
1350
1351	if (flo->lshift < chan->scan_type.shift)
1352		max = flo->max >> (chan->scan_type.shift - flo->lshift);
1353
1354	switch (mask) {
1355	case IIO_CHAN_INFO_RAW:
1356		if (!iio_device_claim_direct(indio_dev))
1357			return -EBUSY;
1358
1359		ret = __stm32_dfsdm_read_info_raw(indio_dev, chan, val);
1360		iio_device_release_direct(indio_dev);
1361		if (ret)
1362			return ret;
1363		return IIO_VAL_INT;
1364
1365	case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1366		*val = adc->oversamp;
1367
1368		return IIO_VAL_INT;
1369
1370	case IIO_CHAN_INFO_SAMP_FREQ:
1371		*val = adc->sample_freq;
1372
1373		return IIO_VAL_INT;
1374
1375	case IIO_CHAN_INFO_SCALE:
1376		/*
1377		 * Scale is expressed in mV.
1378		 * When fast mode is disabled, actual resolution may be lower
1379		 * than 2^n, where n = realbits - 1.
1380		 * This leads to underestimating the input voltage.
1381		 * To compensate this deviation, the voltage reference can be
1382		 * corrected with a factor = realbits resolution / actual max
1383		 */
1384		if (adc->backend) {
1385			ret = iio_backend_read_scale(adc->backend[idx], chan, val, NULL);
1386			if (ret < 0)
1387				return ret;
1388
1389			*val = div_u64((u64)*val * (u64)BIT(DFSDM_DATA_RES - 1), max);
1390			*val2 = chan->scan_type.realbits;
1391			if (chan->differential)
1392				*val *= 2;
1393		}
1394		return IIO_VAL_FRACTIONAL_LOG2;
1395
1396	case IIO_CHAN_INFO_OFFSET:
1397		/*
1398		 * DFSDM output data are in the range [-2^n, 2^n],
1399		 * with n = realbits - 1.
1400		 * - Differential modulator:
1401		 * Offset correspond to SD modulator offset.
1402		 * - Single ended modulator:
1403		 * Input is in [0V, Vref] range,
1404		 * where 0V corresponds to -2^n, and Vref to 2^n.
1405		 * Add 2^n to offset. (i.e. middle of input range)
1406		 * offset = offset(sd) * vref / res(sd) * max / vref.
1407		 */
1408		if (adc->backend) {
1409			ret = iio_backend_read_offset(adc->backend[idx], chan, val, NULL);
1410			if (ret < 0)
1411				return ret;
1412
1413			*val = div_u64((u64)max * *val, BIT(*val2 - 1));
1414			if (!chan->differential)
1415				*val += max;
1416		}
1417		return IIO_VAL_INT;
1418	}
1419
1420	return -EINVAL;
1421}
1422
1423static int stm32_dfsdm_validate_trigger(struct iio_dev *indio_dev,
1424					struct iio_trigger *trig)
1425{
1426	return stm32_dfsdm_get_jextsel(indio_dev, trig) < 0 ? -EINVAL : 0;
1427}
1428
1429static const struct iio_info stm32_dfsdm_info_audio = {
1430	.hwfifo_set_watermark = stm32_dfsdm_set_watermark,
1431	.read_raw = stm32_dfsdm_read_raw,
1432	.write_raw = stm32_dfsdm_write_raw,
1433	.update_scan_mode = stm32_dfsdm_update_scan_mode,
1434};
1435
1436static const struct iio_info stm32_dfsdm_info_adc = {
1437	.hwfifo_set_watermark = stm32_dfsdm_set_watermark,
1438	.read_raw = stm32_dfsdm_read_raw,
1439	.write_raw = stm32_dfsdm_write_raw,
1440	.update_scan_mode = stm32_dfsdm_update_scan_mode,
1441	.validate_trigger = stm32_dfsdm_validate_trigger,
1442};
1443
1444static irqreturn_t stm32_dfsdm_irq(int irq, void *arg)
1445{
1446	struct iio_dev *indio_dev = arg;
1447	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1448	struct regmap *regmap = adc->dfsdm->regmap;
1449	unsigned int status, int_en;
1450
1451	regmap_read(regmap, DFSDM_ISR(adc->fl_id), &status);
1452	regmap_read(regmap, DFSDM_CR2(adc->fl_id), &int_en);
1453
1454	if (status & DFSDM_ISR_REOCF_MASK) {
1455		/* Read the data register clean the IRQ status */
1456		regmap_read(regmap, DFSDM_RDATAR(adc->fl_id), adc->buffer);
1457		complete(&adc->completion);
1458	}
1459
1460	if (status & DFSDM_ISR_ROVRF_MASK) {
1461		if (int_en & DFSDM_CR2_ROVRIE_MASK)
1462			dev_warn(&indio_dev->dev, "Overrun detected\n");
1463		regmap_set_bits(regmap, DFSDM_ICR(adc->fl_id),
1464				DFSDM_ICR_CLRROVRF_MASK);
1465	}
1466
1467	return IRQ_HANDLED;
1468}
1469
1470/*
1471 * Define external info for SPI Frequency and audio sampling rate that can be
1472 * configured by ASoC driver through consumer.h API
1473 */
1474static const struct iio_chan_spec_ext_info dfsdm_adc_audio_ext_info[] = {
1475	/* spi_clk_freq : clock freq on SPI/manchester bus used by channel */
1476	{
1477		.name = "spi_clk_freq",
1478		.shared = IIO_SHARED_BY_TYPE,
1479		.read = dfsdm_adc_audio_get_spiclk,
1480		.write = dfsdm_adc_audio_set_spiclk,
1481	},
1482	{ }
1483};
1484
1485static void stm32_dfsdm_dma_release(struct iio_dev *indio_dev)
1486{
1487	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1488
1489	if (adc->dma_chan) {
1490		dma_free_coherent(adc->dma_chan->device->dev,
1491				  DFSDM_DMA_BUFFER_SIZE,
1492				  adc->rx_buf, adc->dma_buf);
1493		dma_release_channel(adc->dma_chan);
1494	}
1495}
1496
1497static int stm32_dfsdm_dma_request(struct device *dev,
1498				   struct iio_dev *indio_dev)
1499{
1500	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1501
1502	adc->dma_chan = dma_request_chan(dev, "rx");
1503	if (IS_ERR(adc->dma_chan)) {
1504		int ret = PTR_ERR(adc->dma_chan);
1505
1506		adc->dma_chan = NULL;
1507		return ret;
1508	}
1509
1510	adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
1511					 DFSDM_DMA_BUFFER_SIZE,
1512					 &adc->dma_buf, GFP_KERNEL);
1513	if (!adc->rx_buf) {
1514		dma_release_channel(adc->dma_chan);
1515		return -ENOMEM;
1516	}
1517
1518	indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1519	indio_dev->setup_ops = &stm32_dfsdm_buffer_setup_ops;
1520
1521	return 0;
1522}
1523
1524static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev, struct iio_chan_spec *ch,
1525					 struct fwnode_handle *child)
1526{
1527	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1528	int ret;
1529
1530	if (child)
1531		ret = stm32_dfsdm_generic_channel_parse_of(adc->dfsdm, indio_dev, ch, child);
1532	else /* Legacy binding */
1533		ret = stm32_dfsdm_channel_parse_of(adc->dfsdm, indio_dev, ch);
1534	if (ret < 0)
1535		return dev_err_probe(&indio_dev->dev, ret, "Failed to parse channel\n");
1536
1537	ch->type = IIO_VOLTAGE;
1538	ch->indexed = 1;
1539
1540	/*
1541	 * IIO_CHAN_INFO_RAW: used to compute regular conversion
1542	 * IIO_CHAN_INFO_OVERSAMPLING_RATIO: used to set oversampling
1543	 */
1544	if (child) {
1545		ch->info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1546					 BIT(IIO_CHAN_INFO_SCALE) |
1547					 BIT(IIO_CHAN_INFO_OFFSET);
1548	} else {
1549		/* Legacy. Scaling not supported */
1550		ch->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
1551	}
1552
1553	ch->info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) |
1554					BIT(IIO_CHAN_INFO_SAMP_FREQ);
1555
1556	if (adc->dev_data->type == DFSDM_AUDIO) {
1557		ch->ext_info = dfsdm_adc_audio_ext_info;
1558		ch->scan_index = 0;
1559	} else {
1560		ch->scan_type.shift = 8;
1561	}
1562	ch->scan_type.sign = 's';
1563	ch->scan_type.realbits = 24;
1564	ch->scan_type.storagebits = 32;
1565
1566	return stm32_dfsdm_chan_configure(adc->dfsdm,
1567					  &adc->dfsdm->ch_list[ch->channel]);
1568}
1569
1570static int stm32_dfsdm_chan_init(struct iio_dev *indio_dev, struct iio_chan_spec *channels)
1571{
1572	int num_ch = indio_dev->num_channels;
1573	int chan_idx = 0;
1574	int ret;
1575
1576	for (chan_idx = 0; chan_idx < num_ch; chan_idx++) {
1577		channels[chan_idx].scan_index = chan_idx;
1578		ret = stm32_dfsdm_adc_chan_init_one(indio_dev, &channels[chan_idx], NULL);
1579		if (ret < 0)
1580			return dev_err_probe(&indio_dev->dev, ret, "Channels init failed\n");
1581	}
1582
1583	return 0;
1584}
1585
1586static int stm32_dfsdm_generic_chan_init(struct iio_dev *indio_dev, struct iio_chan_spec *channels)
1587{
1588	int chan_idx = 0, ret;
1589
1590	device_for_each_child_node_scoped(&indio_dev->dev, child) {
1591		/* Skip DAI node in DFSDM audio nodes */
1592		if (fwnode_property_present(child, "compatible"))
1593			continue;
1594
1595		channels[chan_idx].scan_index = chan_idx;
1596		ret = stm32_dfsdm_adc_chan_init_one(indio_dev, &channels[chan_idx], child);
1597		if (ret < 0)
1598			return dev_err_probe(&indio_dev->dev, ret, "Channels init failed\n");
1599
1600		chan_idx++;
1601	}
1602
1603	return chan_idx;
1604}
1605
1606static int stm32_dfsdm_audio_init(struct device *dev, struct iio_dev *indio_dev)
1607{
1608	struct iio_chan_spec *ch;
1609	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1610	struct stm32_dfsdm_channel *d_ch;
1611	bool legacy = false;
1612	int num_ch, ret;
1613
1614	/* If st,adc-channels is defined legacy binding is used. Else assume generic binding. */
1615	num_ch = of_property_count_u32_elems(indio_dev->dev.of_node, "st,adc-channels");
1616	if (num_ch == 1)
1617		legacy = true;
1618
1619	ch = devm_kzalloc(&indio_dev->dev, sizeof(*ch), GFP_KERNEL);
1620	if (!ch)
1621		return -ENOMEM;
1622
1623	indio_dev->num_channels = 1;
1624	indio_dev->channels = ch;
1625
1626	if (legacy)
1627		ret = stm32_dfsdm_chan_init(indio_dev, ch);
1628	else
1629		ret = stm32_dfsdm_generic_chan_init(indio_dev, ch);
1630
1631	if (ret < 0) {
1632		dev_err(&indio_dev->dev, "Channels init failed\n");
1633		return ret;
1634	}
1635	ch->info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ);
1636
1637	d_ch = &adc->dfsdm->ch_list[ch->channel];
1638	if (d_ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
1639		adc->spi_freq = adc->dfsdm->spi_master_freq;
1640
1641	return stm32_dfsdm_dma_request(dev, indio_dev);
1642}
1643
1644static int stm32_dfsdm_adc_init(struct device *dev, struct iio_dev *indio_dev)
1645{
1646	struct iio_chan_spec *ch;
1647	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1648	int num_ch, ret;
1649	bool legacy = false;
1650
1651	adc->oversamp = DFSDM_DEFAULT_OVERSAMPLING;
1652	ret = stm32_dfsdm_compute_all_osrs(indio_dev, adc->oversamp);
1653	if (ret < 0)
1654		return ret;
1655
1656	num_ch = device_get_child_node_count(&indio_dev->dev);
1657	if (!num_ch) {
1658		/* No channels nodes found. Assume legacy binding */
1659		num_ch = of_property_count_u32_elems(indio_dev->dev.of_node, "st,adc-channels");
1660		if (num_ch < 0) {
1661			dev_err(&indio_dev->dev, "Bad st,adc-channels\n");
1662			return num_ch;
1663		}
1664
1665		legacy = true;
1666	}
1667
1668	if (num_ch > adc->dfsdm->num_chs) {
1669		dev_err(&indio_dev->dev, "Number of channel [%d] exceeds [%d]\n",
1670			num_ch, adc->dfsdm->num_chs);
1671		return -EINVAL;
1672	}
1673	indio_dev->num_channels = num_ch;
1674
1675	if (legacy) {
1676		/* Bind to SD modulator IIO device. */
1677		adc->hwc = devm_iio_hw_consumer_alloc(&indio_dev->dev);
1678		if (IS_ERR(adc->hwc))
1679			return dev_err_probe(&indio_dev->dev, -EPROBE_DEFER,
1680					     "waiting for SD modulator\n");
1681	} else {
1682		/* Generic binding. SD modulator IIO device not used. Use SD modulator backend. */
1683		adc->hwc = NULL;
1684
1685		adc->backend = devm_kcalloc(&indio_dev->dev, num_ch, sizeof(*adc->backend),
1686					    GFP_KERNEL);
1687		if (!adc->backend)
1688			return -ENOMEM;
1689	}
1690
1691	ch = devm_kcalloc(&indio_dev->dev, num_ch, sizeof(*ch), GFP_KERNEL);
1692	if (!ch)
1693		return -ENOMEM;
1694	indio_dev->channels = ch;
1695
1696	if (legacy)
1697		ret = stm32_dfsdm_chan_init(indio_dev, ch);
1698	else
1699		ret = stm32_dfsdm_generic_chan_init(indio_dev, ch);
1700	if (ret < 0)
1701		return ret;
1702
1703	init_completion(&adc->completion);
1704
1705	/* Optionally request DMA */
1706	ret = stm32_dfsdm_dma_request(dev, indio_dev);
1707	if (ret) {
1708		if (ret != -ENODEV)
1709			return dev_err_probe(dev, ret,
1710					     "DMA channel request failed with\n");
1711
1712		dev_dbg(dev, "No DMA support\n");
1713		return 0;
1714	}
1715
1716	ret = iio_triggered_buffer_setup(indio_dev,
1717					 &iio_pollfunc_store_time, NULL,
1718					 &stm32_dfsdm_buffer_setup_ops);
1719	if (ret) {
1720		stm32_dfsdm_dma_release(indio_dev);
1721		dev_err(&indio_dev->dev, "buffer setup failed\n");
1722		return ret;
1723	}
1724
1725	/* lptimer/timer hardware triggers */
1726	indio_dev->modes |= INDIO_HARDWARE_TRIGGERED;
1727
1728	return 0;
1729}
1730
1731static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_adc_data = {
1732	.type = DFSDM_IIO,
1733	.init = stm32_dfsdm_adc_init,
1734};
1735
1736static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_audio_data = {
1737	.type = DFSDM_AUDIO,
1738	.init = stm32_dfsdm_audio_init,
1739};
1740
1741static const struct of_device_id stm32_dfsdm_adc_match[] = {
1742	{
1743		.compatible = "st,stm32-dfsdm-adc",
1744		.data = &stm32h7_dfsdm_adc_data,
1745	},
1746	{
1747		.compatible = "st,stm32-dfsdm-dmic",
1748		.data = &stm32h7_dfsdm_audio_data,
1749	},
1750	{ }
1751};
1752MODULE_DEVICE_TABLE(of, stm32_dfsdm_adc_match);
1753
1754static int stm32_dfsdm_adc_probe(struct platform_device *pdev)
1755{
1756	struct device *dev = &pdev->dev;
1757	struct stm32_dfsdm_adc *adc;
1758	struct device_node *np = dev->of_node;
1759	const struct stm32_dfsdm_dev_data *dev_data;
1760	struct iio_dev *iio;
1761	char *name;
1762	int ret, irq, val;
1763
1764	dev_data = of_device_get_match_data(dev);
1765	iio = devm_iio_device_alloc(dev, sizeof(*adc));
1766	if (!iio)
1767		return -ENOMEM;
1768
1769	adc = iio_priv(iio);
1770	adc->dfsdm = dev_get_drvdata(dev->parent);
1771
1772	iio->dev.of_node = np;
1773	iio->modes = INDIO_DIRECT_MODE;
1774
1775	platform_set_drvdata(pdev, iio);
1776
1777	ret = of_property_read_u32(dev->of_node, "reg", &adc->fl_id);
1778	if (ret != 0 || adc->fl_id >= adc->dfsdm->num_fls) {
1779		dev_err(dev, "Missing or bad reg property\n");
1780		return -EINVAL;
1781	}
1782
1783	name = devm_kzalloc(dev, sizeof("dfsdm-adc0"), GFP_KERNEL);
1784	if (!name)
1785		return -ENOMEM;
1786	if (dev_data->type == DFSDM_AUDIO) {
1787		iio->info = &stm32_dfsdm_info_audio;
1788		snprintf(name, sizeof("dfsdm-pdm0"), "dfsdm-pdm%d", adc->fl_id);
1789	} else {
1790		iio->info = &stm32_dfsdm_info_adc;
1791		snprintf(name, sizeof("dfsdm-adc0"), "dfsdm-adc%d", adc->fl_id);
1792	}
1793	iio->name = name;
1794
1795	/*
1796	 * In a first step IRQs generated for channels are not treated.
1797	 * So IRQ associated to filter instance 0 is dedicated to the Filter 0.
1798	 */
1799	irq = platform_get_irq(pdev, 0);
1800	if (irq < 0)
1801		return irq;
1802
1803	ret = devm_request_irq(dev, irq, stm32_dfsdm_irq,
1804			       0, pdev->name, iio);
1805	if (ret < 0) {
1806		dev_err(dev, "Failed to request IRQ\n");
1807		return ret;
1808	}
1809
1810	ret = of_property_read_u32(dev->of_node, "st,filter-order", &val);
1811	if (ret < 0) {
1812		dev_err(dev, "Failed to set filter order\n");
1813		return ret;
1814	}
1815
1816	adc->dfsdm->fl_list[adc->fl_id].ford = val;
1817
1818	ret = of_property_read_u32(dev->of_node, "st,filter0-sync", &val);
1819	if (!ret)
1820		adc->dfsdm->fl_list[adc->fl_id].sync_mode = val;
1821
1822	adc->dev_data = dev_data;
1823	ret = dev_data->init(dev, iio);
1824	if (ret < 0)
1825		return ret;
1826
1827	ret = iio_device_register(iio);
1828	if (ret < 0)
1829		goto err_cleanup;
1830
1831	if (dev_data->type == DFSDM_AUDIO) {
1832		ret = of_platform_populate(np, NULL, NULL, dev);
1833		if (ret < 0) {
1834			dev_err(dev, "Failed to find an audio DAI\n");
1835			goto err_unregister;
1836		}
1837	}
1838
1839	return 0;
1840
1841err_unregister:
1842	iio_device_unregister(iio);
1843err_cleanup:
1844	stm32_dfsdm_dma_release(iio);
1845
1846	return ret;
1847}
1848
1849static void stm32_dfsdm_adc_remove(struct platform_device *pdev)
1850{
1851	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1852	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1853
1854	if (adc->dev_data->type == DFSDM_AUDIO)
1855		of_platform_depopulate(&pdev->dev);
1856	iio_device_unregister(indio_dev);
1857	stm32_dfsdm_dma_release(indio_dev);
1858}
1859
1860static int stm32_dfsdm_adc_suspend(struct device *dev)
1861{
1862	struct iio_dev *indio_dev = dev_get_drvdata(dev);
1863
1864	if (iio_buffer_enabled(indio_dev))
1865		stm32_dfsdm_predisable(indio_dev);
1866
1867	return 0;
1868}
1869
1870static int stm32_dfsdm_adc_resume(struct device *dev)
1871{
1872	struct iio_dev *indio_dev = dev_get_drvdata(dev);
1873	struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1874	const struct iio_chan_spec *chan;
1875	struct stm32_dfsdm_channel *ch;
1876	int i, ret;
1877
1878	/* restore channels configuration */
1879	for (i = 0; i < indio_dev->num_channels; i++) {
1880		chan = indio_dev->channels + i;
1881		ch = &adc->dfsdm->ch_list[chan->channel];
1882		ret = stm32_dfsdm_chan_configure(adc->dfsdm, ch);
1883		if (ret)
1884			return ret;
1885	}
1886
1887	if (iio_buffer_enabled(indio_dev))
1888		stm32_dfsdm_postenable(indio_dev);
1889
1890	return 0;
1891}
1892
1893static DEFINE_SIMPLE_DEV_PM_OPS(stm32_dfsdm_adc_pm_ops,
1894				stm32_dfsdm_adc_suspend,
1895				stm32_dfsdm_adc_resume);
1896
1897static struct platform_driver stm32_dfsdm_adc_driver = {
1898	.driver = {
1899		.name = "stm32-dfsdm-adc",
1900		.of_match_table = stm32_dfsdm_adc_match,
1901		.pm = pm_sleep_ptr(&stm32_dfsdm_adc_pm_ops),
1902	},
1903	.probe = stm32_dfsdm_adc_probe,
1904	.remove = stm32_dfsdm_adc_remove,
1905};
1906module_platform_driver(stm32_dfsdm_adc_driver);
1907
1908MODULE_DESCRIPTION("STM32 sigma delta ADC");
1909MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
1910MODULE_LICENSE("GPL v2");
1911MODULE_IMPORT_NS("IIO_BACKEND");