FILE
stm32-adc.c
File preview with syntax highlighting.
linux-6.19.14/drivers/iio/adc/stm32-adc.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * This file is part of STM32 ADC driver 4 * 5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved 6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>. 7 */ 8 9#include <linux/array_size.h> 10#include <linux/clk.h> 11#include <linux/debugfs.h> 12#include <linux/delay.h> 13#include <linux/dma-mapping.h> 14#include <linux/dmaengine.h> 15#include <linux/iio/iio.h> 16#include <linux/iio/buffer.h> 17#include <linux/iio/timer/stm32-lptim-trigger.h> 18#include <linux/iio/timer/stm32-timer-trigger.h> 19#include <linux/iio/trigger.h> 20#include <linux/iio/trigger_consumer.h> 21#include <linux/iio/triggered_buffer.h> 22#include <linux/interrupt.h> 23#include <linux/io.h> 24#include <linux/iopoll.h> 25#include <linux/module.h> 26#include <linux/mod_devicetable.h> 27#include <linux/nvmem-consumer.h> 28#include <linux/platform_device.h> 29#include <linux/pm_runtime.h> 30#include <linux/property.h> 31 32#include "stm32-adc-core.h" 33 34/* Number of linear calibration shadow registers / LINCALRDYW control bits */ 35#define STM32H7_LINCALFACT_NUM 6 36 37/* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */ 38#define STM32H7_BOOST_CLKRATE 20000000UL 39 40#define STM32_ADC_CH_MAX 20 /* max number of channels */ 41#define STM32_ADC_CH_SZ 16 /* max channel name size */ 42#define STM32_ADC_MAX_SQ 16 /* SQ1..SQ16 */ 43#define STM32_ADC_MAX_SMP 7 /* SMPx range is [0..7] */ 44#define STM32_ADC_TIMEOUT_US 100000 45#define STM32_ADC_TIMEOUT (msecs_to_jiffies(STM32_ADC_TIMEOUT_US / 1000)) 46#define STM32_ADC_HW_STOP_DELAY_MS 100 47#define STM32_ADC_VREFINT_VOLTAGE 3300 48 49#define STM32_DMA_BUFFER_SIZE PAGE_SIZE 50 51/* External trigger enable */ 52enum stm32_adc_exten { 53 STM32_EXTEN_SWTRIG, 54 STM32_EXTEN_HWTRIG_RISING_EDGE, 55 STM32_EXTEN_HWTRIG_FALLING_EDGE, 56 STM32_EXTEN_HWTRIG_BOTH_EDGES, 57}; 58 59/* extsel - trigger mux selection value */ 60enum stm32_adc_extsel { 61 STM32_EXT0, 62 STM32_EXT1, 63 STM32_EXT2, 64 STM32_EXT3, 65 STM32_EXT4, 66 STM32_EXT5, 67 STM32_EXT6, 68 STM32_EXT7, 69 STM32_EXT8, 70 STM32_EXT9, 71 STM32_EXT10, 72 STM32_EXT11, 73 STM32_EXT12, 74 STM32_EXT13, 75 STM32_EXT14, 76 STM32_EXT15, 77 STM32_EXT16, 78 STM32_EXT17, 79 STM32_EXT18, 80 STM32_EXT19, 81 STM32_EXT20, 82}; 83 84enum stm32_adc_int_ch { 85 STM32_ADC_INT_CH_NONE = -1, 86 STM32_ADC_INT_CH_VDDCORE, 87 STM32_ADC_INT_CH_VDDCPU, 88 STM32_ADC_INT_CH_VDDQ_DDR, 89 STM32_ADC_INT_CH_VREFINT, 90 STM32_ADC_INT_CH_VBAT, 91 STM32_ADC_INT_CH_NB, 92}; 93 94/** 95 * struct stm32_adc_ic - ADC internal channels 96 * @name: name of the internal channel 97 * @idx: internal channel enum index 98 */ 99struct stm32_adc_ic { 100 const char *name; 101 u32 idx; 102}; 103 104static const struct stm32_adc_ic stm32_adc_ic[STM32_ADC_INT_CH_NB] = { 105 { "vddcore", STM32_ADC_INT_CH_VDDCORE }, 106 { "vddcpu", STM32_ADC_INT_CH_VDDCPU }, 107 { "vddq_ddr", STM32_ADC_INT_CH_VDDQ_DDR }, 108 { "vrefint", STM32_ADC_INT_CH_VREFINT }, 109 { "vbat", STM32_ADC_INT_CH_VBAT }, 110}; 111 112/** 113 * struct stm32_adc_trig_info - ADC trigger info 114 * @name: name of the trigger, corresponding to its source 115 * @extsel: trigger selection 116 */ 117struct stm32_adc_trig_info { 118 const char *name; 119 enum stm32_adc_extsel extsel; 120}; 121 122/** 123 * struct stm32_adc_calib - optional adc calibration data 124 * @lincalfact: Linearity calibration factor 125 * @lincal_saved: Indicates that linear calibration factors are saved 126 */ 127struct stm32_adc_calib { 128 u32 lincalfact[STM32H7_LINCALFACT_NUM]; 129 bool lincal_saved; 130}; 131 132/** 133 * struct stm32_adc_regs - stm32 ADC misc registers & bitfield desc 134 * @reg: register offset 135 * @mask: bitfield mask 136 * @shift: left shift 137 */ 138struct stm32_adc_regs { 139 int reg; 140 int mask; 141 int shift; 142}; 143 144/** 145 * struct stm32_adc_vrefint - stm32 ADC internal reference voltage data 146 * @vrefint_cal: vrefint calibration value from nvmem 147 * @vrefint_data: vrefint actual value 148 */ 149struct stm32_adc_vrefint { 150 u32 vrefint_cal; 151 u32 vrefint_data; 152}; 153 154/** 155 * struct stm32_adc_regspec - stm32 registers definition 156 * @dr: data register offset 157 * @ier_eoc: interrupt enable register & eocie bitfield 158 * @ier_ovr: interrupt enable register & overrun bitfield 159 * @isr_eoc: interrupt status register & eoc bitfield 160 * @isr_ovr: interrupt status register & overrun bitfield 161 * @sqr: reference to sequence registers array 162 * @exten: trigger control register & bitfield 163 * @extsel: trigger selection register & bitfield 164 * @res: resolution selection register & bitfield 165 * @difsel: differential mode selection register & bitfield 166 * @smpr: smpr1 & smpr2 registers offset array 167 * @smp_bits: smpr1 & smpr2 index and bitfields 168 * @or_vddcore: option register & vddcore bitfield 169 * @or_vddcpu: option register & vddcpu bitfield 170 * @or_vddq_ddr: option register & vddq_ddr bitfield 171 * @ccr_vbat: common register & vbat bitfield 172 * @ccr_vref: common register & vrefint bitfield 173 */ 174struct stm32_adc_regspec { 175 const u32 dr; 176 const struct stm32_adc_regs ier_eoc; 177 const struct stm32_adc_regs ier_ovr; 178 const struct stm32_adc_regs isr_eoc; 179 const struct stm32_adc_regs isr_ovr; 180 const struct stm32_adc_regs *sqr; 181 const struct stm32_adc_regs exten; 182 const struct stm32_adc_regs extsel; 183 const struct stm32_adc_regs res; 184 const struct stm32_adc_regs difsel; 185 const u32 smpr[2]; 186 const struct stm32_adc_regs *smp_bits; 187 const struct stm32_adc_regs or_vddcore; 188 const struct stm32_adc_regs or_vddcpu; 189 const struct stm32_adc_regs or_vddq_ddr; 190 const struct stm32_adc_regs ccr_vbat; 191 const struct stm32_adc_regs ccr_vref; 192}; 193 194struct stm32_adc; 195 196/** 197 * struct stm32_adc_cfg - stm32 compatible configuration data 198 * @regs: registers descriptions 199 * @adc_info: per instance input channels definitions 200 * @trigs: external trigger sources 201 * @clk_required: clock is required 202 * @has_vregready: vregready status flag presence 203 * @has_boostmode: boost mode support flag 204 * @has_linearcal: linear calibration support flag 205 * @has_presel: channel preselection support flag 206 * @has_oversampling: oversampling support flag 207 * @prepare: optional prepare routine (power-up, enable) 208 * @start_conv: routine to start conversions 209 * @stop_conv: routine to stop conversions 210 * @unprepare: optional unprepare routine (disable, power-down) 211 * @irq_clear: routine to clear irqs 212 * @set_ovs: routine to set oversampling configuration 213 * @smp_cycles: programmable sampling time (ADC clock cycles) 214 * @ts_int_ch: pointer to array of internal channels minimum sampling time in ns 215 */ 216struct stm32_adc_cfg { 217 const struct stm32_adc_regspec *regs; 218 const struct stm32_adc_info *adc_info; 219 const struct stm32_adc_trig_info *trigs; 220 bool clk_required; 221 bool has_vregready; 222 bool has_boostmode; 223 bool has_linearcal; 224 bool has_presel; 225 bool has_oversampling; 226 int (*prepare)(struct iio_dev *); 227 void (*start_conv)(struct iio_dev *, bool dma); 228 void (*stop_conv)(struct iio_dev *); 229 void (*unprepare)(struct iio_dev *); 230 void (*irq_clear)(struct iio_dev *indio_dev, u32 msk); 231 void (*set_ovs)(struct iio_dev *indio_dev, u32 ovs_idx); 232 const unsigned int *smp_cycles; 233 const unsigned int *ts_int_ch; 234}; 235 236/** 237 * struct stm32_adc - private data of each ADC IIO instance 238 * @common: reference to ADC block common data 239 * @offset: ADC instance register offset in ADC block 240 * @cfg: compatible configuration data 241 * @completion: end of single conversion completion 242 * @buffer: data buffer + 8 bytes for timestamp if enabled 243 * @clk: clock for this adc instance 244 * @irq: interrupt for this adc instance 245 * @lock: spinlock 246 * @bufi: data buffer index 247 * @num_conv: expected number of scan conversions 248 * @res: data resolution (e.g. RES bitfield value) 249 * @trigger_polarity: external trigger polarity (e.g. exten) 250 * @dma_chan: dma channel 251 * @rx_buf: dma rx buffer cpu address 252 * @rx_dma_buf: dma rx buffer bus address 253 * @rx_buf_sz: dma rx buffer size 254 * @difsel: bitmask to set single-ended/differential channel 255 * @pcsel: bitmask to preselect channels on some devices 256 * @smpr_val: sampling time settings (e.g. smpr1 / smpr2) 257 * @cal: optional calibration data on some devices 258 * @vrefint: internal reference voltage data 259 * @chan_name: channel name array 260 * @num_diff: number of differential channels 261 * @int_ch: internal channel indexes array 262 * @nsmps: number of channels with optional sample time 263 * @ovs_idx: current oversampling ratio index (in oversampling array) 264 */ 265struct stm32_adc { 266 struct stm32_adc_common *common; 267 u32 offset; 268 const struct stm32_adc_cfg *cfg; 269 struct completion completion; 270 u16 buffer[STM32_ADC_MAX_SQ + 4] __aligned(8); 271 struct clk *clk; 272 int irq; 273 spinlock_t lock; /* interrupt lock */ 274 unsigned int bufi; 275 unsigned int num_conv; 276 u32 res; 277 u32 trigger_polarity; 278 struct dma_chan *dma_chan; 279 u8 *rx_buf; 280 dma_addr_t rx_dma_buf; 281 unsigned int rx_buf_sz; 282 u32 difsel; 283 u32 pcsel; 284 u32 smpr_val[2]; 285 struct stm32_adc_calib cal; 286 struct stm32_adc_vrefint vrefint; 287 char chan_name[STM32_ADC_CH_MAX][STM32_ADC_CH_SZ]; 288 u32 num_diff; 289 int int_ch[STM32_ADC_INT_CH_NB]; 290 int nsmps; 291 int ovs_idx; 292}; 293 294struct stm32_adc_diff_channel { 295 u32 vinp; 296 u32 vinn; 297}; 298 299/** 300 * struct stm32_adc_info - stm32 ADC, per instance config data 301 * @max_channels: Number of channels 302 * @resolutions: available resolutions 303 * @oversampling: available oversampling ratios 304 * @num_res: number of available resolutions 305 * @num_ovs: number of available oversampling ratios 306 */ 307struct stm32_adc_info { 308 int max_channels; 309 const unsigned int *resolutions; 310 const unsigned int *oversampling; 311 const unsigned int num_res; 312 const unsigned int num_ovs; 313}; 314 315static const unsigned int stm32h7_adc_oversampling_avail[] = { 316 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 317}; 318 319static const unsigned int stm32mp13_adc_oversampling_avail[] = { 320 1, 2, 4, 8, 16, 32, 64, 128, 256, 321}; 322 323static const unsigned int stm32f4_adc_resolutions[] = { 324 /* sorted values so the index matches RES[1:0] in STM32F4_ADC_CR1 */ 325 12, 10, 8, 6, 326}; 327 328/* stm32f4 can have up to 16 channels */ 329static const struct stm32_adc_info stm32f4_adc_info = { 330 .max_channels = 16, 331 .resolutions = stm32f4_adc_resolutions, 332 .num_res = ARRAY_SIZE(stm32f4_adc_resolutions), 333}; 334 335static const unsigned int stm32h7_adc_resolutions[] = { 336 /* sorted values so the index matches RES[2:0] in STM32H7_ADC_CFGR */ 337 16, 14, 12, 10, 8, 338}; 339 340/* stm32h7 can have up to 20 channels */ 341static const struct stm32_adc_info stm32h7_adc_info = { 342 .max_channels = STM32_ADC_CH_MAX, 343 .resolutions = stm32h7_adc_resolutions, 344 .oversampling = stm32h7_adc_oversampling_avail, 345 .num_res = ARRAY_SIZE(stm32h7_adc_resolutions), 346 .num_ovs = ARRAY_SIZE(stm32h7_adc_oversampling_avail), 347}; 348 349/* stm32mp13 can have up to 19 channels */ 350static const struct stm32_adc_info stm32mp13_adc_info = { 351 .max_channels = 19, 352 .resolutions = stm32f4_adc_resolutions, 353 .oversampling = stm32mp13_adc_oversampling_avail, 354 .num_res = ARRAY_SIZE(stm32f4_adc_resolutions), 355 .num_ovs = ARRAY_SIZE(stm32mp13_adc_oversampling_avail), 356}; 357 358/* 359 * stm32f4_sq - describe regular sequence registers 360 * - L: sequence len (register & bit field) 361 * - SQ1..SQ16: sequence entries (register & bit field) 362 */ 363static const struct stm32_adc_regs stm32f4_sq[STM32_ADC_MAX_SQ + 1] = { 364 /* L: len bit field description to be kept as first element */ 365 { STM32F4_ADC_SQR1, GENMASK(23, 20), 20 }, 366 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */ 367 { STM32F4_ADC_SQR3, GENMASK(4, 0), 0 }, 368 { STM32F4_ADC_SQR3, GENMASK(9, 5), 5 }, 369 { STM32F4_ADC_SQR3, GENMASK(14, 10), 10 }, 370 { STM32F4_ADC_SQR3, GENMASK(19, 15), 15 }, 371 { STM32F4_ADC_SQR3, GENMASK(24, 20), 20 }, 372 { STM32F4_ADC_SQR3, GENMASK(29, 25), 25 }, 373 { STM32F4_ADC_SQR2, GENMASK(4, 0), 0 }, 374 { STM32F4_ADC_SQR2, GENMASK(9, 5), 5 }, 375 { STM32F4_ADC_SQR2, GENMASK(14, 10), 10 }, 376 { STM32F4_ADC_SQR2, GENMASK(19, 15), 15 }, 377 { STM32F4_ADC_SQR2, GENMASK(24, 20), 20 }, 378 { STM32F4_ADC_SQR2, GENMASK(29, 25), 25 }, 379 { STM32F4_ADC_SQR1, GENMASK(4, 0), 0 }, 380 { STM32F4_ADC_SQR1, GENMASK(9, 5), 5 }, 381 { STM32F4_ADC_SQR1, GENMASK(14, 10), 10 }, 382 { STM32F4_ADC_SQR1, GENMASK(19, 15), 15 }, 383}; 384 385/* STM32F4 external trigger sources for all instances */ 386static const struct stm32_adc_trig_info stm32f4_adc_trigs[] = { 387 { TIM1_CH1, STM32_EXT0 }, 388 { TIM1_CH2, STM32_EXT1 }, 389 { TIM1_CH3, STM32_EXT2 }, 390 { TIM2_CH2, STM32_EXT3 }, 391 { TIM2_CH3, STM32_EXT4 }, 392 { TIM2_CH4, STM32_EXT5 }, 393 { TIM2_TRGO, STM32_EXT6 }, 394 { TIM3_CH1, STM32_EXT7 }, 395 { TIM3_TRGO, STM32_EXT8 }, 396 { TIM4_CH4, STM32_EXT9 }, 397 { TIM5_CH1, STM32_EXT10 }, 398 { TIM5_CH2, STM32_EXT11 }, 399 { TIM5_CH3, STM32_EXT12 }, 400 { TIM8_CH1, STM32_EXT13 }, 401 { TIM8_TRGO, STM32_EXT14 }, 402 {}, /* sentinel */ 403}; 404 405/* 406 * stm32f4_smp_bits[] - describe sampling time register index & bit fields 407 * Sorted so it can be indexed by channel number. 408 */ 409static const struct stm32_adc_regs stm32f4_smp_bits[] = { 410 /* STM32F4_ADC_SMPR2: smpr[] index, mask, shift for SMP0 to SMP9 */ 411 { 1, GENMASK(2, 0), 0 }, 412 { 1, GENMASK(5, 3), 3 }, 413 { 1, GENMASK(8, 6), 6 }, 414 { 1, GENMASK(11, 9), 9 }, 415 { 1, GENMASK(14, 12), 12 }, 416 { 1, GENMASK(17, 15), 15 }, 417 { 1, GENMASK(20, 18), 18 }, 418 { 1, GENMASK(23, 21), 21 }, 419 { 1, GENMASK(26, 24), 24 }, 420 { 1, GENMASK(29, 27), 27 }, 421 /* STM32F4_ADC_SMPR1, smpr[] index, mask, shift for SMP10 to SMP18 */ 422 { 0, GENMASK(2, 0), 0 }, 423 { 0, GENMASK(5, 3), 3 }, 424 { 0, GENMASK(8, 6), 6 }, 425 { 0, GENMASK(11, 9), 9 }, 426 { 0, GENMASK(14, 12), 12 }, 427 { 0, GENMASK(17, 15), 15 }, 428 { 0, GENMASK(20, 18), 18 }, 429 { 0, GENMASK(23, 21), 21 }, 430 { 0, GENMASK(26, 24), 24 }, 431}; 432 433/* STM32F4 programmable sampling time (ADC clock cycles) */ 434static const unsigned int stm32f4_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = { 435 3, 15, 28, 56, 84, 112, 144, 480, 436}; 437 438static const struct stm32_adc_regspec stm32f4_adc_regspec = { 439 .dr = STM32F4_ADC_DR, 440 .ier_eoc = { STM32F4_ADC_CR1, STM32F4_EOCIE }, 441 .ier_ovr = { STM32F4_ADC_CR1, STM32F4_OVRIE }, 442 .isr_eoc = { STM32F4_ADC_SR, STM32F4_EOC }, 443 .isr_ovr = { STM32F4_ADC_SR, STM32F4_OVR }, 444 .sqr = stm32f4_sq, 445 .exten = { STM32F4_ADC_CR2, STM32F4_EXTEN_MASK, STM32F4_EXTEN_SHIFT }, 446 .extsel = { STM32F4_ADC_CR2, STM32F4_EXTSEL_MASK, 447 STM32F4_EXTSEL_SHIFT }, 448 .res = { STM32F4_ADC_CR1, STM32F4_RES_MASK, STM32F4_RES_SHIFT }, 449 .smpr = { STM32F4_ADC_SMPR1, STM32F4_ADC_SMPR2 }, 450 .smp_bits = stm32f4_smp_bits, 451}; 452 453static const struct stm32_adc_regs stm32h7_sq[STM32_ADC_MAX_SQ + 1] = { 454 /* L: len bit field description to be kept as first element */ 455 { STM32H7_ADC_SQR1, GENMASK(3, 0), 0 }, 456 /* SQ1..SQ16 registers & bit fields (reg, mask, shift) */ 457 { STM32H7_ADC_SQR1, GENMASK(10, 6), 6 }, 458 { STM32H7_ADC_SQR1, GENMASK(16, 12), 12 }, 459 { STM32H7_ADC_SQR1, GENMASK(22, 18), 18 }, 460 { STM32H7_ADC_SQR1, GENMASK(28, 24), 24 }, 461 { STM32H7_ADC_SQR2, GENMASK(4, 0), 0 }, 462 { STM32H7_ADC_SQR2, GENMASK(10, 6), 6 }, 463 { STM32H7_ADC_SQR2, GENMASK(16, 12), 12 }, 464 { STM32H7_ADC_SQR2, GENMASK(22, 18), 18 }, 465 { STM32H7_ADC_SQR2, GENMASK(28, 24), 24 }, 466 { STM32H7_ADC_SQR3, GENMASK(4, 0), 0 }, 467 { STM32H7_ADC_SQR3, GENMASK(10, 6), 6 }, 468 { STM32H7_ADC_SQR3, GENMASK(16, 12), 12 }, 469 { STM32H7_ADC_SQR3, GENMASK(22, 18), 18 }, 470 { STM32H7_ADC_SQR3, GENMASK(28, 24), 24 }, 471 { STM32H7_ADC_SQR4, GENMASK(4, 0), 0 }, 472 { STM32H7_ADC_SQR4, GENMASK(10, 6), 6 }, 473}; 474 475/* STM32H7 external trigger sources for all instances */ 476static const struct stm32_adc_trig_info stm32h7_adc_trigs[] = { 477 { TIM1_CH1, STM32_EXT0 }, 478 { TIM1_CH2, STM32_EXT1 }, 479 { TIM1_CH3, STM32_EXT2 }, 480 { TIM2_CH2, STM32_EXT3 }, 481 { TIM3_TRGO, STM32_EXT4 }, 482 { TIM4_CH4, STM32_EXT5 }, 483 { TIM8_TRGO, STM32_EXT7 }, 484 { TIM8_TRGO2, STM32_EXT8 }, 485 { TIM1_TRGO, STM32_EXT9 }, 486 { TIM1_TRGO2, STM32_EXT10 }, 487 { TIM2_TRGO, STM32_EXT11 }, 488 { TIM4_TRGO, STM32_EXT12 }, 489 { TIM6_TRGO, STM32_EXT13 }, 490 { TIM15_TRGO, STM32_EXT14 }, 491 { TIM3_CH4, STM32_EXT15 }, 492 { LPTIM1_OUT, STM32_EXT18 }, 493 { LPTIM2_OUT, STM32_EXT19 }, 494 { LPTIM3_OUT, STM32_EXT20 }, 495 { } 496}; 497 498/* 499 * stm32h7_smp_bits - describe sampling time register index & bit fields 500 * Sorted so it can be indexed by channel number. 501 */ 502static const struct stm32_adc_regs stm32h7_smp_bits[] = { 503 /* STM32H7_ADC_SMPR1, smpr[] index, mask, shift for SMP0 to SMP9 */ 504 { 0, GENMASK(2, 0), 0 }, 505 { 0, GENMASK(5, 3), 3 }, 506 { 0, GENMASK(8, 6), 6 }, 507 { 0, GENMASK(11, 9), 9 }, 508 { 0, GENMASK(14, 12), 12 }, 509 { 0, GENMASK(17, 15), 15 }, 510 { 0, GENMASK(20, 18), 18 }, 511 { 0, GENMASK(23, 21), 21 }, 512 { 0, GENMASK(26, 24), 24 }, 513 { 0, GENMASK(29, 27), 27 }, 514 /* STM32H7_ADC_SMPR2, smpr[] index, mask, shift for SMP10 to SMP19 */ 515 { 1, GENMASK(2, 0), 0 }, 516 { 1, GENMASK(5, 3), 3 }, 517 { 1, GENMASK(8, 6), 6 }, 518 { 1, GENMASK(11, 9), 9 }, 519 { 1, GENMASK(14, 12), 12 }, 520 { 1, GENMASK(17, 15), 15 }, 521 { 1, GENMASK(20, 18), 18 }, 522 { 1, GENMASK(23, 21), 21 }, 523 { 1, GENMASK(26, 24), 24 }, 524 { 1, GENMASK(29, 27), 27 }, 525}; 526 527/* STM32H7 programmable sampling time (ADC clock cycles, rounded down) */ 528static const unsigned int stm32h7_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = { 529 1, 2, 8, 16, 32, 64, 387, 810, 530}; 531 532static const struct stm32_adc_regspec stm32h7_adc_regspec = { 533 .dr = STM32H7_ADC_DR, 534 .ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE }, 535 .ier_ovr = { STM32H7_ADC_IER, STM32H7_OVRIE }, 536 .isr_eoc = { STM32H7_ADC_ISR, STM32H7_EOC }, 537 .isr_ovr = { STM32H7_ADC_ISR, STM32H7_OVR }, 538 .sqr = stm32h7_sq, 539 .exten = { STM32H7_ADC_CFGR, STM32H7_EXTEN_MASK, STM32H7_EXTEN_SHIFT }, 540 .extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK, 541 STM32H7_EXTSEL_SHIFT }, 542 .res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT }, 543 .difsel = { STM32H7_ADC_DIFSEL, STM32H7_DIFSEL_MASK}, 544 .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 }, 545 .smp_bits = stm32h7_smp_bits, 546}; 547 548/* STM32MP13 programmable sampling time (ADC clock cycles, rounded down) */ 549static const unsigned int stm32mp13_adc_smp_cycles[STM32_ADC_MAX_SMP + 1] = { 550 2, 6, 12, 24, 47, 92, 247, 640, 551}; 552 553static const struct stm32_adc_regspec stm32mp13_adc_regspec = { 554 .dr = STM32H7_ADC_DR, 555 .ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE }, 556 .ier_ovr = { STM32H7_ADC_IER, STM32H7_OVRIE }, 557 .isr_eoc = { STM32H7_ADC_ISR, STM32H7_EOC }, 558 .isr_ovr = { STM32H7_ADC_ISR, STM32H7_OVR }, 559 .sqr = stm32h7_sq, 560 .exten = { STM32H7_ADC_CFGR, STM32H7_EXTEN_MASK, STM32H7_EXTEN_SHIFT }, 561 .extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK, 562 STM32H7_EXTSEL_SHIFT }, 563 .res = { STM32H7_ADC_CFGR, STM32MP13_RES_MASK, STM32MP13_RES_SHIFT }, 564 .difsel = { STM32MP13_ADC_DIFSEL, STM32MP13_DIFSEL_MASK}, 565 .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 }, 566 .smp_bits = stm32h7_smp_bits, 567 .or_vddcore = { STM32MP13_ADC2_OR, STM32MP13_OP0 }, 568 .or_vddcpu = { STM32MP13_ADC2_OR, STM32MP13_OP1 }, 569 .or_vddq_ddr = { STM32MP13_ADC2_OR, STM32MP13_OP2 }, 570 .ccr_vbat = { STM32H7_ADC_CCR, STM32H7_VBATEN }, 571 .ccr_vref = { STM32H7_ADC_CCR, STM32H7_VREFEN }, 572}; 573 574static const struct stm32_adc_regspec stm32mp1_adc_regspec = { 575 .dr = STM32H7_ADC_DR, 576 .ier_eoc = { STM32H7_ADC_IER, STM32H7_EOCIE }, 577 .ier_ovr = { STM32H7_ADC_IER, STM32H7_OVRIE }, 578 .isr_eoc = { STM32H7_ADC_ISR, STM32H7_EOC }, 579 .isr_ovr = { STM32H7_ADC_ISR, STM32H7_OVR }, 580 .sqr = stm32h7_sq, 581 .exten = { STM32H7_ADC_CFGR, STM32H7_EXTEN_MASK, STM32H7_EXTEN_SHIFT }, 582 .extsel = { STM32H7_ADC_CFGR, STM32H7_EXTSEL_MASK, 583 STM32H7_EXTSEL_SHIFT }, 584 .res = { STM32H7_ADC_CFGR, STM32H7_RES_MASK, STM32H7_RES_SHIFT }, 585 .difsel = { STM32H7_ADC_DIFSEL, STM32H7_DIFSEL_MASK}, 586 .smpr = { STM32H7_ADC_SMPR1, STM32H7_ADC_SMPR2 }, 587 .smp_bits = stm32h7_smp_bits, 588 .or_vddcore = { STM32MP1_ADC2_OR, STM32MP1_VDDCOREEN }, 589 .ccr_vbat = { STM32H7_ADC_CCR, STM32H7_VBATEN }, 590 .ccr_vref = { STM32H7_ADC_CCR, STM32H7_VREFEN }, 591}; 592 593/* 594 * STM32 ADC registers access routines 595 * @adc: stm32 adc instance 596 * @reg: reg offset in adc instance 597 * 598 * Note: All instances share same base, with 0x0, 0x100 or 0x200 offset resp. 599 * for adc1, adc2 and adc3. 600 */ 601static u32 stm32_adc_readl(struct stm32_adc *adc, u32 reg) 602{ 603 return readl_relaxed(adc->common->base + adc->offset + reg); 604} 605 606#define stm32_adc_readl_addr(addr) stm32_adc_readl(adc, addr) 607 608#define stm32_adc_readl_poll_timeout(reg, val, cond, sleep_us, timeout_us) \ 609 readx_poll_timeout(stm32_adc_readl_addr, reg, val, \ 610 cond, sleep_us, timeout_us) 611 612static u16 stm32_adc_readw(struct stm32_adc *adc, u32 reg) 613{ 614 return readw_relaxed(adc->common->base + adc->offset + reg); 615} 616 617static void stm32_adc_writel(struct stm32_adc *adc, u32 reg, u32 val) 618{ 619 writel_relaxed(val, adc->common->base + adc->offset + reg); 620} 621 622static void stm32_adc_set_bits(struct stm32_adc *adc, u32 reg, u32 bits) 623{ 624 unsigned long flags; 625 626 spin_lock_irqsave(&adc->lock, flags); 627 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) | bits); 628 spin_unlock_irqrestore(&adc->lock, flags); 629} 630 631static void stm32_adc_set_bits_common(struct stm32_adc *adc, u32 reg, u32 bits) 632{ 633 spin_lock(&adc->common->lock); 634 writel_relaxed(readl_relaxed(adc->common->base + reg) | bits, 635 adc->common->base + reg); 636 spin_unlock(&adc->common->lock); 637} 638 639static void stm32_adc_clr_bits(struct stm32_adc *adc, u32 reg, u32 bits) 640{ 641 unsigned long flags; 642 643 spin_lock_irqsave(&adc->lock, flags); 644 stm32_adc_writel(adc, reg, stm32_adc_readl(adc, reg) & ~bits); 645 spin_unlock_irqrestore(&adc->lock, flags); 646} 647 648static void stm32_adc_clr_bits_common(struct stm32_adc *adc, u32 reg, u32 bits) 649{ 650 spin_lock(&adc->common->lock); 651 writel_relaxed(readl_relaxed(adc->common->base + reg) & ~bits, 652 adc->common->base + reg); 653 spin_unlock(&adc->common->lock); 654} 655 656/** 657 * stm32_adc_conv_irq_enable() - Enable end of conversion interrupt 658 * @adc: stm32 adc instance 659 */ 660static void stm32_adc_conv_irq_enable(struct stm32_adc *adc) 661{ 662 stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg, 663 adc->cfg->regs->ier_eoc.mask); 664}; 665 666/** 667 * stm32_adc_conv_irq_disable() - Disable end of conversion interrupt 668 * @adc: stm32 adc instance 669 */ 670static void stm32_adc_conv_irq_disable(struct stm32_adc *adc) 671{ 672 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg, 673 adc->cfg->regs->ier_eoc.mask); 674} 675 676static void stm32_adc_ovr_irq_enable(struct stm32_adc *adc) 677{ 678 stm32_adc_set_bits(adc, adc->cfg->regs->ier_ovr.reg, 679 adc->cfg->regs->ier_ovr.mask); 680} 681 682static void stm32_adc_ovr_irq_disable(struct stm32_adc *adc) 683{ 684 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_ovr.reg, 685 adc->cfg->regs->ier_ovr.mask); 686} 687 688static void stm32_adc_set_res(struct stm32_adc *adc) 689{ 690 const struct stm32_adc_regs *res = &adc->cfg->regs->res; 691 u32 val; 692 693 val = stm32_adc_readl(adc, res->reg); 694 val = (val & ~res->mask) | (adc->res << res->shift); 695 stm32_adc_writel(adc, res->reg, val); 696} 697 698static int stm32_adc_hw_stop(struct device *dev) 699{ 700 struct iio_dev *indio_dev = dev_get_drvdata(dev); 701 struct stm32_adc *adc = iio_priv(indio_dev); 702 703 if (adc->cfg->unprepare) 704 adc->cfg->unprepare(indio_dev); 705 706 clk_disable_unprepare(adc->clk); 707 708 return 0; 709} 710 711static int stm32_adc_hw_start(struct device *dev) 712{ 713 struct iio_dev *indio_dev = dev_get_drvdata(dev); 714 struct stm32_adc *adc = iio_priv(indio_dev); 715 int ret; 716 717 ret = clk_prepare_enable(adc->clk); 718 if (ret) 719 return ret; 720 721 stm32_adc_set_res(adc); 722 723 if (adc->cfg->prepare) { 724 ret = adc->cfg->prepare(indio_dev); 725 if (ret) 726 goto err_clk_dis; 727 } 728 729 return 0; 730 731err_clk_dis: 732 clk_disable_unprepare(adc->clk); 733 734 return ret; 735} 736 737static void stm32_adc_int_ch_enable(struct iio_dev *indio_dev) 738{ 739 struct stm32_adc *adc = iio_priv(indio_dev); 740 u32 i; 741 742 for (i = 0; i < STM32_ADC_INT_CH_NB; i++) { 743 if (adc->int_ch[i] == STM32_ADC_INT_CH_NONE) 744 continue; 745 746 switch (i) { 747 case STM32_ADC_INT_CH_VDDCORE: 748 dev_dbg(&indio_dev->dev, "Enable VDDCore\n"); 749 stm32_adc_set_bits(adc, adc->cfg->regs->or_vddcore.reg, 750 adc->cfg->regs->or_vddcore.mask); 751 break; 752 case STM32_ADC_INT_CH_VDDCPU: 753 dev_dbg(&indio_dev->dev, "Enable VDDCPU\n"); 754 stm32_adc_set_bits(adc, adc->cfg->regs->or_vddcpu.reg, 755 adc->cfg->regs->or_vddcpu.mask); 756 break; 757 case STM32_ADC_INT_CH_VDDQ_DDR: 758 dev_dbg(&indio_dev->dev, "Enable VDDQ_DDR\n"); 759 stm32_adc_set_bits(adc, adc->cfg->regs->or_vddq_ddr.reg, 760 adc->cfg->regs->or_vddq_ddr.mask); 761 break; 762 case STM32_ADC_INT_CH_VREFINT: 763 dev_dbg(&indio_dev->dev, "Enable VREFInt\n"); 764 stm32_adc_set_bits_common(adc, adc->cfg->regs->ccr_vref.reg, 765 adc->cfg->regs->ccr_vref.mask); 766 break; 767 case STM32_ADC_INT_CH_VBAT: 768 dev_dbg(&indio_dev->dev, "Enable VBAT\n"); 769 stm32_adc_set_bits_common(adc, adc->cfg->regs->ccr_vbat.reg, 770 adc->cfg->regs->ccr_vbat.mask); 771 break; 772 } 773 } 774} 775 776static void stm32_adc_int_ch_disable(struct stm32_adc *adc) 777{ 778 u32 i; 779 780 for (i = 0; i < STM32_ADC_INT_CH_NB; i++) { 781 if (adc->int_ch[i] == STM32_ADC_INT_CH_NONE) 782 continue; 783 784 switch (i) { 785 case STM32_ADC_INT_CH_VDDCORE: 786 stm32_adc_clr_bits(adc, adc->cfg->regs->or_vddcore.reg, 787 adc->cfg->regs->or_vddcore.mask); 788 break; 789 case STM32_ADC_INT_CH_VDDCPU: 790 stm32_adc_clr_bits(adc, adc->cfg->regs->or_vddcpu.reg, 791 adc->cfg->regs->or_vddcpu.mask); 792 break; 793 case STM32_ADC_INT_CH_VDDQ_DDR: 794 stm32_adc_clr_bits(adc, adc->cfg->regs->or_vddq_ddr.reg, 795 adc->cfg->regs->or_vddq_ddr.mask); 796 break; 797 case STM32_ADC_INT_CH_VREFINT: 798 stm32_adc_clr_bits_common(adc, adc->cfg->regs->ccr_vref.reg, 799 adc->cfg->regs->ccr_vref.mask); 800 break; 801 case STM32_ADC_INT_CH_VBAT: 802 stm32_adc_clr_bits_common(adc, adc->cfg->regs->ccr_vbat.reg, 803 adc->cfg->regs->ccr_vbat.mask); 804 break; 805 } 806 } 807} 808 809/** 810 * stm32f4_adc_start_conv() - Start conversions for regular channels. 811 * @indio_dev: IIO device instance 812 * @dma: use dma to transfer conversion result 813 * 814 * Start conversions for regular channels. 815 * Also take care of normal or DMA mode. Circular DMA may be used for regular 816 * conversions, in IIO buffer modes. Otherwise, use ADC interrupt with direct 817 * DR read instead (e.g. read_raw, or triggered buffer mode without DMA). 818 */ 819static void stm32f4_adc_start_conv(struct iio_dev *indio_dev, bool dma) 820{ 821 struct stm32_adc *adc = iio_priv(indio_dev); 822 823 stm32_adc_set_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); 824 825 if (dma) 826 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, 827 STM32F4_DMA | STM32F4_DDS); 828 829 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_EOCS | STM32F4_ADON); 830 831 /* Wait for Power-up time (tSTAB from datasheet) */ 832 usleep_range(2, 3); 833 834 /* Software start ? (e.g. trigger detection disabled ?) */ 835 if (!(stm32_adc_readl(adc, STM32F4_ADC_CR2) & STM32F4_EXTEN_MASK)) 836 stm32_adc_set_bits(adc, STM32F4_ADC_CR2, STM32F4_SWSTART); 837} 838 839static void stm32f4_adc_stop_conv(struct iio_dev *indio_dev) 840{ 841 struct stm32_adc *adc = iio_priv(indio_dev); 842 843 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, STM32F4_EXTEN_MASK); 844 stm32_adc_clr_bits(adc, STM32F4_ADC_SR, STM32F4_STRT); 845 846 stm32_adc_clr_bits(adc, STM32F4_ADC_CR1, STM32F4_SCAN); 847 stm32_adc_clr_bits(adc, STM32F4_ADC_CR2, 848 STM32F4_ADON | STM32F4_DMA | STM32F4_DDS); 849} 850 851static void stm32f4_adc_irq_clear(struct iio_dev *indio_dev, u32 msk) 852{ 853 struct stm32_adc *adc = iio_priv(indio_dev); 854 855 stm32_adc_clr_bits(adc, adc->cfg->regs->isr_eoc.reg, msk); 856} 857 858static void stm32h7_adc_start_conv(struct iio_dev *indio_dev, bool dma) 859{ 860 struct stm32_adc *adc = iio_priv(indio_dev); 861 enum stm32h7_adc_dmngt dmngt; 862 unsigned long flags; 863 u32 val; 864 865 if (dma) 866 dmngt = STM32H7_DMNGT_DMA_CIRC; 867 else 868 dmngt = STM32H7_DMNGT_DR_ONLY; 869 870 spin_lock_irqsave(&adc->lock, flags); 871 val = stm32_adc_readl(adc, STM32H7_ADC_CFGR); 872 val = (val & ~STM32H7_DMNGT_MASK) | (dmngt << STM32H7_DMNGT_SHIFT); 873 stm32_adc_writel(adc, STM32H7_ADC_CFGR, val); 874 spin_unlock_irqrestore(&adc->lock, flags); 875 876 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART); 877} 878 879static void stm32h7_adc_stop_conv(struct iio_dev *indio_dev) 880{ 881 struct stm32_adc *adc = iio_priv(indio_dev); 882 int ret; 883 u32 val; 884 885 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTP); 886 887 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 888 !(val & (STM32H7_ADSTART)), 889 100, STM32_ADC_TIMEOUT_US); 890 if (ret) 891 dev_warn(&indio_dev->dev, "stop failed\n"); 892 893 /* STM32H7_DMNGT_MASK covers STM32MP13_DMAEN & STM32MP13_DMACFG */ 894 stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK); 895} 896 897static void stm32h7_adc_irq_clear(struct iio_dev *indio_dev, u32 msk) 898{ 899 struct stm32_adc *adc = iio_priv(indio_dev); 900 /* On STM32H7 IRQs are cleared by writing 1 into ISR register */ 901 stm32_adc_set_bits(adc, adc->cfg->regs->isr_eoc.reg, msk); 902} 903 904static void stm32mp13_adc_start_conv(struct iio_dev *indio_dev, bool dma) 905{ 906 struct stm32_adc *adc = iio_priv(indio_dev); 907 908 if (dma) 909 stm32_adc_set_bits(adc, STM32H7_ADC_CFGR, 910 STM32MP13_DMAEN | STM32MP13_DMACFG); 911 912 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADSTART); 913} 914 915static void stm32h7_adc_set_ovs(struct iio_dev *indio_dev, u32 ovs_idx) 916{ 917 struct stm32_adc *adc = iio_priv(indio_dev); 918 u32 ovsr_bits, bits, msk; 919 920 msk = STM32H7_ROVSE | STM32H7_OVSR_MASK | STM32H7_OVSS_MASK; 921 stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR2, msk); 922 923 if (!ovs_idx) 924 return; 925 926 /* 927 * Only the oversampling ratios corresponding to 2^ovs_idx are exposed in sysfs. 928 * Oversampling ratios [2,3,...,1024] are mapped on OVSR register values [1,2,...,1023]. 929 * OVSR = 2^ovs_idx - 1 930 * These ratio increase the resolution by ovs_idx bits. Apply a right shift to keep initial 931 * resolution given by "assigned-resolution-bits" property. 932 * OVSS = ovs_idx 933 */ 934 ovsr_bits = GENMASK(ovs_idx - 1, 0); 935 bits = STM32H7_ROVSE | STM32H7_OVSS(ovs_idx) | STM32H7_OVSR(ovsr_bits); 936 937 stm32_adc_set_bits(adc, STM32H7_ADC_CFGR2, bits & msk); 938} 939 940static void stm32mp13_adc_set_ovs(struct iio_dev *indio_dev, u32 ovs_idx) 941{ 942 struct stm32_adc *adc = iio_priv(indio_dev); 943 u32 bits, msk; 944 945 msk = STM32H7_ROVSE | STM32MP13_OVSR_MASK | STM32MP13_OVSS_MASK; 946 stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR2, msk); 947 948 if (!ovs_idx) 949 return; 950 951 /* 952 * The oversampling ratios [2,4,8,..,256] are mapped on OVSR register values [0,1,...,7]. 953 * OVSR = ovs_idx - 1 954 * These ratio increase the resolution by ovs_idx bits. Apply a right shift to keep initial 955 * resolution given by "assigned-resolution-bits" property. 956 * OVSS = ovs_idx 957 */ 958 bits = STM32H7_ROVSE | STM32MP13_OVSS(ovs_idx); 959 if (ovs_idx - 1) 960 bits |= STM32MP13_OVSR(ovs_idx - 1); 961 962 stm32_adc_set_bits(adc, STM32H7_ADC_CFGR2, bits & msk); 963} 964 965static int stm32h7_adc_exit_pwr_down(struct iio_dev *indio_dev) 966{ 967 struct stm32_adc *adc = iio_priv(indio_dev); 968 int ret; 969 u32 val; 970 971 /* Exit deep power down, then enable ADC voltage regulator */ 972 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); 973 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADVREGEN); 974 975 if (adc->cfg->has_boostmode && 976 adc->common->rate > STM32H7_BOOST_CLKRATE) 977 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); 978 979 /* Wait for startup time */ 980 if (!adc->cfg->has_vregready) { 981 usleep_range(10, 20); 982 return 0; 983 } 984 985 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val, 986 val & STM32MP1_VREGREADY, 100, 987 STM32_ADC_TIMEOUT_US); 988 if (ret) { 989 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); 990 dev_err(&indio_dev->dev, "Failed to exit power down\n"); 991 } 992 993 return ret; 994} 995 996static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc) 997{ 998 if (adc->cfg->has_boostmode) 999 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST); 1000 1001 /* Setting DEEPPWD disables ADC vreg and clears ADVREGEN */ 1002 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD); 1003} 1004 1005static int stm32h7_adc_enable(struct iio_dev *indio_dev) 1006{ 1007 struct stm32_adc *adc = iio_priv(indio_dev); 1008 int ret; 1009 u32 val; 1010 1011 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADEN); 1012 1013 /* Poll for ADRDY to be set (after adc startup time) */ 1014 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val, 1015 val & STM32H7_ADRDY, 1016 100, STM32_ADC_TIMEOUT_US); 1017 if (ret) { 1018 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); 1019 dev_err(&indio_dev->dev, "Failed to enable ADC\n"); 1020 } else { 1021 /* Clear ADRDY by writing one */ 1022 stm32_adc_set_bits(adc, STM32H7_ADC_ISR, STM32H7_ADRDY); 1023 } 1024 1025 return ret; 1026} 1027 1028static void stm32h7_adc_disable(struct iio_dev *indio_dev) 1029{ 1030 struct stm32_adc *adc = iio_priv(indio_dev); 1031 int ret; 1032 u32 val; 1033 1034 if (!(stm32_adc_readl(adc, STM32H7_ADC_CR) & STM32H7_ADEN)) 1035 return; 1036 1037 /* Disable ADC and wait until it's effectively disabled */ 1038 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); 1039 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 1040 !(val & STM32H7_ADEN), 100, 1041 STM32_ADC_TIMEOUT_US); 1042 if (ret) 1043 dev_warn(&indio_dev->dev, "Failed to disable\n"); 1044} 1045 1046/** 1047 * stm32h7_adc_read_selfcalib() - read calibration shadow regs, save result 1048 * @indio_dev: IIO device instance 1049 * Note: Must be called once ADC is enabled, so LINCALRDYW[1..6] are writable 1050 */ 1051static int stm32h7_adc_read_selfcalib(struct iio_dev *indio_dev) 1052{ 1053 struct stm32_adc *adc = iio_priv(indio_dev); 1054 int i, ret; 1055 u32 lincalrdyw_mask, val; 1056 1057 /* Read linearity calibration */ 1058 lincalrdyw_mask = STM32H7_LINCALRDYW6; 1059 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) { 1060 /* Clear STM32H7_LINCALRDYW[6..1]: transfer calib to CALFACT2 */ 1061 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); 1062 1063 /* Poll: wait calib data to be ready in CALFACT2 register */ 1064 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 1065 !(val & lincalrdyw_mask), 1066 100, STM32_ADC_TIMEOUT_US); 1067 if (ret) { 1068 dev_err(&indio_dev->dev, "Failed to read calfact\n"); 1069 return ret; 1070 } 1071 1072 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); 1073 adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK); 1074 adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT; 1075 1076 lincalrdyw_mask >>= 1; 1077 } 1078 adc->cal.lincal_saved = true; 1079 1080 return 0; 1081} 1082 1083/** 1084 * stm32h7_adc_restore_selfcalib() - Restore saved self-calibration result 1085 * @indio_dev: IIO device instance 1086 * Note: ADC must be enabled, with no on-going conversions. 1087 */ 1088static int stm32h7_adc_restore_selfcalib(struct iio_dev *indio_dev) 1089{ 1090 struct stm32_adc *adc = iio_priv(indio_dev); 1091 int i, ret; 1092 u32 lincalrdyw_mask, val; 1093 1094 lincalrdyw_mask = STM32H7_LINCALRDYW6; 1095 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) { 1096 /* 1097 * Write saved calibration data to shadow registers: 1098 * Write CALFACT2, and set LINCALRDYW[6..1] bit to trigger 1099 * data write. Then poll to wait for complete transfer. 1100 */ 1101 val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT; 1102 stm32_adc_writel(adc, STM32H7_ADC_CALFACT2, val); 1103 stm32_adc_set_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); 1104 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 1105 val & lincalrdyw_mask, 1106 100, STM32_ADC_TIMEOUT_US); 1107 if (ret) { 1108 dev_err(&indio_dev->dev, "Failed to write calfact\n"); 1109 return ret; 1110 } 1111 1112 /* 1113 * Read back calibration data, has two effects: 1114 * - It ensures bits LINCALRDYW[6..1] are kept cleared 1115 * for next time calibration needs to be restored. 1116 * - BTW, bit clear triggers a read, then check data has been 1117 * correctly written. 1118 */ 1119 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, lincalrdyw_mask); 1120 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 1121 !(val & lincalrdyw_mask), 1122 100, STM32_ADC_TIMEOUT_US); 1123 if (ret) { 1124 dev_err(&indio_dev->dev, "Failed to read calfact\n"); 1125 return ret; 1126 } 1127 val = stm32_adc_readl(adc, STM32H7_ADC_CALFACT2); 1128 if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) { 1129 dev_err(&indio_dev->dev, "calfact not consistent\n"); 1130 return -EIO; 1131 } 1132 1133 lincalrdyw_mask >>= 1; 1134 } 1135 1136 return 0; 1137} 1138 1139/* 1140 * Fixed timeout value for ADC calibration. 1141 * worst cases: 1142 * - low clock frequency 1143 * - maximum prescalers 1144 * Calibration requires: 1145 * - 131,072 ADC clock cycle for the linear calibration 1146 * - 20 ADC clock cycle for the offset calibration 1147 * 1148 * Set to 100ms for now 1149 */ 1150#define STM32H7_ADC_CALIB_TIMEOUT_US 100000 1151 1152/** 1153 * stm32h7_adc_selfcalib() - Procedure to calibrate ADC 1154 * @indio_dev: IIO device instance 1155 * @do_lincal: linear calibration request flag 1156 * Note: Must be called once ADC is out of power down. 1157 * 1158 * Run offset calibration unconditionally. 1159 * Run linear calibration if requested & supported. 1160 */ 1161static int stm32h7_adc_selfcalib(struct iio_dev *indio_dev, int do_lincal) 1162{ 1163 struct stm32_adc *adc = iio_priv(indio_dev); 1164 int ret; 1165 u32 msk = STM32H7_ADCALDIF; 1166 u32 val; 1167 1168 if (adc->cfg->has_linearcal && do_lincal) 1169 msk |= STM32H7_ADCALLIN; 1170 /* ADC must be disabled for calibration */ 1171 stm32h7_adc_disable(indio_dev); 1172 1173 /* 1174 * Select calibration mode: 1175 * - Offset calibration for single ended inputs 1176 * - No linearity calibration (do it later, before reading it) 1177 */ 1178 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, msk); 1179 1180 /* Start calibration, then wait for completion */ 1181 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); 1182 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 1183 !(val & STM32H7_ADCAL), 100, 1184 STM32H7_ADC_CALIB_TIMEOUT_US); 1185 if (ret) { 1186 dev_err(&indio_dev->dev, "calibration (single-ended) error %d\n", ret); 1187 goto out; 1188 } 1189 1190 /* 1191 * Select calibration mode, then start calibration: 1192 * - Offset calibration for differential input 1193 * - Linearity calibration (needs to be done only once for single/diff) 1194 * will run simultaneously with offset calibration. 1195 */ 1196 stm32_adc_set_bits(adc, STM32H7_ADC_CR, msk); 1197 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADCAL); 1198 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, 1199 !(val & STM32H7_ADCAL), 100, 1200 STM32H7_ADC_CALIB_TIMEOUT_US); 1201 if (ret) { 1202 dev_err(&indio_dev->dev, "calibration (diff%s) error %d\n", 1203 (msk & STM32H7_ADCALLIN) ? "+linear" : "", ret); 1204 goto out; 1205 } 1206 1207out: 1208 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, msk); 1209 1210 return ret; 1211} 1212 1213/** 1214 * stm32h7_adc_check_selfcalib() - Check linear calibration status 1215 * @indio_dev: IIO device instance 1216 * 1217 * Used to check if linear calibration has been done. 1218 * Return true if linear calibration factors are already saved in private data 1219 * or if a linear calibration has been done at boot stage. 1220 */ 1221static int stm32h7_adc_check_selfcalib(struct iio_dev *indio_dev) 1222{ 1223 struct stm32_adc *adc = iio_priv(indio_dev); 1224 u32 val; 1225 1226 if (adc->cal.lincal_saved) 1227 return true; 1228 1229 /* 1230 * Check if linear calibration factors are available in ADC registers, 1231 * by checking that all LINCALRDYWx bits are set. 1232 */ 1233 val = stm32_adc_readl(adc, STM32H7_ADC_CR) & STM32H7_LINCALRDYW_MASK; 1234 if (val == STM32H7_LINCALRDYW_MASK) 1235 return true; 1236 1237 return false; 1238} 1239 1240/** 1241 * stm32h7_adc_prepare() - Leave power down mode to enable ADC. 1242 * @indio_dev: IIO device instance 1243 * Leave power down mode. 1244 * Configure channels as single ended or differential before enabling ADC. 1245 * Enable ADC. 1246 * Restore calibration data. 1247 * Pre-select channels that may be used in PCSEL (required by input MUX / IO): 1248 * - Only one input is selected for single ended (e.g. 'vinp') 1249 * - Two inputs are selected for differential channels (e.g. 'vinp' & 'vinn') 1250 */ 1251static int stm32h7_adc_prepare(struct iio_dev *indio_dev) 1252{ 1253 struct stm32_adc *adc = iio_priv(indio_dev); 1254 int lincal_done = false; 1255 int ret; 1256 1257 ret = stm32h7_adc_exit_pwr_down(indio_dev); 1258 if (ret) 1259 return ret; 1260 1261 if (adc->cfg->has_linearcal) 1262 lincal_done = stm32h7_adc_check_selfcalib(indio_dev); 1263 1264 /* Always run offset calibration. Run linear calibration only once */ 1265 ret = stm32h7_adc_selfcalib(indio_dev, !lincal_done); 1266 if (ret < 0) 1267 goto pwr_dwn; 1268 1269 stm32_adc_int_ch_enable(indio_dev); 1270 1271 stm32_adc_writel(adc, adc->cfg->regs->difsel.reg, adc->difsel); 1272 1273 ret = stm32h7_adc_enable(indio_dev); 1274 if (ret) 1275 goto ch_disable; 1276 1277 if (adc->cfg->has_linearcal) { 1278 if (!adc->cal.lincal_saved) 1279 ret = stm32h7_adc_read_selfcalib(indio_dev); 1280 else 1281 ret = stm32h7_adc_restore_selfcalib(indio_dev); 1282 1283 if (ret) 1284 goto disable; 1285 } 1286 1287 if (adc->cfg->has_presel) 1288 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel); 1289 1290 return 0; 1291 1292disable: 1293 stm32h7_adc_disable(indio_dev); 1294ch_disable: 1295 stm32_adc_int_ch_disable(adc); 1296pwr_dwn: 1297 stm32h7_adc_enter_pwr_down(adc); 1298 1299 return ret; 1300} 1301 1302static void stm32h7_adc_unprepare(struct iio_dev *indio_dev) 1303{ 1304 struct stm32_adc *adc = iio_priv(indio_dev); 1305 1306 if (adc->cfg->has_presel) 1307 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, 0); 1308 stm32h7_adc_disable(indio_dev); 1309 stm32_adc_int_ch_disable(adc); 1310 stm32h7_adc_enter_pwr_down(adc); 1311} 1312 1313/** 1314 * stm32_adc_conf_scan_seq() - Build regular channels scan sequence 1315 * @indio_dev: IIO device 1316 * @scan_mask: channels to be converted 1317 * 1318 * Conversion sequence : 1319 * Apply sampling time settings for all channels. 1320 * Configure ADC scan sequence based on selected channels in scan_mask. 1321 * Add channels to SQR registers, from scan_mask LSB to MSB, then 1322 * program sequence len. 1323 */ 1324static int stm32_adc_conf_scan_seq(struct iio_dev *indio_dev, 1325 const unsigned long *scan_mask) 1326{ 1327 struct stm32_adc *adc = iio_priv(indio_dev); 1328 const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr; 1329 const struct iio_chan_spec *chan; 1330 u32 val, bit; 1331 int i = 0; 1332 1333 /* Apply sampling time settings */ 1334 stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]); 1335 stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]); 1336 1337 for_each_set_bit(bit, scan_mask, iio_get_masklength(indio_dev)) { 1338 chan = indio_dev->channels + bit; 1339 /* 1340 * Assign one channel per SQ entry in regular 1341 * sequence, starting with SQ1. 1342 */ 1343 i++; 1344 if (i > STM32_ADC_MAX_SQ) 1345 return -EINVAL; 1346 1347 dev_dbg(&indio_dev->dev, "%s chan %d to SQ%d\n", 1348 __func__, chan->channel, i); 1349 1350 val = stm32_adc_readl(adc, sqr[i].reg); 1351 val &= ~sqr[i].mask; 1352 val |= chan->channel << sqr[i].shift; 1353 stm32_adc_writel(adc, sqr[i].reg, val); 1354 } 1355 1356 if (!i) 1357 return -EINVAL; 1358 1359 /* Sequence len */ 1360 val = stm32_adc_readl(adc, sqr[0].reg); 1361 val &= ~sqr[0].mask; 1362 val |= ((i - 1) << sqr[0].shift); 1363 stm32_adc_writel(adc, sqr[0].reg, val); 1364 1365 return 0; 1366} 1367 1368/** 1369 * stm32_adc_get_trig_extsel() - Get external trigger selection 1370 * @indio_dev: IIO device structure 1371 * @trig: trigger 1372 * 1373 * Returns trigger extsel value, if trig matches, -EINVAL otherwise. 1374 */ 1375static int stm32_adc_get_trig_extsel(struct iio_dev *indio_dev, 1376 struct iio_trigger *trig) 1377{ 1378 struct stm32_adc *adc = iio_priv(indio_dev); 1379 int i; 1380 1381 /* lookup triggers registered by stm32 timer trigger driver */ 1382 for (i = 0; adc->cfg->trigs[i].name; i++) { 1383 /** 1384 * Checking both stm32 timer trigger type and trig name 1385 * should be safe against arbitrary trigger names. 1386 */ 1387 if ((is_stm32_timer_trigger(trig) || 1388 is_stm32_lptim_trigger(trig)) && 1389 !strcmp(adc->cfg->trigs[i].name, trig->name)) { 1390 return adc->cfg->trigs[i].extsel; 1391 } 1392 } 1393 1394 return -EINVAL; 1395} 1396 1397/** 1398 * stm32_adc_set_trig() - Set a regular trigger 1399 * @indio_dev: IIO device 1400 * @trig: IIO trigger 1401 * 1402 * Set trigger source/polarity (e.g. SW, or HW with polarity) : 1403 * - if HW trigger disabled (e.g. trig == NULL, conversion launched by sw) 1404 * - if HW trigger enabled, set source & polarity 1405 */ 1406static int stm32_adc_set_trig(struct iio_dev *indio_dev, 1407 struct iio_trigger *trig) 1408{ 1409 struct stm32_adc *adc = iio_priv(indio_dev); 1410 u32 val, extsel = 0, exten = STM32_EXTEN_SWTRIG; 1411 unsigned long flags; 1412 int ret; 1413 1414 if (trig) { 1415 ret = stm32_adc_get_trig_extsel(indio_dev, trig); 1416 if (ret < 0) 1417 return ret; 1418 1419 /* set trigger source and polarity (default to rising edge) */ 1420 extsel = ret; 1421 exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE; 1422 } 1423 1424 spin_lock_irqsave(&adc->lock, flags); 1425 val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg); 1426 val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask); 1427 val |= exten << adc->cfg->regs->exten.shift; 1428 val |= extsel << adc->cfg->regs->extsel.shift; 1429 stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val); 1430 spin_unlock_irqrestore(&adc->lock, flags); 1431 1432 return 0; 1433} 1434 1435static int stm32_adc_set_trig_pol(struct iio_dev *indio_dev, 1436 const struct iio_chan_spec *chan, 1437 unsigned int type) 1438{ 1439 struct stm32_adc *adc = iio_priv(indio_dev); 1440 1441 adc->trigger_polarity = type; 1442 1443 return 0; 1444} 1445 1446static int stm32_adc_get_trig_pol(struct iio_dev *indio_dev, 1447 const struct iio_chan_spec *chan) 1448{ 1449 struct stm32_adc *adc = iio_priv(indio_dev); 1450 1451 return adc->trigger_polarity; 1452} 1453 1454static const char * const stm32_trig_pol_items[] = { 1455 "rising-edge", "falling-edge", "both-edges", 1456}; 1457 1458static const struct iio_enum stm32_adc_trig_pol = { 1459 .items = stm32_trig_pol_items, 1460 .num_items = ARRAY_SIZE(stm32_trig_pol_items), 1461 .get = stm32_adc_get_trig_pol, 1462 .set = stm32_adc_set_trig_pol, 1463}; 1464 1465/** 1466 * stm32_adc_single_conv() - Performs a single conversion 1467 * @indio_dev: IIO device 1468 * @chan: IIO channel 1469 * @res: conversion result 1470 * 1471 * The function performs a single conversion on a given channel: 1472 * - Apply sampling time settings 1473 * - Program sequencer with one channel (e.g. in SQ1 with len = 1) 1474 * - Use SW trigger 1475 * - Start conversion, then wait for interrupt completion. 1476 */ 1477static int stm32_adc_single_conv(struct iio_dev *indio_dev, 1478 const struct iio_chan_spec *chan, 1479 int *res) 1480{ 1481 struct stm32_adc *adc = iio_priv(indio_dev); 1482 struct device *dev = indio_dev->dev.parent; 1483 const struct stm32_adc_regspec *regs = adc->cfg->regs; 1484 long time_left; 1485 u32 val; 1486 int ret; 1487 1488 reinit_completion(&adc->completion); 1489 1490 adc->bufi = 0; 1491 1492 ret = pm_runtime_resume_and_get(dev); 1493 if (ret < 0) 1494 return ret; 1495 1496 /* Apply sampling time settings */ 1497 stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]); 1498 stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]); 1499 1500 /* Program chan number in regular sequence (SQ1) */ 1501 val = stm32_adc_readl(adc, regs->sqr[1].reg); 1502 val &= ~regs->sqr[1].mask; 1503 val |= chan->channel << regs->sqr[1].shift; 1504 stm32_adc_writel(adc, regs->sqr[1].reg, val); 1505 1506 /* Set regular sequence len (0 for 1 conversion) */ 1507 stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask); 1508 1509 /* Trigger detection disabled (conversion can be launched in SW) */ 1510 stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask); 1511 1512 stm32_adc_conv_irq_enable(adc); 1513 1514 adc->cfg->start_conv(indio_dev, false); 1515 1516 time_left = wait_for_completion_interruptible_timeout( 1517 &adc->completion, STM32_ADC_TIMEOUT); 1518 if (time_left == 0) { 1519 ret = -ETIMEDOUT; 1520 } else if (time_left < 0) { 1521 ret = time_left; 1522 } else { 1523 *res = adc->buffer[0]; 1524 ret = IIO_VAL_INT; 1525 } 1526 1527 adc->cfg->stop_conv(indio_dev); 1528 1529 stm32_adc_conv_irq_disable(adc); 1530 1531 pm_runtime_put_autosuspend(dev); 1532 1533 return ret; 1534} 1535 1536static int stm32_adc_write_raw(struct iio_dev *indio_dev, 1537 struct iio_chan_spec const *chan, 1538 int val, int val2, long mask) 1539{ 1540 struct stm32_adc *adc = iio_priv(indio_dev); 1541 struct device *dev = indio_dev->dev.parent; 1542 int nb = adc->cfg->adc_info->num_ovs; 1543 unsigned int idx; 1544 int ret; 1545 1546 switch (mask) { 1547 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1548 if (val2) 1549 return -EINVAL; 1550 1551 for (idx = 0; idx < nb; idx++) 1552 if (adc->cfg->adc_info->oversampling[idx] == val) 1553 break; 1554 if (idx >= nb) 1555 return -EINVAL; 1556 1557 if (!iio_device_claim_direct(indio_dev)) 1558 return -EBUSY; 1559 1560 ret = pm_runtime_resume_and_get(dev); 1561 if (ret < 0) 1562 goto err; 1563 1564 adc->cfg->set_ovs(indio_dev, idx); 1565 1566 pm_runtime_put_autosuspend(dev); 1567 1568 adc->ovs_idx = idx; 1569 1570err: 1571 iio_device_release_direct(indio_dev); 1572 1573 return ret; 1574 default: 1575 return -EINVAL; 1576 } 1577} 1578 1579static int stm32_adc_read_avail(struct iio_dev *indio_dev, 1580 struct iio_chan_spec const *chan, 1581 const int **vals, int *type, int *length, long m) 1582{ 1583 struct stm32_adc *adc = iio_priv(indio_dev); 1584 1585 switch (m) { 1586 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1587 *type = IIO_VAL_INT; 1588 *length = adc->cfg->adc_info->num_ovs; 1589 *vals = adc->cfg->adc_info->oversampling; 1590 return IIO_AVAIL_LIST; 1591 default: 1592 return -EINVAL; 1593 } 1594} 1595 1596static int stm32_adc_read_raw(struct iio_dev *indio_dev, 1597 struct iio_chan_spec const *chan, 1598 int *val, int *val2, long mask) 1599{ 1600 struct stm32_adc *adc = iio_priv(indio_dev); 1601 int ret; 1602 1603 switch (mask) { 1604 case IIO_CHAN_INFO_RAW: 1605 case IIO_CHAN_INFO_PROCESSED: 1606 if (!iio_device_claim_direct(indio_dev)) 1607 return -EBUSY; 1608 if (chan->type == IIO_VOLTAGE) 1609 ret = stm32_adc_single_conv(indio_dev, chan, val); 1610 else 1611 ret = -EINVAL; 1612 1613 if (mask == IIO_CHAN_INFO_PROCESSED) 1614 *val = STM32_ADC_VREFINT_VOLTAGE * adc->vrefint.vrefint_cal / *val; 1615 1616 iio_device_release_direct(indio_dev); 1617 return ret; 1618 1619 case IIO_CHAN_INFO_SCALE: 1620 if (chan->differential) { 1621 *val = adc->common->vref_mv * 2; 1622 *val2 = chan->scan_type.realbits; 1623 } else { 1624 *val = adc->common->vref_mv; 1625 *val2 = chan->scan_type.realbits; 1626 } 1627 return IIO_VAL_FRACTIONAL_LOG2; 1628 1629 case IIO_CHAN_INFO_OFFSET: 1630 if (chan->differential) 1631 /* ADC_full_scale / 2 */ 1632 *val = -((1 << chan->scan_type.realbits) / 2); 1633 else 1634 *val = 0; 1635 return IIO_VAL_INT; 1636 1637 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1638 *val = adc->cfg->adc_info->oversampling[adc->ovs_idx]; 1639 return IIO_VAL_INT; 1640 1641 default: 1642 return -EINVAL; 1643 } 1644} 1645 1646static void stm32_adc_irq_clear(struct iio_dev *indio_dev, u32 msk) 1647{ 1648 struct stm32_adc *adc = iio_priv(indio_dev); 1649 1650 adc->cfg->irq_clear(indio_dev, msk); 1651} 1652 1653static irqreturn_t stm32_adc_threaded_isr(int irq, void *data) 1654{ 1655 struct iio_dev *indio_dev = data; 1656 struct stm32_adc *adc = iio_priv(indio_dev); 1657 const struct stm32_adc_regspec *regs = adc->cfg->regs; 1658 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); 1659 1660 /* Check ovr status right now, as ovr mask should be already disabled */ 1661 if (status & regs->isr_ovr.mask) { 1662 /* 1663 * Clear ovr bit to avoid subsequent calls to IRQ handler. 1664 * This requires to stop ADC first. OVR bit state in ISR, 1665 * is propaged to CSR register by hardware. 1666 */ 1667 adc->cfg->stop_conv(indio_dev); 1668 stm32_adc_irq_clear(indio_dev, regs->isr_ovr.mask); 1669 dev_err(&indio_dev->dev, "Overrun, stopping: restart needed\n"); 1670 return IRQ_HANDLED; 1671 } 1672 1673 return IRQ_NONE; 1674} 1675 1676static irqreturn_t stm32_adc_isr(int irq, void *data) 1677{ 1678 struct iio_dev *indio_dev = data; 1679 struct stm32_adc *adc = iio_priv(indio_dev); 1680 const struct stm32_adc_regspec *regs = adc->cfg->regs; 1681 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); 1682 1683 if (status & regs->isr_ovr.mask) { 1684 /* 1685 * Overrun occurred on regular conversions: data for wrong 1686 * channel may be read. Unconditionally disable interrupts 1687 * to stop processing data and print error message. 1688 * Restarting the capture can be done by disabling, then 1689 * re-enabling it (e.g. write 0, then 1 to buffer/enable). 1690 */ 1691 stm32_adc_ovr_irq_disable(adc); 1692 stm32_adc_conv_irq_disable(adc); 1693 return IRQ_WAKE_THREAD; 1694 } 1695 1696 if (status & regs->isr_eoc.mask) { 1697 /* Reading DR also clears EOC status flag */ 1698 adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr); 1699 if (iio_buffer_enabled(indio_dev)) { 1700 adc->bufi++; 1701 if (adc->bufi >= adc->num_conv) { 1702 stm32_adc_conv_irq_disable(adc); 1703 iio_trigger_poll(indio_dev->trig); 1704 } 1705 } else { 1706 complete(&adc->completion); 1707 } 1708 return IRQ_HANDLED; 1709 } 1710 1711 return IRQ_NONE; 1712} 1713 1714/** 1715 * stm32_adc_validate_trigger() - validate trigger for stm32 adc 1716 * @indio_dev: IIO device 1717 * @trig: new trigger 1718 * 1719 * Returns: 0 if trig matches one of the triggers registered by stm32 adc 1720 * driver, -EINVAL otherwise. 1721 */ 1722static int stm32_adc_validate_trigger(struct iio_dev *indio_dev, 1723 struct iio_trigger *trig) 1724{ 1725 return stm32_adc_get_trig_extsel(indio_dev, trig) < 0 ? -EINVAL : 0; 1726} 1727 1728static int stm32_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val) 1729{ 1730 struct stm32_adc *adc = iio_priv(indio_dev); 1731 unsigned int watermark = STM32_DMA_BUFFER_SIZE / 2; 1732 unsigned int rx_buf_sz = STM32_DMA_BUFFER_SIZE; 1733 1734 /* 1735 * dma cyclic transfers are used, buffer is split into two periods. 1736 * There should be : 1737 * - always one buffer (period) dma is working on 1738 * - one buffer (period) driver can push data. 1739 */ 1740 watermark = min(watermark, val * (unsigned)(sizeof(u16))); 1741 adc->rx_buf_sz = min(rx_buf_sz, watermark * 2 * adc->num_conv); 1742 1743 return 0; 1744} 1745 1746static int stm32_adc_update_scan_mode(struct iio_dev *indio_dev, 1747 const unsigned long *scan_mask) 1748{ 1749 struct stm32_adc *adc = iio_priv(indio_dev); 1750 struct device *dev = indio_dev->dev.parent; 1751 int ret; 1752 1753 ret = pm_runtime_resume_and_get(dev); 1754 if (ret < 0) 1755 return ret; 1756 1757 adc->num_conv = bitmap_weight(scan_mask, iio_get_masklength(indio_dev)); 1758 1759 ret = stm32_adc_conf_scan_seq(indio_dev, scan_mask); 1760 pm_runtime_put_autosuspend(dev); 1761 1762 return ret; 1763} 1764 1765static int stm32_adc_fwnode_xlate(struct iio_dev *indio_dev, 1766 const struct fwnode_reference_args *iiospec) 1767{ 1768 int i; 1769 1770 for (i = 0; i < indio_dev->num_channels; i++) 1771 if (indio_dev->channels[i].channel == iiospec->args[0]) 1772 return i; 1773 1774 return -EINVAL; 1775} 1776 1777/** 1778 * stm32_adc_debugfs_reg_access - read or write register value 1779 * @indio_dev: IIO device structure 1780 * @reg: register offset 1781 * @writeval: value to write 1782 * @readval: value to read 1783 * 1784 * To read a value from an ADC register: 1785 * echo [ADC reg offset] > direct_reg_access 1786 * cat direct_reg_access 1787 * 1788 * To write a value in a ADC register: 1789 * echo [ADC_reg_offset] [value] > direct_reg_access 1790 */ 1791static int stm32_adc_debugfs_reg_access(struct iio_dev *indio_dev, 1792 unsigned reg, unsigned writeval, 1793 unsigned *readval) 1794{ 1795 struct stm32_adc *adc = iio_priv(indio_dev); 1796 struct device *dev = indio_dev->dev.parent; 1797 int ret; 1798 1799 ret = pm_runtime_resume_and_get(dev); 1800 if (ret < 0) 1801 return ret; 1802 1803 if (!readval) 1804 stm32_adc_writel(adc, reg, writeval); 1805 else 1806 *readval = stm32_adc_readl(adc, reg); 1807 1808 pm_runtime_put_autosuspend(dev); 1809 1810 return 0; 1811} 1812 1813static const struct iio_info stm32_adc_iio_info = { 1814 .read_raw = stm32_adc_read_raw, 1815 .write_raw = stm32_adc_write_raw, 1816 .read_avail = stm32_adc_read_avail, 1817 .validate_trigger = stm32_adc_validate_trigger, 1818 .hwfifo_set_watermark = stm32_adc_set_watermark, 1819 .update_scan_mode = stm32_adc_update_scan_mode, 1820 .debugfs_reg_access = stm32_adc_debugfs_reg_access, 1821 .fwnode_xlate = stm32_adc_fwnode_xlate, 1822}; 1823 1824static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc) 1825{ 1826 struct dma_tx_state state; 1827 enum dma_status status; 1828 1829 status = dmaengine_tx_status(adc->dma_chan, 1830 adc->dma_chan->cookie, 1831 &state); 1832 if (status == DMA_IN_PROGRESS) { 1833 /* Residue is size in bytes from end of buffer */ 1834 unsigned int i = adc->rx_buf_sz - state.residue; 1835 unsigned int size; 1836 1837 /* Return available bytes */ 1838 if (i >= adc->bufi) 1839 size = i - adc->bufi; 1840 else 1841 size = adc->rx_buf_sz + i - adc->bufi; 1842 1843 return size; 1844 } 1845 1846 return 0; 1847} 1848 1849static void stm32_adc_dma_buffer_done(void *data) 1850{ 1851 struct iio_dev *indio_dev = data; 1852 struct stm32_adc *adc = iio_priv(indio_dev); 1853 int residue = stm32_adc_dma_residue(adc); 1854 1855 /* 1856 * In DMA mode the trigger services of IIO are not used 1857 * (e.g. no call to iio_trigger_poll). 1858 * Calling irq handler associated to the hardware trigger is not 1859 * relevant as the conversions have already been done. Data 1860 * transfers are performed directly in DMA callback instead. 1861 * This implementation avoids to call trigger irq handler that 1862 * may sleep, in an atomic context (DMA irq handler context). 1863 */ 1864 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); 1865 1866 while (residue >= indio_dev->scan_bytes) { 1867 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi]; 1868 1869 iio_push_to_buffers(indio_dev, buffer); 1870 1871 residue -= indio_dev->scan_bytes; 1872 adc->bufi += indio_dev->scan_bytes; 1873 if (adc->bufi >= adc->rx_buf_sz) 1874 adc->bufi = 0; 1875 } 1876} 1877 1878static int stm32_adc_dma_start(struct iio_dev *indio_dev) 1879{ 1880 struct stm32_adc *adc = iio_priv(indio_dev); 1881 struct dma_async_tx_descriptor *desc; 1882 dma_cookie_t cookie; 1883 int ret; 1884 1885 if (!adc->dma_chan) 1886 return 0; 1887 1888 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__, 1889 adc->rx_buf_sz, adc->rx_buf_sz / 2); 1890 1891 /* Prepare a DMA cyclic transaction */ 1892 desc = dmaengine_prep_dma_cyclic(adc->dma_chan, 1893 adc->rx_dma_buf, 1894 adc->rx_buf_sz, adc->rx_buf_sz / 2, 1895 DMA_DEV_TO_MEM, 1896 DMA_PREP_INTERRUPT); 1897 if (!desc) 1898 return -EBUSY; 1899 1900 desc->callback = stm32_adc_dma_buffer_done; 1901 desc->callback_param = indio_dev; 1902 1903 cookie = dmaengine_submit(desc); 1904 ret = dma_submit_error(cookie); 1905 if (ret) { 1906 dmaengine_terminate_sync(adc->dma_chan); 1907 return ret; 1908 } 1909 1910 /* Issue pending DMA requests */ 1911 dma_async_issue_pending(adc->dma_chan); 1912 1913 return 0; 1914} 1915 1916static int stm32_adc_buffer_postenable(struct iio_dev *indio_dev) 1917{ 1918 struct stm32_adc *adc = iio_priv(indio_dev); 1919 struct device *dev = indio_dev->dev.parent; 1920 int ret; 1921 1922 ret = pm_runtime_resume_and_get(dev); 1923 if (ret < 0) 1924 return ret; 1925 1926 ret = stm32_adc_set_trig(indio_dev, indio_dev->trig); 1927 if (ret) { 1928 dev_err(&indio_dev->dev, "Can't set trigger\n"); 1929 goto err_pm_put; 1930 } 1931 1932 ret = stm32_adc_dma_start(indio_dev); 1933 if (ret) { 1934 dev_err(&indio_dev->dev, "Can't start dma\n"); 1935 goto err_clr_trig; 1936 } 1937 1938 /* Reset adc buffer index */ 1939 adc->bufi = 0; 1940 1941 stm32_adc_ovr_irq_enable(adc); 1942 1943 if (!adc->dma_chan) 1944 stm32_adc_conv_irq_enable(adc); 1945 1946 adc->cfg->start_conv(indio_dev, !!adc->dma_chan); 1947 1948 return 0; 1949 1950err_clr_trig: 1951 stm32_adc_set_trig(indio_dev, NULL); 1952err_pm_put: 1953 pm_runtime_put_autosuspend(dev); 1954 1955 return ret; 1956} 1957 1958static int stm32_adc_buffer_predisable(struct iio_dev *indio_dev) 1959{ 1960 struct stm32_adc *adc = iio_priv(indio_dev); 1961 struct device *dev = indio_dev->dev.parent; 1962 1963 adc->cfg->stop_conv(indio_dev); 1964 if (!adc->dma_chan) 1965 stm32_adc_conv_irq_disable(adc); 1966 1967 stm32_adc_ovr_irq_disable(adc); 1968 1969 if (adc->dma_chan) 1970 dmaengine_terminate_sync(adc->dma_chan); 1971 1972 if (stm32_adc_set_trig(indio_dev, NULL)) 1973 dev_err(&indio_dev->dev, "Can't clear trigger\n"); 1974 1975 pm_runtime_put_autosuspend(dev); 1976 1977 return 0; 1978} 1979 1980static const struct iio_buffer_setup_ops stm32_adc_buffer_setup_ops = { 1981 .postenable = &stm32_adc_buffer_postenable, 1982 .predisable = &stm32_adc_buffer_predisable, 1983}; 1984 1985static irqreturn_t stm32_adc_trigger_handler(int irq, void *p) 1986{ 1987 struct iio_poll_func *pf = p; 1988 struct iio_dev *indio_dev = pf->indio_dev; 1989 struct stm32_adc *adc = iio_priv(indio_dev); 1990 1991 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); 1992 1993 /* reset buffer index */ 1994 adc->bufi = 0; 1995 iio_push_to_buffers_with_ts(indio_dev, adc->buffer, sizeof(adc->buffer), 1996 pf->timestamp); 1997 iio_trigger_notify_done(indio_dev->trig); 1998 1999 /* re-enable eoc irq */ 2000 stm32_adc_conv_irq_enable(adc); 2001 2002 return IRQ_HANDLED; 2003} 2004 2005static const struct iio_chan_spec_ext_info stm32_adc_ext_info[] = { 2006 IIO_ENUM("trigger_polarity", IIO_SHARED_BY_ALL, &stm32_adc_trig_pol), 2007 { 2008 .name = "trigger_polarity_available", 2009 .shared = IIO_SHARED_BY_ALL, 2010 .read = iio_enum_available_read, 2011 .private = (uintptr_t)&stm32_adc_trig_pol, 2012 }, 2013 { } 2014}; 2015 2016static void stm32_adc_debugfs_init(struct iio_dev *indio_dev) 2017{ 2018 struct stm32_adc *adc = iio_priv(indio_dev); 2019 struct dentry *d = iio_get_debugfs_dentry(indio_dev); 2020 struct stm32_adc_calib *cal = &adc->cal; 2021 char buf[16]; 2022 unsigned int i; 2023 2024 if (!adc->cfg->has_linearcal) 2025 return; 2026 2027 for (i = 0; i < STM32H7_LINCALFACT_NUM; i++) { 2028 snprintf(buf, sizeof(buf), "lincalfact%d", i + 1); 2029 debugfs_create_u32(buf, 0444, d, &cal->lincalfact[i]); 2030 } 2031} 2032 2033static int stm32_adc_fw_get_resolution(struct iio_dev *indio_dev) 2034{ 2035 struct device *dev = &indio_dev->dev; 2036 struct stm32_adc *adc = iio_priv(indio_dev); 2037 unsigned int i; 2038 u32 res; 2039 2040 if (device_property_read_u32(dev, "assigned-resolution-bits", &res)) 2041 res = adc->cfg->adc_info->resolutions[0]; 2042 2043 for (i = 0; i < adc->cfg->adc_info->num_res; i++) 2044 if (res == adc->cfg->adc_info->resolutions[i]) 2045 break; 2046 if (i >= adc->cfg->adc_info->num_res) { 2047 dev_err(&indio_dev->dev, "Bad resolution: %u bits\n", res); 2048 return -EINVAL; 2049 } 2050 2051 dev_dbg(&indio_dev->dev, "Using %u bits resolution\n", res); 2052 adc->res = i; 2053 2054 return 0; 2055} 2056 2057static void stm32_adc_smpr_init(struct stm32_adc *adc, int channel, u32 smp_ns) 2058{ 2059 const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel]; 2060 u32 period_ns, shift = smpr->shift, mask = smpr->mask; 2061 unsigned int i, smp, r = smpr->reg; 2062 2063 /* 2064 * For internal channels, ensure that the sampling time cannot 2065 * be lower than the one specified in the datasheet 2066 */ 2067 for (i = 0; i < STM32_ADC_INT_CH_NB; i++) 2068 if (channel == adc->int_ch[i] && adc->int_ch[i] != STM32_ADC_INT_CH_NONE) 2069 smp_ns = max(smp_ns, adc->cfg->ts_int_ch[i]); 2070 2071 /* Determine sampling time (ADC clock cycles) */ 2072 period_ns = NSEC_PER_SEC / adc->common->rate; 2073 for (smp = 0; smp <= STM32_ADC_MAX_SMP; smp++) 2074 if ((period_ns * adc->cfg->smp_cycles[smp]) >= smp_ns) 2075 break; 2076 if (smp > STM32_ADC_MAX_SMP) 2077 smp = STM32_ADC_MAX_SMP; 2078 2079 /* pre-build sampling time registers (e.g. smpr1, smpr2) */ 2080 adc->smpr_val[r] = (adc->smpr_val[r] & ~mask) | (smp << shift); 2081} 2082 2083static void stm32_adc_chan_init_one(struct iio_dev *indio_dev, 2084 struct iio_chan_spec *chan, u32 vinp, 2085 u32 vinn, int scan_index, bool differential) 2086{ 2087 struct stm32_adc *adc = iio_priv(indio_dev); 2088 char *name = adc->chan_name[vinp]; 2089 2090 chan->type = IIO_VOLTAGE; 2091 chan->channel = vinp; 2092 if (differential) { 2093 chan->differential = 1; 2094 chan->channel2 = vinn; 2095 snprintf(name, STM32_ADC_CH_SZ, "in%d-in%d", vinp, vinn); 2096 } else { 2097 snprintf(name, STM32_ADC_CH_SZ, "in%d", vinp); 2098 } 2099 chan->datasheet_name = name; 2100 chan->scan_index = scan_index; 2101 chan->indexed = 1; 2102 if (chan->channel == adc->int_ch[STM32_ADC_INT_CH_VREFINT]) 2103 chan->info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED); 2104 else 2105 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 2106 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | 2107 BIT(IIO_CHAN_INFO_OFFSET); 2108 if (adc->cfg->has_oversampling) { 2109 chan->info_mask_shared_by_all |= BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO); 2110 chan->info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO); 2111 } 2112 chan->scan_type.sign = 'u'; 2113 chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res]; 2114 chan->scan_type.storagebits = 16; 2115 chan->ext_info = stm32_adc_ext_info; 2116 2117 /* pre-build selected channels mask */ 2118 adc->pcsel |= BIT(chan->channel); 2119 if (differential) { 2120 /* pre-build diff channels mask */ 2121 adc->difsel |= BIT(chan->channel) & adc->cfg->regs->difsel.mask; 2122 /* Also add negative input to pre-selected channels */ 2123 adc->pcsel |= BIT(chan->channel2); 2124 } 2125} 2126 2127static int stm32_adc_get_legacy_chan_count(struct iio_dev *indio_dev, struct stm32_adc *adc) 2128{ 2129 struct device *dev = &indio_dev->dev; 2130 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; 2131 int num_channels = 0, ret; 2132 2133 dev_dbg(&indio_dev->dev, "using legacy channel config\n"); 2134 2135 ret = device_property_count_u32(dev, "st,adc-channels"); 2136 if (ret > adc_info->max_channels) { 2137 dev_err(&indio_dev->dev, "Bad st,adc-channels?\n"); 2138 return -EINVAL; 2139 } else if (ret > 0) { 2140 num_channels += ret; 2141 } 2142 2143 /* 2144 * each st,adc-diff-channels is a group of 2 u32 so we divide @ret 2145 * to get the *real* number of channels. 2146 */ 2147 ret = device_property_count_u32(dev, "st,adc-diff-channels"); 2148 if (ret > 0) { 2149 ret /= (int)(sizeof(struct stm32_adc_diff_channel) / sizeof(u32)); 2150 if (ret > adc_info->max_channels) { 2151 dev_err(&indio_dev->dev, "Bad st,adc-diff-channels?\n"); 2152 return -EINVAL; 2153 } else if (ret > 0) { 2154 adc->num_diff = ret; 2155 num_channels += ret; 2156 } 2157 } 2158 2159 /* Optional sample time is provided either for each, or all channels */ 2160 adc->nsmps = device_property_count_u32(dev, "st,min-sample-time-nsecs"); 2161 if (adc->nsmps > 1 && adc->nsmps != num_channels) { 2162 dev_err(&indio_dev->dev, "Invalid st,min-sample-time-nsecs\n"); 2163 return -EINVAL; 2164 } 2165 2166 return num_channels; 2167} 2168 2169static int stm32_adc_legacy_chan_init(struct iio_dev *indio_dev, 2170 struct stm32_adc *adc, 2171 struct iio_chan_spec *channels, 2172 int nchans) 2173{ 2174 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; 2175 struct stm32_adc_diff_channel diff[STM32_ADC_CH_MAX]; 2176 struct device *dev = &indio_dev->dev; 2177 u32 num_diff = adc->num_diff; 2178 int num_se = nchans - num_diff; 2179 int size = num_diff * sizeof(*diff) / sizeof(u32); 2180 int scan_index = 0, ret, i, c; 2181 u32 smp = 0, smps[STM32_ADC_CH_MAX], chans[STM32_ADC_CH_MAX]; 2182 2183 if (num_diff) { 2184 ret = device_property_read_u32_array(dev, "st,adc-diff-channels", 2185 (u32 *)diff, size); 2186 if (ret) { 2187 dev_err(&indio_dev->dev, "Failed to get diff channels %d\n", ret); 2188 return ret; 2189 } 2190 2191 for (i = 0; i < num_diff; i++) { 2192 if (diff[i].vinp >= adc_info->max_channels || 2193 diff[i].vinn >= adc_info->max_channels) { 2194 dev_err(&indio_dev->dev, "Invalid channel in%d-in%d\n", 2195 diff[i].vinp, diff[i].vinn); 2196 return -EINVAL; 2197 } 2198 2199 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], 2200 diff[i].vinp, diff[i].vinn, 2201 scan_index, true); 2202 scan_index++; 2203 } 2204 } 2205 if (num_se > 0) { 2206 ret = device_property_read_u32_array(dev, "st,adc-channels", chans, num_se); 2207 if (ret) { 2208 dev_err(&indio_dev->dev, "Failed to get st,adc-channels %d\n", ret); 2209 return ret; 2210 } 2211 2212 for (c = 0; c < num_se; c++) { 2213 if (chans[c] >= adc_info->max_channels) { 2214 dev_err(&indio_dev->dev, "Invalid channel %d\n", 2215 chans[c]); 2216 return -EINVAL; 2217 } 2218 2219 /* Channel can't be configured both as single-ended & diff */ 2220 for (i = 0; i < num_diff; i++) { 2221 if (chans[c] == diff[i].vinp) { 2222 dev_err(&indio_dev->dev, "channel %d misconfigured\n", 2223 chans[c]); 2224 return -EINVAL; 2225 } 2226 } 2227 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], 2228 chans[c], 0, scan_index, false); 2229 scan_index++; 2230 } 2231 } 2232 2233 if (adc->nsmps > 0) { 2234 ret = device_property_read_u32_array(dev, "st,min-sample-time-nsecs", 2235 smps, adc->nsmps); 2236 if (ret) 2237 return ret; 2238 } 2239 2240 for (i = 0; i < scan_index; i++) { 2241 /* 2242 * This check is used with the above logic so that smp value 2243 * will only be modified if valid u32 value can be decoded. This 2244 * allows to get either no value, 1 shared value for all indexes, 2245 * or one value per channel. The point is to have the same 2246 * behavior as 'of_property_read_u32_index()'. 2247 */ 2248 if (i < adc->nsmps) 2249 smp = smps[i]; 2250 2251 /* Prepare sampling time settings */ 2252 stm32_adc_smpr_init(adc, channels[i].channel, smp); 2253 } 2254 2255 return scan_index; 2256} 2257 2258static int stm32_adc_populate_int_ch(struct iio_dev *indio_dev, const char *ch_name, 2259 int chan) 2260{ 2261 struct stm32_adc *adc = iio_priv(indio_dev); 2262 u16 vrefint; 2263 int i, ret; 2264 2265 for (i = 0; i < STM32_ADC_INT_CH_NB; i++) { 2266 if (!strncmp(stm32_adc_ic[i].name, ch_name, STM32_ADC_CH_SZ)) { 2267 /* Check internal channel availability */ 2268 switch (i) { 2269 case STM32_ADC_INT_CH_VDDCORE: 2270 if (!adc->cfg->regs->or_vddcore.reg) 2271 dev_warn(&indio_dev->dev, 2272 "%s channel not available\n", ch_name); 2273 break; 2274 case STM32_ADC_INT_CH_VDDCPU: 2275 if (!adc->cfg->regs->or_vddcpu.reg) 2276 dev_warn(&indio_dev->dev, 2277 "%s channel not available\n", ch_name); 2278 break; 2279 case STM32_ADC_INT_CH_VDDQ_DDR: 2280 if (!adc->cfg->regs->or_vddq_ddr.reg) 2281 dev_warn(&indio_dev->dev, 2282 "%s channel not available\n", ch_name); 2283 break; 2284 case STM32_ADC_INT_CH_VREFINT: 2285 if (!adc->cfg->regs->ccr_vref.reg) 2286 dev_warn(&indio_dev->dev, 2287 "%s channel not available\n", ch_name); 2288 break; 2289 case STM32_ADC_INT_CH_VBAT: 2290 if (!adc->cfg->regs->ccr_vbat.reg) 2291 dev_warn(&indio_dev->dev, 2292 "%s channel not available\n", ch_name); 2293 break; 2294 } 2295 2296 if (stm32_adc_ic[i].idx != STM32_ADC_INT_CH_VREFINT) { 2297 adc->int_ch[i] = chan; 2298 break; 2299 } 2300 2301 /* Get calibration data for vrefint channel */ 2302 ret = nvmem_cell_read_u16(&indio_dev->dev, "vrefint", &vrefint); 2303 if (ret && ret != -ENOENT) { 2304 return dev_err_probe(indio_dev->dev.parent, ret, 2305 "nvmem access error\n"); 2306 } 2307 if (ret == -ENOENT) { 2308 dev_dbg(&indio_dev->dev, "vrefint calibration not found. Skip vrefint channel\n"); 2309 return ret; 2310 } else if (!vrefint) { 2311 dev_dbg(&indio_dev->dev, "Null vrefint calibration value. Skip vrefint channel\n"); 2312 return -ENOENT; 2313 } 2314 adc->int_ch[i] = chan; 2315 adc->vrefint.vrefint_cal = vrefint; 2316 } 2317 } 2318 2319 return 0; 2320} 2321 2322static int stm32_adc_generic_chan_init(struct iio_dev *indio_dev, 2323 struct stm32_adc *adc, 2324 struct iio_chan_spec *channels) 2325{ 2326 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; 2327 struct device *dev = &indio_dev->dev; 2328 const char *name; 2329 int val, scan_index = 0, ret; 2330 bool differential; 2331 u32 vin[2]; 2332 2333 device_for_each_child_node_scoped(dev, child) { 2334 ret = fwnode_property_read_u32(child, "reg", &val); 2335 if (ret) 2336 return dev_err_probe(dev, ret, 2337 "Missing channel index\n"); 2338 2339 ret = fwnode_property_read_string(child, "label", &name); 2340 /* label is optional */ 2341 if (!ret) { 2342 if (strlen(name) >= STM32_ADC_CH_SZ) 2343 return dev_err_probe(dev, -EINVAL, 2344 "Label %s exceeds %d characters\n", 2345 name, STM32_ADC_CH_SZ); 2346 2347 strscpy(adc->chan_name[val], name, STM32_ADC_CH_SZ); 2348 ret = stm32_adc_populate_int_ch(indio_dev, name, val); 2349 if (ret == -ENOENT) 2350 continue; 2351 else if (ret) 2352 return ret; 2353 } else if (ret != -EINVAL) { 2354 return dev_err_probe(dev, ret, "Invalid label\n"); 2355 } 2356 2357 if (val >= adc_info->max_channels) 2358 return dev_err_probe(dev, -EINVAL, 2359 "Invalid channel %d\n", val); 2360 2361 differential = false; 2362 ret = fwnode_property_read_u32_array(child, "diff-channels", vin, 2); 2363 /* diff-channels is optional */ 2364 if (!ret) { 2365 differential = true; 2366 if (vin[0] != val || vin[1] >= adc_info->max_channels) 2367 return dev_err_probe(dev, -EINVAL, 2368 "Invalid channel in%d-in%d\n", 2369 vin[0], vin[1]); 2370 } else if (ret != -EINVAL) { 2371 return dev_err_probe(dev, ret, 2372 "Invalid diff-channels property\n"); 2373 } 2374 2375 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], val, 2376 vin[1], scan_index, differential); 2377 2378 val = 0; 2379 ret = fwnode_property_read_u32(child, "st,min-sample-time-ns", &val); 2380 /* st,min-sample-time-ns is optional */ 2381 if (ret && ret != -EINVAL) 2382 return dev_err_probe(dev, ret, 2383 "Invalid st,min-sample-time-ns property\n"); 2384 2385 stm32_adc_smpr_init(adc, channels[scan_index].channel, val); 2386 if (differential) 2387 stm32_adc_smpr_init(adc, vin[1], val); 2388 2389 scan_index++; 2390 } 2391 2392 return scan_index; 2393} 2394 2395static int stm32_adc_chan_fw_init(struct iio_dev *indio_dev, bool timestamping) 2396{ 2397 struct stm32_adc *adc = iio_priv(indio_dev); 2398 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; 2399 struct iio_chan_spec *channels; 2400 int scan_index = 0, num_channels = 0, ret, i; 2401 bool legacy = false; 2402 2403 for (i = 0; i < STM32_ADC_INT_CH_NB; i++) 2404 adc->int_ch[i] = STM32_ADC_INT_CH_NONE; 2405 2406 num_channels = device_get_child_node_count(&indio_dev->dev); 2407 /* If no channels have been found, fallback to channels legacy properties. */ 2408 if (!num_channels) { 2409 legacy = true; 2410 2411 ret = stm32_adc_get_legacy_chan_count(indio_dev, adc); 2412 if (!ret) { 2413 dev_err(indio_dev->dev.parent, "No channel found\n"); 2414 return -ENODATA; 2415 } else if (ret < 0) { 2416 return ret; 2417 } 2418 2419 num_channels = ret; 2420 } 2421 2422 if (num_channels > adc_info->max_channels) { 2423 dev_err(&indio_dev->dev, "Channel number [%d] exceeds %d\n", 2424 num_channels, adc_info->max_channels); 2425 return -EINVAL; 2426 } 2427 2428 if (timestamping) 2429 num_channels++; 2430 2431 channels = devm_kcalloc(&indio_dev->dev, num_channels, 2432 sizeof(struct iio_chan_spec), GFP_KERNEL); 2433 if (!channels) 2434 return -ENOMEM; 2435 2436 if (legacy) 2437 ret = stm32_adc_legacy_chan_init(indio_dev, adc, channels, 2438 timestamping ? num_channels - 1 : num_channels); 2439 else 2440 ret = stm32_adc_generic_chan_init(indio_dev, adc, channels); 2441 if (ret < 0) 2442 return ret; 2443 scan_index = ret; 2444 2445 if (timestamping) { 2446 struct iio_chan_spec *timestamp = &channels[scan_index]; 2447 2448 timestamp->type = IIO_TIMESTAMP; 2449 timestamp->channel = -1; 2450 timestamp->scan_index = scan_index; 2451 timestamp->scan_type.sign = 's'; 2452 timestamp->scan_type.realbits = 64; 2453 timestamp->scan_type.storagebits = 64; 2454 2455 scan_index++; 2456 } 2457 2458 indio_dev->num_channels = scan_index; 2459 indio_dev->channels = channels; 2460 2461 return 0; 2462} 2463 2464static int stm32_adc_dma_request(struct device *dev, struct iio_dev *indio_dev) 2465{ 2466 struct stm32_adc *adc = iio_priv(indio_dev); 2467 struct dma_slave_config config = { }; 2468 int ret; 2469 2470 adc->dma_chan = dma_request_chan(dev, "rx"); 2471 if (IS_ERR(adc->dma_chan)) { 2472 ret = PTR_ERR(adc->dma_chan); 2473 if (ret != -ENODEV) 2474 return dev_err_probe(dev, ret, 2475 "DMA channel request failed with\n"); 2476 2477 /* DMA is optional: fall back to IRQ mode */ 2478 adc->dma_chan = NULL; 2479 return 0; 2480 } 2481 2482 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev, 2483 STM32_DMA_BUFFER_SIZE, 2484 &adc->rx_dma_buf, GFP_KERNEL); 2485 if (!adc->rx_buf) { 2486 ret = -ENOMEM; 2487 goto err_release; 2488 } 2489 2490 /* Configure DMA channel to read data register */ 2491 config.src_addr = (dma_addr_t)adc->common->phys_base; 2492 config.src_addr += adc->offset + adc->cfg->regs->dr; 2493 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 2494 2495 ret = dmaengine_slave_config(adc->dma_chan, &config); 2496 if (ret) 2497 goto err_free; 2498 2499 return 0; 2500 2501err_free: 2502 dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE, 2503 adc->rx_buf, adc->rx_dma_buf); 2504err_release: 2505 dma_release_channel(adc->dma_chan); 2506 2507 return ret; 2508} 2509 2510static int stm32_adc_probe(struct platform_device *pdev) 2511{ 2512 struct iio_dev *indio_dev; 2513 struct device *dev = &pdev->dev; 2514 irqreturn_t (*handler)(int irq, void *p) = NULL; 2515 struct stm32_adc *adc; 2516 bool timestamping = false; 2517 int ret; 2518 2519 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc)); 2520 if (!indio_dev) 2521 return -ENOMEM; 2522 2523 adc = iio_priv(indio_dev); 2524 adc->common = dev_get_drvdata(pdev->dev.parent); 2525 spin_lock_init(&adc->lock); 2526 init_completion(&adc->completion); 2527 adc->cfg = device_get_match_data(dev); 2528 2529 indio_dev->name = dev_name(&pdev->dev); 2530 device_set_node(&indio_dev->dev, dev_fwnode(&pdev->dev)); 2531 indio_dev->info = &stm32_adc_iio_info; 2532 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_HARDWARE_TRIGGERED; 2533 2534 platform_set_drvdata(pdev, indio_dev); 2535 2536 ret = device_property_read_u32(dev, "reg", &adc->offset); 2537 if (ret != 0) { 2538 dev_err(&pdev->dev, "missing reg property\n"); 2539 return -EINVAL; 2540 } 2541 2542 adc->irq = platform_get_irq(pdev, 0); 2543 if (adc->irq < 0) 2544 return adc->irq; 2545 2546 ret = devm_request_threaded_irq(&pdev->dev, adc->irq, stm32_adc_isr, 2547 stm32_adc_threaded_isr, 2548 0, pdev->name, indio_dev); 2549 if (ret) { 2550 dev_err(&pdev->dev, "failed to request IRQ\n"); 2551 return ret; 2552 } 2553 2554 adc->clk = devm_clk_get(&pdev->dev, NULL); 2555 if (IS_ERR(adc->clk)) { 2556 ret = PTR_ERR(adc->clk); 2557 if (ret == -ENOENT && !adc->cfg->clk_required) { 2558 adc->clk = NULL; 2559 } else { 2560 dev_err(&pdev->dev, "Can't get clock\n"); 2561 return ret; 2562 } 2563 } 2564 2565 ret = stm32_adc_fw_get_resolution(indio_dev); 2566 if (ret < 0) 2567 return ret; 2568 2569 ret = stm32_adc_dma_request(dev, indio_dev); 2570 if (ret < 0) 2571 return ret; 2572 2573 if (!adc->dma_chan) { 2574 /* For PIO mode only, iio_pollfunc_store_time stores a timestamp 2575 * in the primary trigger IRQ handler and stm32_adc_trigger_handler 2576 * runs in the IRQ thread to push out buffer along with timestamp. 2577 */ 2578 handler = &stm32_adc_trigger_handler; 2579 timestamping = true; 2580 } 2581 2582 ret = stm32_adc_chan_fw_init(indio_dev, timestamping); 2583 if (ret < 0) 2584 goto err_dma_disable; 2585 2586 ret = iio_triggered_buffer_setup(indio_dev, 2587 &iio_pollfunc_store_time, handler, 2588 &stm32_adc_buffer_setup_ops); 2589 if (ret) { 2590 dev_err(&pdev->dev, "buffer setup failed\n"); 2591 goto err_dma_disable; 2592 } 2593 2594 /* Get stm32-adc-core PM online */ 2595 pm_runtime_get_noresume(dev); 2596 pm_runtime_set_active(dev); 2597 pm_runtime_set_autosuspend_delay(dev, STM32_ADC_HW_STOP_DELAY_MS); 2598 pm_runtime_use_autosuspend(dev); 2599 pm_runtime_enable(dev); 2600 2601 ret = stm32_adc_hw_start(dev); 2602 if (ret) 2603 goto err_buffer_cleanup; 2604 2605 ret = iio_device_register(indio_dev); 2606 if (ret) { 2607 dev_err(&pdev->dev, "iio dev register failed\n"); 2608 goto err_hw_stop; 2609 } 2610 2611 pm_runtime_put_autosuspend(dev); 2612 2613 if (IS_ENABLED(CONFIG_DEBUG_FS)) 2614 stm32_adc_debugfs_init(indio_dev); 2615 2616 return 0; 2617 2618err_hw_stop: 2619 stm32_adc_hw_stop(dev); 2620 2621err_buffer_cleanup: 2622 pm_runtime_disable(dev); 2623 pm_runtime_set_suspended(dev); 2624 pm_runtime_put_noidle(dev); 2625 iio_triggered_buffer_cleanup(indio_dev); 2626 2627err_dma_disable: 2628 if (adc->dma_chan) { 2629 dma_free_coherent(adc->dma_chan->device->dev, 2630 STM32_DMA_BUFFER_SIZE, 2631 adc->rx_buf, adc->rx_dma_buf); 2632 dma_release_channel(adc->dma_chan); 2633 } 2634 2635 return ret; 2636} 2637 2638static void stm32_adc_remove(struct platform_device *pdev) 2639{ 2640 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 2641 struct stm32_adc *adc = iio_priv(indio_dev); 2642 2643 pm_runtime_get_sync(&pdev->dev); 2644 /* iio_device_unregister() also removes debugfs entries */ 2645 iio_device_unregister(indio_dev); 2646 stm32_adc_hw_stop(&pdev->dev); 2647 pm_runtime_disable(&pdev->dev); 2648 pm_runtime_set_suspended(&pdev->dev); 2649 pm_runtime_put_noidle(&pdev->dev); 2650 iio_triggered_buffer_cleanup(indio_dev); 2651 if (adc->dma_chan) { 2652 dma_free_coherent(adc->dma_chan->device->dev, 2653 STM32_DMA_BUFFER_SIZE, 2654 adc->rx_buf, adc->rx_dma_buf); 2655 dma_release_channel(adc->dma_chan); 2656 } 2657} 2658 2659static int stm32_adc_suspend(struct device *dev) 2660{ 2661 struct iio_dev *indio_dev = dev_get_drvdata(dev); 2662 2663 if (iio_buffer_enabled(indio_dev)) 2664 stm32_adc_buffer_predisable(indio_dev); 2665 2666 return pm_runtime_force_suspend(dev); 2667} 2668 2669static int stm32_adc_resume(struct device *dev) 2670{ 2671 struct iio_dev *indio_dev = dev_get_drvdata(dev); 2672 int ret; 2673 2674 ret = pm_runtime_force_resume(dev); 2675 if (ret < 0) 2676 return ret; 2677 2678 if (!iio_buffer_enabled(indio_dev)) 2679 return 0; 2680 2681 ret = stm32_adc_update_scan_mode(indio_dev, 2682 indio_dev->active_scan_mask); 2683 if (ret < 0) 2684 return ret; 2685 2686 return stm32_adc_buffer_postenable(indio_dev); 2687} 2688 2689static int stm32_adc_runtime_suspend(struct device *dev) 2690{ 2691 return stm32_adc_hw_stop(dev); 2692} 2693 2694static int stm32_adc_runtime_resume(struct device *dev) 2695{ 2696 return stm32_adc_hw_start(dev); 2697} 2698 2699static const struct dev_pm_ops stm32_adc_pm_ops = { 2700 SYSTEM_SLEEP_PM_OPS(stm32_adc_suspend, stm32_adc_resume) 2701 RUNTIME_PM_OPS(stm32_adc_runtime_suspend, stm32_adc_runtime_resume, 2702 NULL) 2703}; 2704 2705static const struct stm32_adc_cfg stm32f4_adc_cfg = { 2706 .regs = &stm32f4_adc_regspec, 2707 .adc_info = &stm32f4_adc_info, 2708 .trigs = stm32f4_adc_trigs, 2709 .clk_required = true, 2710 .start_conv = stm32f4_adc_start_conv, 2711 .stop_conv = stm32f4_adc_stop_conv, 2712 .smp_cycles = stm32f4_adc_smp_cycles, 2713 .irq_clear = stm32f4_adc_irq_clear, 2714}; 2715 2716static const unsigned int stm32_adc_min_ts_h7[] = { 0, 0, 0, 4300, 9000 }; 2717static_assert(ARRAY_SIZE(stm32_adc_min_ts_h7) == STM32_ADC_INT_CH_NB); 2718 2719static const struct stm32_adc_cfg stm32h7_adc_cfg = { 2720 .regs = &stm32h7_adc_regspec, 2721 .adc_info = &stm32h7_adc_info, 2722 .trigs = stm32h7_adc_trigs, 2723 .has_boostmode = true, 2724 .has_linearcal = true, 2725 .has_presel = true, 2726 .has_oversampling = true, 2727 .start_conv = stm32h7_adc_start_conv, 2728 .stop_conv = stm32h7_adc_stop_conv, 2729 .prepare = stm32h7_adc_prepare, 2730 .unprepare = stm32h7_adc_unprepare, 2731 .smp_cycles = stm32h7_adc_smp_cycles, 2732 .irq_clear = stm32h7_adc_irq_clear, 2733 .ts_int_ch = stm32_adc_min_ts_h7, 2734 .set_ovs = stm32h7_adc_set_ovs, 2735}; 2736 2737static const unsigned int stm32_adc_min_ts_mp1[] = { 100, 100, 100, 4300, 9800 }; 2738static_assert(ARRAY_SIZE(stm32_adc_min_ts_mp1) == STM32_ADC_INT_CH_NB); 2739 2740static const struct stm32_adc_cfg stm32mp1_adc_cfg = { 2741 .regs = &stm32mp1_adc_regspec, 2742 .adc_info = &stm32h7_adc_info, 2743 .trigs = stm32h7_adc_trigs, 2744 .has_vregready = true, 2745 .has_boostmode = true, 2746 .has_linearcal = true, 2747 .has_presel = true, 2748 .has_oversampling = true, 2749 .start_conv = stm32h7_adc_start_conv, 2750 .stop_conv = stm32h7_adc_stop_conv, 2751 .prepare = stm32h7_adc_prepare, 2752 .unprepare = stm32h7_adc_unprepare, 2753 .smp_cycles = stm32h7_adc_smp_cycles, 2754 .irq_clear = stm32h7_adc_irq_clear, 2755 .ts_int_ch = stm32_adc_min_ts_mp1, 2756 .set_ovs = stm32h7_adc_set_ovs, 2757}; 2758 2759static const unsigned int stm32_adc_min_ts_mp13[] = { 100, 0, 0, 4300, 9800 }; 2760static_assert(ARRAY_SIZE(stm32_adc_min_ts_mp13) == STM32_ADC_INT_CH_NB); 2761 2762static const struct stm32_adc_cfg stm32mp13_adc_cfg = { 2763 .regs = &stm32mp13_adc_regspec, 2764 .adc_info = &stm32mp13_adc_info, 2765 .trigs = stm32h7_adc_trigs, 2766 .has_oversampling = true, 2767 .start_conv = stm32mp13_adc_start_conv, 2768 .stop_conv = stm32h7_adc_stop_conv, 2769 .prepare = stm32h7_adc_prepare, 2770 .unprepare = stm32h7_adc_unprepare, 2771 .smp_cycles = stm32mp13_adc_smp_cycles, 2772 .irq_clear = stm32h7_adc_irq_clear, 2773 .ts_int_ch = stm32_adc_min_ts_mp13, 2774 .set_ovs = stm32mp13_adc_set_ovs, 2775}; 2776 2777static const struct of_device_id stm32_adc_of_match[] = { 2778 { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg }, 2779 { .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg }, 2780 { .compatible = "st,stm32mp1-adc", .data = (void *)&stm32mp1_adc_cfg }, 2781 { .compatible = "st,stm32mp13-adc", .data = (void *)&stm32mp13_adc_cfg }, 2782 { } 2783}; 2784MODULE_DEVICE_TABLE(of, stm32_adc_of_match); 2785 2786static struct platform_driver stm32_adc_driver = { 2787 .probe = stm32_adc_probe, 2788 .remove = stm32_adc_remove, 2789 .driver = { 2790 .name = "stm32-adc", 2791 .of_match_table = stm32_adc_of_match, 2792 .pm = pm_ptr(&stm32_adc_pm_ops), 2793 }, 2794}; 2795module_platform_driver(stm32_adc_driver); 2796 2797MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>"); 2798MODULE_DESCRIPTION("STMicroelectronics STM32 ADC IIO driver"); 2799MODULE_LICENSE("GPL v2"); 2800MODULE_ALIAS("platform:stm32-adc");
~/
Read-only file preview.