spear_adc.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * ST SPEAr ADC driver
  4 *
  5 * Copyright 2012 Stefan Roese <sr@denx.de>
  6 */
  7
  8#include <linux/mod_devicetable.h>
  9#include <linux/module.h>
 10#include <linux/platform_device.h>
 11#include <linux/property.h>
 12#include <linux/interrupt.h>
 13#include <linux/device.h>
 14#include <linux/kernel.h>
 15#include <linux/slab.h>
 16#include <linux/io.h>
 17#include <linux/bitfield.h>
 18#include <linux/clk.h>
 19#include <linux/err.h>
 20#include <linux/completion.h>
 21
 22#include <linux/iio/iio.h>
 23#include <linux/iio/sysfs.h>
 24
 25/* SPEAR registers definitions */
 26#define SPEAR600_ADC_SCAN_RATE_LO(x)	((x) & 0xFFFF)
 27#define SPEAR600_ADC_SCAN_RATE_HI(x)	(((x) >> 0x10) & 0xFFFF)
 28#define SPEAR_ADC_CLK_LOW(x)		(((x) & 0xf) << 0)
 29#define SPEAR_ADC_CLK_HIGH(x)		(((x) & 0xf) << 4)
 30
 31/* Bit definitions for SPEAR_ADC_STATUS */
 32#define SPEAR_ADC_STATUS_START_CONVERSION	BIT(0)
 33#define SPEAR_ADC_STATUS_CHANNEL_NUM_MASK	GENMASK(3, 1)
 34#define SPEAR_ADC_STATUS_ADC_ENABLE		BIT(4)
 35#define SPEAR_ADC_STATUS_AVG_SAMPLE_MASK	GENMASK(8, 5)
 36#define SPEAR_ADC_STATUS_VREF_INTERNAL		BIT(9)
 37
 38#define SPEAR_ADC_DATA_MASK		0x03ff
 39#define SPEAR_ADC_DATA_BITS		10
 40
 41#define SPEAR_ADC_MOD_NAME "spear-adc"
 42
 43#define SPEAR_ADC_CHANNEL_NUM		8
 44
 45#define SPEAR_ADC_CLK_MIN			2500000
 46#define SPEAR_ADC_CLK_MAX			20000000
 47
 48struct adc_regs_spear3xx {
 49	u32 status;
 50	u32 average;
 51	u32 scan_rate;
 52	u32 clk;	/* Not avail for 1340 & 1310 */
 53	u32 ch_ctrl[SPEAR_ADC_CHANNEL_NUM];
 54	u32 ch_data[SPEAR_ADC_CHANNEL_NUM];
 55};
 56
 57struct chan_data {
 58	u32 lsb;
 59	u32 msb;
 60};
 61
 62struct adc_regs_spear6xx {
 63	u32 status;
 64	u32 pad[2];
 65	u32 clk;
 66	u32 ch_ctrl[SPEAR_ADC_CHANNEL_NUM];
 67	struct chan_data ch_data[SPEAR_ADC_CHANNEL_NUM];
 68	u32 scan_rate_lo;
 69	u32 scan_rate_hi;
 70	struct chan_data average;
 71};
 72
 73struct spear_adc_state {
 74	struct device *dev;
 75	struct adc_regs_spear3xx __iomem *adc_base_spear3xx;
 76	struct adc_regs_spear6xx __iomem *adc_base_spear6xx;
 77	struct clk *clk;
 78	struct completion completion;
 79	/*
 80	 * Lock to protect the device state during a potential concurrent
 81	 * read access from userspace. Reading a raw value requires a sequence
 82	 * of register writes, then a wait for a completion callback,
 83	 * and finally a register read, during which userspace could issue
 84	 * another read request. This lock protects a read access from
 85	 * ocurring before another one has finished.
 86	 */
 87	struct mutex lock;
 88	u32 current_clk;
 89	u32 sampling_freq;
 90	u32 avg_samples;
 91	u32 vref_external;
 92	u32 value;
 93};
 94
 95/*
 96 * Functions to access some SPEAr ADC register. Abstracted into
 97 * static inline functions, because of different register offsets
 98 * on different SoC variants (SPEAr300 vs SPEAr600 etc).
 99 */
100static void spear_adc_set_status(struct spear_adc_state *st, u32 val)
101{
102	__raw_writel(val, &st->adc_base_spear6xx->status);
103}
104
105static void spear_adc_set_clk(struct spear_adc_state *st, u32 val)
106{
107	u32 clk_high, clk_low, count;
108	u32 apb_clk = clk_get_rate(st->clk);
109
110	count = DIV_ROUND_UP(apb_clk, val);
111	clk_low = count / 2;
112	clk_high = count - clk_low;
113	st->current_clk = apb_clk / count;
114
115	__raw_writel(SPEAR_ADC_CLK_LOW(clk_low) | SPEAR_ADC_CLK_HIGH(clk_high),
116		     &st->adc_base_spear6xx->clk);
117}
118
119static void spear_adc_set_ctrl(struct spear_adc_state *st, int n,
120			       u32 val)
121{
122	__raw_writel(val, &st->adc_base_spear6xx->ch_ctrl[n]);
123}
124
125static u32 spear_adc_get_average(struct spear_adc_state *st)
126{
127	if (device_is_compatible(st->dev, "st,spear600-adc")) {
128		return __raw_readl(&st->adc_base_spear6xx->average.msb) &
129			SPEAR_ADC_DATA_MASK;
130	} else {
131		return __raw_readl(&st->adc_base_spear3xx->average) &
132			SPEAR_ADC_DATA_MASK;
133	}
134}
135
136static void spear_adc_set_scanrate(struct spear_adc_state *st, u32 rate)
137{
138	if (device_is_compatible(st->dev, "st,spear600-adc")) {
139		__raw_writel(SPEAR600_ADC_SCAN_RATE_LO(rate),
140			     &st->adc_base_spear6xx->scan_rate_lo);
141		__raw_writel(SPEAR600_ADC_SCAN_RATE_HI(rate),
142			     &st->adc_base_spear6xx->scan_rate_hi);
143	} else {
144		__raw_writel(rate, &st->adc_base_spear3xx->scan_rate);
145	}
146}
147
148static int spear_adc_read_raw(struct iio_dev *indio_dev,
149			      struct iio_chan_spec const *chan,
150			      int *val,
151			      int *val2,
152			      long mask)
153{
154	struct spear_adc_state *st = iio_priv(indio_dev);
155	u32 status;
156
157	switch (mask) {
158	case IIO_CHAN_INFO_RAW:
159		mutex_lock(&st->lock);
160
161		status = FIELD_PREP(SPEAR_ADC_STATUS_CHANNEL_NUM_MASK, chan->channel) |
162			FIELD_PREP(SPEAR_ADC_STATUS_AVG_SAMPLE_MASK, st->avg_samples) |
163			SPEAR_ADC_STATUS_START_CONVERSION |
164			SPEAR_ADC_STATUS_ADC_ENABLE;
165		if (st->vref_external == 0)
166			status |= SPEAR_ADC_STATUS_VREF_INTERNAL;
167
168		spear_adc_set_status(st, status);
169		wait_for_completion(&st->completion); /* set by ISR */
170		*val = st->value;
171
172		mutex_unlock(&st->lock);
173
174		return IIO_VAL_INT;
175
176	case IIO_CHAN_INFO_SCALE:
177		*val = st->vref_external;
178		*val2 = SPEAR_ADC_DATA_BITS;
179		return IIO_VAL_FRACTIONAL_LOG2;
180	case IIO_CHAN_INFO_SAMP_FREQ:
181		*val = st->current_clk;
182		return IIO_VAL_INT;
183	}
184
185	return -EINVAL;
186}
187
188static int spear_adc_write_raw(struct iio_dev *indio_dev,
189			       struct iio_chan_spec const *chan,
190			       int val,
191			       int val2,
192			       long mask)
193{
194	struct spear_adc_state *st = iio_priv(indio_dev);
195	int ret = 0;
196
197	if (mask != IIO_CHAN_INFO_SAMP_FREQ)
198		return -EINVAL;
199
200	mutex_lock(&st->lock);
201
202	if ((val < SPEAR_ADC_CLK_MIN) ||
203	    (val > SPEAR_ADC_CLK_MAX) ||
204	    (val2 != 0)) {
205		ret = -EINVAL;
206		goto out;
207	}
208
209	spear_adc_set_clk(st, val);
210
211out:
212	mutex_unlock(&st->lock);
213	return ret;
214}
215
216#define SPEAR_ADC_CHAN(idx) {				\
217	.type = IIO_VOLTAGE,				\
218	.indexed = 1,					\
219	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),	\
220	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
221	.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
222	.channel = idx,					\
223}
224
225static const struct iio_chan_spec spear_adc_iio_channels[] = {
226	SPEAR_ADC_CHAN(0),
227	SPEAR_ADC_CHAN(1),
228	SPEAR_ADC_CHAN(2),
229	SPEAR_ADC_CHAN(3),
230	SPEAR_ADC_CHAN(4),
231	SPEAR_ADC_CHAN(5),
232	SPEAR_ADC_CHAN(6),
233	SPEAR_ADC_CHAN(7),
234};
235
236static irqreturn_t spear_adc_isr(int irq, void *dev_id)
237{
238	struct spear_adc_state *st = dev_id;
239
240	/* Read value to clear IRQ */
241	st->value = spear_adc_get_average(st);
242	complete(&st->completion);
243
244	return IRQ_HANDLED;
245}
246
247static int spear_adc_configure(struct spear_adc_state *st)
248{
249	int i;
250
251	/* Reset ADC core */
252	spear_adc_set_status(st, 0);
253	__raw_writel(0, &st->adc_base_spear6xx->clk);
254	for (i = 0; i < 8; i++)
255		spear_adc_set_ctrl(st, i, 0);
256	spear_adc_set_scanrate(st, 0);
257
258	spear_adc_set_clk(st, st->sampling_freq);
259
260	return 0;
261}
262
263static const struct iio_info spear_adc_info = {
264	.read_raw = &spear_adc_read_raw,
265	.write_raw = &spear_adc_write_raw,
266};
267
268static int spear_adc_probe(struct platform_device *pdev)
269{
270	struct device *dev = &pdev->dev;
271	struct spear_adc_state *st;
272	struct iio_dev *indio_dev = NULL;
273	int ret = -ENODEV;
274	int irq;
275
276	indio_dev = devm_iio_device_alloc(dev, sizeof(struct spear_adc_state));
277	if (!indio_dev)
278		return -ENOMEM;
279
280	st = iio_priv(indio_dev);
281	st->dev = dev;
282
283	mutex_init(&st->lock);
284
285	/*
286	 * SPEAr600 has a different register layout than other SPEAr SoC's
287	 * (e.g. SPEAr3xx). Let's provide two register base addresses
288	 * to support multi-arch kernels.
289	 */
290	st->adc_base_spear6xx = devm_platform_ioremap_resource(pdev, 0);
291	if (IS_ERR(st->adc_base_spear6xx))
292		return PTR_ERR(st->adc_base_spear6xx);
293
294	st->adc_base_spear3xx =
295		(struct adc_regs_spear3xx __iomem *)st->adc_base_spear6xx;
296
297	st->clk = devm_clk_get_enabled(dev, NULL);
298	if (IS_ERR(st->clk))
299		return dev_err_probe(dev, PTR_ERR(st->clk),
300				     "failed enabling clock\n");
301
302	irq = platform_get_irq(pdev, 0);
303	if (irq < 0)
304		return irq;
305
306	ret = devm_request_irq(dev, irq, spear_adc_isr, 0, SPEAR_ADC_MOD_NAME,
307			       st);
308	if (ret < 0)
309		return dev_err_probe(dev, ret, "failed requesting interrupt\n");
310
311	if (device_property_read_u32(dev, "sampling-frequency", &st->sampling_freq))
312		return dev_err_probe(dev, -EINVAL,
313				     "sampling-frequency missing in DT\n");
314
315	/*
316	 * Optional avg_samples defaults to 0, resulting in single data
317	 * conversion
318	 */
319	device_property_read_u32(dev, "average-samples", &st->avg_samples);
320
321	/*
322	 * Optional vref_external defaults to 0, resulting in internal vref
323	 * selection
324	 */
325	device_property_read_u32(dev, "vref-external", &st->vref_external);
326
327	spear_adc_configure(st);
328
329	init_completion(&st->completion);
330
331	indio_dev->name = SPEAR_ADC_MOD_NAME;
332	indio_dev->info = &spear_adc_info;
333	indio_dev->modes = INDIO_DIRECT_MODE;
334	indio_dev->channels = spear_adc_iio_channels;
335	indio_dev->num_channels = ARRAY_SIZE(spear_adc_iio_channels);
336
337	ret = devm_iio_device_register(dev, indio_dev);
338	if (ret)
339		return ret;
340
341	dev_info(dev, "SPEAR ADC driver loaded, IRQ %d\n", irq);
342
343	return 0;
344}
345
346static const struct of_device_id spear_adc_dt_ids[] = {
347	{ .compatible = "st,spear600-adc", },
348	{ }
349};
350MODULE_DEVICE_TABLE(of, spear_adc_dt_ids);
351
352static struct platform_driver spear_adc_driver = {
353	.probe		= spear_adc_probe,
354	.driver		= {
355		.name	= SPEAR_ADC_MOD_NAME,
356		.of_match_table = spear_adc_dt_ids,
357	},
358};
359
360module_platform_driver(spear_adc_driver);
361
362MODULE_AUTHOR("Stefan Roese <sr@denx.de>");
363MODULE_DESCRIPTION("SPEAr ADC driver");
364MODULE_LICENSE("GPL");