rzn1-adc.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Renesas RZ/N1 ADC driver
  4 *
  5 * Copyright (C) 2025 Schneider-Electric
  6 *
  7 * Author: Herve Codina <herve.codina@bootlin.com>
  8 *
  9 * The RZ/N1 ADC controller can handle channels from its internal ADC1 and/or
 10 * ADC2 cores. The driver use ADC1 and/or ADC2 cores depending on the presence
 11 * of the related power supplies (AVDD and VREF) description in the device-tree.
 12 */
 13
 14#include <linux/array_size.h>
 15#include <linux/bitfield.h>
 16#include <linux/bits.h>
 17#include <linux/cleanup.h>
 18#include <linux/clk.h>
 19#include <linux/dev_printk.h>
 20#include <linux/err.h>
 21#include <linux/iio/iio.h>
 22#include <linux/io.h>
 23#include <linux/iopoll.h>
 24#include <linux/mod_devicetable.h>
 25#include <linux/module.h>
 26#include <linux/mutex.h>
 27#include <linux/platform_device.h>
 28#include <linux/pm_runtime.h>
 29#include <linux/regulator/consumer.h>
 30#include <linux/types.h>
 31
 32#define RZN1_ADC_CONTROL_REG			0x02c
 33#define RZN1_ADC_CONTROL_ADC_BUSY		BIT(6)
 34
 35#define RZN1_ADC_FORCE_REG			0x030
 36#define RZN1_ADC_SET_FORCE_REG			0x034
 37#define RZN1_ADC_CLEAR_FORCE_REG		0x038
 38#define RZN1_ADC_FORCE_VC(_n)			BIT(_n)
 39
 40#define RZN1_ADC_CONFIG_REG			0x040
 41#define RZN1_ADC_CONFIG_ADC_POWER_DOWN		BIT(3)
 42
 43#define RZN1_ADC_VC_REG(_n)			(0x0c0 + 4 * (_n))
 44#define RZN1_ADC_VC_ADC2_ENABLE			BIT(16)
 45#define RZN1_ADC_VC_ADC1_ENABLE			BIT(15)
 46#define RZN1_ADC_VC_ADC2_CHANNEL_SEL_MASK	GENMASK(5, 3)
 47#define RZN1_ADC_VC_ADC1_CHANNEL_SEL_MASK	GENMASK(2, 0)
 48
 49#define RZN1_ADC_ADC1_DATA_REG(_n)		(0x100 + 4 * (_n))
 50#define RZN1_ADC_ADC2_DATA_REG(_n)		(0x140 + 4 * (_n))
 51#define RZN1_ADC_ADCX_DATA_DATA_MASK		GENMASK(11, 0)
 52
 53#define RZN1_ADC_NO_CHANNEL	-1
 54
 55#define RZN1_ADC_CHANNEL_SHARED_SCALE(_ch, _ds_name) {		\
 56	.type = IIO_VOLTAGE,					\
 57	.indexed = 1,						\
 58	.channel = (_ch),					\
 59	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
 60	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
 61	.datasheet_name = (_ds_name),				\
 62}
 63
 64#define RZN1_ADC_CHANNEL_SEPARATED_SCALE(_ch, _ds_name) {	\
 65	.type = IIO_VOLTAGE,					\
 66	.indexed = 1,						\
 67	.channel = (_ch),					\
 68	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |		\
 69			      BIT(IIO_CHAN_INFO_SCALE),		\
 70	.datasheet_name = (_ds_name),				\
 71}
 72
 73/*
 74 * 8 ADC1_IN signals existed numbered 0..4, 6..8
 75 * ADCx_IN5 doesn't exist in RZ/N1 datasheet
 76 */
 77static struct iio_chan_spec rzn1_adc1_channels[] = {
 78	RZN1_ADC_CHANNEL_SHARED_SCALE(0, "ADC1_IN0"),
 79	RZN1_ADC_CHANNEL_SHARED_SCALE(1, "ADC1_IN1"),
 80	RZN1_ADC_CHANNEL_SHARED_SCALE(2, "ADC1_IN2"),
 81	RZN1_ADC_CHANNEL_SHARED_SCALE(3, "ADC1_IN3"),
 82	RZN1_ADC_CHANNEL_SHARED_SCALE(4, "ADC1_IN4"),
 83	RZN1_ADC_CHANNEL_SHARED_SCALE(5, "ADC1_IN6"),
 84	RZN1_ADC_CHANNEL_SHARED_SCALE(6, "ADC1_IN7"),
 85	RZN1_ADC_CHANNEL_SHARED_SCALE(7, "ADC1_IN8"),
 86};
 87
 88static struct iio_chan_spec rzn1_adc2_channels[] = {
 89	RZN1_ADC_CHANNEL_SHARED_SCALE(8,  "ADC2_IN0"),
 90	RZN1_ADC_CHANNEL_SHARED_SCALE(9,  "ADC2_IN1"),
 91	RZN1_ADC_CHANNEL_SHARED_SCALE(10, "ADC2_IN2"),
 92	RZN1_ADC_CHANNEL_SHARED_SCALE(11, "ADC2_IN3"),
 93	RZN1_ADC_CHANNEL_SHARED_SCALE(12, "ADC2_IN4"),
 94	RZN1_ADC_CHANNEL_SHARED_SCALE(13, "ADC2_IN6"),
 95	RZN1_ADC_CHANNEL_SHARED_SCALE(14, "ADC2_IN7"),
 96	RZN1_ADC_CHANNEL_SHARED_SCALE(15, "ADC2_IN8"),
 97};
 98
 99/*
100 * If both ADCs core are used, scale cannot be common. Indeed, scale is
101 * based on Vref connected on each ADC core.
102 */
103static struct iio_chan_spec rzn1_adc1_adc2_channels[] = {
104	RZN1_ADC_CHANNEL_SEPARATED_SCALE(0, "ADC1_IN0"),
105	RZN1_ADC_CHANNEL_SEPARATED_SCALE(1, "ADC1_IN1"),
106	RZN1_ADC_CHANNEL_SEPARATED_SCALE(2, "ADC1_IN2"),
107	RZN1_ADC_CHANNEL_SEPARATED_SCALE(3, "ADC1_IN3"),
108	RZN1_ADC_CHANNEL_SEPARATED_SCALE(4, "ADC1_IN4"),
109	RZN1_ADC_CHANNEL_SEPARATED_SCALE(5, "ADC1_IN6"),
110	RZN1_ADC_CHANNEL_SEPARATED_SCALE(6, "ADC1_IN7"),
111	RZN1_ADC_CHANNEL_SEPARATED_SCALE(7, "ADC1_IN8"),
112	RZN1_ADC_CHANNEL_SEPARATED_SCALE(8,  "ADC2_IN0"),
113	RZN1_ADC_CHANNEL_SEPARATED_SCALE(9,  "ADC2_IN1"),
114	RZN1_ADC_CHANNEL_SEPARATED_SCALE(10, "ADC2_IN2"),
115	RZN1_ADC_CHANNEL_SEPARATED_SCALE(11, "ADC2_IN3"),
116	RZN1_ADC_CHANNEL_SEPARATED_SCALE(12, "ADC2_IN4"),
117	RZN1_ADC_CHANNEL_SEPARATED_SCALE(13, "ADC2_IN6"),
118	RZN1_ADC_CHANNEL_SEPARATED_SCALE(14, "ADC2_IN7"),
119	RZN1_ADC_CHANNEL_SEPARATED_SCALE(15, "ADC2_IN8"),
120};
121
122struct rzn1_adc {
123	struct device *dev;
124	void __iomem *regs;
125	struct mutex lock; /* ADC lock */
126	int adc1_vref_mV; /* ADC1 Vref in mV. Negative if ADC1 is not used */
127	int adc2_vref_mV; /* ADC2 Vref in mV. Negative if ADC2 is not used */
128};
129
130static int rzn1_adc_power(struct rzn1_adc *rzn1_adc, bool power)
131{
132	u32 v;
133
134	writel(power ? 0 : RZN1_ADC_CONFIG_ADC_POWER_DOWN,
135	       rzn1_adc->regs + RZN1_ADC_CONFIG_REG);
136
137	/* Wait for the ADC_BUSY to clear */
138	return readl_poll_timeout_atomic(rzn1_adc->regs + RZN1_ADC_CONTROL_REG,
139					 v, !(v & RZN1_ADC_CONTROL_ADC_BUSY),
140					 0, 500);
141}
142
143static void rzn1_adc_vc_setup_conversion(struct rzn1_adc *rzn1_adc, u32 ch,
144					 int adc1_ch, int adc2_ch)
145{
146	u32 vc = 0;
147
148	if (adc1_ch != RZN1_ADC_NO_CHANNEL)
149		vc |= RZN1_ADC_VC_ADC1_ENABLE |
150		      FIELD_PREP(RZN1_ADC_VC_ADC1_CHANNEL_SEL_MASK, adc1_ch);
151
152	if (adc2_ch != RZN1_ADC_NO_CHANNEL)
153		vc |= RZN1_ADC_VC_ADC2_ENABLE |
154		      FIELD_PREP(RZN1_ADC_VC_ADC2_CHANNEL_SEL_MASK, adc2_ch);
155
156	writel(vc, rzn1_adc->regs + RZN1_ADC_VC_REG(ch));
157}
158
159static int rzn1_adc_vc_start_conversion(struct rzn1_adc *rzn1_adc, u32 ch)
160{
161	u32 val;
162
163	val = readl(rzn1_adc->regs + RZN1_ADC_FORCE_REG);
164	if (val & RZN1_ADC_FORCE_VC(ch))
165		return -EBUSY;
166
167	writel(RZN1_ADC_FORCE_VC(ch), rzn1_adc->regs + RZN1_ADC_SET_FORCE_REG);
168
169	return 0;
170}
171
172static void rzn1_adc_vc_stop_conversion(struct rzn1_adc *rzn1_adc, u32 ch)
173{
174	writel(RZN1_ADC_FORCE_VC(ch), rzn1_adc->regs + RZN1_ADC_CLEAR_FORCE_REG);
175}
176
177static int rzn1_adc_vc_wait_conversion(struct rzn1_adc *rzn1_adc, u32 ch,
178				       u32 *adc1_data, u32 *adc2_data)
179{
180	u32 data_reg;
181	int ret;
182	u32 v;
183
184	/*
185	 * When a VC is selected, it needs 20 ADC clocks to perform the
186	 * conversion.
187	 *
188	 * The worst case is when the 16 VCs need to perform a conversion and
189	 * our VC is the lowest in term of priority.
190	 *
191	 * In that case, the conversion is performed in 16 * 20 ADC clocks.
192	 *
193	 * The ADC clock can be set from 4MHz to 20MHz. This leads to a worst
194	 * case of  16 * 20 * 1/4Mhz = 80us.
195	 *
196	 * Round it up to 100us.
197	 */
198
199	/* Wait for the ADC_FORCE_VC(n) to clear */
200	ret = readl_poll_timeout_atomic(rzn1_adc->regs + RZN1_ADC_FORCE_REG,
201					v, !(v & RZN1_ADC_FORCE_VC(ch)),
202					0, 100);
203	if (ret)
204		return ret;
205
206	if (adc1_data) {
207		data_reg = readl(rzn1_adc->regs + RZN1_ADC_ADC1_DATA_REG(ch));
208		*adc1_data = FIELD_GET(RZN1_ADC_ADCX_DATA_DATA_MASK, data_reg);
209	}
210
211	if (adc2_data) {
212		data_reg = readl(rzn1_adc->regs + RZN1_ADC_ADC2_DATA_REG(ch));
213		*adc2_data = FIELD_GET(RZN1_ADC_ADCX_DATA_DATA_MASK, data_reg);
214	}
215
216	return 0;
217}
218
219static int rzn1_adc_read_raw_ch(struct rzn1_adc *rzn1_adc, unsigned int chan, int *val)
220{
221	u32 *adc1_data, *adc2_data;
222	int adc1_ch, adc2_ch;
223	u32 adc_data;
224	int ret;
225
226	/*
227	 * IIO chan are decoupled from chans used in rzn1_adc_vc_*() functions.
228	 * The RZ/N1 ADC VC controller can handle on a single VC chan one
229	 * channel from the ADC1 core and one channel from the ADC2 core.
230	 *
231	 * Even if IIO chans are mapped 1:1 to ADC core chans and so uses only
232	 * a chan from ADC1 or a chan from ADC2, future improvements can define
233	 * an IIO chan that uses one chan from ADC1 and one chan from ADC2.
234	 */
235
236	if (chan < 8) {
237		/* chan 0..7 used to get ADC1 ch 0..7 */
238		adc1_ch = chan;
239		adc1_data = &adc_data;
240		adc2_ch = RZN1_ADC_NO_CHANNEL;
241		adc2_data = NULL;
242	} else if (chan < 16) {
243		/* chan 8..15 used to get ADC2 ch 0..7 */
244		adc1_ch = RZN1_ADC_NO_CHANNEL;
245		adc1_data = NULL;
246		adc2_ch = chan - 8;
247		adc2_data = &adc_data;
248	} else {
249		return -EINVAL;
250	}
251
252	ACQUIRE(pm_runtime_active_auto_try_enabled, pm)(rzn1_adc->dev);
253	ret = ACQUIRE_ERR(pm_runtime_active_auto_try_enabled, &pm);
254	if (ret < 0)
255		return ret;
256
257	scoped_guard(mutex, &rzn1_adc->lock) {
258		rzn1_adc_vc_setup_conversion(rzn1_adc, chan, adc1_ch, adc2_ch);
259
260		ret = rzn1_adc_vc_start_conversion(rzn1_adc, chan);
261		if (ret)
262			return ret;
263
264		ret = rzn1_adc_vc_wait_conversion(rzn1_adc, chan, adc1_data, adc2_data);
265		if (ret) {
266			rzn1_adc_vc_stop_conversion(rzn1_adc, chan);
267			return ret;
268		}
269	}
270
271	*val = adc_data;
272	ret = IIO_VAL_INT;
273
274	return 0;
275}
276
277static int rzn1_adc_get_vref_mV(struct rzn1_adc *rzn1_adc, unsigned int chan)
278{
279	/* chan 0..7 use ADC1 ch 0..7. Vref related to ADC1 core */
280	if (chan < 8)
281		return rzn1_adc->adc1_vref_mV;
282
283	/* chan 8..15 use ADC2 ch 0..7. Vref related to ADC2 core */
284	if (chan < 16)
285		return rzn1_adc->adc2_vref_mV;
286
287	return -EINVAL;
288}
289
290static int rzn1_adc_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
291			     int *val, int *val2, long mask)
292{
293	struct rzn1_adc *rzn1_adc = iio_priv(indio_dev);
294	int ret;
295
296	switch (mask) {
297	case IIO_CHAN_INFO_RAW:
298		ret = rzn1_adc_read_raw_ch(rzn1_adc, chan->channel, val);
299		if (ret)
300			return ret;
301		return IIO_VAL_INT;
302
303	case IIO_CHAN_INFO_SCALE:
304		ret = rzn1_adc_get_vref_mV(rzn1_adc, chan->channel);
305		if (ret < 0)
306			return ret;
307		*val = ret;
308		*val2 = 12;
309		return IIO_VAL_FRACTIONAL_LOG2;
310
311	default:
312		return -EINVAL;
313	}
314}
315
316static const struct iio_info rzn1_adc_info = {
317	.read_raw = &rzn1_adc_read_raw,
318};
319
320static int rzn1_adc_set_iio_dev_channels(struct rzn1_adc *rzn1_adc,
321					 struct iio_dev *indio_dev)
322{
323	/*
324	 * When an ADC core is not used, its related vref_mV is set to a
325	 * negative error code. Use the correct IIO channels table based on
326	 * those vref_mV values.
327	 */
328	if (rzn1_adc->adc1_vref_mV >= 0) {
329		if (rzn1_adc->adc2_vref_mV >= 0) {
330			indio_dev->channels = rzn1_adc1_adc2_channels;
331			indio_dev->num_channels = ARRAY_SIZE(rzn1_adc1_adc2_channels);
332		} else {
333			indio_dev->channels = rzn1_adc1_channels;
334			indio_dev->num_channels = ARRAY_SIZE(rzn1_adc1_channels);
335		}
336		return 0;
337	}
338
339	if (rzn1_adc->adc2_vref_mV >= 0) {
340		indio_dev->channels = rzn1_adc2_channels;
341		indio_dev->num_channels = ARRAY_SIZE(rzn1_adc2_channels);
342		return 0;
343	}
344
345	return dev_err_probe(rzn1_adc->dev, -ENODEV,
346			     "Failed to set IIO channels, no ADC core used\n");
347}
348
349static int rzn1_adc_core_get_regulators(struct rzn1_adc *rzn1_adc,
350					int *adc_vref_mV,
351					const char *avdd_name, const char *vref_name)
352{
353	struct device *dev = rzn1_adc->dev;
354	int ret;
355
356	/*
357	 * For a given ADC core (ADC1 or ADC2), both regulators (AVDD and VREF)
358	 * must be available in order to have the ADC core used.
359	 *
360	 * We use the regulators presence to check the usage of the related
361	 * ADC core. If both regulators are available, the ADC core is used.
362	 * Otherwise, the ADC core is not used.
363	 *
364	 * The adc_vref_mV value is set to a negative error code (-ENODEV) when
365	 * the ADC core is not used. Otherwise it is set to the VRef mV value.
366	 */
367
368	*adc_vref_mV = -ENODEV;
369
370	ret = devm_regulator_get_enable_optional(dev, avdd_name);
371	if (ret == -ENODEV)
372		return 0;
373	if (ret < 0)
374		return dev_err_probe(dev, ret, "Failed to get '%s' regulator\n",
375				     avdd_name);
376
377	ret = devm_regulator_get_enable_read_voltage(dev, vref_name);
378	if (ret == -ENODEV)
379		return 0;
380	if (ret < 0)
381		return dev_err_probe(dev, ret, "Failed to get '%s' regulator\n",
382				     vref_name);
383
384	/*
385	 * Both regulators are available.
386	 * Set adc_vref_mV to the Vref value in mV. This, as the value set is
387	 * positive, also signals that the ADC is used.
388	 */
389	*adc_vref_mV = ret / 1000;
390
391	return 0;
392}
393
394static int rzn1_adc_probe(struct platform_device *pdev)
395{
396	struct device *dev = &pdev->dev;
397	struct iio_dev *indio_dev;
398	struct rzn1_adc *rzn1_adc;
399	struct clk *clk;
400	int ret;
401
402	indio_dev = devm_iio_device_alloc(dev, sizeof(*rzn1_adc));
403	if (!indio_dev)
404		return -ENOMEM;
405
406	rzn1_adc = iio_priv(indio_dev);
407	rzn1_adc->dev = dev;
408
409	ret = devm_mutex_init(dev, &rzn1_adc->lock);
410	if (ret)
411		return ret;
412
413	rzn1_adc->regs = devm_platform_ioremap_resource(pdev, 0);
414	if (IS_ERR(rzn1_adc->regs))
415		return PTR_ERR(rzn1_adc->regs);
416
417	clk = devm_clk_get_enabled(dev, "pclk");
418	if (IS_ERR(clk))
419		return dev_err_probe(dev, PTR_ERR(clk), "Failed to get pclk\n");
420
421	clk = devm_clk_get_enabled(dev, "adc");
422	if (IS_ERR(clk))
423		return dev_err_probe(dev, PTR_ERR(clk), "Failed to get adc clk\n");
424
425	ret = rzn1_adc_core_get_regulators(rzn1_adc, &rzn1_adc->adc1_vref_mV,
426					   "adc1-avdd", "adc1-vref");
427	if (ret)
428		return ret;
429
430	ret = rzn1_adc_core_get_regulators(rzn1_adc, &rzn1_adc->adc2_vref_mV,
431					   "adc2-avdd", "adc2-vref");
432	if (ret)
433		return ret;
434
435	platform_set_drvdata(pdev, rzn1_adc);
436
437	indio_dev->name = "rzn1-adc";
438	indio_dev->info = &rzn1_adc_info;
439	indio_dev->modes = INDIO_DIRECT_MODE;
440	ret = rzn1_adc_set_iio_dev_channels(rzn1_adc, indio_dev);
441	if (ret)
442		return ret;
443
444	pm_runtime_set_autosuspend_delay(dev, 500);
445	pm_runtime_use_autosuspend(dev);
446	ret = devm_pm_runtime_enable(dev);
447	if (ret)
448		return dev_err_probe(dev, ret, "Failed to enable runtime PM\n");
449
450	return devm_iio_device_register(dev, indio_dev);
451}
452
453static int rzn1_adc_pm_runtime_suspend(struct device *dev)
454{
455	struct rzn1_adc *rzn1_adc = dev_get_drvdata(dev);
456
457	return rzn1_adc_power(rzn1_adc, false);
458}
459
460static int rzn1_adc_pm_runtime_resume(struct device *dev)
461{
462	struct rzn1_adc *rzn1_adc = dev_get_drvdata(dev);
463
464	return rzn1_adc_power(rzn1_adc, true);
465}
466
467static DEFINE_RUNTIME_DEV_PM_OPS(rzn1_adc_pm_ops,
468				 rzn1_adc_pm_runtime_suspend,
469				 rzn1_adc_pm_runtime_resume,
470				 NULL);
471
472static const struct of_device_id rzn1_adc_of_match[] = {
473	{ .compatible = "renesas,rzn1-adc" },
474	{ }
475};
476MODULE_DEVICE_TABLE(of, rzn1_adc_of_match);
477
478static struct platform_driver rzn1_adc_driver = {
479	.probe = rzn1_adc_probe,
480	.driver = {
481		.name = "rzn1-adc",
482		.of_match_table = rzn1_adc_of_match,
483		.pm = pm_ptr(&rzn1_adc_pm_ops),
484	},
485};
486module_platform_driver(rzn1_adc_driver);
487
488MODULE_AUTHOR("Herve Codina <herve.codina@bootlin.com>");
489MODULE_DESCRIPTION("Renesas RZ/N1 ADC Driver");
490MODULE_LICENSE("GPL");