rzg2l_adc.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * RZ/G2L A/D Converter driver
  4 *
  5 *  Copyright (c) 2021 Renesas Electronics Europe GmbH
  6 *
  7 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
  8 */
  9
 10#include <linux/bitfield.h>
 11#include <linux/cleanup.h>
 12#include <linux/completion.h>
 13#include <linux/delay.h>
 14#include <linux/iio/adc-helpers.h>
 15#include <linux/iio/iio.h>
 16#include <linux/interrupt.h>
 17#include <linux/io.h>
 18#include <linux/iopoll.h>
 19#include <linux/mod_devicetable.h>
 20#include <linux/module.h>
 21#include <linux/platform_device.h>
 22#include <linux/pm_runtime.h>
 23#include <linux/property.h>
 24#include <linux/reset.h>
 25
 26#define DRIVER_NAME		"rzg2l-adc"
 27
 28#define RZG2L_ADM(n)			((n) * 0x4)
 29#define RZG2L_ADM0_ADCE			BIT(0)
 30#define RZG2L_ADM0_ADBSY		BIT(1)
 31#define RZG2L_ADM0_PWDWNB		BIT(2)
 32#define RZG2L_ADM0_SRESB		BIT(15)
 33#define RZG2L_ADM1_TRG			BIT(0)
 34#define RZG2L_ADM1_MS			BIT(2)
 35#define RZG2L_ADM1_BS			BIT(4)
 36#define RZG2L_ADM1_EGA_MASK		GENMASK(13, 12)
 37#define RZG2L_ADM3_ADIL_MASK		GENMASK(31, 24)
 38#define RZG2L_ADM3_ADCMP_MASK		GENMASK(23, 16)
 39
 40#define RZG2L_ADINT			0x20
 41#define RZG2L_ADINT_CSEEN		BIT(16)
 42#define RZG2L_ADINT_INTS		BIT(31)
 43
 44#define RZG2L_ADSTS			0x24
 45#define RZG2L_ADSTS_CSEST		BIT(16)
 46
 47#define RZG2L_ADIVC			0x28
 48#define RZG2L_ADIVC_DIVADC_MASK		GENMASK(8, 0)
 49#define RZG2L_ADIVC_DIVADC_4		FIELD_PREP(RZG2L_ADIVC_DIVADC_MASK, 0x4)
 50
 51#define RZG2L_ADFIL			0x2c
 52
 53#define RZG2L_ADCR(n)			(0x30 + ((n) * 0x4))
 54#define RZG2L_ADCR_AD_MASK		GENMASK(11, 0)
 55
 56#define RZG2L_ADC_MAX_CHANNELS		9
 57#define RZG2L_ADC_TIMEOUT		usecs_to_jiffies(1 * 4)
 58
 59/**
 60 * struct rzg2l_adc_hw_params - ADC hardware specific parameters
 61 * @default_adsmp: default ADC sampling period (see ADM3 register); index 0 is
 62 * used for voltage channels, index 1 is used for temperature channel
 63 * @adsmp_mask: ADC sampling period mask (see ADM3 register)
 64 * @adint_inten_mask: conversion end interrupt mask (see ADINT register)
 65 * @default_adcmp: default ADC cmp (see ADM3 register)
 66 * @num_channels: number of supported channels
 67 * @adivc: specifies if ADVIC register is available
 68 */
 69struct rzg2l_adc_hw_params {
 70	u16 default_adsmp[2];
 71	u16 adsmp_mask;
 72	u16 adint_inten_mask;
 73	u8 default_adcmp;
 74	u8 num_channels;
 75	bool adivc;
 76};
 77
 78struct rzg2l_adc_data {
 79	const struct iio_chan_spec *channels;
 80	u8 num_channels;
 81};
 82
 83struct rzg2l_adc {
 84	void __iomem *base;
 85	struct reset_control *presetn;
 86	struct reset_control *adrstn;
 87	const struct rzg2l_adc_data *data;
 88	const struct rzg2l_adc_hw_params *hw_params;
 89	struct completion completion;
 90	struct mutex lock;
 91	u16 last_val[RZG2L_ADC_MAX_CHANNELS];
 92};
 93
 94/**
 95 * struct rzg2l_adc_channel - ADC channel descriptor
 96 * @name: ADC channel name
 97 * @type: ADC channel type
 98 */
 99struct rzg2l_adc_channel {
100	const char * const name;
101	enum iio_chan_type type;
102};
103
104static const struct rzg2l_adc_channel rzg2l_adc_channels[] = {
105	{ "adc0", IIO_VOLTAGE },
106	{ "adc1", IIO_VOLTAGE },
107	{ "adc2", IIO_VOLTAGE },
108	{ "adc3", IIO_VOLTAGE },
109	{ "adc4", IIO_VOLTAGE },
110	{ "adc5", IIO_VOLTAGE },
111	{ "adc6", IIO_VOLTAGE },
112	{ "adc7", IIO_VOLTAGE },
113	{ "adc8", IIO_TEMP },
114};
115
116static unsigned int rzg2l_adc_readl(struct rzg2l_adc *adc, u32 reg)
117{
118	return readl(adc->base + reg);
119}
120
121static void rzg2l_adc_writel(struct rzg2l_adc *adc, unsigned int reg, u32 val)
122{
123	writel(val, adc->base + reg);
124}
125
126static void rzg2l_adc_pwr(struct rzg2l_adc *adc, bool on)
127{
128	u32 reg;
129
130	reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
131	if (on)
132		reg |= RZG2L_ADM0_PWDWNB;
133	else
134		reg &= ~RZG2L_ADM0_PWDWNB;
135	rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);
136	udelay(2);
137}
138
139static void rzg2l_adc_start_stop(struct rzg2l_adc *adc, bool start)
140{
141	int ret;
142	u32 reg;
143
144	reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
145	if (start)
146		reg |= RZG2L_ADM0_ADCE;
147	else
148		reg &= ~RZG2L_ADM0_ADCE;
149	rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);
150
151	if (start)
152		return;
153
154	ret = read_poll_timeout(rzg2l_adc_readl, reg, !(reg & (RZG2L_ADM0_ADBSY | RZG2L_ADM0_ADCE)),
155				200, 1000, true, adc, RZG2L_ADM(0));
156	if (ret)
157		pr_err("%s stopping ADC timed out\n", __func__);
158}
159
160static void rzg2l_set_trigger(struct rzg2l_adc *adc)
161{
162	u32 reg;
163
164	/*
165	 * Setup ADM1 for SW trigger
166	 * EGA[13:12] - Set 00 to indicate hardware trigger is invalid
167	 * BS[4] - Enable 1-buffer mode
168	 * MS[1] - Enable Select mode
169	 * TRG[0] - Enable software trigger mode
170	 */
171	reg = rzg2l_adc_readl(adc, RZG2L_ADM(1));
172	reg &= ~RZG2L_ADM1_EGA_MASK;
173	reg &= ~RZG2L_ADM1_BS;
174	reg &= ~RZG2L_ADM1_TRG;
175	reg |= RZG2L_ADM1_MS;
176	rzg2l_adc_writel(adc, RZG2L_ADM(1), reg);
177}
178
179static u8 rzg2l_adc_ch_to_adsmp_index(u8 ch)
180{
181	if (rzg2l_adc_channels[ch].type == IIO_VOLTAGE)
182		return 0;
183
184	return 1;
185}
186
187static int rzg2l_adc_conversion_setup(struct rzg2l_adc *adc, u8 ch)
188{
189	const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
190	u8 index = rzg2l_adc_ch_to_adsmp_index(ch);
191	u32 reg;
192
193	if (rzg2l_adc_readl(adc, RZG2L_ADM(0)) & RZG2L_ADM0_ADBSY)
194		return -EBUSY;
195
196	rzg2l_set_trigger(adc);
197
198	/* Select analog input channel subjected to conversion. */
199	reg = rzg2l_adc_readl(adc, RZG2L_ADM(2));
200	reg &= ~GENMASK(hw_params->num_channels - 1, 0);
201	reg |= BIT(ch);
202	rzg2l_adc_writel(adc, RZG2L_ADM(2), reg);
203
204	reg = rzg2l_adc_readl(adc, RZG2L_ADM(3));
205	reg &= ~hw_params->adsmp_mask;
206	reg |= hw_params->default_adsmp[index];
207	rzg2l_adc_writel(adc, RZG2L_ADM(3), reg);
208
209	/*
210	 * Setup ADINT
211	 * INTS[31] - Select pulse signal
212	 * CSEEN[16] - Enable channel select error interrupt
213	 * INTEN[7:0] - Select channel interrupt
214	 */
215	reg = rzg2l_adc_readl(adc, RZG2L_ADINT);
216	reg &= ~RZG2L_ADINT_INTS;
217	reg &= ~hw_params->adint_inten_mask;
218	reg |= (RZG2L_ADINT_CSEEN | BIT(ch));
219	rzg2l_adc_writel(adc, RZG2L_ADINT, reg);
220
221	return 0;
222}
223
224static int rzg2l_adc_conversion(struct iio_dev *indio_dev, struct rzg2l_adc *adc, u8 ch)
225{
226	const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
227	struct device *dev = indio_dev->dev.parent;
228	int ret;
229
230	ret = pm_runtime_resume_and_get(dev);
231	if (ret)
232		return ret;
233
234	ret = rzg2l_adc_conversion_setup(adc, ch);
235	if (ret)
236		goto rpm_put;
237
238	reinit_completion(&adc->completion);
239
240	rzg2l_adc_start_stop(adc, true);
241
242	if (!wait_for_completion_timeout(&adc->completion, RZG2L_ADC_TIMEOUT)) {
243		rzg2l_adc_writel(adc, RZG2L_ADINT,
244				 rzg2l_adc_readl(adc, RZG2L_ADINT) & ~hw_params->adint_inten_mask);
245		ret = -ETIMEDOUT;
246	}
247
248	rzg2l_adc_start_stop(adc, false);
249
250rpm_put:
251	pm_runtime_put_autosuspend(dev);
252	return ret;
253}
254
255static int rzg2l_adc_read_raw(struct iio_dev *indio_dev,
256			      struct iio_chan_spec const *chan,
257			      int *val, int *val2, long mask)
258{
259	struct rzg2l_adc *adc = iio_priv(indio_dev);
260	int ret;
261
262	switch (mask) {
263	case IIO_CHAN_INFO_RAW: {
264		if (chan->type != IIO_VOLTAGE && chan->type != IIO_TEMP)
265			return -EINVAL;
266
267		guard(mutex)(&adc->lock);
268
269		ret = rzg2l_adc_conversion(indio_dev, adc, chan->channel);
270		if (ret)
271			return ret;
272
273		*val = adc->last_val[chan->channel];
274
275		return IIO_VAL_INT;
276	}
277
278	default:
279		return -EINVAL;
280	}
281}
282
283static int rzg2l_adc_read_label(struct iio_dev *iio_dev,
284				const struct iio_chan_spec *chan,
285				char *label)
286{
287	return sysfs_emit(label, "%s\n", rzg2l_adc_channels[chan->channel].name);
288}
289
290static const struct iio_info rzg2l_adc_iio_info = {
291	.read_raw = rzg2l_adc_read_raw,
292	.read_label = rzg2l_adc_read_label,
293};
294
295static irqreturn_t rzg2l_adc_isr(int irq, void *dev_id)
296{
297	struct rzg2l_adc *adc = dev_id;
298	const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
299	unsigned long intst;
300	u32 reg;
301	int ch;
302
303	reg = rzg2l_adc_readl(adc, RZG2L_ADSTS);
304
305	/* A/D conversion channel select error interrupt */
306	if (reg & RZG2L_ADSTS_CSEST) {
307		rzg2l_adc_writel(adc, RZG2L_ADSTS, reg);
308		return IRQ_HANDLED;
309	}
310
311	intst = reg & GENMASK(hw_params->num_channels - 1, 0);
312	if (!intst)
313		return IRQ_NONE;
314
315	for_each_set_bit(ch, &intst, hw_params->num_channels)
316		adc->last_val[ch] = rzg2l_adc_readl(adc, RZG2L_ADCR(ch)) & RZG2L_ADCR_AD_MASK;
317
318	/* clear the channel interrupt */
319	rzg2l_adc_writel(adc, RZG2L_ADSTS, reg);
320
321	complete(&adc->completion);
322
323	return IRQ_HANDLED;
324}
325
326static const struct iio_chan_spec rzg2l_adc_chan_template = {
327	.indexed = 1,
328	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
329};
330
331static int rzg2l_adc_parse_properties(struct platform_device *pdev, struct rzg2l_adc *adc)
332{
333	const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
334	struct iio_chan_spec *chan_array;
335	struct rzg2l_adc_data *data;
336	int num_channels;
337	u8 i;
338
339	data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
340	if (!data)
341		return -ENOMEM;
342
343	num_channels = devm_iio_adc_device_alloc_chaninfo_se(&pdev->dev,
344						&rzg2l_adc_chan_template,
345						hw_params->num_channels - 1,
346						&chan_array);
347	if (num_channels < 0)
348		return num_channels;
349
350	if (num_channels > hw_params->num_channels)
351		return dev_err_probe(&pdev->dev, -EINVAL,
352				     "num of channel children out of range\n");
353
354	for (i = 0; i < num_channels; i++) {
355		int channel = chan_array[i].channel;
356
357		chan_array[i].datasheet_name = rzg2l_adc_channels[channel].name;
358		chan_array[i].type = rzg2l_adc_channels[channel].type;
359	}
360
361	data->num_channels = num_channels;
362	data->channels = chan_array;
363	adc->data = data;
364
365	return 0;
366}
367
368static int rzg2l_adc_hw_init(struct device *dev, struct rzg2l_adc *adc)
369{
370	const struct rzg2l_adc_hw_params *hw_params = adc->hw_params;
371	u32 reg;
372	int ret;
373
374	ret = pm_runtime_resume_and_get(dev);
375	if (ret)
376		return ret;
377
378	/* SW reset */
379	reg = rzg2l_adc_readl(adc, RZG2L_ADM(0));
380	reg |= RZG2L_ADM0_SRESB;
381	rzg2l_adc_writel(adc, RZG2L_ADM(0), reg);
382
383	ret = read_poll_timeout(rzg2l_adc_readl, reg, reg & RZG2L_ADM0_SRESB,
384				200, 1000, false, adc, RZG2L_ADM(0));
385	if (ret)
386		goto exit_hw_init;
387
388	if (hw_params->adivc) {
389		/* Only division by 4 can be set */
390		reg = rzg2l_adc_readl(adc, RZG2L_ADIVC);
391		reg &= ~RZG2L_ADIVC_DIVADC_MASK;
392		reg |= RZG2L_ADIVC_DIVADC_4;
393		rzg2l_adc_writel(adc, RZG2L_ADIVC, reg);
394	}
395
396	/*
397	 * Setup AMD3
398	 * ADIL[31:24] - Should be always set to 0
399	 * ADCMP[23:16] - Should be always set to 0xe
400	 * ADSMP[15:0] - Set default (0x578) sampling period
401	 */
402	reg = rzg2l_adc_readl(adc, RZG2L_ADM(3));
403	reg &= ~RZG2L_ADM3_ADIL_MASK;
404	reg &= ~RZG2L_ADM3_ADCMP_MASK;
405	reg &= ~hw_params->adsmp_mask;
406	reg |= FIELD_PREP(RZG2L_ADM3_ADCMP_MASK, hw_params->default_adcmp) |
407	       hw_params->default_adsmp[0];
408
409	rzg2l_adc_writel(adc, RZG2L_ADM(3), reg);
410
411exit_hw_init:
412	pm_runtime_put_autosuspend(dev);
413	return ret;
414}
415
416static int rzg2l_adc_probe(struct platform_device *pdev)
417{
418	struct device *dev = &pdev->dev;
419	struct iio_dev *indio_dev;
420	struct rzg2l_adc *adc;
421	int ret;
422	int irq;
423
424	indio_dev = devm_iio_device_alloc(dev, sizeof(*adc));
425	if (!indio_dev)
426		return -ENOMEM;
427
428	platform_set_drvdata(pdev, indio_dev);
429
430	adc = iio_priv(indio_dev);
431
432	adc->hw_params = device_get_match_data(dev);
433	if (!adc->hw_params || adc->hw_params->num_channels > RZG2L_ADC_MAX_CHANNELS)
434		return -EINVAL;
435
436	ret = rzg2l_adc_parse_properties(pdev, adc);
437	if (ret)
438		return ret;
439
440	mutex_init(&adc->lock);
441
442	adc->base = devm_platform_ioremap_resource(pdev, 0);
443	if (IS_ERR(adc->base))
444		return PTR_ERR(adc->base);
445
446	adc->adrstn = devm_reset_control_get_exclusive_deasserted(dev, "adrst-n");
447	if (IS_ERR(adc->adrstn))
448		return dev_err_probe(dev, PTR_ERR(adc->adrstn),
449				     "failed to get/deassert adrst-n\n");
450
451	adc->presetn = devm_reset_control_get_exclusive_deasserted(dev, "presetn");
452	if (IS_ERR(adc->presetn))
453		return dev_err_probe(dev, PTR_ERR(adc->presetn),
454				     "failed to get/deassert presetn\n");
455
456	pm_runtime_set_autosuspend_delay(dev, 300);
457	pm_runtime_use_autosuspend(dev);
458	ret = devm_pm_runtime_enable(dev);
459	if (ret)
460		return ret;
461
462	ret = rzg2l_adc_hw_init(dev, adc);
463	if (ret)
464		return dev_err_probe(&pdev->dev, ret,
465				     "failed to initialize ADC HW\n");
466
467	irq = platform_get_irq(pdev, 0);
468	if (irq < 0)
469		return irq;
470
471	ret = devm_request_irq(dev, irq, rzg2l_adc_isr,
472			       0, dev_name(dev), adc);
473	if (ret < 0)
474		return ret;
475
476	init_completion(&adc->completion);
477
478	indio_dev->name = DRIVER_NAME;
479	indio_dev->info = &rzg2l_adc_iio_info;
480	indio_dev->modes = INDIO_DIRECT_MODE;
481	indio_dev->channels = adc->data->channels;
482	indio_dev->num_channels = adc->data->num_channels;
483
484	return devm_iio_device_register(dev, indio_dev);
485}
486
487static const struct rzg2l_adc_hw_params rzg2l_hw_params = {
488	.num_channels = 8,
489	.default_adcmp = 0xe,
490	.default_adsmp = { 0x578 },
491	.adsmp_mask = GENMASK(15, 0),
492	.adint_inten_mask = GENMASK(7, 0),
493	.adivc = true
494};
495
496static const struct rzg2l_adc_hw_params rzg3s_hw_params = {
497	.num_channels = 9,
498	.default_adcmp = 0x1d,
499	.default_adsmp = { 0x7f, 0xff },
500	.adsmp_mask = GENMASK(7, 0),
501	.adint_inten_mask = GENMASK(11, 0),
502};
503
504static const struct of_device_id rzg2l_adc_match[] = {
505	{ .compatible = "renesas,r9a08g045-adc", .data = &rzg3s_hw_params },
506	{ .compatible = "renesas,rzg2l-adc", .data = &rzg2l_hw_params },
507	{ }
508};
509MODULE_DEVICE_TABLE(of, rzg2l_adc_match);
510
511static int rzg2l_adc_pm_runtime_suspend(struct device *dev)
512{
513	struct iio_dev *indio_dev = dev_get_drvdata(dev);
514	struct rzg2l_adc *adc = iio_priv(indio_dev);
515
516	rzg2l_adc_pwr(adc, false);
517
518	return 0;
519}
520
521static int rzg2l_adc_pm_runtime_resume(struct device *dev)
522{
523	struct iio_dev *indio_dev = dev_get_drvdata(dev);
524	struct rzg2l_adc *adc = iio_priv(indio_dev);
525
526	rzg2l_adc_pwr(adc, true);
527
528	return 0;
529}
530
531static int rzg2l_adc_suspend(struct device *dev)
532{
533	struct iio_dev *indio_dev = dev_get_drvdata(dev);
534	struct rzg2l_adc *adc = iio_priv(indio_dev);
535	struct reset_control_bulk_data resets[] = {
536		{ .rstc = adc->presetn },
537		{ .rstc = adc->adrstn },
538	};
539	int ret;
540
541	ret = pm_runtime_force_suspend(dev);
542	if (ret)
543		return ret;
544
545	ret = reset_control_bulk_assert(ARRAY_SIZE(resets), resets);
546	if (ret)
547		goto rpm_restore;
548
549	return 0;
550
551rpm_restore:
552	pm_runtime_force_resume(dev);
553	return ret;
554}
555
556static int rzg2l_adc_resume(struct device *dev)
557{
558	struct iio_dev *indio_dev = dev_get_drvdata(dev);
559	struct rzg2l_adc *adc = iio_priv(indio_dev);
560	struct reset_control_bulk_data resets[] = {
561		{ .rstc = adc->adrstn },
562		{ .rstc = adc->presetn },
563	};
564	int ret;
565
566	ret = reset_control_bulk_deassert(ARRAY_SIZE(resets), resets);
567	if (ret)
568		return ret;
569
570	ret = pm_runtime_force_resume(dev);
571	if (ret)
572		goto resets_restore;
573
574	ret = rzg2l_adc_hw_init(dev, adc);
575	if (ret)
576		goto rpm_restore;
577
578	return 0;
579
580rpm_restore:
581	pm_runtime_force_suspend(dev);
582resets_restore:
583	reset_control_bulk_assert(ARRAY_SIZE(resets), resets);
584	return ret;
585}
586
587static const struct dev_pm_ops rzg2l_adc_pm_ops = {
588	RUNTIME_PM_OPS(rzg2l_adc_pm_runtime_suspend, rzg2l_adc_pm_runtime_resume, NULL)
589	SYSTEM_SLEEP_PM_OPS(rzg2l_adc_suspend, rzg2l_adc_resume)
590};
591
592static struct platform_driver rzg2l_adc_driver = {
593	.probe		= rzg2l_adc_probe,
594	.driver		= {
595		.name		= DRIVER_NAME,
596		.of_match_table = rzg2l_adc_match,
597		.pm		= pm_ptr(&rzg2l_adc_pm_ops),
598	},
599};
600
601module_platform_driver(rzg2l_adc_driver);
602
603MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
604MODULE_DESCRIPTION("Renesas RZ/G2L ADC driver");
605MODULE_LICENSE("GPL v2");
606MODULE_IMPORT_NS("IIO_DRIVER");