rohm-bd79112.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * ROHM ADC driver for BD79112 signal monitoring hub.
  4 * Copyright (C) 2025, ROHM Semiconductor.
  5 *
  6 * SPI communication derived from ad7923.c and ti-ads7950.c
  7 */
  8
  9#include <linux/array_size.h>
 10#include <linux/bitfield.h>
 11#include <linux/bitops.h>
 12#include <linux/bits.h>
 13#include <linux/dev_printk.h>
 14#include <linux/err.h>
 15#include <linux/errno.h>
 16#include <linux/gpio/driver.h>
 17#include <linux/mod_devicetable.h>
 18#include <linux/module.h>
 19#include <linux/regmap.h>
 20#include <linux/regulator/consumer.h>
 21#include <linux/spi/spi.h>
 22#include <linux/types.h>
 23#include <asm/byteorder.h>
 24
 25#include <linux/iio/adc-helpers.h>
 26#include <linux/iio/iio.h>
 27
 28#define BD79112_MAX_NUM_CHANNELS 32
 29
 30struct bd79112_data {
 31	struct spi_device *spi;
 32	struct regmap *map;
 33	struct device *dev;
 34	struct gpio_chip gc;
 35	unsigned long gpio_valid_mask;
 36	unsigned int vref_mv;
 37	struct spi_transfer read_xfer[2];
 38	struct spi_transfer write_xfer;
 39	struct spi_message read_msg;
 40	struct spi_message write_msg;
 41	/* 16-bit TX, valid data in high byte */
 42	u8 read_tx[2] __aligned(IIO_DMA_MINALIGN);
 43	/* 8-bit address followed by 8-bit data */
 44	u8 reg_write_tx[2];
 45	/* 12-bit of ADC data or 8 bit of reg data */
 46	__be16 read_rx;
 47};
 48
 49/*
 50 * The ADC data is read issuing SPI-command matching the channel number.
 51 * We treat this as a register address.
 52 */
 53#define BD79112_REG_AGIO0A		0x00
 54#define BD79112_REG_AGIO15B		0x1f
 55
 56/*
 57 * ADC STATUS_FLAG appended to ADC data will be set, if the ADC result is being
 58 * read for a channel, which input pin is muxed to be a GPIO.
 59 */
 60#define BD79112_ADC_STATUS_FLAG BIT(14)
 61
 62/*
 63 * The BD79112 requires "R/W bit" to be set for SPI register (not ADC data)
 64 * reads and an "IOSET bit" to be set for read/write operations (which aren't
 65 * reading the ADC data).
 66 */
 67#define BD79112_BIT_RW			BIT(4)
 68#define BD79112_BIT_IO			BIT(5)
 69
 70#define BD79112_REG_GPI_VALUE_B8_15	(BD79112_BIT_IO | 0x0)
 71#define BD79112_REG_GPI_VALUE_B0_B7	(BD79112_BIT_IO | 0x1)
 72#define BD79112_REG_GPI_VALUE_A8_15	(BD79112_BIT_IO | 0x2)
 73#define BD79112_REG_GPI_VALUE_A0_A7	(BD79112_BIT_IO | 0x3)
 74
 75#define BD79112_REG_GPI_EN_B7_B15	(BD79112_BIT_IO | 0x4)
 76#define BD79112_REG_GPI_EN_B0_B7	(BD79112_BIT_IO | 0x5)
 77#define BD79112_REG_GPI_EN_A8_A15	(BD79112_BIT_IO | 0x6)
 78#define BD79112_REG_GPI_EN_A0_A7	(BD79112_BIT_IO | 0x7)
 79
 80#define BD79112_REG_GPO_EN_B7_B15	(BD79112_BIT_IO | 0x8)
 81#define BD79112_REG_GPO_EN_B0_B7	(BD79112_BIT_IO | 0x9)
 82#define BD79112_REG_GPO_EN_A8_A15	(BD79112_BIT_IO | 0xa)
 83#define BD79112_REG_GPO_EN_A0_A7	(BD79112_BIT_IO | 0xb)
 84
 85#define BD79112_NUM_GPIO_EN_REGS	8
 86#define BD79112_FIRST_GPIO_EN_REG	BD79112_REG_GPI_EN_B7_B15
 87
 88#define BD79112_REG_GPO_VALUE_B8_15	(BD79112_BIT_IO | 0xc)
 89#define BD79112_REG_GPO_VALUE_B0_B7	(BD79112_BIT_IO | 0xd)
 90#define BD79112_REG_GPO_VALUE_A8_15	(BD79112_BIT_IO | 0xe)
 91#define BD79112_REG_GPO_VALUE_A0_A7	(BD79112_BIT_IO | 0xf)
 92
 93#define BD79112_REG_MAX BD79112_REG_GPO_VALUE_A0_A7
 94
 95/*
 96 * Read transaction consists of two 16-bit sequences separated by CSB.
 97 * For register read, 'IOSET' bit must be set. For ADC read, IOSET is cleared
 98 * and ADDR equals the channel number (0 ... 31).
 99 *
100 * First 16-bit sequence, MOSI as below, MISO data ignored:
101 * - SCK: | 1 | 2 |   3   |    4   | 5 .. 8 | 9 .. 16 |
102 * - MOSI:| 0 | 0 | IOSET | RW (1) |  ADDR  |  8'b0   |
103 *
104 * CSB released and re-acquired between these sequences
105 *
106 * Second 16-bit sequence, MISO as below, MOSI data ignored:
107 *   For Register read data is 8 bits:
108 *   - SCK: | 1 .. 8 |   9 .. 16   |
109 *   - MISO:|  8'b0  | 8-bit data  |
110 *
111 *   For ADC read data is 12 bits:
112 *   - SCK: | 1 |      2      | 3  4 |   4 .. 16   |
113 *   - MISO:| 0 | STATUS_FLAG | 2'b0 | 12-bit data |
114 *     The 'STATUS_FLAG' is set if the read input pin was configured as a GPIO.
115 */
116static int bd79112_reg_read(void *context, unsigned int reg, unsigned int *val)
117{
118	struct bd79112_data *data = context;
119	int ret;
120
121	if (reg & BD79112_BIT_IO)
122		reg |= BD79112_BIT_RW;
123
124	data->read_tx[0] = reg;
125
126	ret = spi_sync(data->spi, &data->read_msg);
127	if (!ret)
128		*val = be16_to_cpu(data->read_rx);
129
130	return ret;
131}
132
133/*
134 * Write, single 16-bit sequence (broken down below):
135 *
136 * First 8-bit, MOSI as below, MISO data ignored:
137 * - SCK: | 1 | 2 | 3   | 4     | 5 .. 8 |
138 * - MOSI:| 0 | 0 |IOSET| RW(0) | ADDR   |
139 *
140 * Last 8 SCK cycles (b8 ... b15), MISO contains register data, MOSI ignored.
141 * - SCK: | 9 .. 16 |
142 * - MISO:|  data   |
143 */
144static int bd79112_reg_write(void *context, unsigned int reg, unsigned int val)
145{
146	struct bd79112_data *data = context;
147
148	data->reg_write_tx[0] = reg;
149	data->reg_write_tx[1] = val;
150
151	return spi_sync(data->spi, &data->write_msg);
152}
153
154static int _get_gpio_reg(unsigned int offset, unsigned int base)
155{
156	int regoffset = offset / 8;
157
158	if (offset > 31)
159		return -EINVAL;
160
161	return base - regoffset;
162}
163
164#define GET_GPIO_BIT(offset) BIT((offset) % 8)
165#define GET_GPO_EN_REG(offset)  _get_gpio_reg((offset), BD79112_REG_GPO_EN_A0_A7)
166#define GET_GPI_EN_REG(offset)  _get_gpio_reg((offset), BD79112_REG_GPI_EN_A0_A7)
167#define GET_GPO_VAL_REG(offset)  _get_gpio_reg((offset), BD79112_REG_GPO_VALUE_A0_A7)
168#define GET_GPI_VAL_REG(offset)  _get_gpio_reg((offset), BD79112_REG_GPI_VALUE_A0_A7)
169
170static const struct regmap_range bd71815_volatile_ro_ranges[] = {
171	/* Read ADC data */
172	regmap_reg_range(BD79112_REG_AGIO0A, BD79112_REG_AGIO15B),
173	/* GPI state */
174	regmap_reg_range(BD79112_REG_GPI_VALUE_B8_15, BD79112_REG_GPI_VALUE_A0_A7),
175};
176
177static const struct regmap_access_table bd79112_volatile_regs = {
178	.yes_ranges = &bd71815_volatile_ro_ranges[0],
179	.n_yes_ranges = ARRAY_SIZE(bd71815_volatile_ro_ranges),
180};
181
182static const struct regmap_access_table bd79112_ro_regs = {
183	.no_ranges = &bd71815_volatile_ro_ranges[0],
184	.n_no_ranges = ARRAY_SIZE(bd71815_volatile_ro_ranges),
185};
186
187static const struct regmap_config bd79112_regmap = {
188	.reg_read = bd79112_reg_read,
189	.reg_write = bd79112_reg_write,
190	.volatile_table = &bd79112_volatile_regs,
191	.wr_table = &bd79112_ro_regs,
192	.cache_type = REGCACHE_MAPLE,
193	.max_register = BD79112_REG_MAX,
194};
195
196static int bd79112_read_raw(struct iio_dev *indio_dev,
197			    struct iio_chan_spec const *chan, int *val,
198			    int *val2, long m)
199{
200	struct bd79112_data *data = iio_priv(indio_dev);
201	int ret;
202
203	switch (m) {
204	case IIO_CHAN_INFO_RAW:
205		ret = regmap_read(data->map, chan->channel, val);
206		if (ret < 0)
207			return ret;
208
209		return IIO_VAL_INT;
210
211	case IIO_CHAN_INFO_SCALE:
212		*val = data->vref_mv;
213		*val2 = 12;
214
215		return IIO_VAL_FRACTIONAL_LOG2;
216	default:
217		return -EINVAL;
218	}
219}
220
221static const struct iio_info bd79112_info = {
222	.read_raw = bd79112_read_raw,
223};
224
225static const struct iio_chan_spec bd79112_chan_template = {
226	.type = IIO_VOLTAGE,
227	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
228	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
229	.indexed = 1,
230};
231
232static int bd79112_gpio_init_valid_mask(struct gpio_chip *gc,
233					unsigned long *valid_mask,
234					unsigned int ngpios)
235{
236	struct bd79112_data *data = gpiochip_get_data(gc);
237
238	*valid_mask = data->gpio_valid_mask;
239
240	return 0;
241}
242
243static int bd79112_gpio_dir_get(struct gpio_chip *gc, unsigned int offset)
244{
245	struct bd79112_data *data = gpiochip_get_data(gc);
246	unsigned int reg, bit, val;
247	int ret;
248
249	bit = GET_GPIO_BIT(offset);
250	reg = GET_GPO_EN_REG(offset);
251
252	ret = regmap_read(data->map, reg, &val);
253	if (ret)
254		return ret;
255
256	if (bit & val)
257		return GPIO_LINE_DIRECTION_OUT;
258
259	reg = GET_GPI_EN_REG(offset);
260	ret = regmap_read(data->map, reg, &val);
261	if (ret)
262		return ret;
263
264	if (bit & val)
265		return GPIO_LINE_DIRECTION_IN;
266
267	/*
268	 * Ouch. Seems the pin is ADC input - shouldn't happen as changing mux
269	 * at runtime is not supported and non GPIO pins should be invalidated
270	 * by the valid_mask at probe. Maybe someone wrote a register bypassing
271	 * the driver?
272	 */
273	dev_err(data->dev, "Pin not a GPIO\n");
274
275	return -EINVAL;
276}
277
278static int bd79112_gpio_get(struct gpio_chip *gc, unsigned int offset)
279{
280	struct bd79112_data *data = gpiochip_get_data(gc);
281	unsigned int reg, bit, val;
282	int ret;
283
284	bit = GET_GPIO_BIT(offset);
285	reg = GET_GPI_VAL_REG(offset);
286
287	ret = regmap_read(data->map, reg, &val);
288	if (ret)
289		return ret;
290
291	return !!(val & bit);
292}
293
294static int bd79112_gpio_set(struct gpio_chip *gc, unsigned int offset,
295			    int value)
296{
297	struct bd79112_data *data = gpiochip_get_data(gc);
298	unsigned int reg, bit;
299
300	bit = GET_GPIO_BIT(offset);
301	reg = GET_GPO_VAL_REG(offset);
302
303	return regmap_assign_bits(data->map, reg, bit, value);
304}
305
306static int bd79112_gpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
307				     unsigned long *bits)
308{
309	struct bd79112_data *data = gpiochip_get_data(gc);
310	unsigned long i, bank_mask;
311
312	for_each_set_clump8(i, bank_mask, mask, gc->ngpio) {
313		unsigned long bank_bits;
314		unsigned int reg;
315		int ret;
316
317		bank_bits = bitmap_get_value8(bits, i);
318		reg = BD79112_REG_GPO_VALUE_A0_A7 - i / 8;
319		ret = regmap_update_bits(data->map, reg, bank_mask, bank_bits);
320		if (ret)
321			return ret;
322	}
323
324	return 0;
325}
326
327static int bd79112_gpio_dir_set(struct bd79112_data *data, unsigned int offset,
328				int dir)
329{
330	unsigned int gpi_reg, gpo_reg, bit;
331	int ret;
332
333	bit = GET_GPIO_BIT(offset);
334	gpi_reg = GET_GPI_EN_REG(offset);
335	gpo_reg =  GET_GPO_EN_REG(offset);
336
337	if (dir == GPIO_LINE_DIRECTION_OUT) {
338		ret = regmap_clear_bits(data->map, gpi_reg, bit);
339		if (ret)
340			return ret;
341
342		return regmap_set_bits(data->map, gpo_reg, bit);
343	}
344
345	ret = regmap_set_bits(data->map, gpi_reg, bit);
346	if (ret)
347		return ret;
348
349	return regmap_clear_bits(data->map, gpo_reg, bit);
350}
351
352static int bd79112_gpio_input(struct gpio_chip *gc, unsigned int offset)
353{
354	struct bd79112_data *data = gpiochip_get_data(gc);
355
356	return bd79112_gpio_dir_set(data, offset, GPIO_LINE_DIRECTION_IN);
357}
358
359static int bd79112_gpio_output(struct gpio_chip *gc, unsigned int offset,
360			       int value)
361{
362	struct bd79112_data *data = gpiochip_get_data(gc);
363	int ret;
364
365	ret = bd79112_gpio_set(gc, offset, value);
366	if (ret)
367		return ret;
368
369	return bd79112_gpio_dir_set(data, offset, GPIO_LINE_DIRECTION_OUT);
370}
371
372static const struct gpio_chip bd79112_gpio_chip = {
373	.label			= "bd79112-gpio",
374	.get_direction		= bd79112_gpio_dir_get,
375	.direction_input	= bd79112_gpio_input,
376	.direction_output	= bd79112_gpio_output,
377	.get			= bd79112_gpio_get,
378	.set			= bd79112_gpio_set,
379	.set_multiple		= bd79112_gpio_set_multiple,
380	.init_valid_mask	= bd79112_gpio_init_valid_mask,
381	.can_sleep		= true,
382	.ngpio			= 32,
383	.base			= -1,
384};
385
386static unsigned int bd79112_get_gpio_pins(const struct iio_chan_spec *cs, int num_channels)
387{
388	unsigned int i, gpio_channels;
389
390	/*
391	 * Let's initialize the mux config to say that all 32 channels are
392	 * GPIOs. Then we can just loop through the iio_chan_spec and clear the
393	 * bits for found ADC channels.
394	 */
395	gpio_channels = GENMASK(31, 0);
396	for (i = 0; i < num_channels; i++)
397		gpio_channels &= ~BIT(cs[i].channel);
398
399	return gpio_channels;
400}
401
402/* ADC channels as named in the data-sheet */
403static const char * const bd79112_chan_names[] = {
404	"AGIO0A", "AGIO1A", "AGIO2A", "AGIO3A",		/* 0 - 3 */
405	"AGIO4A", "AGIO5A", "AGIO6A", "AGIO7A",		/* 4 - 7 */
406	"AGIO8A", "AGIO9A", "AGIO10A", "AGIO11A",	/* 8 - 11 */
407	"AGIO12A", "AGIO13A", "AGIO14A", "AGIO15A",	/* 12 - 15 */
408	"AGIO0B", "AGIO1B", "AGIO2B", "AGIO3B",		/* 16 - 19 */
409	"AGIO4B", "AGIO5B", "AGIO6B", "AGIO7B",		/* 20 - 23 */
410	"AGIO8B", "AGIO9B", "AGIO10B", "AGIO11B",	/* 24 - 27 */
411	"AGIO12B", "AGIO13B", "AGIO14B", "AGIO15B",	/* 28 - 31 */
412};
413
414static int bd79112_probe(struct spi_device *spi)
415{
416	struct bd79112_data *data;
417	struct iio_dev *iio_dev;
418	struct iio_chan_spec *cs;
419	struct device *dev = &spi->dev;
420	unsigned long gpio_pins, pin;
421	unsigned int i;
422	int ret;
423
424	iio_dev = devm_iio_device_alloc(dev, sizeof(*data));
425	if (!iio_dev)
426		return -ENOMEM;
427
428	data = iio_priv(iio_dev);
429	data->spi = spi;
430	data->dev = dev;
431	data->map = devm_regmap_init(dev, NULL, data, &bd79112_regmap);
432	if (IS_ERR(data->map))
433		return dev_err_probe(dev, PTR_ERR(data->map),
434				     "Failed to initialize Regmap\n");
435
436	ret = devm_regulator_get_enable_read_voltage(dev, "vdd");
437	if (ret < 0)
438		return dev_err_probe(dev, ret, "Failed to get the Vdd\n");
439
440	data->vref_mv = ret / 1000;
441
442	ret = devm_regulator_get_enable(dev, "iovdd");
443	if (ret < 0)
444		return dev_err_probe(dev, ret, "Failed to enable I/O voltage\n");
445
446	data->read_xfer[0].tx_buf = &data->read_tx[0];
447	data->read_xfer[0].len = sizeof(data->read_tx);
448	data->read_xfer[0].cs_change = 1;
449	data->read_xfer[1].rx_buf = &data->read_rx;
450	data->read_xfer[1].len = sizeof(data->read_rx);
451	spi_message_init_with_transfers(&data->read_msg, data->read_xfer, 2);
452	ret = devm_spi_optimize_message(dev, spi, &data->read_msg);
453	if (ret < 0)
454		return dev_err_probe(dev, ret,
455				     "Failed to optimize SPI read message\n");
456
457	data->write_xfer.tx_buf = &data->reg_write_tx[0];
458	data->write_xfer.len = sizeof(data->reg_write_tx);
459	spi_message_init_with_transfers(&data->write_msg, &data->write_xfer, 1);
460	ret = devm_spi_optimize_message(dev, spi, &data->write_msg);
461	if (ret < 0)
462		return dev_err_probe(dev, ret,
463				     "Failed to optimize SPI write message\n");
464
465	ret = devm_iio_adc_device_alloc_chaninfo_se(dev, &bd79112_chan_template,
466						    BD79112_MAX_NUM_CHANNELS - 1,
467						    &cs);
468
469	/* Register all pins as GPIOs if there are no ADC channels */
470	if (ret == -ENOENT)
471		goto register_gpios;
472
473	if (ret < 0)
474		return ret;
475
476	iio_dev->num_channels = ret;
477	iio_dev->channels = cs;
478
479	for (i = 0; i < iio_dev->num_channels; i++)
480		cs[i].datasheet_name = bd79112_chan_names[cs[i].channel];
481
482	iio_dev->info = &bd79112_info;
483	iio_dev->name = "bd79112";
484	iio_dev->modes = INDIO_DIRECT_MODE;
485
486	/*
487	 * Ensure all channels are ADCs. This allows us to register the IIO
488	 * device early (before checking which pins are to be used for GPIO)
489	 * without having to worry about some pins being initially used for
490	 * GPIO.
491	 */
492	for (i = 0; i < BD79112_NUM_GPIO_EN_REGS; i++) {
493		ret = regmap_write(data->map, BD79112_FIRST_GPIO_EN_REG + i, 0);
494		if (ret)
495			return dev_err_probe(dev, ret,
496					     "Failed to initialize channels\n");
497	}
498
499	ret = devm_iio_device_register(data->dev, iio_dev);
500	if (ret)
501		return dev_err_probe(data->dev, ret, "Failed to register ADC\n");
502
503register_gpios:
504	gpio_pins = bd79112_get_gpio_pins(iio_dev->channels,
505					  iio_dev->num_channels);
506
507	/* If all channels are reserved for ADC, then we're done. */
508	if (!gpio_pins)
509		return 0;
510
511	/* Default all the GPIO pins to GPI */
512	for_each_set_bit(pin, &gpio_pins, BD79112_MAX_NUM_CHANNELS) {
513		ret = bd79112_gpio_dir_set(data, pin, GPIO_LINE_DIRECTION_IN);
514		if (ret)
515			return dev_err_probe(dev, ret,
516					     "Failed to mark pin as GPI\n");
517	}
518
519	data->gpio_valid_mask = gpio_pins;
520	data->gc = bd79112_gpio_chip;
521	data->gc.parent = dev;
522
523	return devm_gpiochip_add_data(dev, &data->gc, data);
524}
525
526static const struct of_device_id bd79112_of_match[] = {
527	{ .compatible = "rohm,bd79112" },
528	{ }
529};
530MODULE_DEVICE_TABLE(of, bd79112_of_match);
531
532static const struct spi_device_id bd79112_id[] = {
533	{ "bd79112" },
534	{ }
535};
536MODULE_DEVICE_TABLE(spi, bd79112_id);
537
538static struct spi_driver bd79112_driver = {
539	.driver = {
540		.name = "bd79112",
541		.of_match_table = bd79112_of_match,
542	},
543	.probe = bd79112_probe,
544	.id_table = bd79112_id,
545};
546module_spi_driver(bd79112_driver);
547
548MODULE_AUTHOR("Matti Vaittinen <mazziesaccount@gmail.com>");
549MODULE_DESCRIPTION("Driver for ROHM BD79112 ADC/GPIO");
550MODULE_LICENSE("GPL");
551MODULE_IMPORT_NS("IIO_DRIVER");