max1363.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * iio/adc/max1363.c
   4  * Copyright (C) 2008-2010 Jonathan Cameron
   5  *
   6  * based on linux/drivers/i2c/chips/max123x
   7  * Copyright (C) 2002-2004 Stefan Eletzhofer
   8  *
   9  * based on linux/drivers/acron/char/pcf8583.c
  10  * Copyright (C) 2000 Russell King
  11  *
  12  * Driver for max1363 and similar chips.
  13  */
  14
  15#include <linux/interrupt.h>
  16#include <linux/cleanup.h>
  17#include <linux/device.h>
  18#include <linux/kernel.h>
  19#include <linux/sysfs.h>
  20#include <linux/list.h>
  21#include <linux/i2c.h>
  22#include <linux/regulator/consumer.h>
  23#include <linux/slab.h>
  24#include <linux/err.h>
  25#include <linux/module.h>
  26#include <linux/mod_devicetable.h>
  27#include <linux/property.h>
  28#include <linux/unaligned.h>
  29
  30#include <linux/iio/iio.h>
  31#include <linux/iio/sysfs.h>
  32#include <linux/iio/events.h>
  33#include <linux/iio/buffer.h>
  34#include <linux/iio/kfifo_buf.h>
  35#include <linux/iio/trigger_consumer.h>
  36#include <linux/iio/triggered_buffer.h>
  37
  38#define MAX1363_SETUP_BYTE(a) ((a) | 0x80)
  39
  40/* There is a fair bit more defined here than currently
  41 * used, but the intention is to support everything these
  42 * chips do in the long run */
  43
  44/* see data sheets */
  45/* max1363 and max1236, max1237, max1238, max1239 */
  46#define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD	0x00
  47#define MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF	0x20
  48#define MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT	0x40
  49#define MAX1363_SETUP_AIN3_IS_REF_REF_IS_INT	0x60
  50#define MAX1363_SETUP_POWER_UP_INT_REF		0x10
  51#define MAX1363_SETUP_POWER_DOWN_INT_REF	0x00
  52
  53/* think about including max11600 etc - more settings */
  54#define MAX1363_SETUP_EXT_CLOCK			0x08
  55#define MAX1363_SETUP_INT_CLOCK			0x00
  56#define MAX1363_SETUP_UNIPOLAR			0x00
  57#define MAX1363_SETUP_BIPOLAR			0x04
  58#define MAX1363_SETUP_RESET			0x00
  59#define MAX1363_SETUP_NORESET			0x02
  60/* max1363 only - though don't care on others.
  61 * For now monitor modes are not implemented as the relevant
  62 * line is not connected on my test board.
  63 * The definitions are here as I intend to add this soon.
  64 */
  65#define MAX1363_SETUP_MONITOR_SETUP		0x01
  66
  67/* Specific to the max1363 */
  68#define MAX1363_MON_RESET_CHAN(a) (1 << ((a) + 4))
  69#define MAX1363_MON_INT_ENABLE			0x01
  70
  71/* defined for readability reasons */
  72/* All chips */
  73#define MAX1363_CONFIG_BYTE(a) ((a))
  74
  75#define MAX1363_CONFIG_SE			0x01
  76#define MAX1363_CONFIG_DE			0x00
  77#define MAX1363_CONFIG_SCAN_TO_CS		0x00
  78#define MAX1363_CONFIG_SCAN_SINGLE_8		0x20
  79#define MAX1363_CONFIG_SCAN_MONITOR_MODE	0x40
  80#define MAX1363_CONFIG_SCAN_SINGLE_1		0x60
  81/* max123{6-9} only */
  82#define MAX1236_SCAN_MID_TO_CHANNEL		0x40
  83
  84/* max1363 only - merely part of channel selects or don't care for others */
  85#define MAX1363_CONFIG_EN_MON_MODE_READ 0x18
  86
  87#define MAX1363_CHANNEL_SEL(a) ((a) << 1)
  88
  89/* max1363 strictly 0x06 - but doesn't matter */
  90#define MAX1363_CHANNEL_SEL_MASK		0x1E
  91#define MAX1363_SCAN_MASK			0x60
  92#define MAX1363_SE_DE_MASK			0x01
  93
  94#define MAX1363_MAX_CHANNELS 25
  95/**
  96 * struct max1363_mode - scan mode information
  97 * @conf:	The corresponding value of the configuration register
  98 * @modemask:	Bit mask corresponding to channels enabled in this mode
  99 */
 100struct max1363_mode {
 101	int8_t		conf;
 102	DECLARE_BITMAP(modemask, MAX1363_MAX_CHANNELS);
 103};
 104
 105/* This must be maintained along side the max1363_mode_table in max1363_core */
 106enum max1363_modes {
 107	/* Single read of a single channel */
 108	_s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
 109	/* Differential single read */
 110	d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
 111	d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
 112	/* Scan to channel and mid to channel where overlapping */
 113	s0to1, s0to2, s2to3, s0to3, s0to4, s0to5, s0to6,
 114	s6to7, s0to7, s6to8, s0to8, s6to9,
 115	s0to9, s6to10, s0to10, s6to11, s0to11,
 116	/* Differential scan to channel and mid to channel where overlapping */
 117	d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9,
 118	d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2,
 119	d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8,
 120	d7m6to11m10, d1m0to11m10,
 121};
 122
 123/**
 124 * struct max1363_chip_info - chip specifc information
 125 * @info:		iio core function callbacks structure
 126 * @channels:		channel specification
 127 * @num_channels:       number of channels
 128 * @mode_list:		array of available scan modes
 129 * @default_mode:	the scan mode in which the chip starts up
 130 * @int_vref_mv:	the internal reference voltage
 131 * @num_modes:		number of modes
 132 * @bits:		accuracy of the adc in bits
 133 */
 134struct max1363_chip_info {
 135	const struct iio_info		*info;
 136	const struct iio_chan_spec	*channels;
 137	int				num_channels;
 138	const enum max1363_modes	*mode_list;
 139	enum max1363_modes		default_mode;
 140	u16				int_vref_mv;
 141	u8				num_modes;
 142	u8				bits;
 143};
 144
 145/**
 146 * struct max1363_state - driver instance specific data
 147 * @client:		i2c_client
 148 * @setupbyte:		cache of current device setup byte
 149 * @configbyte:		cache of current device config byte
 150 * @chip_info:		chip model specific constants, available modes, etc.
 151 * @current_mode:	the scan mode of this chip
 152 * @requestedmask:	a valid requested set of channels
 153 * @lock:		lock to ensure state is consistent
 154 * @monitor_on:		whether monitor mode is enabled
 155 * @monitor_speed:	parameter corresponding to device monitor speed setting
 156 * @mask_high:		bitmask for enabled high thresholds
 157 * @mask_low:		bitmask for enabled low thresholds
 158 * @thresh_high:	high threshold values
 159 * @thresh_low:		low threshold values
 160 * @vref:		Reference voltage regulator
 161 * @vref_uv:		Actual (external or internal) reference voltage
 162 * @send:		function used to send data to the chip
 163 * @recv:		function used to receive data from the chip
 164 * @data:		buffer to store channel data and timestamp
 165 */
 166struct max1363_state {
 167	struct i2c_client		*client;
 168	u8				setupbyte;
 169	u8				configbyte;
 170	const struct max1363_chip_info	*chip_info;
 171	const struct max1363_mode	*current_mode;
 172	u32				requestedmask;
 173	struct mutex			lock;
 174
 175	/* Using monitor modes and buffer at the same time is
 176	   currently not supported */
 177	bool				monitor_on;
 178	unsigned int			monitor_speed:3;
 179	u8				mask_high;
 180	u8				mask_low;
 181	/* 4x unipolar first then the fours bipolar ones */
 182	s16				thresh_high[8];
 183	s16				thresh_low[8];
 184	struct regulator		*vref;
 185	u32				vref_uv;
 186	int				(*send)(const struct i2c_client *client,
 187						const char *buf, int count);
 188	int				(*recv)(const struct i2c_client *client,
 189						char *buf, int count);
 190	struct {
 191		u8 buf[MAX1363_MAX_CHANNELS * 2];
 192		aligned_s64 ts;
 193	} data;
 194};
 195
 196#define MAX1363_MODE_SINGLE(_num, _mask) {				\
 197		.conf = MAX1363_CHANNEL_SEL(_num)			\
 198			| MAX1363_CONFIG_SCAN_SINGLE_1			\
 199			| MAX1363_CONFIG_SE,				\
 200			.modemask[0] = _mask,				\
 201			}
 202
 203#define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) {			\
 204		.conf = MAX1363_CHANNEL_SEL(_num)			\
 205			| MAX1363_CONFIG_SCAN_TO_CS			\
 206			| MAX1363_CONFIG_SE,				\
 207			.modemask[0] = _mask,				\
 208			}
 209
 210/* note not available for max1363 hence naming */
 211#define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) {		\
 212		.conf = MAX1363_CHANNEL_SEL(_num)			\
 213			| MAX1236_SCAN_MID_TO_CHANNEL			\
 214			| MAX1363_CONFIG_SE,				\
 215			.modemask[0] = _mask				\
 216}
 217
 218#define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) {			\
 219		.conf = MAX1363_CHANNEL_SEL(_nump)			\
 220			| MAX1363_CONFIG_SCAN_SINGLE_1			\
 221			| MAX1363_CONFIG_DE,				\
 222			.modemask[0] = _mask				\
 223			}
 224
 225/* Can't think how to automate naming so specify for now */
 226#define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) {	\
 227		.conf = MAX1363_CHANNEL_SEL(_num)			\
 228			| MAX1363_CONFIG_SCAN_TO_CS			\
 229			| MAX1363_CONFIG_DE,				\
 230			.modemask[0] = _mask				\
 231			}
 232
 233/* note only available for max1363 hence naming */
 234#define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) {	\
 235		.conf = MAX1363_CHANNEL_SEL(_num)			\
 236			| MAX1236_SCAN_MID_TO_CHANNEL			\
 237			| MAX1363_CONFIG_SE,				\
 238			.modemask[0] = _mask				\
 239}
 240
 241static const struct max1363_mode max1363_mode_table[] = {
 242	/* All of the single channel options first */
 243	MAX1363_MODE_SINGLE(0, 1 << 0),
 244	MAX1363_MODE_SINGLE(1, 1 << 1),
 245	MAX1363_MODE_SINGLE(2, 1 << 2),
 246	MAX1363_MODE_SINGLE(3, 1 << 3),
 247	MAX1363_MODE_SINGLE(4, 1 << 4),
 248	MAX1363_MODE_SINGLE(5, 1 << 5),
 249	MAX1363_MODE_SINGLE(6, 1 << 6),
 250	MAX1363_MODE_SINGLE(7, 1 << 7),
 251	MAX1363_MODE_SINGLE(8, 1 << 8),
 252	MAX1363_MODE_SINGLE(9, 1 << 9),
 253	MAX1363_MODE_SINGLE(10, 1 << 10),
 254	MAX1363_MODE_SINGLE(11, 1 << 11),
 255
 256	MAX1363_MODE_DIFF_SINGLE(0, 1, 1 << 12),
 257	MAX1363_MODE_DIFF_SINGLE(2, 3, 1 << 13),
 258	MAX1363_MODE_DIFF_SINGLE(4, 5, 1 << 14),
 259	MAX1363_MODE_DIFF_SINGLE(6, 7, 1 << 15),
 260	MAX1363_MODE_DIFF_SINGLE(8, 9, 1 << 16),
 261	MAX1363_MODE_DIFF_SINGLE(10, 11, 1 << 17),
 262	MAX1363_MODE_DIFF_SINGLE(1, 0, 1 << 18),
 263	MAX1363_MODE_DIFF_SINGLE(3, 2, 1 << 19),
 264	MAX1363_MODE_DIFF_SINGLE(5, 4, 1 << 20),
 265	MAX1363_MODE_DIFF_SINGLE(7, 6, 1 << 21),
 266	MAX1363_MODE_DIFF_SINGLE(9, 8, 1 << 22),
 267	MAX1363_MODE_DIFF_SINGLE(11, 10, 1 << 23),
 268
 269	/* The multichannel scans next */
 270	MAX1363_MODE_SCAN_TO_CHANNEL(1, 0x003),
 271	MAX1363_MODE_SCAN_TO_CHANNEL(2, 0x007),
 272	MAX1236_MODE_SCAN_MID_TO_CHANNEL(2, 3, 0x00C),
 273	MAX1363_MODE_SCAN_TO_CHANNEL(3, 0x00F),
 274	MAX1363_MODE_SCAN_TO_CHANNEL(4, 0x01F),
 275	MAX1363_MODE_SCAN_TO_CHANNEL(5, 0x03F),
 276	MAX1363_MODE_SCAN_TO_CHANNEL(6, 0x07F),
 277	MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 7, 0x0C0),
 278	MAX1363_MODE_SCAN_TO_CHANNEL(7, 0x0FF),
 279	MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 8, 0x1C0),
 280	MAX1363_MODE_SCAN_TO_CHANNEL(8, 0x1FF),
 281	MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 9, 0x3C0),
 282	MAX1363_MODE_SCAN_TO_CHANNEL(9, 0x3FF),
 283	MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 10, 0x7C0),
 284	MAX1363_MODE_SCAN_TO_CHANNEL(10, 0x7FF),
 285	MAX1236_MODE_SCAN_MID_TO_CHANNEL(6, 11, 0xFC0),
 286	MAX1363_MODE_SCAN_TO_CHANNEL(11, 0xFFF),
 287
 288	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(2, 2, 0x003000),
 289	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(4, 3, 0x007000),
 290	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(6, 4, 0x00F000),
 291	MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(8, 2, 0x018000),
 292	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(8, 5, 0x01F000),
 293	MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(10, 3, 0x038000),
 294	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(10, 6, 0x3F000),
 295	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(3, 2, 0x0C0000),
 296	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(5, 3, 0x1C0000),
 297	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(7, 4, 0x3C0000),
 298	MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(9, 2, 0x600000),
 299	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(9, 5, 0x7C0000),
 300	MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(11, 3, 0xE00000),
 301	MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(11, 6, 0xFC0000),
 302};
 303
 304static const struct max1363_mode
 305*max1363_match_mode(const unsigned long *mask,
 306	const struct max1363_chip_info *ci)
 307{
 308	int i;
 309	if (mask)
 310		for (i = 0; i < ci->num_modes; i++)
 311			if (bitmap_subset(mask,
 312					  max1363_mode_table[ci->mode_list[i]].
 313					  modemask,
 314					  MAX1363_MAX_CHANNELS))
 315				return &max1363_mode_table[ci->mode_list[i]];
 316	return NULL;
 317}
 318
 319static int max1363_smbus_send(const struct i2c_client *client, const char *buf,
 320		int count)
 321{
 322	int i, err;
 323
 324	for (i = err = 0; err == 0 && i < count; ++i)
 325		err = i2c_smbus_write_byte(client, buf[i]);
 326
 327	return err ? err : count;
 328}
 329
 330static int max1363_smbus_recv(const struct i2c_client *client, char *buf,
 331		int count)
 332{
 333	int i, ret;
 334
 335	for (i = 0; i < count; ++i) {
 336		ret = i2c_smbus_read_byte(client);
 337		if (ret < 0)
 338			return ret;
 339		buf[i] = ret;
 340	}
 341
 342	return count;
 343}
 344
 345static int max1363_write_basic_config(struct max1363_state *st)
 346{
 347	u8 tx_buf[2] = { st->setupbyte, st->configbyte };
 348
 349	return st->send(st->client, tx_buf, 2);
 350}
 351
 352static int max1363_set_scan_mode(struct max1363_state *st)
 353{
 354	st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
 355			    | MAX1363_SCAN_MASK
 356			    | MAX1363_SE_DE_MASK);
 357	st->configbyte |= st->current_mode->conf;
 358
 359	return max1363_write_basic_config(st);
 360}
 361
 362static int max1363_read_single_chan(struct iio_dev *indio_dev,
 363				    struct iio_chan_spec const *chan,
 364				    int *val,
 365				    long m)
 366{
 367	s32 data;
 368	u8 rxbuf[2];
 369	struct max1363_state *st = iio_priv(indio_dev);
 370	struct i2c_client *client = st->client;
 371
 372	guard(mutex)(&st->lock);
 373
 374	/*
 375	 * If monitor mode is enabled, the method for reading a single
 376	 * channel will have to be rather different and has not yet
 377	 * been implemented.
 378	 *
 379	 * Also, cannot read directly if buffered capture enabled.
 380	 */
 381	if (st->monitor_on)
 382		return -EBUSY;
 383
 384	/* Check to see if current scan mode is correct */
 385	if (st->current_mode != &max1363_mode_table[chan->address]) {
 386		int ret;
 387
 388		/* Update scan mode if needed */
 389		st->current_mode = &max1363_mode_table[chan->address];
 390		ret = max1363_set_scan_mode(st);
 391		if (ret < 0)
 392			return ret;
 393	}
 394	if (st->chip_info->bits != 8) {
 395		/* Get reading */
 396		data = st->recv(client, rxbuf, 2);
 397		if (data < 0)
 398			return data;
 399
 400		data = get_unaligned_be16(rxbuf) &
 401			((1 << st->chip_info->bits) - 1);
 402	} else {
 403		/* Get reading */
 404		data = st->recv(client, rxbuf, 1);
 405		if (data < 0)
 406			return data;
 407
 408		data = rxbuf[0];
 409	}
 410	*val = data;
 411
 412	return 0;
 413}
 414
 415static int max1363_read_raw(struct iio_dev *indio_dev,
 416			    struct iio_chan_spec const *chan,
 417			    int *val,
 418			    int *val2,
 419			    long m)
 420{
 421	struct max1363_state *st = iio_priv(indio_dev);
 422	int ret;
 423
 424	switch (m) {
 425	case IIO_CHAN_INFO_RAW:
 426		if (!iio_device_claim_direct(indio_dev))
 427			return -EBUSY;
 428
 429		ret = max1363_read_single_chan(indio_dev, chan, val, m);
 430		iio_device_release_direct(indio_dev);
 431		if (ret < 0)
 432			return ret;
 433		return IIO_VAL_INT;
 434	case IIO_CHAN_INFO_SCALE:
 435		*val = st->vref_uv / 1000;
 436		*val2 = st->chip_info->bits;
 437		return IIO_VAL_FRACTIONAL_LOG2;
 438	default:
 439		return -EINVAL;
 440	}
 441	return 0;
 442}
 443
 444/* Applies to max1363 */
 445static const enum max1363_modes max1363_mode_list[] = {
 446	_s0, _s1, _s2, _s3,
 447	s0to1, s0to2, s0to3,
 448	d0m1, d2m3, d1m0, d3m2,
 449	d0m1to2m3, d1m0to3m2,
 450};
 451
 452static const struct iio_event_spec max1363_events[] = {
 453	{
 454		.type = IIO_EV_TYPE_THRESH,
 455		.dir = IIO_EV_DIR_RISING,
 456		.mask_separate = BIT(IIO_EV_INFO_VALUE) |
 457			BIT(IIO_EV_INFO_ENABLE),
 458	}, {
 459		.type = IIO_EV_TYPE_THRESH,
 460		.dir = IIO_EV_DIR_FALLING,
 461		.mask_separate = BIT(IIO_EV_INFO_VALUE) |
 462			BIT(IIO_EV_INFO_ENABLE),
 463	},
 464};
 465
 466#define MAX1363_CHAN_U(num, addr, si, bits, ev_spec, num_ev_spec)	\
 467	{								\
 468		.type = IIO_VOLTAGE,					\
 469		.indexed = 1,						\
 470		.channel = num,						\
 471		.address = addr,					\
 472		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
 473		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
 474		.datasheet_name = "AIN"#num,				\
 475		.scan_type = {						\
 476			.sign = 'u',					\
 477			.realbits = bits,				\
 478			.storagebits = (bits > 8) ? 16 : 8,		\
 479			.endianness = IIO_BE,				\
 480		},							\
 481		.scan_index = si,					\
 482		.event_spec = ev_spec,					\
 483		.num_event_specs = num_ev_spec,				\
 484	}
 485
 486/* bipolar channel */
 487#define MAX1363_CHAN_B(num, num2, addr, si, bits, ev_spec, num_ev_spec)	\
 488	{								\
 489		.type = IIO_VOLTAGE,					\
 490		.differential = 1,					\
 491		.indexed = 1,						\
 492		.channel = num,						\
 493		.channel2 = num2,					\
 494		.address = addr,					\
 495		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
 496		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
 497		.datasheet_name = "AIN"#num"-AIN"#num2,			\
 498		.scan_type = {						\
 499			.sign = 's',					\
 500			.realbits = bits,				\
 501			.storagebits = (bits > 8) ? 16 : 8,		\
 502			.endianness = IIO_BE,				\
 503		},							\
 504		.scan_index = si,					\
 505		.event_spec = ev_spec,					\
 506		.num_event_specs = num_ev_spec,				\
 507	}
 508
 509#define MAX1363_4X_CHANS(bits, ev_spec, num_ev_spec) {			\
 510	MAX1363_CHAN_U(0, _s0, 0, bits, ev_spec, num_ev_spec),		\
 511	MAX1363_CHAN_U(1, _s1, 1, bits, ev_spec, num_ev_spec),		\
 512	MAX1363_CHAN_U(2, _s2, 2, bits, ev_spec, num_ev_spec),		\
 513	MAX1363_CHAN_U(3, _s3, 3, bits, ev_spec, num_ev_spec),		\
 514	MAX1363_CHAN_B(0, 1, d0m1, 12, bits, ev_spec, num_ev_spec),	\
 515	MAX1363_CHAN_B(2, 3, d2m3, 13, bits, ev_spec, num_ev_spec),	\
 516	MAX1363_CHAN_B(1, 0, d1m0, 18, bits, ev_spec, num_ev_spec),	\
 517	MAX1363_CHAN_B(3, 2, d3m2, 19, bits, ev_spec, num_ev_spec),	\
 518	IIO_CHAN_SOFT_TIMESTAMP(8)					\
 519	}
 520
 521static const struct iio_chan_spec max1036_channels[] =
 522	MAX1363_4X_CHANS(8, NULL, 0);
 523static const struct iio_chan_spec max1136_channels[] =
 524	MAX1363_4X_CHANS(10, NULL, 0);
 525static const struct iio_chan_spec max1236_channels[] =
 526	MAX1363_4X_CHANS(12, NULL, 0);
 527static const struct iio_chan_spec max1361_channels[] =
 528	MAX1363_4X_CHANS(10, max1363_events, ARRAY_SIZE(max1363_events));
 529static const struct iio_chan_spec max1363_channels[] =
 530	MAX1363_4X_CHANS(12, max1363_events, ARRAY_SIZE(max1363_events));
 531
 532/* Applies to max1236, max1237 */
 533static const enum max1363_modes max1236_mode_list[] = {
 534	_s0, _s1, _s2, _s3,
 535	s0to1, s0to2, s2to3, s0to3,
 536	d0m1, d2m3, d1m0, d3m2,
 537	d0m1to2m3, d1m0to3m2,
 538};
 539
 540/* Applies to max1238, max1239 */
 541static const enum max1363_modes max1238_mode_list[] = {
 542	_s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7, _s8, _s9, _s10, _s11,
 543	s0to1, s0to2, s0to3, s0to4, s0to5, s0to6,
 544	s6to7, s6to8, s6to9, s6to10, s6to11,
 545	s0to7, s0to8, s0to9, s0to10, s0to11,
 546	d0m1, d2m3, d4m5, d6m7, d8m9, d10m11,
 547	d1m0, d3m2, d5m4, d7m6, d9m8, d11m10,
 548	d0m1to2m3, d0m1to4m5, d0m1to6m7, d6m7to8m9,
 549	d0m1to8m9, d6m7to10m11, d0m1to10m11, d1m0to3m2,
 550	d1m0to5m4, d1m0to7m6, d7m6to9m8, d1m0to9m8,
 551	d7m6to11m10, d1m0to11m10,
 552};
 553
 554#define MAX1363_12X_CHANS(bits) {				\
 555	MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0),		\
 556	MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0),		\
 557	MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0),		\
 558	MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0),		\
 559	MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0),		\
 560	MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0),		\
 561	MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0),		\
 562	MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0),		\
 563	MAX1363_CHAN_U(8, _s8, 8, bits, NULL, 0),		\
 564	MAX1363_CHAN_U(9, _s9, 9, bits, NULL, 0),		\
 565	MAX1363_CHAN_U(10, _s10, 10, bits, NULL, 0),		\
 566	MAX1363_CHAN_U(11, _s11, 11, bits, NULL, 0),		\
 567	MAX1363_CHAN_B(0, 1, d0m1, 12, bits, NULL, 0),		\
 568	MAX1363_CHAN_B(2, 3, d2m3, 13, bits, NULL, 0),		\
 569	MAX1363_CHAN_B(4, 5, d4m5, 14, bits, NULL, 0),		\
 570	MAX1363_CHAN_B(6, 7, d6m7, 15, bits, NULL, 0),		\
 571	MAX1363_CHAN_B(8, 9, d8m9, 16, bits, NULL, 0),		\
 572	MAX1363_CHAN_B(10, 11, d10m11, 17, bits, NULL, 0),	\
 573	MAX1363_CHAN_B(1, 0, d1m0, 18, bits, NULL, 0),		\
 574	MAX1363_CHAN_B(3, 2, d3m2, 19, bits, NULL, 0),		\
 575	MAX1363_CHAN_B(5, 4, d5m4, 20, bits, NULL, 0),		\
 576	MAX1363_CHAN_B(7, 6, d7m6, 21, bits, NULL, 0),		\
 577	MAX1363_CHAN_B(9, 8, d9m8, 22, bits, NULL, 0),		\
 578	MAX1363_CHAN_B(11, 10, d11m10, 23, bits, NULL, 0),	\
 579	IIO_CHAN_SOFT_TIMESTAMP(24)				\
 580	}
 581static const struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
 582static const struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
 583static const struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
 584
 585static const enum max1363_modes max11607_mode_list[] = {
 586	_s0, _s1, _s2, _s3,
 587	s0to1, s0to2, s2to3,
 588	s0to3,
 589	d0m1, d2m3, d1m0, d3m2,
 590	d0m1to2m3, d1m0to3m2,
 591};
 592
 593static const enum max1363_modes max11608_mode_list[] = {
 594	_s0, _s1, _s2, _s3, _s4, _s5, _s6, _s7,
 595	s0to1, s0to2, s0to3, s0to4, s0to5, s0to6, s6to7, s0to7,
 596	d0m1, d2m3, d4m5, d6m7,
 597	d1m0, d3m2, d5m4, d7m6,
 598	d0m1to2m3, d0m1to4m5, d0m1to6m7,
 599	d1m0to3m2, d1m0to5m4, d1m0to7m6,
 600};
 601
 602#define MAX1363_8X_CHANS(bits) {			\
 603	MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0),	\
 604	MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0),	\
 605	MAX1363_CHAN_U(2, _s2, 2, bits, NULL, 0),	\
 606	MAX1363_CHAN_U(3, _s3, 3, bits, NULL, 0),	\
 607	MAX1363_CHAN_U(4, _s4, 4, bits, NULL, 0),	\
 608	MAX1363_CHAN_U(5, _s5, 5, bits, NULL, 0),	\
 609	MAX1363_CHAN_U(6, _s6, 6, bits, NULL, 0),	\
 610	MAX1363_CHAN_U(7, _s7, 7, bits, NULL, 0),	\
 611	MAX1363_CHAN_B(0, 1, d0m1, 12, bits, NULL, 0),	\
 612	MAX1363_CHAN_B(2, 3, d2m3, 13, bits, NULL, 0),	\
 613	MAX1363_CHAN_B(4, 5, d4m5, 14, bits, NULL, 0),	\
 614	MAX1363_CHAN_B(6, 7, d6m7, 15, bits, NULL, 0),	\
 615	MAX1363_CHAN_B(1, 0, d1m0, 18, bits, NULL, 0),	\
 616	MAX1363_CHAN_B(3, 2, d3m2, 19, bits, NULL, 0),	\
 617	MAX1363_CHAN_B(5, 4, d5m4, 20, bits, NULL, 0),	\
 618	MAX1363_CHAN_B(7, 6, d7m6, 21, bits, NULL, 0),	\
 619	IIO_CHAN_SOFT_TIMESTAMP(16)			\
 620}
 621static const struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
 622static const struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
 623static const struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
 624
 625static const enum max1363_modes max11644_mode_list[] = {
 626	_s0, _s1, s0to1, d0m1, d1m0,
 627};
 628
 629#define MAX1363_2X_CHANS(bits) {			\
 630	MAX1363_CHAN_U(0, _s0, 0, bits, NULL, 0),	\
 631	MAX1363_CHAN_U(1, _s1, 1, bits, NULL, 0),	\
 632	MAX1363_CHAN_B(0, 1, d0m1, 2, bits, NULL, 0),	\
 633	MAX1363_CHAN_B(1, 0, d1m0, 3, bits, NULL, 0),	\
 634	IIO_CHAN_SOFT_TIMESTAMP(4)			\
 635	}
 636
 637static const struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10);
 638static const struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12);
 639
 640enum { max1361,
 641       max1362,
 642       max1363,
 643       max1364,
 644       max1036,
 645       max1037,
 646       max1038,
 647       max1039,
 648       max1136,
 649       max1137,
 650       max1138,
 651       max1139,
 652       max1236,
 653       max1237,
 654       max1238,
 655       max1239,
 656       max11600,
 657       max11601,
 658       max11602,
 659       max11603,
 660       max11604,
 661       max11605,
 662       max11606,
 663       max11607,
 664       max11608,
 665       max11609,
 666       max11610,
 667       max11611,
 668       max11612,
 669       max11613,
 670       max11614,
 671       max11615,
 672       max11616,
 673       max11617,
 674       max11644,
 675       max11645,
 676       max11646,
 677       max11647
 678};
 679
 680static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600,
 681					      8300, 4200, 2000, 1000 };
 682
 683static ssize_t max1363_monitor_show_freq(struct device *dev,
 684					struct device_attribute *attr,
 685					char *buf)
 686{
 687	struct max1363_state *st = iio_priv(dev_to_iio_dev(dev));
 688	return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]);
 689}
 690
 691static ssize_t max1363_monitor_store_freq(struct device *dev,
 692					struct device_attribute *attr,
 693					const char *buf,
 694					size_t len)
 695{
 696	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 697	struct max1363_state *st = iio_priv(indio_dev);
 698	int i, ret;
 699	unsigned long val;
 700	bool found = false;
 701
 702	ret = kstrtoul(buf, 10, &val);
 703	if (ret)
 704		return -EINVAL;
 705	for (i = 0; i < ARRAY_SIZE(max1363_monitor_speeds); i++)
 706		if (val == max1363_monitor_speeds[i]) {
 707			found = true;
 708			break;
 709		}
 710	if (!found)
 711		return -EINVAL;
 712
 713	scoped_guard(mutex, &st->lock)
 714		st->monitor_speed = i;
 715
 716	return 0;
 717}
 718
 719static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR,
 720			max1363_monitor_show_freq,
 721			max1363_monitor_store_freq);
 722
 723static IIO_CONST_ATTR(sampling_frequency_available,
 724		"133000 665000 33300 16600 8300 4200 2000 1000");
 725
 726static int max1363_read_thresh(struct iio_dev *indio_dev,
 727	const struct iio_chan_spec *chan, enum iio_event_type type,
 728	enum iio_event_direction dir, enum iio_event_info info, int *val,
 729	int *val2)
 730{
 731	struct max1363_state *st = iio_priv(indio_dev);
 732	if (dir == IIO_EV_DIR_FALLING)
 733		*val = st->thresh_low[chan->channel];
 734	else
 735		*val = st->thresh_high[chan->channel];
 736	return IIO_VAL_INT;
 737}
 738
 739static int max1363_write_thresh(struct iio_dev *indio_dev,
 740	const struct iio_chan_spec *chan, enum iio_event_type type,
 741	enum iio_event_direction dir, enum iio_event_info info, int val,
 742	int val2)
 743{
 744	struct max1363_state *st = iio_priv(indio_dev);
 745	/* make it handle signed correctly as well */
 746	switch (st->chip_info->bits) {
 747	case 10:
 748		if (val > 0x3FF)
 749			return -EINVAL;
 750		break;
 751	case 12:
 752		if (val > 0xFFF)
 753			return -EINVAL;
 754		break;
 755	}
 756
 757	switch (dir) {
 758	case IIO_EV_DIR_FALLING:
 759		st->thresh_low[chan->channel] = val;
 760		break;
 761	case IIO_EV_DIR_RISING:
 762		st->thresh_high[chan->channel] = val;
 763		break;
 764	default:
 765		return -EINVAL;
 766	}
 767
 768	return 0;
 769}
 770
 771static const u64 max1363_event_codes[] = {
 772	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
 773			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
 774	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
 775			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
 776	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
 777			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
 778	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
 779			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING),
 780	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 0,
 781			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
 782	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 1,
 783			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
 784	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 2,
 785			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
 786	IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, 3,
 787			     IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING),
 788};
 789
 790static irqreturn_t max1363_event_handler(int irq, void *private)
 791{
 792	struct iio_dev *indio_dev = private;
 793	struct max1363_state *st = iio_priv(indio_dev);
 794	s64 timestamp = iio_get_time_ns(indio_dev);
 795	unsigned long mask, loc;
 796	u8 rx;
 797	u8 tx[2] = { st->setupbyte,
 798		     MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 };
 799
 800	st->recv(st->client, &rx, 1);
 801	mask = rx;
 802	for_each_set_bit(loc, &mask, 8)
 803		iio_push_event(indio_dev, max1363_event_codes[loc], timestamp);
 804	st->send(st->client, tx, 2);
 805
 806	return IRQ_HANDLED;
 807}
 808
 809static int max1363_read_event_config(struct iio_dev *indio_dev,
 810	const struct iio_chan_spec *chan, enum iio_event_type type,
 811	enum iio_event_direction dir)
 812{
 813	struct max1363_state *st = iio_priv(indio_dev);
 814	int val;
 815	int number = chan->channel;
 816
 817	guard(mutex)(&st->lock);
 818	if (dir == IIO_EV_DIR_FALLING)
 819		val = (1 << number) & st->mask_low;
 820	else
 821		val = (1 << number) & st->mask_high;
 822
 823	return val;
 824}
 825
 826static int max1363_monitor_mode_update(struct max1363_state *st, int enabled)
 827{
 828	int ret, i = 3, j;
 829	unsigned long numelements;
 830	int len;
 831	const long *modemask;
 832
 833	if (!enabled) {
 834		/* transition to buffered capture is not currently supported */
 835		st->setupbyte &= ~MAX1363_SETUP_MONITOR_SETUP;
 836		st->configbyte &= ~MAX1363_SCAN_MASK;
 837		st->monitor_on = false;
 838		return max1363_write_basic_config(st);
 839	}
 840
 841	/* Ensure we are in the relevant mode */
 842	st->setupbyte |= MAX1363_SETUP_MONITOR_SETUP;
 843	st->configbyte &= ~(MAX1363_CHANNEL_SEL_MASK
 844			    | MAX1363_SCAN_MASK
 845			| MAX1363_SE_DE_MASK);
 846	st->configbyte |= MAX1363_CONFIG_SCAN_MONITOR_MODE;
 847	if ((st->mask_low | st->mask_high) & 0x0F) {
 848		st->configbyte |= max1363_mode_table[s0to3].conf;
 849		modemask = max1363_mode_table[s0to3].modemask;
 850	} else if ((st->mask_low | st->mask_high) & 0x30) {
 851		st->configbyte |= max1363_mode_table[d0m1to2m3].conf;
 852		modemask = max1363_mode_table[d0m1to2m3].modemask;
 853	} else {
 854		st->configbyte |= max1363_mode_table[d1m0to3m2].conf;
 855		modemask = max1363_mode_table[d1m0to3m2].modemask;
 856	}
 857	numelements = bitmap_weight(modemask, MAX1363_MAX_CHANNELS);
 858	len = 3 * numelements + 3;
 859	u8 *tx_buf __free(kfree) = kmalloc(len, GFP_KERNEL);
 860	if (!tx_buf)
 861		return -ENOMEM;
 862
 863	tx_buf[0] = st->configbyte;
 864	tx_buf[1] = st->setupbyte;
 865	tx_buf[2] = (st->monitor_speed << 1);
 866
 867	/*
 868	 * So we need to do yet another bit of nefarious scan mode
 869	 * setup to match what we need.
 870	 */
 871	for (j = 0; j < 8; j++)
 872		if (test_bit(j, modemask)) {
 873			/* Establish the mode is in the scan */
 874			if (st->mask_low & (1 << j)) {
 875				tx_buf[i] = (st->thresh_low[j] >> 4) & 0xFF;
 876				tx_buf[i + 1] = (st->thresh_low[j] << 4) & 0xF0;
 877			} else if (j < 4) {
 878				tx_buf[i] = 0;
 879				tx_buf[i + 1] = 0;
 880			} else {
 881				tx_buf[i] = 0x80;
 882				tx_buf[i + 1] = 0;
 883			}
 884			if (st->mask_high & (1 << j)) {
 885				tx_buf[i + 1] |=
 886					(st->thresh_high[j] >> 8) & 0x0F;
 887				tx_buf[i + 2] = st->thresh_high[j] & 0xFF;
 888			} else if (j < 4) {
 889				tx_buf[i + 1] |= 0x0F;
 890				tx_buf[i + 2] = 0xFF;
 891			} else {
 892				tx_buf[i + 1] |= 0x07;
 893				tx_buf[i + 2] = 0xFF;
 894			}
 895			i += 3;
 896		}
 897
 898
 899	ret = st->send(st->client, tx_buf, len);
 900	if (ret < 0)
 901		return ret;
 902	if (ret != len)
 903		return -EIO;
 904
 905	/*
 906	 * Now that we hopefully have sensible thresholds in place it is
 907	 * time to turn the interrupts on.
 908	 * It is unclear from the data sheet if this should be necessary
 909	 * (i.e. whether monitor mode setup is atomic) but it appears to
 910	 * be in practice.
 911	 */
 912	tx_buf[0] = st->setupbyte;
 913	tx_buf[1] = MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0;
 914	ret = st->send(st->client, tx_buf, 2);
 915	if (ret < 0)
 916		return ret;
 917	if (ret != 2)
 918		return -EIO;
 919
 920	st->monitor_on = true;
 921
 922	return 0;
 923}
 924
 925/*
 926 * To keep this manageable we always use one of 3 scan modes.
 927 * Scan 0...3, 0-1,2-3 and 1-0,3-2
 928 */
 929
 930static inline int __max1363_check_event_mask(int thismask, int checkmask)
 931{
 932	int ret = 0;
 933	/* Is it unipolar */
 934	if (thismask < 4) {
 935		if (checkmask & ~0x0F) {
 936			ret = -EBUSY;
 937			goto error_ret;
 938		}
 939	} else if (thismask < 6) {
 940		if (checkmask & ~0x30) {
 941			ret = -EBUSY;
 942			goto error_ret;
 943		}
 944	} else if (checkmask & ~0xC0)
 945		ret = -EBUSY;
 946error_ret:
 947	return ret;
 948}
 949
 950static int __max1363_write_event_config(struct max1363_state *st,
 951	const struct iio_chan_spec *chan,
 952	enum iio_event_direction dir, bool state)
 953{
 954	int number = chan->channel;
 955	u16 unifiedmask;
 956	int ret;
 957
 958	guard(mutex)(&st->lock);
 959
 960	unifiedmask = st->mask_low | st->mask_high;
 961	if (dir == IIO_EV_DIR_FALLING) {
 962
 963		if (state == 0)
 964			st->mask_low &= ~(1 << number);
 965		else {
 966			ret = __max1363_check_event_mask((1 << number),
 967							 unifiedmask);
 968			if (ret)
 969				return ret;
 970			st->mask_low |= (1 << number);
 971		}
 972	} else {
 973		if (state == 0)
 974			st->mask_high &= ~(1 << number);
 975		else {
 976			ret = __max1363_check_event_mask((1 << number),
 977							 unifiedmask);
 978			if (ret)
 979				return ret;
 980			st->mask_high |= (1 << number);
 981		}
 982	}
 983
 984	return 0;
 985
 986}
 987static int max1363_write_event_config(struct iio_dev *indio_dev,
 988	const struct iio_chan_spec *chan, enum iio_event_type type,
 989	enum iio_event_direction dir, bool state)
 990{
 991	struct max1363_state *st = iio_priv(indio_dev);
 992	int ret;
 993
 994	if (!iio_device_claim_direct(indio_dev))
 995		return -EBUSY;
 996
 997	ret = __max1363_write_event_config(st, chan,  dir, state);
 998	iio_device_release_direct(indio_dev);
 999	max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low));
1000
1001	return ret;
1002}
1003
1004/*
1005 * As with scan_elements, only certain sets of these can
1006 * be combined.
1007 */
1008static struct attribute *max1363_event_attributes[] = {
1009	&iio_dev_attr_sampling_frequency.dev_attr.attr,
1010	&iio_const_attr_sampling_frequency_available.dev_attr.attr,
1011	NULL,
1012};
1013
1014static const struct attribute_group max1363_event_attribute_group = {
1015	.attrs = max1363_event_attributes,
1016};
1017
1018static int max1363_update_scan_mode(struct iio_dev *indio_dev,
1019				    const unsigned long *scan_mask)
1020{
1021	struct max1363_state *st = iio_priv(indio_dev);
1022
1023	/*
1024	 * Need to figure out the current mode based upon the requested
1025	 * scan mask in iio_dev
1026	 */
1027	st->current_mode = max1363_match_mode(scan_mask, st->chip_info);
1028	if (!st->current_mode)
1029		return -EINVAL;
1030	max1363_set_scan_mode(st);
1031	return 0;
1032}
1033
1034static const struct iio_info max1238_info = {
1035	.read_raw = &max1363_read_raw,
1036	.update_scan_mode = &max1363_update_scan_mode,
1037};
1038
1039static const struct iio_info max1363_info = {
1040	.read_event_value = &max1363_read_thresh,
1041	.write_event_value = &max1363_write_thresh,
1042	.read_event_config = &max1363_read_event_config,
1043	.write_event_config = &max1363_write_event_config,
1044	.read_raw = &max1363_read_raw,
1045	.update_scan_mode = &max1363_update_scan_mode,
1046	.event_attrs = &max1363_event_attribute_group,
1047};
1048
1049/* max1363 and max1368 tested - rest from data sheet */
1050static const struct max1363_chip_info max1363_chip_info_tbl[] = {
1051	[max1361] = {
1052		.bits = 10,
1053		.int_vref_mv = 2048,
1054		.mode_list = max1363_mode_list,
1055		.num_modes = ARRAY_SIZE(max1363_mode_list),
1056		.default_mode = s0to3,
1057		.channels = max1361_channels,
1058		.num_channels = ARRAY_SIZE(max1361_channels),
1059		.info = &max1363_info,
1060	},
1061	[max1362] = {
1062		.bits = 10,
1063		.int_vref_mv = 4096,
1064		.mode_list = max1363_mode_list,
1065		.num_modes = ARRAY_SIZE(max1363_mode_list),
1066		.default_mode = s0to3,
1067		.channels = max1361_channels,
1068		.num_channels = ARRAY_SIZE(max1361_channels),
1069		.info = &max1363_info,
1070	},
1071	[max1363] = {
1072		.bits = 12,
1073		.int_vref_mv = 2048,
1074		.mode_list = max1363_mode_list,
1075		.num_modes = ARRAY_SIZE(max1363_mode_list),
1076		.default_mode = s0to3,
1077		.channels = max1363_channels,
1078		.num_channels = ARRAY_SIZE(max1363_channels),
1079		.info = &max1363_info,
1080	},
1081	[max1364] = {
1082		.bits = 12,
1083		.int_vref_mv = 4096,
1084		.mode_list = max1363_mode_list,
1085		.num_modes = ARRAY_SIZE(max1363_mode_list),
1086		.default_mode = s0to3,
1087		.channels = max1363_channels,
1088		.num_channels = ARRAY_SIZE(max1363_channels),
1089		.info = &max1363_info,
1090	},
1091	[max1036] = {
1092		.bits = 8,
1093		.int_vref_mv = 4096,
1094		.mode_list = max1236_mode_list,
1095		.num_modes = ARRAY_SIZE(max1236_mode_list),
1096		.default_mode = s0to3,
1097		.info = &max1238_info,
1098		.channels = max1036_channels,
1099		.num_channels = ARRAY_SIZE(max1036_channels),
1100	},
1101	[max1037] = {
1102		.bits = 8,
1103		.int_vref_mv = 2048,
1104		.mode_list = max1236_mode_list,
1105		.num_modes = ARRAY_SIZE(max1236_mode_list),
1106		.default_mode = s0to3,
1107		.info = &max1238_info,
1108		.channels = max1036_channels,
1109		.num_channels = ARRAY_SIZE(max1036_channels),
1110	},
1111	[max1038] = {
1112		.bits = 8,
1113		.int_vref_mv = 4096,
1114		.mode_list = max1238_mode_list,
1115		.num_modes = ARRAY_SIZE(max1238_mode_list),
1116		.default_mode = s0to11,
1117		.info = &max1238_info,
1118		.channels = max1038_channels,
1119		.num_channels = ARRAY_SIZE(max1038_channels),
1120	},
1121	[max1039] = {
1122		.bits = 8,
1123		.int_vref_mv = 2048,
1124		.mode_list = max1238_mode_list,
1125		.num_modes = ARRAY_SIZE(max1238_mode_list),
1126		.default_mode = s0to11,
1127		.info = &max1238_info,
1128		.channels = max1038_channels,
1129		.num_channels = ARRAY_SIZE(max1038_channels),
1130	},
1131	[max1136] = {
1132		.bits = 10,
1133		.int_vref_mv = 4096,
1134		.mode_list = max1236_mode_list,
1135		.num_modes = ARRAY_SIZE(max1236_mode_list),
1136		.default_mode = s0to3,
1137		.info = &max1238_info,
1138		.channels = max1136_channels,
1139		.num_channels = ARRAY_SIZE(max1136_channels),
1140	},
1141	[max1137] = {
1142		.bits = 10,
1143		.int_vref_mv = 2048,
1144		.mode_list = max1236_mode_list,
1145		.num_modes = ARRAY_SIZE(max1236_mode_list),
1146		.default_mode = s0to3,
1147		.info = &max1238_info,
1148		.channels = max1136_channels,
1149		.num_channels = ARRAY_SIZE(max1136_channels),
1150	},
1151	[max1138] = {
1152		.bits = 10,
1153		.int_vref_mv = 4096,
1154		.mode_list = max1238_mode_list,
1155		.num_modes = ARRAY_SIZE(max1238_mode_list),
1156		.default_mode = s0to11,
1157		.info = &max1238_info,
1158		.channels = max1138_channels,
1159		.num_channels = ARRAY_SIZE(max1138_channels),
1160	},
1161	[max1139] = {
1162		.bits = 10,
1163		.int_vref_mv = 2048,
1164		.mode_list = max1238_mode_list,
1165		.num_modes = ARRAY_SIZE(max1238_mode_list),
1166		.default_mode = s0to11,
1167		.info = &max1238_info,
1168		.channels = max1138_channels,
1169		.num_channels = ARRAY_SIZE(max1138_channels),
1170	},
1171	[max1236] = {
1172		.bits = 12,
1173		.int_vref_mv = 4096,
1174		.mode_list = max1236_mode_list,
1175		.num_modes = ARRAY_SIZE(max1236_mode_list),
1176		.default_mode = s0to3,
1177		.info = &max1238_info,
1178		.channels = max1236_channels,
1179		.num_channels = ARRAY_SIZE(max1236_channels),
1180	},
1181	[max1237] = {
1182		.bits = 12,
1183		.int_vref_mv = 2048,
1184		.mode_list = max1236_mode_list,
1185		.num_modes = ARRAY_SIZE(max1236_mode_list),
1186		.default_mode = s0to3,
1187		.info = &max1238_info,
1188		.channels = max1236_channels,
1189		.num_channels = ARRAY_SIZE(max1236_channels),
1190	},
1191	[max1238] = {
1192		.bits = 12,
1193		.int_vref_mv = 4096,
1194		.mode_list = max1238_mode_list,
1195		.num_modes = ARRAY_SIZE(max1238_mode_list),
1196		.default_mode = s0to11,
1197		.info = &max1238_info,
1198		.channels = max1238_channels,
1199		.num_channels = ARRAY_SIZE(max1238_channels),
1200	},
1201	[max1239] = {
1202		.bits = 12,
1203		.int_vref_mv = 2048,
1204		.mode_list = max1238_mode_list,
1205		.num_modes = ARRAY_SIZE(max1238_mode_list),
1206		.default_mode = s0to11,
1207		.info = &max1238_info,
1208		.channels = max1238_channels,
1209		.num_channels = ARRAY_SIZE(max1238_channels),
1210	},
1211	[max11600] = {
1212		.bits = 8,
1213		.int_vref_mv = 4096,
1214		.mode_list = max11607_mode_list,
1215		.num_modes = ARRAY_SIZE(max11607_mode_list),
1216		.default_mode = s0to3,
1217		.info = &max1238_info,
1218		.channels = max1036_channels,
1219		.num_channels = ARRAY_SIZE(max1036_channels),
1220	},
1221	[max11601] = {
1222		.bits = 8,
1223		.int_vref_mv = 2048,
1224		.mode_list = max11607_mode_list,
1225		.num_modes = ARRAY_SIZE(max11607_mode_list),
1226		.default_mode = s0to3,
1227		.info = &max1238_info,
1228		.channels = max1036_channels,
1229		.num_channels = ARRAY_SIZE(max1036_channels),
1230	},
1231	[max11602] = {
1232		.bits = 8,
1233		.int_vref_mv = 4096,
1234		.mode_list = max11608_mode_list,
1235		.num_modes = ARRAY_SIZE(max11608_mode_list),
1236		.default_mode = s0to7,
1237		.info = &max1238_info,
1238		.channels = max11602_channels,
1239		.num_channels = ARRAY_SIZE(max11602_channels),
1240	},
1241	[max11603] = {
1242		.bits = 8,
1243		.int_vref_mv = 2048,
1244		.mode_list = max11608_mode_list,
1245		.num_modes = ARRAY_SIZE(max11608_mode_list),
1246		.default_mode = s0to7,
1247		.info = &max1238_info,
1248		.channels = max11602_channels,
1249		.num_channels = ARRAY_SIZE(max11602_channels),
1250	},
1251	[max11604] = {
1252		.bits = 8,
1253		.int_vref_mv = 4096,
1254		.mode_list = max1238_mode_list,
1255		.num_modes = ARRAY_SIZE(max1238_mode_list),
1256		.default_mode = s0to11,
1257		.info = &max1238_info,
1258		.channels = max1038_channels,
1259		.num_channels = ARRAY_SIZE(max1038_channels),
1260	},
1261	[max11605] = {
1262		.bits = 8,
1263		.int_vref_mv = 2048,
1264		.mode_list = max1238_mode_list,
1265		.num_modes = ARRAY_SIZE(max1238_mode_list),
1266		.default_mode = s0to11,
1267		.info = &max1238_info,
1268		.channels = max1038_channels,
1269		.num_channels = ARRAY_SIZE(max1038_channels),
1270	},
1271	[max11606] = {
1272		.bits = 10,
1273		.int_vref_mv = 4096,
1274		.mode_list = max11607_mode_list,
1275		.num_modes = ARRAY_SIZE(max11607_mode_list),
1276		.default_mode = s0to3,
1277		.info = &max1238_info,
1278		.channels = max1136_channels,
1279		.num_channels = ARRAY_SIZE(max1136_channels),
1280	},
1281	[max11607] = {
1282		.bits = 10,
1283		.int_vref_mv = 2048,
1284		.mode_list = max11607_mode_list,
1285		.num_modes = ARRAY_SIZE(max11607_mode_list),
1286		.default_mode = s0to3,
1287		.info = &max1238_info,
1288		.channels = max1136_channels,
1289		.num_channels = ARRAY_SIZE(max1136_channels),
1290	},
1291	[max11608] = {
1292		.bits = 10,
1293		.int_vref_mv = 4096,
1294		.mode_list = max11608_mode_list,
1295		.num_modes = ARRAY_SIZE(max11608_mode_list),
1296		.default_mode = s0to7,
1297		.info = &max1238_info,
1298		.channels = max11608_channels,
1299		.num_channels = ARRAY_SIZE(max11608_channels),
1300	},
1301	[max11609] = {
1302		.bits = 10,
1303		.int_vref_mv = 2048,
1304		.mode_list = max11608_mode_list,
1305		.num_modes = ARRAY_SIZE(max11608_mode_list),
1306		.default_mode = s0to7,
1307		.info = &max1238_info,
1308		.channels = max11608_channels,
1309		.num_channels = ARRAY_SIZE(max11608_channels),
1310	},
1311	[max11610] = {
1312		.bits = 10,
1313		.int_vref_mv = 4096,
1314		.mode_list = max1238_mode_list,
1315		.num_modes = ARRAY_SIZE(max1238_mode_list),
1316		.default_mode = s0to11,
1317		.info = &max1238_info,
1318		.channels = max1138_channels,
1319		.num_channels = ARRAY_SIZE(max1138_channels),
1320	},
1321	[max11611] = {
1322		.bits = 10,
1323		.int_vref_mv = 2048,
1324		.mode_list = max1238_mode_list,
1325		.num_modes = ARRAY_SIZE(max1238_mode_list),
1326		.default_mode = s0to11,
1327		.info = &max1238_info,
1328		.channels = max1138_channels,
1329		.num_channels = ARRAY_SIZE(max1138_channels),
1330	},
1331	[max11612] = {
1332		.bits = 12,
1333		.int_vref_mv = 4096,
1334		.mode_list = max11607_mode_list,
1335		.num_modes = ARRAY_SIZE(max11607_mode_list),
1336		.default_mode = s0to3,
1337		.info = &max1238_info,
1338		.channels = max1363_channels,
1339		.num_channels = ARRAY_SIZE(max1363_channels),
1340	},
1341	[max11613] = {
1342		.bits = 12,
1343		.int_vref_mv = 2048,
1344		.mode_list = max11607_mode_list,
1345		.num_modes = ARRAY_SIZE(max11607_mode_list),
1346		.default_mode = s0to3,
1347		.info = &max1238_info,
1348		.channels = max1363_channels,
1349		.num_channels = ARRAY_SIZE(max1363_channels),
1350	},
1351	[max11614] = {
1352		.bits = 12,
1353		.int_vref_mv = 4096,
1354		.mode_list = max11608_mode_list,
1355		.num_modes = ARRAY_SIZE(max11608_mode_list),
1356		.default_mode = s0to7,
1357		.info = &max1238_info,
1358		.channels = max11614_channels,
1359		.num_channels = ARRAY_SIZE(max11614_channels),
1360	},
1361	[max11615] = {
1362		.bits = 12,
1363		.int_vref_mv = 2048,
1364		.mode_list = max11608_mode_list,
1365		.num_modes = ARRAY_SIZE(max11608_mode_list),
1366		.default_mode = s0to7,
1367		.info = &max1238_info,
1368		.channels = max11614_channels,
1369		.num_channels = ARRAY_SIZE(max11614_channels),
1370	},
1371	[max11616] = {
1372		.bits = 12,
1373		.int_vref_mv = 4096,
1374		.mode_list = max1238_mode_list,
1375		.num_modes = ARRAY_SIZE(max1238_mode_list),
1376		.default_mode = s0to11,
1377		.info = &max1238_info,
1378		.channels = max1238_channels,
1379		.num_channels = ARRAY_SIZE(max1238_channels),
1380	},
1381	[max11617] = {
1382		.bits = 12,
1383		.int_vref_mv = 2048,
1384		.mode_list = max1238_mode_list,
1385		.num_modes = ARRAY_SIZE(max1238_mode_list),
1386		.default_mode = s0to11,
1387		.info = &max1238_info,
1388		.channels = max1238_channels,
1389		.num_channels = ARRAY_SIZE(max1238_channels),
1390	},
1391	[max11644] = {
1392		.bits = 12,
1393		.int_vref_mv = 4096,
1394		.mode_list = max11644_mode_list,
1395		.num_modes = ARRAY_SIZE(max11644_mode_list),
1396		.default_mode = s0to1,
1397		.info = &max1238_info,
1398		.channels = max11644_channels,
1399		.num_channels = ARRAY_SIZE(max11644_channels),
1400	},
1401	[max11645] = {
1402		.bits = 12,
1403		.int_vref_mv = 2048,
1404		.mode_list = max11644_mode_list,
1405		.num_modes = ARRAY_SIZE(max11644_mode_list),
1406		.default_mode = s0to1,
1407		.info = &max1238_info,
1408		.channels = max11644_channels,
1409		.num_channels = ARRAY_SIZE(max11644_channels),
1410	},
1411	[max11646] = {
1412		.bits = 10,
1413		.int_vref_mv = 4096,
1414		.mode_list = max11644_mode_list,
1415		.num_modes = ARRAY_SIZE(max11644_mode_list),
1416		.default_mode = s0to1,
1417		.info = &max1238_info,
1418		.channels = max11646_channels,
1419		.num_channels = ARRAY_SIZE(max11646_channels),
1420	},
1421	[max11647] = {
1422		.bits = 10,
1423		.int_vref_mv = 2048,
1424		.mode_list = max11644_mode_list,
1425		.num_modes = ARRAY_SIZE(max11644_mode_list),
1426		.default_mode = s0to1,
1427		.info = &max1238_info,
1428		.channels = max11646_channels,
1429		.num_channels = ARRAY_SIZE(max11646_channels),
1430	},
1431};
1432
1433static int max1363_initial_setup(struct max1363_state *st)
1434{
1435	st->setupbyte = MAX1363_SETUP_INT_CLOCK
1436		| MAX1363_SETUP_UNIPOLAR
1437		| MAX1363_SETUP_NORESET;
1438
1439	if (st->vref)
1440		st->setupbyte |= MAX1363_SETUP_AIN3_IS_REF_EXT_TO_REF;
1441	else
1442		st->setupbyte |= MAX1363_SETUP_POWER_UP_INT_REF
1443		  | MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_INT;
1444
1445	/* Set scan mode writes the config anyway so wait until then */
1446	st->setupbyte = MAX1363_SETUP_BYTE(st->setupbyte);
1447	st->current_mode = &max1363_mode_table[st->chip_info->default_mode];
1448	st->configbyte = MAX1363_CONFIG_BYTE(st->configbyte);
1449
1450	return max1363_set_scan_mode(st);
1451}
1452
1453static int max1363_alloc_scan_masks(struct iio_dev *indio_dev)
1454{
1455	struct max1363_state *st = iio_priv(indio_dev);
1456	unsigned long *masks;
1457	int i;
1458
1459	masks = devm_kzalloc(&indio_dev->dev,
1460			array3_size(BITS_TO_LONGS(MAX1363_MAX_CHANNELS),
1461				    sizeof(long),
1462				    st->chip_info->num_modes + 1),
1463			GFP_KERNEL);
1464	if (!masks)
1465		return -ENOMEM;
1466
1467	for (i = 0; i < st->chip_info->num_modes; i++)
1468		bitmap_copy(masks + BITS_TO_LONGS(MAX1363_MAX_CHANNELS)*i,
1469			    max1363_mode_table[st->chip_info->mode_list[i]]
1470			    .modemask, MAX1363_MAX_CHANNELS);
1471
1472	indio_dev->available_scan_masks = masks;
1473
1474	return 0;
1475}
1476
1477static irqreturn_t max1363_trigger_handler(int irq, void *p)
1478{
1479	struct iio_poll_func *pf = p;
1480	struct iio_dev *indio_dev = pf->indio_dev;
1481	struct max1363_state *st = iio_priv(indio_dev);
1482	int b_sent;
1483	unsigned long numvals = bitmap_weight(st->current_mode->modemask,
1484					      MAX1363_MAX_CHANNELS);
1485
1486	/* Monitor mode prevents reading. Whilst not currently implemented
1487	 * might as well have this test in here in the meantime as it does
1488	 * no harm.
1489	 */
1490	if (numvals == 0)
1491		goto done;
1492
1493	if (st->chip_info->bits != 8)
1494		b_sent = st->recv(st->client, st->data.buf, numvals * 2);
1495	else
1496		b_sent = st->recv(st->client, st->data.buf, numvals);
1497	if (b_sent < 0)
1498		goto done;
1499
1500	iio_push_to_buffers_with_ts(indio_dev, &st->data, sizeof(st->data),
1501				    iio_get_time_ns(indio_dev));
1502
1503done:
1504	iio_trigger_notify_done(indio_dev->trig);
1505
1506	return IRQ_HANDLED;
1507}
1508
1509#define MAX1363_COMPATIBLE(of_compatible, cfg) {		\
1510			.compatible = of_compatible,		\
1511			.data = &max1363_chip_info_tbl[cfg],	\
1512}
1513
1514static const struct of_device_id max1363_of_match[] = {
1515	MAX1363_COMPATIBLE("maxim,max1361", max1361),
1516	MAX1363_COMPATIBLE("maxim,max1362", max1362),
1517	MAX1363_COMPATIBLE("maxim,max1363", max1363),
1518	MAX1363_COMPATIBLE("maxim,max1364", max1364),
1519	MAX1363_COMPATIBLE("maxim,max1036", max1036),
1520	MAX1363_COMPATIBLE("maxim,max1037", max1037),
1521	MAX1363_COMPATIBLE("maxim,max1038", max1038),
1522	MAX1363_COMPATIBLE("maxim,max1039", max1039),
1523	MAX1363_COMPATIBLE("maxim,max1136", max1136),
1524	MAX1363_COMPATIBLE("maxim,max1137", max1137),
1525	MAX1363_COMPATIBLE("maxim,max1138", max1138),
1526	MAX1363_COMPATIBLE("maxim,max1139", max1139),
1527	MAX1363_COMPATIBLE("maxim,max1236", max1236),
1528	MAX1363_COMPATIBLE("maxim,max1237", max1237),
1529	MAX1363_COMPATIBLE("maxim,max1238", max1238),
1530	MAX1363_COMPATIBLE("maxim,max1239", max1239),
1531	MAX1363_COMPATIBLE("maxim,max11600", max11600),
1532	MAX1363_COMPATIBLE("maxim,max11601", max11601),
1533	MAX1363_COMPATIBLE("maxim,max11602", max11602),
1534	MAX1363_COMPATIBLE("maxim,max11603", max11603),
1535	MAX1363_COMPATIBLE("maxim,max11604", max11604),
1536	MAX1363_COMPATIBLE("maxim,max11605", max11605),
1537	MAX1363_COMPATIBLE("maxim,max11606", max11606),
1538	MAX1363_COMPATIBLE("maxim,max11607", max11607),
1539	MAX1363_COMPATIBLE("maxim,max11608", max11608),
1540	MAX1363_COMPATIBLE("maxim,max11609", max11609),
1541	MAX1363_COMPATIBLE("maxim,max11610", max11610),
1542	MAX1363_COMPATIBLE("maxim,max11611", max11611),
1543	MAX1363_COMPATIBLE("maxim,max11612", max11612),
1544	MAX1363_COMPATIBLE("maxim,max11613", max11613),
1545	MAX1363_COMPATIBLE("maxim,max11614", max11614),
1546	MAX1363_COMPATIBLE("maxim,max11615", max11615),
1547	MAX1363_COMPATIBLE("maxim,max11616", max11616),
1548	MAX1363_COMPATIBLE("maxim,max11617", max11617),
1549	MAX1363_COMPATIBLE("maxim,max11644", max11644),
1550	MAX1363_COMPATIBLE("maxim,max11645", max11645),
1551	MAX1363_COMPATIBLE("maxim,max11646", max11646),
1552	MAX1363_COMPATIBLE("maxim,max11647", max11647),
1553	{ }
1554};
1555MODULE_DEVICE_TABLE(of, max1363_of_match);
1556
1557static int max1363_probe(struct i2c_client *client)
1558{
1559	const struct i2c_device_id *id = i2c_client_get_device_id(client);
1560	int ret;
1561	struct max1363_state *st;
1562	struct iio_dev *indio_dev;
1563
1564	indio_dev = devm_iio_device_alloc(&client->dev,
1565					  sizeof(struct max1363_state));
1566	if (!indio_dev)
1567		return -ENOMEM;
1568
1569	st = iio_priv(indio_dev);
1570
1571	mutex_init(&st->lock);
1572	ret = devm_regulator_get_enable(&client->dev, "vcc");
1573	if (ret)
1574		return ret;
1575
1576	st->chip_info = i2c_get_match_data(client);
1577	st->client = client;
1578
1579	ret = devm_regulator_get_enable_read_voltage(&client->dev, "vref");
1580	if (ret < 0 && ret != -ENODEV)
1581		return ret;
1582
1583
1584	st->vref_uv = ret == -ENODEV ? st->chip_info->int_vref_mv * 1000 : ret;
1585
1586	if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1587		st->send = i2c_master_send;
1588		st->recv = i2c_master_recv;
1589	} else if (i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE)
1590			&& st->chip_info->bits == 8) {
1591		st->send = max1363_smbus_send;
1592		st->recv = max1363_smbus_recv;
1593	} else {
1594		return -EOPNOTSUPP;
1595	}
1596
1597	ret = max1363_alloc_scan_masks(indio_dev);
1598	if (ret)
1599		return ret;
1600
1601	indio_dev->name = id->name;
1602	indio_dev->channels = st->chip_info->channels;
1603	indio_dev->num_channels = st->chip_info->num_channels;
1604	indio_dev->info = st->chip_info->info;
1605	indio_dev->modes = INDIO_DIRECT_MODE;
1606	ret = max1363_initial_setup(st);
1607	if (ret < 0)
1608		return ret;
1609
1610	ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL,
1611					      &max1363_trigger_handler, NULL);
1612	if (ret)
1613		return ret;
1614
1615	if (client->irq) {
1616		ret = devm_request_threaded_irq(&client->dev, st->client->irq,
1617					   NULL,
1618					   &max1363_event_handler,
1619					   IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1620					   "max1363_event",
1621					   indio_dev);
1622
1623		if (ret)
1624			return ret;
1625	}
1626
1627	return devm_iio_device_register(&client->dev, indio_dev);
1628}
1629
1630#define MAX1363_ID_TABLE(_name, cfg) {				\
1631	.name = _name,						\
1632	.driver_data = (kernel_ulong_t)&max1363_chip_info_tbl[cfg],	\
1633}
1634
1635static const struct i2c_device_id max1363_id[] = {
1636	MAX1363_ID_TABLE("max1361", max1361),
1637	MAX1363_ID_TABLE("max1362", max1362),
1638	MAX1363_ID_TABLE("max1363", max1363),
1639	MAX1363_ID_TABLE("max1364", max1364),
1640	MAX1363_ID_TABLE("max1036", max1036),
1641	MAX1363_ID_TABLE("max1037", max1037),
1642	MAX1363_ID_TABLE("max1038", max1038),
1643	MAX1363_ID_TABLE("max1039", max1039),
1644	MAX1363_ID_TABLE("max1136", max1136),
1645	MAX1363_ID_TABLE("max1137", max1137),
1646	MAX1363_ID_TABLE("max1138", max1138),
1647	MAX1363_ID_TABLE("max1139", max1139),
1648	MAX1363_ID_TABLE("max1236", max1236),
1649	MAX1363_ID_TABLE("max1237", max1237),
1650	MAX1363_ID_TABLE("max1238", max1238),
1651	MAX1363_ID_TABLE("max1239", max1239),
1652	MAX1363_ID_TABLE("max11600", max11600),
1653	MAX1363_ID_TABLE("max11601", max11601),
1654	MAX1363_ID_TABLE("max11602", max11602),
1655	MAX1363_ID_TABLE("max11603", max11603),
1656	MAX1363_ID_TABLE("max11604", max11604),
1657	MAX1363_ID_TABLE("max11605", max11605),
1658	MAX1363_ID_TABLE("max11606", max11606),
1659	MAX1363_ID_TABLE("max11607", max11607),
1660	MAX1363_ID_TABLE("max11608", max11608),
1661	MAX1363_ID_TABLE("max11609", max11609),
1662	MAX1363_ID_TABLE("max11610", max11610),
1663	MAX1363_ID_TABLE("max11611", max11611),
1664	MAX1363_ID_TABLE("max11612", max11612),
1665	MAX1363_ID_TABLE("max11613", max11613),
1666	MAX1363_ID_TABLE("max11614", max11614),
1667	MAX1363_ID_TABLE("max11615", max11615),
1668	MAX1363_ID_TABLE("max11616", max11616),
1669	MAX1363_ID_TABLE("max11617", max11617),
1670	MAX1363_ID_TABLE("max11644", max11644),
1671	MAX1363_ID_TABLE("max11645", max11645),
1672	MAX1363_ID_TABLE("max11646", max11646),
1673	MAX1363_ID_TABLE("max11647", max11647),
1674	{ }
1675};
1676
1677MODULE_DEVICE_TABLE(i2c, max1363_id);
1678
1679static struct i2c_driver max1363_driver = {
1680	.driver = {
1681		.name = "max1363",
1682		.of_match_table = max1363_of_match,
1683	},
1684	.probe = max1363_probe,
1685	.id_table = max1363_id,
1686};
1687module_i2c_driver(max1363_driver);
1688
1689MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
1690MODULE_DESCRIPTION("Maxim 1363 ADC");
1691MODULE_LICENSE("GPL v2");