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max1027.c
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linux-6.19.14/drivers/iio/adc/max1027.c
1// SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * iio/adc/max1027.c 4 * Copyright (C) 2014 Philippe Reynes 5 * 6 * based on linux/drivers/iio/ad7923.c 7 * Copyright 2011 Analog Devices Inc (from AD7923 Driver) 8 * Copyright 2012 CS Systemes d'Information 9 * 10 * max1027.c 11 * 12 * Partial support for max1027 and similar chips. 13 */ 14 15#include <linux/kernel.h> 16#include <linux/module.h> 17#include <linux/mod_devicetable.h> 18#include <linux/spi/spi.h> 19#include <linux/delay.h> 20 21#include <linux/iio/iio.h> 22#include <linux/iio/buffer.h> 23#include <linux/iio/trigger.h> 24#include <linux/iio/trigger_consumer.h> 25#include <linux/iio/triggered_buffer.h> 26 27#define MAX1027_CONV_REG BIT(7) 28#define MAX1027_SETUP_REG BIT(6) 29#define MAX1027_AVG_REG BIT(5) 30#define MAX1027_RST_REG BIT(4) 31 32/* conversion register */ 33#define MAX1027_TEMP BIT(0) 34#define MAX1027_SCAN_0_N (0x00 << 1) 35#define MAX1027_SCAN_N_M (0x01 << 1) 36#define MAX1027_SCAN_N (0x02 << 1) 37#define MAX1027_NOSCAN (0x03 << 1) 38#define MAX1027_CHAN(n) ((n) << 3) 39 40/* setup register */ 41#define MAX1027_UNIPOLAR 0x02 42#define MAX1027_BIPOLAR 0x03 43#define MAX1027_REF_MODE0 (0x00 << 2) 44#define MAX1027_REF_MODE1 (0x01 << 2) 45#define MAX1027_REF_MODE2 (0x02 << 2) 46#define MAX1027_REF_MODE3 (0x03 << 2) 47#define MAX1027_CKS_MODE0 (0x00 << 4) 48#define MAX1027_CKS_MODE1 (0x01 << 4) 49#define MAX1027_CKS_MODE2 (0x02 << 4) 50#define MAX1027_CKS_MODE3 (0x03 << 4) 51 52/* averaging register */ 53#define MAX1027_NSCAN_4 0x00 54#define MAX1027_NSCAN_8 0x01 55#define MAX1027_NSCAN_12 0x02 56#define MAX1027_NSCAN_16 0x03 57#define MAX1027_NAVG_4 (0x00 << 2) 58#define MAX1027_NAVG_8 (0x01 << 2) 59#define MAX1027_NAVG_16 (0x02 << 2) 60#define MAX1027_NAVG_32 (0x03 << 2) 61#define MAX1027_AVG_EN BIT(4) 62 63/* Device can achieve 300ksps so we assume a 3.33us conversion delay */ 64#define MAX1027_CONVERSION_UDELAY 4 65 66enum max1027_id { 67 max1027, 68 max1029, 69 max1031, 70 max1227, 71 max1229, 72 max1231, 73}; 74 75static const struct spi_device_id max1027_id[] = { 76 { "max1027", max1027 }, 77 { "max1029", max1029 }, 78 { "max1031", max1031 }, 79 { "max1227", max1227 }, 80 { "max1229", max1229 }, 81 { "max1231", max1231 }, 82 { } 83}; 84MODULE_DEVICE_TABLE(spi, max1027_id); 85 86static const struct of_device_id max1027_adc_dt_ids[] = { 87 { .compatible = "maxim,max1027" }, 88 { .compatible = "maxim,max1029" }, 89 { .compatible = "maxim,max1031" }, 90 { .compatible = "maxim,max1227" }, 91 { .compatible = "maxim,max1229" }, 92 { .compatible = "maxim,max1231" }, 93 { } 94}; 95MODULE_DEVICE_TABLE(of, max1027_adc_dt_ids); 96 97#define MAX1027_V_CHAN(index, depth) \ 98 { \ 99 .type = IIO_VOLTAGE, \ 100 .indexed = 1, \ 101 .channel = index, \ 102 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 103 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 104 .scan_index = index + 1, \ 105 .scan_type = { \ 106 .sign = 'u', \ 107 .realbits = depth, \ 108 .storagebits = 16, \ 109 .shift = (depth == 10) ? 2 : 0, \ 110 .endianness = IIO_BE, \ 111 }, \ 112 } 113 114#define MAX1027_T_CHAN \ 115 { \ 116 .type = IIO_TEMP, \ 117 .channel = 0, \ 118 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 119 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 120 .scan_index = 0, \ 121 .scan_type = { \ 122 .sign = 'u', \ 123 .realbits = 12, \ 124 .storagebits = 16, \ 125 .endianness = IIO_BE, \ 126 }, \ 127 } 128 129#define MAX1X27_CHANNELS(depth) \ 130 MAX1027_T_CHAN, \ 131 MAX1027_V_CHAN(0, depth), \ 132 MAX1027_V_CHAN(1, depth), \ 133 MAX1027_V_CHAN(2, depth), \ 134 MAX1027_V_CHAN(3, depth), \ 135 MAX1027_V_CHAN(4, depth), \ 136 MAX1027_V_CHAN(5, depth), \ 137 MAX1027_V_CHAN(6, depth), \ 138 MAX1027_V_CHAN(7, depth) 139 140#define MAX1X29_CHANNELS(depth) \ 141 MAX1X27_CHANNELS(depth), \ 142 MAX1027_V_CHAN(8, depth), \ 143 MAX1027_V_CHAN(9, depth), \ 144 MAX1027_V_CHAN(10, depth), \ 145 MAX1027_V_CHAN(11, depth) 146 147#define MAX1X31_CHANNELS(depth) \ 148 MAX1X29_CHANNELS(depth), \ 149 MAX1027_V_CHAN(12, depth), \ 150 MAX1027_V_CHAN(13, depth), \ 151 MAX1027_V_CHAN(14, depth), \ 152 MAX1027_V_CHAN(15, depth) 153 154static const struct iio_chan_spec max1027_channels[] = { 155 MAX1X27_CHANNELS(10), 156}; 157 158static const struct iio_chan_spec max1029_channels[] = { 159 MAX1X29_CHANNELS(10), 160}; 161 162static const struct iio_chan_spec max1031_channels[] = { 163 MAX1X31_CHANNELS(10), 164}; 165 166static const struct iio_chan_spec max1227_channels[] = { 167 MAX1X27_CHANNELS(12), 168}; 169 170static const struct iio_chan_spec max1229_channels[] = { 171 MAX1X29_CHANNELS(12), 172}; 173 174static const struct iio_chan_spec max1231_channels[] = { 175 MAX1X31_CHANNELS(12), 176}; 177 178/* 179 * These devices are able to scan from 0 to N, N being the highest voltage 180 * channel requested by the user. The temperature can be included or not, 181 * but cannot be retrieved alone. Based on the below 182 * ->available_scan_masks, the core will select the most appropriate 183 * ->active_scan_mask and the "minimum" number of channels will be 184 * scanned and pushed to the buffers. 185 * 186 * For example, if the user wants channels 1, 4 and 5, all channels from 187 * 0 to 5 will be scanned and pushed to the IIO buffers. The core will then 188 * filter out the unneeded samples based on the ->active_scan_mask that has 189 * been selected and only channels 1, 4 and 5 will be available to the user 190 * in the shared buffer. 191 */ 192#define MAX1X27_SCAN_MASK_TEMP BIT(0) 193 194#define MAX1X27_SCAN_MASKS(temp) \ 195 GENMASK(1, 1 - (temp)), GENMASK(2, 1 - (temp)), \ 196 GENMASK(3, 1 - (temp)), GENMASK(4, 1 - (temp)), \ 197 GENMASK(5, 1 - (temp)), GENMASK(6, 1 - (temp)), \ 198 GENMASK(7, 1 - (temp)), GENMASK(8, 1 - (temp)) 199 200#define MAX1X29_SCAN_MASKS(temp) \ 201 MAX1X27_SCAN_MASKS(temp), \ 202 GENMASK(9, 1 - (temp)), GENMASK(10, 1 - (temp)), \ 203 GENMASK(11, 1 - (temp)), GENMASK(12, 1 - (temp)) 204 205#define MAX1X31_SCAN_MASKS(temp) \ 206 MAX1X29_SCAN_MASKS(temp), \ 207 GENMASK(13, 1 - (temp)), GENMASK(14, 1 - (temp)), \ 208 GENMASK(15, 1 - (temp)), GENMASK(16, 1 - (temp)) 209 210static const unsigned long max1027_available_scan_masks[] = { 211 MAX1X27_SCAN_MASKS(0), 212 MAX1X27_SCAN_MASKS(1), 213 0x00000000, 214}; 215 216static const unsigned long max1029_available_scan_masks[] = { 217 MAX1X29_SCAN_MASKS(0), 218 MAX1X29_SCAN_MASKS(1), 219 0x00000000, 220}; 221 222static const unsigned long max1031_available_scan_masks[] = { 223 MAX1X31_SCAN_MASKS(0), 224 MAX1X31_SCAN_MASKS(1), 225 0x00000000, 226}; 227 228struct max1027_chip_info { 229 const struct iio_chan_spec *channels; 230 unsigned int num_channels; 231 const unsigned long *available_scan_masks; 232}; 233 234static const struct max1027_chip_info max1027_chip_info_tbl[] = { 235 [max1027] = { 236 .channels = max1027_channels, 237 .num_channels = ARRAY_SIZE(max1027_channels), 238 .available_scan_masks = max1027_available_scan_masks, 239 }, 240 [max1029] = { 241 .channels = max1029_channels, 242 .num_channels = ARRAY_SIZE(max1029_channels), 243 .available_scan_masks = max1029_available_scan_masks, 244 }, 245 [max1031] = { 246 .channels = max1031_channels, 247 .num_channels = ARRAY_SIZE(max1031_channels), 248 .available_scan_masks = max1031_available_scan_masks, 249 }, 250 [max1227] = { 251 .channels = max1227_channels, 252 .num_channels = ARRAY_SIZE(max1227_channels), 253 .available_scan_masks = max1027_available_scan_masks, 254 }, 255 [max1229] = { 256 .channels = max1229_channels, 257 .num_channels = ARRAY_SIZE(max1229_channels), 258 .available_scan_masks = max1029_available_scan_masks, 259 }, 260 [max1231] = { 261 .channels = max1231_channels, 262 .num_channels = ARRAY_SIZE(max1231_channels), 263 .available_scan_masks = max1031_available_scan_masks, 264 }, 265}; 266 267struct max1027_state { 268 const struct max1027_chip_info *info; 269 struct spi_device *spi; 270 struct iio_trigger *trig; 271 __be16 *buffer; 272 struct mutex lock; 273 struct completion complete; 274 275 u8 reg __aligned(IIO_DMA_MINALIGN); 276}; 277 278static int max1027_wait_eoc(struct iio_dev *indio_dev) 279{ 280 struct max1027_state *st = iio_priv(indio_dev); 281 unsigned int conversion_time = MAX1027_CONVERSION_UDELAY; 282 int ret; 283 284 if (st->spi->irq) { 285 ret = wait_for_completion_timeout(&st->complete, 286 msecs_to_jiffies(1000)); 287 reinit_completion(&st->complete); 288 if (!ret) 289 return -ETIMEDOUT; 290 } else { 291 if (indio_dev->active_scan_mask) 292 conversion_time *= hweight32(*indio_dev->active_scan_mask); 293 294 usleep_range(conversion_time, conversion_time * 2); 295 } 296 297 return 0; 298} 299 300/* Scan from chan 0 to the highest requested channel. Include temperature on demand. */ 301static int max1027_configure_chans_and_start(struct iio_dev *indio_dev) 302{ 303 struct max1027_state *st = iio_priv(indio_dev); 304 305 st->reg = MAX1027_CONV_REG | MAX1027_SCAN_0_N; 306 st->reg |= MAX1027_CHAN(fls(*indio_dev->active_scan_mask) - 2); 307 if (*indio_dev->active_scan_mask & MAX1X27_SCAN_MASK_TEMP) 308 st->reg |= MAX1027_TEMP; 309 310 return spi_write(st->spi, &st->reg, 1); 311} 312 313static int max1027_enable_trigger(struct iio_dev *indio_dev, bool enable) 314{ 315 struct max1027_state *st = iio_priv(indio_dev); 316 317 st->reg = MAX1027_SETUP_REG | MAX1027_REF_MODE2; 318 319 /* 320 * Start acquisition on: 321 * MODE0: external hardware trigger wired to the cnvst input pin 322 * MODE2: conversion register write 323 */ 324 if (enable) 325 st->reg |= MAX1027_CKS_MODE0; 326 else 327 st->reg |= MAX1027_CKS_MODE2; 328 329 return spi_write(st->spi, &st->reg, 1); 330} 331 332static int max1027_read_single_value(struct iio_dev *indio_dev, 333 struct iio_chan_spec const *chan, 334 int *val) 335{ 336 int ret; 337 struct max1027_state *st = iio_priv(indio_dev); 338 339 /* Configure conversion register with the requested chan */ 340 st->reg = MAX1027_CONV_REG | MAX1027_CHAN(chan->channel) | 341 MAX1027_NOSCAN; 342 if (chan->type == IIO_TEMP) 343 st->reg |= MAX1027_TEMP; 344 ret = spi_write(st->spi, &st->reg, 1); 345 if (ret < 0) { 346 dev_err(&indio_dev->dev, 347 "Failed to configure conversion register\n"); 348 return ret; 349 } 350 351 /* 352 * For an unknown reason, when we use the mode "10" (write 353 * conversion register), the interrupt doesn't occur every time. 354 * So we just wait the maximum conversion time and deliver the value. 355 */ 356 ret = max1027_wait_eoc(indio_dev); 357 if (ret) 358 return ret; 359 360 /* Read result */ 361 ret = spi_read(st->spi, st->buffer, (chan->type == IIO_TEMP) ? 4 : 2); 362 if (ret < 0) 363 return ret; 364 365 *val = be16_to_cpu(st->buffer[0]); 366 367 return IIO_VAL_INT; 368} 369 370static int max1027_read_raw(struct iio_dev *indio_dev, 371 struct iio_chan_spec const *chan, 372 int *val, int *val2, long mask) 373{ 374 int ret = 0; 375 struct max1027_state *st = iio_priv(indio_dev); 376 377 guard(mutex)(&st->lock); 378 379 switch (mask) { 380 case IIO_CHAN_INFO_RAW: 381 if (!iio_device_claim_direct(indio_dev)) 382 return -EBUSY; 383 384 ret = max1027_read_single_value(indio_dev, chan, val); 385 iio_device_release_direct(indio_dev); 386 return ret; 387 case IIO_CHAN_INFO_SCALE: 388 switch (chan->type) { 389 case IIO_TEMP: 390 *val = 1; 391 *val2 = 8; 392 return IIO_VAL_FRACTIONAL; 393 case IIO_VOLTAGE: 394 *val = 2500; 395 *val2 = chan->scan_type.realbits; 396 return IIO_VAL_FRACTIONAL_LOG2; 397 default: 398 return -EINVAL; 399 } 400 default: 401 return -EINVAL; 402 } 403} 404 405static int max1027_debugfs_reg_access(struct iio_dev *indio_dev, 406 unsigned int reg, unsigned int writeval, 407 unsigned int *readval) 408{ 409 struct max1027_state *st = iio_priv(indio_dev); 410 u8 *val = (u8 *)st->buffer; 411 412 if (readval) { 413 int ret = spi_read(st->spi, val, 2); 414 *readval = be16_to_cpu(st->buffer[0]); 415 return ret; 416 } 417 418 *val = (u8)writeval; 419 return spi_write(st->spi, val, 1); 420} 421 422static int max1027_set_cnvst_trigger_state(struct iio_trigger *trig, bool state) 423{ 424 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 425 int ret; 426 427 /* 428 * In order to disable the convst trigger, start acquisition on 429 * conversion register write, which basically disables triggering 430 * conversions upon cnvst changes and thus has the effect of disabling 431 * the external hardware trigger. 432 */ 433 ret = max1027_enable_trigger(indio_dev, state); 434 if (ret) 435 return ret; 436 437 if (state) { 438 ret = max1027_configure_chans_and_start(indio_dev); 439 if (ret) 440 return ret; 441 } 442 443 return 0; 444} 445 446static int max1027_read_scan(struct iio_dev *indio_dev) 447{ 448 struct max1027_state *st = iio_priv(indio_dev); 449 unsigned int scanned_chans; 450 int ret; 451 452 scanned_chans = fls(*indio_dev->active_scan_mask) - 1; 453 if (*indio_dev->active_scan_mask & MAX1X27_SCAN_MASK_TEMP) 454 scanned_chans++; 455 456 /* fill buffer with all channel */ 457 ret = spi_read(st->spi, st->buffer, scanned_chans * 2); 458 if (ret < 0) 459 return ret; 460 461 iio_push_to_buffers(indio_dev, st->buffer); 462 463 return 0; 464} 465 466static irqreturn_t max1027_handler(int irq, void *private) 467{ 468 struct iio_dev *indio_dev = private; 469 struct max1027_state *st = iio_priv(indio_dev); 470 471 /* 472 * If buffers are disabled (raw read) or when using external triggers, 473 * we just need to unlock the waiters which will then handle the data. 474 * 475 * When using the internal trigger, we must hand-off the choice of the 476 * handler to the core which will then lookup through the interrupt tree 477 * for the right handler registered with iio_triggered_buffer_setup() 478 * to execute, as this trigger might very well be used in conjunction 479 * with another device. The core will then call the relevant handler to 480 * perform the data processing step. 481 */ 482 if (!iio_buffer_enabled(indio_dev)) 483 complete(&st->complete); 484 else 485 iio_trigger_poll(indio_dev->trig); 486 487 return IRQ_HANDLED; 488} 489 490static irqreturn_t max1027_trigger_handler(int irq, void *private) 491{ 492 struct iio_poll_func *pf = private; 493 struct iio_dev *indio_dev = pf->indio_dev; 494 int ret; 495 496 if (!iio_trigger_using_own(indio_dev)) { 497 ret = max1027_configure_chans_and_start(indio_dev); 498 if (ret) 499 goto out; 500 501 /* This is a threaded handler, it is fine to wait for an IRQ */ 502 ret = max1027_wait_eoc(indio_dev); 503 if (ret) 504 goto out; 505 } 506 507 ret = max1027_read_scan(indio_dev); 508out: 509 if (ret) 510 dev_err(&indio_dev->dev, 511 "Cannot read scanned values (%d)\n", ret); 512 513 iio_trigger_notify_done(indio_dev->trig); 514 515 return IRQ_HANDLED; 516} 517 518static const struct iio_trigger_ops max1027_trigger_ops = { 519 .validate_device = &iio_trigger_validate_own_device, 520 .set_trigger_state = &max1027_set_cnvst_trigger_state, 521}; 522 523static const struct iio_info max1027_info = { 524 .read_raw = &max1027_read_raw, 525 .debugfs_reg_access = &max1027_debugfs_reg_access, 526}; 527 528static int max1027_probe(struct spi_device *spi) 529{ 530 int ret; 531 struct iio_dev *indio_dev; 532 struct max1027_state *st; 533 534 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 535 if (!indio_dev) { 536 pr_err("Can't allocate iio device\n"); 537 return -ENOMEM; 538 } 539 540 st = iio_priv(indio_dev); 541 st->spi = spi; 542 st->info = &max1027_chip_info_tbl[spi_get_device_id(spi)->driver_data]; 543 544 mutex_init(&st->lock); 545 init_completion(&st->complete); 546 547 indio_dev->name = spi_get_device_id(spi)->name; 548 indio_dev->info = &max1027_info; 549 indio_dev->modes = INDIO_DIRECT_MODE; 550 indio_dev->channels = st->info->channels; 551 indio_dev->num_channels = st->info->num_channels; 552 indio_dev->available_scan_masks = st->info->available_scan_masks; 553 554 st->buffer = devm_kmalloc_array(&indio_dev->dev, 555 indio_dev->num_channels, 2, 556 GFP_KERNEL); 557 if (!st->buffer) 558 return -ENOMEM; 559 560 /* Enable triggered buffers */ 561 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, 562 &iio_pollfunc_store_time, 563 &max1027_trigger_handler, 564 NULL); 565 if (ret < 0) { 566 dev_err(&indio_dev->dev, "Failed to setup buffer\n"); 567 return ret; 568 } 569 570 /* If there is an EOC interrupt, register the cnvst hardware trigger */ 571 if (spi->irq) { 572 st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-trigger", 573 indio_dev->name); 574 if (!st->trig) { 575 ret = -ENOMEM; 576 dev_err(&indio_dev->dev, 577 "Failed to allocate iio trigger\n"); 578 return ret; 579 } 580 581 st->trig->ops = &max1027_trigger_ops; 582 iio_trigger_set_drvdata(st->trig, indio_dev); 583 ret = devm_iio_trigger_register(&indio_dev->dev, 584 st->trig); 585 if (ret < 0) { 586 dev_err(&indio_dev->dev, 587 "Failed to register iio trigger\n"); 588 return ret; 589 } 590 591 ret = devm_request_irq(&spi->dev, spi->irq, max1027_handler, 592 IRQF_TRIGGER_FALLING, 593 spi->dev.driver->name, indio_dev); 594 if (ret < 0) { 595 dev_err(&indio_dev->dev, "Failed to allocate IRQ.\n"); 596 return ret; 597 } 598 } 599 600 /* Internal reset */ 601 st->reg = MAX1027_RST_REG; 602 ret = spi_write(st->spi, &st->reg, 1); 603 if (ret < 0) { 604 dev_err(&indio_dev->dev, "Failed to reset the ADC\n"); 605 return ret; 606 } 607 608 /* Disable averaging */ 609 st->reg = MAX1027_AVG_REG; 610 ret = spi_write(st->spi, &st->reg, 1); 611 if (ret < 0) { 612 dev_err(&indio_dev->dev, "Failed to configure averaging register\n"); 613 return ret; 614 } 615 616 /* Assume conversion on register write for now */ 617 ret = max1027_enable_trigger(indio_dev, false); 618 if (ret) 619 return ret; 620 621 return devm_iio_device_register(&spi->dev, indio_dev); 622} 623 624static struct spi_driver max1027_driver = { 625 .driver = { 626 .name = "max1027", 627 .of_match_table = max1027_adc_dt_ids, 628 }, 629 .probe = max1027_probe, 630 .id_table = max1027_id, 631}; 632module_spi_driver(max1027_driver); 633 634MODULE_AUTHOR("Philippe Reynes <tremyfr@yahoo.fr>"); 635MODULE_DESCRIPTION("MAX1X27/MAX1X29/MAX1X31 ADC"); 636MODULE_LICENSE("GPL v2");
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