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exynos_adc.c

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linux-6.19.14/drivers/iio/adc/exynos_adc.c C 
  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 *  exynos_adc.c - Support for ADC in EXYNOS SoCs
  4 *
  5 *  8 ~ 10 channel, 10/12-bit ADC
  6 *
  7 *  Copyright (C) 2013 Naveen Krishna Chatradhi <ch.naveen@samsung.com>
  8 */
  9
 10#include <linux/compiler.h>
 11#include <linux/module.h>
 12#include <linux/platform_device.h>
 13#include <linux/interrupt.h>
 14#include <linux/delay.h>
 15#include <linux/errno.h>
 16#include <linux/kernel.h>
 17#include <linux/slab.h>
 18#include <linux/io.h>
 19#include <linux/clk.h>
 20#include <linux/completion.h>
 21#include <linux/of.h>
 22#include <linux/regulator/consumer.h>
 23#include <linux/of_platform.h>
 24#include <linux/err.h>
 25
 26#include <linux/iio/iio.h>
 27#include <linux/iio/machine.h>
 28#include <linux/iio/driver.h>
 29#include <linux/mfd/syscon.h>
 30#include <linux/regmap.h>
 31
 32/* S3C/EXYNOS4412/5250 ADC_V1 registers definitions */
 33#define ADC_V1_CON(x)		((x) + 0x00)
 34#define ADC_V1_DLY(x)		((x) + 0x08)
 35#define ADC_V1_DATX(x)		((x) + 0x0C)
 36#define ADC_V1_DATY(x)		((x) + 0x10)
 37#define ADC_V1_UPDN(x)		((x) + 0x14)
 38#define ADC_V1_INTCLR(x)	((x) + 0x18)
 39#define ADC_V1_MUX(x)		((x) + 0x1c)
 40
 41/* Future ADC_V2 registers definitions */
 42#define ADC_V2_CON1(x)		((x) + 0x00)
 43#define ADC_V2_CON2(x)		((x) + 0x04)
 44#define ADC_V2_STAT(x)		((x) + 0x08)
 45#define ADC_V2_INT_EN(x)	((x) + 0x10)
 46#define ADC_V2_INT_ST(x)	((x) + 0x14)
 47#define ADC_V2_VER(x)		((x) + 0x20)
 48
 49/* Bit definitions for ADC_V1 */
 50#define ADC_V1_CON_RES		(1u << 16)
 51#define ADC_V1_CON_PRSCEN	(1u << 14)
 52#define ADC_V1_CON_PRSCLV(x)	(((x) & 0xFF) << 6)
 53#define ADC_V1_CON_STANDBY	(1u << 2)
 54
 55/* Bit definitions for S3C2410 / S3C6410 ADC */
 56#define ADC_S3C2410_CON_SELMUX(x) (((x) & 7) << 3)
 57
 58/* ADCTSC Register Bits */
 59#define ADC_S3C2443_TSC_UD_SEN		(1u << 8)
 60#define ADC_S3C2410_TSC_YM_SEN		(1u << 7)
 61#define ADC_S3C2410_TSC_YP_SEN		(1u << 6)
 62#define ADC_S3C2410_TSC_XM_SEN		(1u << 5)
 63#define ADC_S3C2410_TSC_XP_SEN		(1u << 4)
 64#define ADC_S3C2410_TSC_XY_PST(x)	(((x) & 0x3) << 0)
 65
 66#define ADC_TSC_WAIT4INT (ADC_S3C2410_TSC_YM_SEN | \
 67			 ADC_S3C2410_TSC_YP_SEN | \
 68			 ADC_S3C2410_TSC_XP_SEN | \
 69			 ADC_S3C2410_TSC_XY_PST(3))
 70
 71/* Bit definitions for ADC_V2 */
 72#define ADC_V2_CON1_SOFT_RESET	(1u << 2)
 73
 74#define ADC_V2_CON2_OSEL	(1u << 10)
 75#define ADC_V2_CON2_ESEL	(1u << 9)
 76#define ADC_V2_CON2_HIGHF	(1u << 8)
 77#define ADC_V2_CON2_C_TIME(x)	(((x) & 7) << 4)
 78#define ADC_V2_CON2_ACH_SEL(x)	(((x) & 0xF) << 0)
 79#define ADC_V2_CON2_ACH_MASK	0xF
 80
 81#define MAX_ADC_V2_CHANNELS		10
 82#define MAX_ADC_V1_CHANNELS		8
 83#define MAX_EXYNOS3250_ADC_CHANNELS	2
 84#define MAX_EXYNOS4212_ADC_CHANNELS	4
 85#define MAX_S5PV210_ADC_CHANNELS	10
 86
 87/* Bit definitions common for ADC_V1 and ADC_V2 */
 88#define ADC_CON_EN_START	(1u << 0)
 89#define ADC_CON_EN_START_MASK	(0x3 << 0)
 90#define ADC_DATX_PRESSED	(1u << 15)
 91#define ADC_DATX_MASK		0xFFF
 92#define ADC_DATY_MASK		0xFFF
 93
 94#define EXYNOS_ADC_TIMEOUT	(msecs_to_jiffies(100))
 95
 96#define EXYNOS_ADCV1_PHY_OFFSET	0x0718
 97#define EXYNOS_ADCV2_PHY_OFFSET	0x0720
 98
 99struct exynos_adc {
100	struct exynos_adc_data	*data;
101	struct device		*dev;
102	void __iomem		*regs;
103	struct regmap		*pmu_map;
104	struct clk		*clk;
105	struct clk		*sclk;
106	unsigned int		irq;
107	struct regulator	*vdd;
108
109	struct completion	completion;
110
111	u32			value;
112	unsigned int            version;
113
114	/*
115	 * Lock to protect from potential concurrent access to the
116	 * completion callback during a manual conversion. For this driver
117	 * a wait-callback is used to wait for the conversion result,
118	 * so in the meantime no other read request (or conversion start)
119	 * must be performed, otherwise it would interfere with the
120	 * current conversion result.
121	 */
122	struct mutex		lock;
123};
124
125struct exynos_adc_data {
126	int num_channels;
127	bool needs_sclk;
128	bool needs_adc_phy;
129	int phy_offset;
130	u32 mask;
131
132	void (*init_hw)(struct exynos_adc *info);
133	void (*exit_hw)(struct exynos_adc *info);
134	void (*clear_irq)(struct exynos_adc *info);
135	void (*start_conv)(struct exynos_adc *info, unsigned long addr);
136};
137
138static void exynos_adc_unprepare_clk(struct exynos_adc *info)
139{
140	if (info->data->needs_sclk)
141		clk_unprepare(info->sclk);
142	clk_unprepare(info->clk);
143}
144
145static int exynos_adc_prepare_clk(struct exynos_adc *info)
146{
147	int ret;
148
149	ret = clk_prepare(info->clk);
150	if (ret) {
151		dev_err(info->dev, "failed preparing adc clock: %d\n", ret);
152		return ret;
153	}
154
155	if (info->data->needs_sclk) {
156		ret = clk_prepare(info->sclk);
157		if (ret) {
158			clk_unprepare(info->clk);
159			dev_err(info->dev,
160				"failed preparing sclk_adc clock: %d\n", ret);
161			return ret;
162		}
163	}
164
165	return 0;
166}
167
168static void exynos_adc_disable_clk(struct exynos_adc *info)
169{
170	if (info->data->needs_sclk)
171		clk_disable(info->sclk);
172	clk_disable(info->clk);
173}
174
175static int exynos_adc_enable_clk(struct exynos_adc *info)
176{
177	int ret;
178
179	ret = clk_enable(info->clk);
180	if (ret) {
181		dev_err(info->dev, "failed enabling adc clock: %d\n", ret);
182		return ret;
183	}
184
185	if (info->data->needs_sclk) {
186		ret = clk_enable(info->sclk);
187		if (ret) {
188			clk_disable(info->clk);
189			dev_err(info->dev,
190				"failed enabling sclk_adc clock: %d\n", ret);
191			return ret;
192		}
193	}
194
195	return 0;
196}
197
198static void exynos_adc_v1_init_hw(struct exynos_adc *info)
199{
200	u32 con1;
201
202	if (info->data->needs_adc_phy)
203		regmap_write(info->pmu_map, info->data->phy_offset, 1);
204
205	/* set default prescaler values and Enable prescaler */
206	con1 =  ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
207
208	/* Enable 12-bit ADC resolution */
209	con1 |= ADC_V1_CON_RES;
210	writel(con1, ADC_V1_CON(info->regs));
211
212	/* set touchscreen delay */
213	writel(10000, ADC_V1_DLY(info->regs));
214}
215
216static void exynos_adc_v1_exit_hw(struct exynos_adc *info)
217{
218	u32 con;
219
220	if (info->data->needs_adc_phy)
221		regmap_write(info->pmu_map, info->data->phy_offset, 0);
222
223	con = readl(ADC_V1_CON(info->regs));
224	con |= ADC_V1_CON_STANDBY;
225	writel(con, ADC_V1_CON(info->regs));
226}
227
228static void exynos_adc_v1_clear_irq(struct exynos_adc *info)
229{
230	writel(1, ADC_V1_INTCLR(info->regs));
231}
232
233static void exynos_adc_v1_start_conv(struct exynos_adc *info,
234				     unsigned long addr)
235{
236	u32 con1;
237
238	writel(addr, ADC_V1_MUX(info->regs));
239
240	con1 = readl(ADC_V1_CON(info->regs));
241	writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
242}
243
244/* Exynos4212 and 4412 is like ADCv1 but with four channels only */
245static const struct exynos_adc_data exynos4212_adc_data = {
246	.num_channels	= MAX_EXYNOS4212_ADC_CHANNELS,
247	.mask		= ADC_DATX_MASK,	/* 12 bit ADC resolution */
248	.needs_adc_phy	= true,
249	.phy_offset	= EXYNOS_ADCV1_PHY_OFFSET,
250
251	.init_hw	= exynos_adc_v1_init_hw,
252	.exit_hw	= exynos_adc_v1_exit_hw,
253	.clear_irq	= exynos_adc_v1_clear_irq,
254	.start_conv	= exynos_adc_v1_start_conv,
255};
256
257static const struct exynos_adc_data exynos_adc_v1_data = {
258	.num_channels	= MAX_ADC_V1_CHANNELS,
259	.mask		= ADC_DATX_MASK,	/* 12 bit ADC resolution */
260	.needs_adc_phy	= true,
261	.phy_offset	= EXYNOS_ADCV1_PHY_OFFSET,
262
263	.init_hw	= exynos_adc_v1_init_hw,
264	.exit_hw	= exynos_adc_v1_exit_hw,
265	.clear_irq	= exynos_adc_v1_clear_irq,
266	.start_conv	= exynos_adc_v1_start_conv,
267};
268
269static const struct exynos_adc_data exynos_adc_s5pv210_data = {
270	.num_channels	= MAX_S5PV210_ADC_CHANNELS,
271	.mask		= ADC_DATX_MASK,	/* 12 bit ADC resolution */
272
273	.init_hw	= exynos_adc_v1_init_hw,
274	.exit_hw	= exynos_adc_v1_exit_hw,
275	.clear_irq	= exynos_adc_v1_clear_irq,
276	.start_conv	= exynos_adc_v1_start_conv,
277};
278
279static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info,
280					  unsigned long addr)
281{
282	u32 con1;
283
284	con1 = readl(ADC_V1_CON(info->regs));
285	con1 &= ~ADC_S3C2410_CON_SELMUX(0x7);
286	con1 |= ADC_S3C2410_CON_SELMUX(addr);
287	writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
288}
289
290static struct exynos_adc_data const exynos_adc_s3c64xx_data = {
291	.num_channels	= MAX_ADC_V1_CHANNELS,
292	.mask		= ADC_DATX_MASK,	/* 12 bit ADC resolution */
293
294	.init_hw	= exynos_adc_v1_init_hw,
295	.exit_hw	= exynos_adc_v1_exit_hw,
296	.clear_irq	= exynos_adc_v1_clear_irq,
297	.start_conv	= exynos_adc_s3c64xx_start_conv,
298};
299
300static void exynos_adc_v2_init_hw(struct exynos_adc *info)
301{
302	u32 con1, con2;
303
304	if (info->data->needs_adc_phy)
305		regmap_write(info->pmu_map, info->data->phy_offset, 1);
306
307	con1 = ADC_V2_CON1_SOFT_RESET;
308	writel(con1, ADC_V2_CON1(info->regs));
309
310	con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
311		ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
312	writel(con2, ADC_V2_CON2(info->regs));
313
314	/* Enable interrupts */
315	writel(1, ADC_V2_INT_EN(info->regs));
316}
317
318static void exynos_adc_v2_exit_hw(struct exynos_adc *info)
319{
320	u32 con;
321
322	if (info->data->needs_adc_phy)
323		regmap_write(info->pmu_map, info->data->phy_offset, 0);
324
325	con = readl(ADC_V2_CON1(info->regs));
326	con &= ~ADC_CON_EN_START;
327	writel(con, ADC_V2_CON1(info->regs));
328}
329
330static void exynos_adc_v2_clear_irq(struct exynos_adc *info)
331{
332	writel(1, ADC_V2_INT_ST(info->regs));
333}
334
335static void exynos_adc_v2_start_conv(struct exynos_adc *info,
336				     unsigned long addr)
337{
338	u32 con1, con2;
339
340	con2 = readl(ADC_V2_CON2(info->regs));
341	con2 &= ~ADC_V2_CON2_ACH_MASK;
342	con2 |= ADC_V2_CON2_ACH_SEL(addr);
343	writel(con2, ADC_V2_CON2(info->regs));
344
345	con1 = readl(ADC_V2_CON1(info->regs));
346	writel(con1 | ADC_CON_EN_START, ADC_V2_CON1(info->regs));
347}
348
349static const struct exynos_adc_data exynos_adc_v2_data = {
350	.num_channels	= MAX_ADC_V2_CHANNELS,
351	.mask		= ADC_DATX_MASK, /* 12 bit ADC resolution */
352	.needs_adc_phy	= true,
353	.phy_offset	= EXYNOS_ADCV2_PHY_OFFSET,
354
355	.init_hw	= exynos_adc_v2_init_hw,
356	.exit_hw	= exynos_adc_v2_exit_hw,
357	.clear_irq	= exynos_adc_v2_clear_irq,
358	.start_conv	= exynos_adc_v2_start_conv,
359};
360
361static const struct exynos_adc_data exynos3250_adc_data = {
362	.num_channels	= MAX_EXYNOS3250_ADC_CHANNELS,
363	.mask		= ADC_DATX_MASK, /* 12 bit ADC resolution */
364	.needs_sclk	= true,
365	.needs_adc_phy	= true,
366	.phy_offset	= EXYNOS_ADCV1_PHY_OFFSET,
367
368	.init_hw	= exynos_adc_v2_init_hw,
369	.exit_hw	= exynos_adc_v2_exit_hw,
370	.clear_irq	= exynos_adc_v2_clear_irq,
371	.start_conv	= exynos_adc_v2_start_conv,
372};
373
374static void exynos_adc_exynos7_init_hw(struct exynos_adc *info)
375{
376	u32 con1, con2;
377
378	con1 = ADC_V2_CON1_SOFT_RESET;
379	writel(con1, ADC_V2_CON1(info->regs));
380
381	con2 = readl(ADC_V2_CON2(info->regs));
382	con2 &= ~ADC_V2_CON2_C_TIME(7);
383	con2 |= ADC_V2_CON2_C_TIME(0);
384	writel(con2, ADC_V2_CON2(info->regs));
385
386	/* Enable interrupts */
387	writel(1, ADC_V2_INT_EN(info->regs));
388}
389
390static const struct exynos_adc_data exynos7_adc_data = {
391	.num_channels	= MAX_ADC_V1_CHANNELS,
392	.mask		= ADC_DATX_MASK, /* 12 bit ADC resolution */
393
394	.init_hw	= exynos_adc_exynos7_init_hw,
395	.exit_hw	= exynos_adc_v2_exit_hw,
396	.clear_irq	= exynos_adc_v2_clear_irq,
397	.start_conv	= exynos_adc_v2_start_conv,
398};
399
400static const struct of_device_id exynos_adc_match[] = {
401	{
402		.compatible = "samsung,s3c6410-adc",
403		.data = &exynos_adc_s3c64xx_data,
404	}, {
405		.compatible = "samsung,s5pv210-adc",
406		.data = &exynos_adc_s5pv210_data,
407	}, {
408		.compatible = "samsung,exynos4212-adc",
409		.data = &exynos4212_adc_data,
410	}, {
411		.compatible = "samsung,exynos-adc-v1",
412		.data = &exynos_adc_v1_data,
413	}, {
414		.compatible = "samsung,exynos-adc-v2",
415		.data = &exynos_adc_v2_data,
416	}, {
417		.compatible = "samsung,exynos3250-adc",
418		.data = &exynos3250_adc_data,
419	}, {
420		.compatible = "samsung,exynos7-adc",
421		.data = &exynos7_adc_data,
422	},
423	{ }
424};
425MODULE_DEVICE_TABLE(of, exynos_adc_match);
426
427static struct exynos_adc_data *exynos_adc_get_data(struct platform_device *pdev)
428{
429	const struct of_device_id *match;
430
431	match = of_match_node(exynos_adc_match, pdev->dev.of_node);
432	return (struct exynos_adc_data *)match->data;
433}
434
435static int exynos_read_raw(struct iio_dev *indio_dev,
436				struct iio_chan_spec const *chan,
437				int *val,
438				int *val2,
439				long mask)
440{
441	struct exynos_adc *info = iio_priv(indio_dev);
442	unsigned long time_left;
443	int ret;
444
445	if (mask == IIO_CHAN_INFO_SCALE) {
446		ret = regulator_get_voltage(info->vdd);
447		if (ret < 0)
448			return ret;
449
450		/* Regulator voltage is in uV, but need mV */
451		*val = ret / 1000;
452		*val2 = info->data->mask;
453
454		return IIO_VAL_FRACTIONAL;
455	} else if (mask != IIO_CHAN_INFO_RAW) {
456		return -EINVAL;
457	}
458
459	mutex_lock(&info->lock);
460	reinit_completion(&info->completion);
461
462	/* Select the channel to be used and Trigger conversion */
463	if (info->data->start_conv)
464		info->data->start_conv(info, chan->address);
465
466	time_left = wait_for_completion_timeout(&info->completion,
467						EXYNOS_ADC_TIMEOUT);
468	if (time_left == 0) {
469		dev_warn(&indio_dev->dev, "Conversion timed out! Resetting\n");
470		if (info->data->init_hw)
471			info->data->init_hw(info);
472		ret = -ETIMEDOUT;
473	} else {
474		*val = info->value;
475		*val2 = 0;
476		ret = IIO_VAL_INT;
477	}
478
479	mutex_unlock(&info->lock);
480
481	return ret;
482}
483
484static irqreturn_t exynos_adc_isr(int irq, void *dev_id)
485{
486	struct exynos_adc *info = dev_id;
487	u32 mask = info->data->mask;
488
489	/* Read value */
490	info->value = readl(ADC_V1_DATX(info->regs)) & mask;
491
492	/* clear irq */
493	if (info->data->clear_irq)
494		info->data->clear_irq(info);
495
496	complete(&info->completion);
497
498	return IRQ_HANDLED;
499}
500
501static int exynos_adc_reg_access(struct iio_dev *indio_dev,
502			      unsigned reg, unsigned writeval,
503			      unsigned *readval)
504{
505	struct exynos_adc *info = iio_priv(indio_dev);
506
507	if (readval == NULL)
508		return -EINVAL;
509
510	*readval = readl(info->regs + reg);
511
512	return 0;
513}
514
515static const struct iio_info exynos_adc_iio_info = {
516	.read_raw = &exynos_read_raw,
517	.debugfs_reg_access = &exynos_adc_reg_access,
518};
519
520#define ADC_CHANNEL(_index, _id) {			\
521	.type = IIO_VOLTAGE,				\
522	.indexed = 1,					\
523	.channel = _index,				\
524	.address = _index,				\
525	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),	\
526	.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE),	\
527	.datasheet_name = _id,				\
528}
529
530static const struct iio_chan_spec exynos_adc_iio_channels[] = {
531	ADC_CHANNEL(0, "adc0"),
532	ADC_CHANNEL(1, "adc1"),
533	ADC_CHANNEL(2, "adc2"),
534	ADC_CHANNEL(3, "adc3"),
535	ADC_CHANNEL(4, "adc4"),
536	ADC_CHANNEL(5, "adc5"),
537	ADC_CHANNEL(6, "adc6"),
538	ADC_CHANNEL(7, "adc7"),
539	ADC_CHANNEL(8, "adc8"),
540	ADC_CHANNEL(9, "adc9"),
541};
542
543static int exynos_adc_probe(struct platform_device *pdev)
544{
545	struct exynos_adc *info = NULL;
546	struct device_node *np = pdev->dev.of_node;
547	struct iio_dev *indio_dev = NULL;
548	int ret;
549	int irq;
550
551	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct exynos_adc));
552	if (!indio_dev)
553		return -ENOMEM;
554
555	info = iio_priv(indio_dev);
556
557	info->data = exynos_adc_get_data(pdev);
558	if (!info->data) {
559		dev_err(&pdev->dev, "failed getting exynos_adc_data\n");
560		return -EINVAL;
561	}
562
563	info->regs = devm_platform_ioremap_resource(pdev, 0);
564	if (IS_ERR(info->regs))
565		return PTR_ERR(info->regs);
566
567
568	if (info->data->needs_adc_phy) {
569		info->pmu_map = syscon_regmap_lookup_by_phandle(
570					pdev->dev.of_node,
571					"samsung,syscon-phandle");
572		if (IS_ERR(info->pmu_map)) {
573			dev_err(&pdev->dev, "syscon regmap lookup failed.\n");
574			return PTR_ERR(info->pmu_map);
575		}
576	}
577
578	irq = platform_get_irq(pdev, 0);
579	if (irq < 0)
580		return irq;
581	info->irq = irq;
582	info->dev = &pdev->dev;
583
584	init_completion(&info->completion);
585
586	info->clk = devm_clk_get(&pdev->dev, "adc");
587	if (IS_ERR(info->clk)) {
588		dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
589							PTR_ERR(info->clk));
590		return PTR_ERR(info->clk);
591	}
592
593	if (info->data->needs_sclk) {
594		info->sclk = devm_clk_get(&pdev->dev, "sclk");
595		if (IS_ERR(info->sclk)) {
596			dev_err(&pdev->dev,
597				"failed getting sclk clock, err = %ld\n",
598				PTR_ERR(info->sclk));
599			return PTR_ERR(info->sclk);
600		}
601	}
602
603	info->vdd = devm_regulator_get(&pdev->dev, "vdd");
604	if (IS_ERR(info->vdd))
605		return dev_err_probe(&pdev->dev, PTR_ERR(info->vdd),
606				     "failed getting regulator");
607
608	ret = regulator_enable(info->vdd);
609	if (ret)
610		return ret;
611
612	ret = exynos_adc_prepare_clk(info);
613	if (ret)
614		goto err_disable_reg;
615
616	ret = exynos_adc_enable_clk(info);
617	if (ret)
618		goto err_unprepare_clk;
619
620	platform_set_drvdata(pdev, indio_dev);
621
622	indio_dev->name = dev_name(&pdev->dev);
623	indio_dev->info = &exynos_adc_iio_info;
624	indio_dev->modes = INDIO_DIRECT_MODE;
625	indio_dev->channels = exynos_adc_iio_channels;
626	indio_dev->num_channels = info->data->num_channels;
627
628	mutex_init(&info->lock);
629
630	ret = request_irq(info->irq, exynos_adc_isr,
631					0, dev_name(&pdev->dev), info);
632	if (ret < 0) {
633		dev_err(&pdev->dev, "failed requesting irq, irq = %d\n",
634							info->irq);
635		goto err_disable_clk;
636	}
637
638	ret = iio_device_register(indio_dev);
639	if (ret)
640		goto err_irq;
641
642	if (info->data->init_hw)
643		info->data->init_hw(info);
644
645	ret = of_platform_populate(np, exynos_adc_match, NULL, &indio_dev->dev);
646	if (ret < 0) {
647		dev_err(&pdev->dev, "failed adding child nodes\n");
648		goto err_of_populate;
649	}
650
651	return 0;
652
653err_of_populate:
654	of_platform_depopulate(&indio_dev->dev);
655	iio_device_unregister(indio_dev);
656err_irq:
657	free_irq(info->irq, info);
658err_disable_clk:
659	if (info->data->exit_hw)
660		info->data->exit_hw(info);
661	exynos_adc_disable_clk(info);
662err_unprepare_clk:
663	exynos_adc_unprepare_clk(info);
664err_disable_reg:
665	regulator_disable(info->vdd);
666	return ret;
667}
668
669static void exynos_adc_remove(struct platform_device *pdev)
670{
671	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
672	struct exynos_adc *info = iio_priv(indio_dev);
673
674	of_platform_depopulate(&indio_dev->dev);
675	iio_device_unregister(indio_dev);
676	free_irq(info->irq, info);
677	if (info->data->exit_hw)
678		info->data->exit_hw(info);
679	exynos_adc_disable_clk(info);
680	exynos_adc_unprepare_clk(info);
681	regulator_disable(info->vdd);
682}
683
684static int exynos_adc_suspend(struct device *dev)
685{
686	struct iio_dev *indio_dev = dev_get_drvdata(dev);
687	struct exynos_adc *info = iio_priv(indio_dev);
688
689	if (info->data->exit_hw)
690		info->data->exit_hw(info);
691	exynos_adc_disable_clk(info);
692	regulator_disable(info->vdd);
693
694	return 0;
695}
696
697static int exynos_adc_resume(struct device *dev)
698{
699	struct iio_dev *indio_dev = dev_get_drvdata(dev);
700	struct exynos_adc *info = iio_priv(indio_dev);
701	int ret;
702
703	ret = regulator_enable(info->vdd);
704	if (ret)
705		return ret;
706
707	ret = exynos_adc_enable_clk(info);
708	if (ret)
709		return ret;
710
711	if (info->data->init_hw)
712		info->data->init_hw(info);
713
714	return 0;
715}
716
717static DEFINE_SIMPLE_DEV_PM_OPS(exynos_adc_pm_ops, exynos_adc_suspend,
718				exynos_adc_resume);
719
720static struct platform_driver exynos_adc_driver = {
721	.probe		= exynos_adc_probe,
722	.remove		= exynos_adc_remove,
723	.driver		= {
724		.name	= "exynos-adc",
725		.of_match_table = exynos_adc_match,
726		.pm	= pm_sleep_ptr(&exynos_adc_pm_ops),
727	},
728};
729
730module_platform_driver(exynos_adc_driver);
731
732MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>");
733MODULE_DESCRIPTION("Samsung EXYNOS5 ADC driver");
734MODULE_LICENSE("GPL v2");
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