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axp20x_adc.c

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linux-6.19.14/drivers/iio/adc/axp20x_adc.c C 
   1// SPDX-License-Identifier: GPL-2.0-only
   2/* ADC driver for AXP20X and AXP22X PMICs
   3 *
   4 * Copyright (c) 2016 Free Electrons NextThing Co.
   5 *	Quentin Schulz <quentin.schulz@free-electrons.com>
   6 */
   7
   8#include <linux/unaligned.h>
   9#include <linux/bitfield.h>
  10#include <linux/completion.h>
  11#include <linux/interrupt.h>
  12#include <linux/io.h>
  13#include <linux/module.h>
  14#include <linux/mod_devicetable.h>
  15#include <linux/platform_device.h>
  16#include <linux/pm_runtime.h>
  17#include <linux/property.h>
  18#include <linux/regmap.h>
  19#include <linux/thermal.h>
  20
  21#include <linux/iio/iio.h>
  22#include <linux/iio/driver.h>
  23#include <linux/iio/machine.h>
  24#include <linux/mfd/axp20x.h>
  25
  26#define AXP192_ADC_EN1_MASK			GENMASK(7, 0)
  27#define AXP192_ADC_EN2_MASK			(GENMASK(3, 0) | BIT(7))
  28
  29#define AXP20X_ADC_EN1_MASK			GENMASK(7, 0)
  30#define AXP20X_ADC_EN2_MASK			(GENMASK(3, 2) | BIT(7))
  31
  32#define AXP22X_ADC_EN1_MASK			(GENMASK(7, 5) | BIT(0))
  33
  34#define AXP717_ADC_EN1_MASK			GENMASK(7, 0)
  35
  36#define AXP192_GPIO30_IN_RANGE_GPIO0		BIT(0)
  37#define AXP192_GPIO30_IN_RANGE_GPIO1		BIT(1)
  38#define AXP192_GPIO30_IN_RANGE_GPIO2		BIT(2)
  39#define AXP192_GPIO30_IN_RANGE_GPIO3		BIT(3)
  40
  41#define AXP20X_GPIO10_IN_RANGE_GPIO0		BIT(0)
  42#define AXP20X_GPIO10_IN_RANGE_GPIO1		BIT(1)
  43
  44#define AXP20X_ADC_RATE_MASK			GENMASK(7, 6)
  45#define AXP20X_ADC_RATE_HZ(x)			((ilog2((x) / 25) << 6) & AXP20X_ADC_RATE_MASK)
  46
  47#define AXP22X_ADC_RATE_HZ(x)			((ilog2((x) / 100) << 6) & AXP20X_ADC_RATE_MASK)
  48
  49#define AXP717_ADC_DATA_TS			0x00
  50#define AXP717_ADC_DATA_TEMP			0x01
  51#define AXP717_ADC_DATA_VMID			0x02
  52#define AXP717_ADC_DATA_BKUP_BATT		0x03
  53
  54#define AXP717_ADC_DATA_MASK			GENMASK(13, 0)
  55
  56#define AXP813_V_I_ADC_RATE_MASK		GENMASK(5, 4)
  57#define AXP813_ADC_RATE_MASK			(AXP20X_ADC_RATE_MASK | AXP813_V_I_ADC_RATE_MASK)
  58#define AXP813_TS_GPIO0_ADC_RATE_HZ(x)		AXP20X_ADC_RATE_HZ(x)
  59#define AXP813_V_I_ADC_RATE_HZ(x)		((ilog2((x) / 100) << 4) & AXP813_V_I_ADC_RATE_MASK)
  60#define AXP813_ADC_RATE_HZ(x)			(AXP20X_ADC_RATE_HZ(x) | AXP813_V_I_ADC_RATE_HZ(x))
  61
  62#define AXP20X_ADC_CHANNEL(_channel, _name, _type, _reg)	\
  63	{							\
  64		.type = _type,					\
  65		.indexed = 1,					\
  66		.channel = _channel,				\
  67		.address = _reg,				\
  68		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |	\
  69				      BIT(IIO_CHAN_INFO_SCALE),	\
  70		.datasheet_name = _name,			\
  71	}
  72
  73#define AXP20X_ADC_CHANNEL_OFFSET(_channel, _name, _type, _reg) \
  74	{							\
  75		.type = _type,					\
  76		.indexed = 1,					\
  77		.channel = _channel,				\
  78		.address = _reg,				\
  79		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |	\
  80				      BIT(IIO_CHAN_INFO_SCALE) |\
  81				      BIT(IIO_CHAN_INFO_OFFSET),\
  82		.datasheet_name = _name,			\
  83	}
  84
  85struct axp_data;
  86
  87struct axp20x_adc_iio {
  88	struct regmap		*regmap;
  89	const struct axp_data	*data;
  90};
  91
  92enum axp192_adc_channel_v {
  93	AXP192_ACIN_V = 0,
  94	AXP192_VBUS_V,
  95	AXP192_TS_IN,
  96	AXP192_GPIO0_V,
  97	AXP192_GPIO1_V,
  98	AXP192_GPIO2_V,
  99	AXP192_GPIO3_V,
 100	AXP192_IPSOUT_V,
 101	AXP192_BATT_V,
 102};
 103
 104enum axp192_adc_channel_i {
 105	AXP192_ACIN_I = 0,
 106	AXP192_VBUS_I,
 107	AXP192_BATT_CHRG_I,
 108	AXP192_BATT_DISCHRG_I,
 109};
 110
 111enum axp20x_adc_channel_v {
 112	AXP20X_ACIN_V = 0,
 113	AXP20X_VBUS_V,
 114	AXP20X_TS_IN,
 115	AXP20X_GPIO0_V,
 116	AXP20X_GPIO1_V,
 117	AXP20X_IPSOUT_V,
 118	AXP20X_BATT_V,
 119};
 120
 121enum axp20x_adc_channel_i {
 122	AXP20X_ACIN_I = 0,
 123	AXP20X_VBUS_I,
 124	AXP20X_BATT_CHRG_I,
 125	AXP20X_BATT_DISCHRG_I,
 126};
 127
 128enum axp22x_adc_channel_v {
 129	AXP22X_TS_IN = 0,
 130	AXP22X_BATT_V,
 131};
 132
 133enum axp22x_adc_channel_i {
 134	AXP22X_BATT_CHRG_I = 1,
 135	AXP22X_BATT_DISCHRG_I,
 136};
 137
 138enum axp717_adc_channel_v {
 139	AXP717_BATT_V = 0,
 140	AXP717_TS_IN,
 141	AXP717_VBUS_V,
 142	AXP717_VSYS_V,
 143	AXP717_DIE_TEMP_V,
 144	AXP717_VMID_V = 6,
 145	AXP717_BKUP_BATT_V,
 146};
 147
 148enum axp717_adc_channel_i {
 149	AXP717_BATT_CHRG_I = 5,
 150};
 151
 152enum axp813_adc_channel_v {
 153	AXP813_TS_IN = 0,
 154	AXP813_GPIO0_V,
 155	AXP813_BATT_V,
 156};
 157
 158static const struct iio_map axp20x_maps[] = {
 159	IIO_MAP("vbus_v", "axp20x-usb-power-supply", "vbus_v"),
 160	IIO_MAP("vbus_i", "axp20x-usb-power-supply", "vbus_i"),
 161	IIO_MAP("acin_v", "axp20x-ac-power-supply", "acin_v"),
 162	IIO_MAP("acin_i", "axp20x-ac-power-supply", "acin_i"),
 163	IIO_MAP("batt_v", "axp20x-battery-power-supply", "batt_v"),
 164	IIO_MAP("batt_chrg_i", "axp20x-battery-power-supply", "batt_chrg_i"),
 165	IIO_MAP("batt_dischrg_i", "axp20x-battery-power-supply", "batt_dischrg_i"),
 166	{ }
 167};
 168
 169static const struct iio_map axp22x_maps[] = {
 170	IIO_MAP("batt_v", "axp20x-battery-power-supply", "batt_v"),
 171	IIO_MAP("batt_chrg_i", "axp20x-battery-power-supply", "batt_chrg_i"),
 172	IIO_MAP("batt_dischrg_i", "axp20x-battery-power-supply", "batt_dischrg_i"),
 173	{ }
 174};
 175
 176static const struct iio_map axp717_maps[] = {
 177	{
 178		.consumer_dev_name = "axp20x-usb-power-supply",
 179		.consumer_channel = "vbus_v",
 180		.adc_channel_label = "vbus_v",
 181	}, {
 182		.consumer_dev_name = "axp20x-battery-power-supply",
 183		.consumer_channel = "batt_v",
 184		.adc_channel_label = "batt_v",
 185	}, {
 186		.consumer_dev_name = "axp20x-battery-power-supply",
 187		.consumer_channel = "batt_chrg_i",
 188		.adc_channel_label = "batt_chrg_i",
 189	},
 190	{ }
 191};
 192
 193/*
 194 * Channels are mapped by physical system. Their channels share the same index.
 195 * i.e. acin_i is in_current0_raw and acin_v is in_voltage0_raw.
 196 * The only exception is for the battery. batt_v will be in_voltage6_raw and
 197 * charge current in_current6_raw and discharge current will be in_current7_raw.
 198 */
 199static const struct iio_chan_spec axp192_adc_channels[] = {
 200	AXP20X_ADC_CHANNEL(AXP192_ACIN_V, "acin_v", IIO_VOLTAGE,
 201			   AXP20X_ACIN_V_ADC_H),
 202	AXP20X_ADC_CHANNEL(AXP192_ACIN_I, "acin_i", IIO_CURRENT,
 203			   AXP20X_ACIN_I_ADC_H),
 204	AXP20X_ADC_CHANNEL(AXP192_VBUS_V, "vbus_v", IIO_VOLTAGE,
 205			   AXP20X_VBUS_V_ADC_H),
 206	AXP20X_ADC_CHANNEL(AXP192_VBUS_I, "vbus_i", IIO_CURRENT,
 207			   AXP20X_VBUS_I_ADC_H),
 208	{
 209		.type = IIO_TEMP,
 210		.address = AXP20X_TEMP_ADC_H,
 211		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 212				      BIT(IIO_CHAN_INFO_SCALE) |
 213				      BIT(IIO_CHAN_INFO_OFFSET),
 214		.datasheet_name = "pmic_temp",
 215	},
 216	AXP20X_ADC_CHANNEL_OFFSET(AXP192_GPIO0_V, "gpio0_v", IIO_VOLTAGE,
 217				  AXP20X_GPIO0_V_ADC_H),
 218	AXP20X_ADC_CHANNEL_OFFSET(AXP192_GPIO1_V, "gpio1_v", IIO_VOLTAGE,
 219				  AXP20X_GPIO1_V_ADC_H),
 220	AXP20X_ADC_CHANNEL_OFFSET(AXP192_GPIO2_V, "gpio2_v", IIO_VOLTAGE,
 221				  AXP192_GPIO2_V_ADC_H),
 222	AXP20X_ADC_CHANNEL_OFFSET(AXP192_GPIO3_V, "gpio3_v", IIO_VOLTAGE,
 223				  AXP192_GPIO3_V_ADC_H),
 224	AXP20X_ADC_CHANNEL(AXP192_IPSOUT_V, "ipsout_v", IIO_VOLTAGE,
 225			   AXP20X_IPSOUT_V_HIGH_H),
 226	AXP20X_ADC_CHANNEL(AXP192_BATT_V, "batt_v", IIO_VOLTAGE,
 227			   AXP20X_BATT_V_H),
 228	AXP20X_ADC_CHANNEL(AXP192_BATT_CHRG_I, "batt_chrg_i", IIO_CURRENT,
 229			   AXP20X_BATT_CHRG_I_H),
 230	AXP20X_ADC_CHANNEL(AXP192_BATT_DISCHRG_I, "batt_dischrg_i", IIO_CURRENT,
 231			   AXP20X_BATT_DISCHRG_I_H),
 232	AXP20X_ADC_CHANNEL(AXP192_TS_IN, "ts_v", IIO_VOLTAGE,
 233			   AXP20X_TS_IN_H),
 234};
 235
 236static const struct iio_chan_spec axp20x_adc_channels[] = {
 237	AXP20X_ADC_CHANNEL(AXP20X_ACIN_V, "acin_v", IIO_VOLTAGE,
 238			   AXP20X_ACIN_V_ADC_H),
 239	AXP20X_ADC_CHANNEL(AXP20X_ACIN_I, "acin_i", IIO_CURRENT,
 240			   AXP20X_ACIN_I_ADC_H),
 241	AXP20X_ADC_CHANNEL(AXP20X_VBUS_V, "vbus_v", IIO_VOLTAGE,
 242			   AXP20X_VBUS_V_ADC_H),
 243	AXP20X_ADC_CHANNEL(AXP20X_VBUS_I, "vbus_i", IIO_CURRENT,
 244			   AXP20X_VBUS_I_ADC_H),
 245	{
 246		.type = IIO_TEMP,
 247		.address = AXP20X_TEMP_ADC_H,
 248		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 249				      BIT(IIO_CHAN_INFO_SCALE) |
 250				      BIT(IIO_CHAN_INFO_OFFSET),
 251		.datasheet_name = "pmic_temp",
 252	},
 253	AXP20X_ADC_CHANNEL_OFFSET(AXP20X_GPIO0_V, "gpio0_v", IIO_VOLTAGE,
 254				  AXP20X_GPIO0_V_ADC_H),
 255	AXP20X_ADC_CHANNEL_OFFSET(AXP20X_GPIO1_V, "gpio1_v", IIO_VOLTAGE,
 256				  AXP20X_GPIO1_V_ADC_H),
 257	AXP20X_ADC_CHANNEL(AXP20X_IPSOUT_V, "ipsout_v", IIO_VOLTAGE,
 258			   AXP20X_IPSOUT_V_HIGH_H),
 259	AXP20X_ADC_CHANNEL(AXP20X_BATT_V, "batt_v", IIO_VOLTAGE,
 260			   AXP20X_BATT_V_H),
 261	AXP20X_ADC_CHANNEL(AXP20X_BATT_CHRG_I, "batt_chrg_i", IIO_CURRENT,
 262			   AXP20X_BATT_CHRG_I_H),
 263	AXP20X_ADC_CHANNEL(AXP20X_BATT_DISCHRG_I, "batt_dischrg_i", IIO_CURRENT,
 264			   AXP20X_BATT_DISCHRG_I_H),
 265	AXP20X_ADC_CHANNEL(AXP20X_TS_IN, "ts_v", IIO_VOLTAGE,
 266			   AXP20X_TS_IN_H),
 267};
 268
 269static const struct iio_chan_spec axp22x_adc_channels[] = {
 270	{
 271		.type = IIO_TEMP,
 272		.address = AXP22X_PMIC_TEMP_H,
 273		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 274				      BIT(IIO_CHAN_INFO_SCALE) |
 275				      BIT(IIO_CHAN_INFO_OFFSET),
 276		.datasheet_name = "pmic_temp",
 277	},
 278	AXP20X_ADC_CHANNEL(AXP22X_BATT_V, "batt_v", IIO_VOLTAGE,
 279			   AXP20X_BATT_V_H),
 280	AXP20X_ADC_CHANNEL(AXP22X_BATT_CHRG_I, "batt_chrg_i", IIO_CURRENT,
 281			   AXP20X_BATT_CHRG_I_H),
 282	AXP20X_ADC_CHANNEL(AXP22X_BATT_DISCHRG_I, "batt_dischrg_i", IIO_CURRENT,
 283			   AXP20X_BATT_DISCHRG_I_H),
 284	AXP20X_ADC_CHANNEL(AXP22X_TS_IN, "ts_v", IIO_VOLTAGE,
 285			   AXP22X_TS_ADC_H),
 286};
 287
 288/*
 289 * Scale and offset is unknown for temp, ts, batt_chrg_i, vmid_v, and
 290 * bkup_batt_v channels. Leaving scale and offset undefined for now.
 291 */
 292static const struct iio_chan_spec axp717_adc_channels[] = {
 293	AXP20X_ADC_CHANNEL(AXP717_BATT_V, "batt_v", IIO_VOLTAGE,
 294			   AXP717_BATT_V_H),
 295	AXP20X_ADC_CHANNEL(AXP717_TS_IN, "ts_v", IIO_VOLTAGE,
 296			   AXP717_ADC_DATA_H),
 297	AXP20X_ADC_CHANNEL(AXP717_VBUS_V, "vbus_v", IIO_VOLTAGE,
 298			   AXP717_VBUS_V_H),
 299	AXP20X_ADC_CHANNEL(AXP717_VSYS_V, "vsys_v", IIO_VOLTAGE,
 300			   AXP717_VSYS_V_H),
 301	AXP20X_ADC_CHANNEL(AXP717_DIE_TEMP_V, "pmic_temp", IIO_TEMP,
 302			   AXP717_ADC_DATA_H),
 303	AXP20X_ADC_CHANNEL(AXP717_BATT_CHRG_I, "batt_chrg_i", IIO_CURRENT,
 304			   AXP717_BATT_CHRG_I_H),
 305	AXP20X_ADC_CHANNEL(AXP717_VMID_V, "vmid_v", IIO_VOLTAGE,
 306			   AXP717_ADC_DATA_H),
 307	AXP20X_ADC_CHANNEL(AXP717_BKUP_BATT_V, "bkup_batt_v", IIO_VOLTAGE,
 308			   AXP717_ADC_DATA_H),
 309};
 310
 311static const struct iio_chan_spec axp813_adc_channels[] = {
 312	{
 313		.type = IIO_TEMP,
 314		.address = AXP22X_PMIC_TEMP_H,
 315		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 316				      BIT(IIO_CHAN_INFO_SCALE) |
 317				      BIT(IIO_CHAN_INFO_OFFSET),
 318		.datasheet_name = "pmic_temp",
 319	},
 320	AXP20X_ADC_CHANNEL(AXP813_GPIO0_V, "gpio0_v", IIO_VOLTAGE,
 321			   AXP288_GP_ADC_H),
 322	AXP20X_ADC_CHANNEL(AXP813_BATT_V, "batt_v", IIO_VOLTAGE,
 323			   AXP20X_BATT_V_H),
 324	AXP20X_ADC_CHANNEL(AXP22X_BATT_CHRG_I, "batt_chrg_i", IIO_CURRENT,
 325			   AXP20X_BATT_CHRG_I_H),
 326	AXP20X_ADC_CHANNEL(AXP22X_BATT_DISCHRG_I, "batt_dischrg_i", IIO_CURRENT,
 327			   AXP20X_BATT_DISCHRG_I_H),
 328	AXP20X_ADC_CHANNEL(AXP813_TS_IN, "ts_v", IIO_VOLTAGE,
 329			   AXP288_TS_ADC_H),
 330};
 331
 332static int axp192_adc_raw(struct iio_dev *indio_dev,
 333			  struct iio_chan_spec const *chan, int *val)
 334{
 335	struct axp20x_adc_iio *info = iio_priv(indio_dev);
 336	int ret, size;
 337
 338	if (chan->type == IIO_CURRENT &&
 339	    (chan->channel == AXP192_BATT_CHRG_I ||
 340	     chan->channel == AXP192_BATT_DISCHRG_I))
 341		size = 13;
 342	else
 343		size = 12;
 344
 345	ret = axp20x_read_variable_width(info->regmap, chan->address, size);
 346	if (ret < 0)
 347		return ret;
 348
 349	*val = ret;
 350	return IIO_VAL_INT;
 351}
 352
 353static int axp20x_adc_raw(struct iio_dev *indio_dev,
 354			  struct iio_chan_spec const *chan, int *val)
 355{
 356	struct axp20x_adc_iio *info = iio_priv(indio_dev);
 357	int ret, size;
 358
 359	/*
 360	 * N.B.:  Unlike the Chinese datasheets tell, the charging current is
 361	 * stored on 12 bits, not 13 bits. Only discharging current is on 13
 362	 * bits.
 363	 */
 364	if (chan->type == IIO_CURRENT && chan->channel == AXP20X_BATT_DISCHRG_I)
 365		size = 13;
 366	else
 367		size = 12;
 368
 369	ret = axp20x_read_variable_width(info->regmap, chan->address, size);
 370	if (ret < 0)
 371		return ret;
 372
 373	*val = ret;
 374	return IIO_VAL_INT;
 375}
 376
 377static int axp22x_adc_raw(struct iio_dev *indio_dev,
 378			  struct iio_chan_spec const *chan, int *val)
 379{
 380	struct axp20x_adc_iio *info = iio_priv(indio_dev);
 381	int ret;
 382
 383	ret = axp20x_read_variable_width(info->regmap, chan->address, 12);
 384	if (ret < 0)
 385		return ret;
 386
 387	*val = ret;
 388	return IIO_VAL_INT;
 389}
 390
 391static int axp717_adc_raw(struct iio_dev *indio_dev,
 392			  struct iio_chan_spec const *chan, int *val)
 393{
 394	struct axp20x_adc_iio *info = iio_priv(indio_dev);
 395	u8 bulk_reg[2];
 396	int ret;
 397
 398	/*
 399	 * A generic "ADC data" channel is used for TS, tdie, vmid,
 400	 * and vbackup. This channel must both first be enabled and
 401	 * also selected before it can be read.
 402	 */
 403	switch (chan->channel) {
 404	case AXP717_TS_IN:
 405		regmap_write(info->regmap, AXP717_ADC_DATA_SEL,
 406			     AXP717_ADC_DATA_TS);
 407		break;
 408	case AXP717_DIE_TEMP_V:
 409		regmap_write(info->regmap, AXP717_ADC_DATA_SEL,
 410			     AXP717_ADC_DATA_TEMP);
 411		break;
 412	case AXP717_VMID_V:
 413		regmap_write(info->regmap, AXP717_ADC_DATA_SEL,
 414			     AXP717_ADC_DATA_VMID);
 415		break;
 416	case AXP717_BKUP_BATT_V:
 417		regmap_write(info->regmap, AXP717_ADC_DATA_SEL,
 418			     AXP717_ADC_DATA_BKUP_BATT);
 419		break;
 420	default:
 421		break;
 422	}
 423
 424	/*
 425	 * All channels are 14 bits, with the first 2 bits on the high
 426	 * register reserved and the remaining bits as the ADC value.
 427	 */
 428	ret = regmap_bulk_read(info->regmap, chan->address, bulk_reg, 2);
 429	if (ret < 0)
 430		return ret;
 431
 432	*val = FIELD_GET(AXP717_ADC_DATA_MASK, get_unaligned_be16(bulk_reg));
 433	return IIO_VAL_INT;
 434}
 435
 436static int axp813_adc_raw(struct iio_dev *indio_dev,
 437			  struct iio_chan_spec const *chan, int *val)
 438{
 439	struct axp20x_adc_iio *info = iio_priv(indio_dev);
 440	int ret;
 441
 442	ret = axp20x_read_variable_width(info->regmap, chan->address, 12);
 443	if (ret < 0)
 444		return ret;
 445
 446	*val = ret;
 447	return IIO_VAL_INT;
 448}
 449
 450static int axp192_adc_scale_voltage(int channel, int *val, int *val2)
 451{
 452	switch (channel) {
 453	case AXP192_ACIN_V:
 454	case AXP192_VBUS_V:
 455		*val = 1;
 456		*val2 = 700000;
 457		return IIO_VAL_INT_PLUS_MICRO;
 458
 459	case AXP192_GPIO0_V:
 460	case AXP192_GPIO1_V:
 461	case AXP192_GPIO2_V:
 462	case AXP192_GPIO3_V:
 463		*val = 0;
 464		*val2 = 500000;
 465		return IIO_VAL_INT_PLUS_MICRO;
 466
 467	case AXP192_BATT_V:
 468		*val = 1;
 469		*val2 = 100000;
 470		return IIO_VAL_INT_PLUS_MICRO;
 471
 472	case AXP192_IPSOUT_V:
 473		*val = 1;
 474		*val2 = 400000;
 475		return IIO_VAL_INT_PLUS_MICRO;
 476
 477	case AXP192_TS_IN:
 478		/* 0.8 mV per LSB */
 479		*val = 0;
 480		*val2 = 800000;
 481		return IIO_VAL_INT_PLUS_MICRO;
 482
 483	default:
 484		return -EINVAL;
 485	}
 486}
 487
 488static int axp20x_adc_scale_voltage(int channel, int *val, int *val2)
 489{
 490	switch (channel) {
 491	case AXP20X_ACIN_V:
 492	case AXP20X_VBUS_V:
 493		*val = 1;
 494		*val2 = 700000;
 495		return IIO_VAL_INT_PLUS_MICRO;
 496
 497	case AXP20X_GPIO0_V:
 498	case AXP20X_GPIO1_V:
 499		*val = 0;
 500		*val2 = 500000;
 501		return IIO_VAL_INT_PLUS_MICRO;
 502
 503	case AXP20X_BATT_V:
 504		*val = 1;
 505		*val2 = 100000;
 506		return IIO_VAL_INT_PLUS_MICRO;
 507
 508	case AXP20X_IPSOUT_V:
 509		*val = 1;
 510		*val2 = 400000;
 511		return IIO_VAL_INT_PLUS_MICRO;
 512
 513	case AXP20X_TS_IN:
 514		/* 0.8 mV per LSB */
 515		*val = 0;
 516		*val2 = 800000;
 517		return IIO_VAL_INT_PLUS_MICRO;
 518
 519	default:
 520		return -EINVAL;
 521	}
 522}
 523
 524static int axp22x_adc_scale_voltage(int channel, int *val, int *val2)
 525{
 526	switch (channel) {
 527	case AXP22X_BATT_V:
 528		/* 1.1 mV per LSB */
 529		*val = 1;
 530		*val2 = 100000;
 531		return IIO_VAL_INT_PLUS_MICRO;
 532
 533	case AXP22X_TS_IN:
 534		/* 0.8 mV per LSB */
 535		*val = 0;
 536		*val2 = 800000;
 537		return IIO_VAL_INT_PLUS_MICRO;
 538
 539	default:
 540		return -EINVAL;
 541	}
 542}
 543static int axp813_adc_scale_voltage(int channel, int *val, int *val2)
 544{
 545	switch (channel) {
 546	case AXP813_GPIO0_V:
 547		*val = 0;
 548		*val2 = 800000;
 549		return IIO_VAL_INT_PLUS_MICRO;
 550
 551	case AXP813_BATT_V:
 552		*val = 1;
 553		*val2 = 100000;
 554		return IIO_VAL_INT_PLUS_MICRO;
 555
 556	case AXP813_TS_IN:
 557		/* 0.8 mV per LSB */
 558		*val = 0;
 559		*val2 = 800000;
 560		return IIO_VAL_INT_PLUS_MICRO;
 561
 562	default:
 563		return -EINVAL;
 564	}
 565}
 566
 567static int axp20x_adc_scale_current(int channel, int *val, int *val2)
 568{
 569	switch (channel) {
 570	case AXP20X_ACIN_I:
 571		*val = 0;
 572		*val2 = 625000;
 573		return IIO_VAL_INT_PLUS_MICRO;
 574
 575	case AXP20X_VBUS_I:
 576		*val = 0;
 577		*val2 = 375000;
 578		return IIO_VAL_INT_PLUS_MICRO;
 579
 580	case AXP20X_BATT_DISCHRG_I:
 581	case AXP20X_BATT_CHRG_I:
 582		*val = 0;
 583		*val2 = 500000;
 584		return IIO_VAL_INT_PLUS_MICRO;
 585
 586	default:
 587		return -EINVAL;
 588	}
 589}
 590
 591static int axp192_adc_scale(struct iio_chan_spec const *chan, int *val,
 592			    int *val2)
 593{
 594	switch (chan->type) {
 595	case IIO_VOLTAGE:
 596		return axp192_adc_scale_voltage(chan->channel, val, val2);
 597
 598	case IIO_CURRENT:
 599		/*
 600		 * AXP192 current channels are identical to the AXP20x,
 601		 * therefore we can re-use the scaling function.
 602		 */
 603		return axp20x_adc_scale_current(chan->channel, val, val2);
 604
 605	case IIO_TEMP:
 606		*val = 100;
 607		return IIO_VAL_INT;
 608
 609	default:
 610		return -EINVAL;
 611	}
 612}
 613
 614static int axp20x_adc_scale(struct iio_chan_spec const *chan, int *val,
 615			    int *val2)
 616{
 617	switch (chan->type) {
 618	case IIO_VOLTAGE:
 619		return axp20x_adc_scale_voltage(chan->channel, val, val2);
 620
 621	case IIO_CURRENT:
 622		return axp20x_adc_scale_current(chan->channel, val, val2);
 623
 624	case IIO_TEMP:
 625		*val = 100;
 626		return IIO_VAL_INT;
 627
 628	default:
 629		return -EINVAL;
 630	}
 631}
 632
 633static int axp22x_adc_scale(struct iio_chan_spec const *chan, int *val,
 634			    int *val2)
 635{
 636	switch (chan->type) {
 637	case IIO_VOLTAGE:
 638		return axp22x_adc_scale_voltage(chan->channel, val, val2);
 639
 640	case IIO_CURRENT:
 641		*val = 1;
 642		return IIO_VAL_INT;
 643
 644	case IIO_TEMP:
 645		*val = 100;
 646		return IIO_VAL_INT;
 647
 648	default:
 649		return -EINVAL;
 650	}
 651}
 652
 653static int axp717_adc_scale(struct iio_chan_spec const *chan, int *val,
 654			    int *val2)
 655{
 656	switch (chan->type) {
 657	case IIO_VOLTAGE:
 658		*val = 1;
 659		return IIO_VAL_INT;
 660
 661	case IIO_CURRENT:
 662		*val = 1;
 663		return IIO_VAL_INT;
 664
 665	case IIO_TEMP:
 666		*val = 100;
 667		return IIO_VAL_INT;
 668
 669	default:
 670		return -EINVAL;
 671	}
 672}
 673
 674static int axp813_adc_scale(struct iio_chan_spec const *chan, int *val,
 675			    int *val2)
 676{
 677	switch (chan->type) {
 678	case IIO_VOLTAGE:
 679		return axp813_adc_scale_voltage(chan->channel, val, val2);
 680
 681	case IIO_CURRENT:
 682		*val = 1;
 683		return IIO_VAL_INT;
 684
 685	case IIO_TEMP:
 686		*val = 100;
 687		return IIO_VAL_INT;
 688
 689	default:
 690		return -EINVAL;
 691	}
 692}
 693
 694static int axp192_adc_offset_voltage(struct iio_dev *indio_dev, int channel,
 695				     int *val)
 696{
 697	struct axp20x_adc_iio *info = iio_priv(indio_dev);
 698	unsigned int regval;
 699	int ret;
 700
 701	ret = regmap_read(info->regmap, AXP192_GPIO30_IN_RANGE, &regval);
 702	if (ret < 0)
 703		return ret;
 704
 705	switch (channel) {
 706	case AXP192_GPIO0_V:
 707		regval = FIELD_GET(AXP192_GPIO30_IN_RANGE_GPIO0, regval);
 708		break;
 709
 710	case AXP192_GPIO1_V:
 711		regval = FIELD_GET(AXP192_GPIO30_IN_RANGE_GPIO1, regval);
 712		break;
 713
 714	case AXP192_GPIO2_V:
 715		regval = FIELD_GET(AXP192_GPIO30_IN_RANGE_GPIO2, regval);
 716		break;
 717
 718	case AXP192_GPIO3_V:
 719		regval = FIELD_GET(AXP192_GPIO30_IN_RANGE_GPIO3, regval);
 720		break;
 721
 722	default:
 723		return -EINVAL;
 724	}
 725
 726	*val = regval ? 700000 : 0;
 727	return IIO_VAL_INT;
 728}
 729
 730static int axp20x_adc_offset_voltage(struct iio_dev *indio_dev, int channel,
 731				     int *val)
 732{
 733	struct axp20x_adc_iio *info = iio_priv(indio_dev);
 734	unsigned int regval;
 735	int ret;
 736
 737	ret = regmap_read(info->regmap, AXP20X_GPIO10_IN_RANGE, &regval);
 738	if (ret < 0)
 739		return ret;
 740
 741	switch (channel) {
 742	case AXP20X_GPIO0_V:
 743		regval = FIELD_GET(AXP20X_GPIO10_IN_RANGE_GPIO0, regval);
 744		break;
 745
 746	case AXP20X_GPIO1_V:
 747		regval = FIELD_GET(AXP20X_GPIO10_IN_RANGE_GPIO1, regval);
 748		break;
 749
 750	default:
 751		return -EINVAL;
 752	}
 753
 754	*val = regval ? 700000 : 0;
 755	return IIO_VAL_INT;
 756}
 757
 758static int axp192_adc_offset(struct iio_dev *indio_dev,
 759			     struct iio_chan_spec const *chan, int *val)
 760{
 761	switch (chan->type) {
 762	case IIO_VOLTAGE:
 763		return axp192_adc_offset_voltage(indio_dev, chan->channel, val);
 764
 765	case IIO_TEMP:
 766		*val = -1447;
 767		return IIO_VAL_INT;
 768
 769	default:
 770		return -EINVAL;
 771	}
 772}
 773
 774static int axp20x_adc_offset(struct iio_dev *indio_dev,
 775			     struct iio_chan_spec const *chan, int *val)
 776{
 777	switch (chan->type) {
 778	case IIO_VOLTAGE:
 779		return axp20x_adc_offset_voltage(indio_dev, chan->channel, val);
 780
 781	case IIO_TEMP:
 782		*val = -1447;
 783		return IIO_VAL_INT;
 784
 785	default:
 786		return -EINVAL;
 787	}
 788}
 789
 790static int axp192_read_raw(struct iio_dev *indio_dev,
 791			   struct iio_chan_spec const *chan, int *val,
 792			   int *val2, long mask)
 793{
 794	switch (mask) {
 795	case IIO_CHAN_INFO_OFFSET:
 796		return axp192_adc_offset(indio_dev, chan, val);
 797
 798	case IIO_CHAN_INFO_SCALE:
 799		return axp192_adc_scale(chan, val, val2);
 800
 801	case IIO_CHAN_INFO_RAW:
 802		return axp192_adc_raw(indio_dev, chan, val);
 803
 804	default:
 805		return -EINVAL;
 806	}
 807}
 808
 809static int axp20x_read_raw(struct iio_dev *indio_dev,
 810			   struct iio_chan_spec const *chan, int *val,
 811			   int *val2, long mask)
 812{
 813	switch (mask) {
 814	case IIO_CHAN_INFO_OFFSET:
 815		return axp20x_adc_offset(indio_dev, chan, val);
 816
 817	case IIO_CHAN_INFO_SCALE:
 818		return axp20x_adc_scale(chan, val, val2);
 819
 820	case IIO_CHAN_INFO_RAW:
 821		return axp20x_adc_raw(indio_dev, chan, val);
 822
 823	default:
 824		return -EINVAL;
 825	}
 826}
 827
 828static int axp22x_read_raw(struct iio_dev *indio_dev,
 829			   struct iio_chan_spec const *chan, int *val,
 830			   int *val2, long mask)
 831{
 832	switch (mask) {
 833	case IIO_CHAN_INFO_OFFSET:
 834		/* For PMIC temp only */
 835		*val = -2677;
 836		return IIO_VAL_INT;
 837
 838	case IIO_CHAN_INFO_SCALE:
 839		return axp22x_adc_scale(chan, val, val2);
 840
 841	case IIO_CHAN_INFO_RAW:
 842		return axp22x_adc_raw(indio_dev, chan, val);
 843
 844	default:
 845		return -EINVAL;
 846	}
 847}
 848
 849static int axp717_read_raw(struct iio_dev *indio_dev,
 850			   struct iio_chan_spec const *chan, int *val,
 851			   int *val2, long mask)
 852{
 853	switch (mask) {
 854	case IIO_CHAN_INFO_SCALE:
 855		return axp717_adc_scale(chan, val, val2);
 856
 857	case IIO_CHAN_INFO_RAW:
 858		return axp717_adc_raw(indio_dev, chan, val);
 859
 860	default:
 861		return -EINVAL;
 862	}
 863}
 864
 865static int axp813_read_raw(struct iio_dev *indio_dev,
 866			   struct iio_chan_spec const *chan, int *val,
 867			   int *val2, long mask)
 868{
 869	switch (mask) {
 870	case IIO_CHAN_INFO_OFFSET:
 871		*val = -2667;
 872		return IIO_VAL_INT;
 873
 874	case IIO_CHAN_INFO_SCALE:
 875		return axp813_adc_scale(chan, val, val2);
 876
 877	case IIO_CHAN_INFO_RAW:
 878		return axp813_adc_raw(indio_dev, chan, val);
 879
 880	default:
 881		return -EINVAL;
 882	}
 883}
 884
 885static int axp192_write_raw(struct iio_dev *indio_dev,
 886			    struct iio_chan_spec const *chan, int val, int val2,
 887			    long mask)
 888{
 889	struct axp20x_adc_iio *info = iio_priv(indio_dev);
 890	unsigned int regmask, regval;
 891
 892	/*
 893	 * The AXP192 PMIC allows the user to choose between 0V and 0.7V offsets
 894	 * for (independently) GPIO0-3 when in ADC mode.
 895	 */
 896	if (mask != IIO_CHAN_INFO_OFFSET)
 897		return -EINVAL;
 898
 899	if (val != 0 && val != 700000)
 900		return -EINVAL;
 901
 902	switch (chan->channel) {
 903	case AXP192_GPIO0_V:
 904		regmask = AXP192_GPIO30_IN_RANGE_GPIO0;
 905		regval = FIELD_PREP(AXP192_GPIO30_IN_RANGE_GPIO0, !!val);
 906		break;
 907
 908	case AXP192_GPIO1_V:
 909		regmask = AXP192_GPIO30_IN_RANGE_GPIO1;
 910		regval = FIELD_PREP(AXP192_GPIO30_IN_RANGE_GPIO1, !!val);
 911		break;
 912
 913	case AXP192_GPIO2_V:
 914		regmask = AXP192_GPIO30_IN_RANGE_GPIO2;
 915		regval = FIELD_PREP(AXP192_GPIO30_IN_RANGE_GPIO2, !!val);
 916		break;
 917
 918	case AXP192_GPIO3_V:
 919		regmask = AXP192_GPIO30_IN_RANGE_GPIO3;
 920		regval = FIELD_PREP(AXP192_GPIO30_IN_RANGE_GPIO3, !!val);
 921		break;
 922
 923	default:
 924		return -EINVAL;
 925	}
 926
 927	return regmap_update_bits(info->regmap, AXP192_GPIO30_IN_RANGE, regmask, regval);
 928}
 929
 930static int axp20x_write_raw(struct iio_dev *indio_dev,
 931			    struct iio_chan_spec const *chan, int val, int val2,
 932			    long mask)
 933{
 934	struct axp20x_adc_iio *info = iio_priv(indio_dev);
 935	unsigned int regmask, regval;
 936
 937	/*
 938	 * The AXP20X PMIC allows the user to choose between 0V and 0.7V offsets
 939	 * for (independently) GPIO0 and GPIO1 when in ADC mode.
 940	 */
 941	if (mask != IIO_CHAN_INFO_OFFSET)
 942		return -EINVAL;
 943
 944	if (val != 0 && val != 700000)
 945		return -EINVAL;
 946
 947	switch (chan->channel) {
 948	case AXP20X_GPIO0_V:
 949		regmask = AXP20X_GPIO10_IN_RANGE_GPIO0;
 950		regval = FIELD_PREP(AXP20X_GPIO10_IN_RANGE_GPIO0, !!val);
 951		break;
 952
 953	case AXP20X_GPIO1_V:
 954		regmask = AXP20X_GPIO10_IN_RANGE_GPIO1;
 955		regval = FIELD_PREP(AXP20X_GPIO10_IN_RANGE_GPIO1, !!val);
 956		break;
 957
 958	default:
 959		return -EINVAL;
 960	}
 961
 962	return regmap_update_bits(info->regmap, AXP20X_GPIO10_IN_RANGE, regmask, regval);
 963}
 964
 965static const struct iio_info axp192_adc_iio_info = {
 966	.read_raw = axp192_read_raw,
 967	.write_raw = axp192_write_raw,
 968};
 969
 970static const struct iio_info axp20x_adc_iio_info = {
 971	.read_raw = axp20x_read_raw,
 972	.write_raw = axp20x_write_raw,
 973};
 974
 975static const struct iio_info axp22x_adc_iio_info = {
 976	.read_raw = axp22x_read_raw,
 977};
 978
 979static const struct iio_info axp717_adc_iio_info = {
 980	.read_raw = axp717_read_raw,
 981};
 982
 983static const struct iio_info axp813_adc_iio_info = {
 984	.read_raw = axp813_read_raw,
 985};
 986
 987static int axp20x_adc_rate(struct axp20x_adc_iio *info, int rate)
 988{
 989	return regmap_update_bits(info->regmap, AXP20X_ADC_RATE,
 990				  AXP20X_ADC_RATE_MASK,
 991				  AXP20X_ADC_RATE_HZ(rate));
 992}
 993
 994static int axp22x_adc_rate(struct axp20x_adc_iio *info, int rate)
 995{
 996	return regmap_update_bits(info->regmap, AXP20X_ADC_RATE,
 997				  AXP20X_ADC_RATE_MASK,
 998				  AXP22X_ADC_RATE_HZ(rate));
 999}
1000
1001static int axp813_adc_rate(struct axp20x_adc_iio *info, int rate)
1002{
1003	return regmap_update_bits(info->regmap, AXP813_ADC_RATE,
1004				 AXP813_ADC_RATE_MASK,
1005				 AXP813_ADC_RATE_HZ(rate));
1006}
1007
1008struct axp_data {
1009	const struct iio_info		*iio_info;
1010	int				num_channels;
1011	struct iio_chan_spec const	*channels;
1012	unsigned long			adc_en1;
1013	unsigned long			adc_en1_mask;
1014	unsigned long			adc_en2;
1015	unsigned long			adc_en2_mask;
1016	int				(*adc_rate)(struct axp20x_adc_iio *info,
1017						    int rate);
1018	const struct iio_map		*maps;
1019};
1020
1021static const struct axp_data axp192_data = {
1022	.iio_info = &axp192_adc_iio_info,
1023	.num_channels = ARRAY_SIZE(axp192_adc_channels),
1024	.channels = axp192_adc_channels,
1025	.adc_en1_mask = AXP192_ADC_EN1_MASK,
1026	.adc_en2_mask = AXP192_ADC_EN2_MASK,
1027	.adc_rate = axp20x_adc_rate,
1028	.maps = axp20x_maps,
1029};
1030
1031static const struct axp_data axp20x_data = {
1032	.iio_info = &axp20x_adc_iio_info,
1033	.num_channels = ARRAY_SIZE(axp20x_adc_channels),
1034	.channels = axp20x_adc_channels,
1035	.adc_en1 = AXP20X_ADC_EN1,
1036	.adc_en1_mask = AXP20X_ADC_EN1_MASK,
1037	.adc_en2 = AXP20X_ADC_EN2,
1038	.adc_en2_mask = AXP20X_ADC_EN2_MASK,
1039	.adc_rate = axp20x_adc_rate,
1040	.maps = axp20x_maps,
1041};
1042
1043static const struct axp_data axp22x_data = {
1044	.iio_info = &axp22x_adc_iio_info,
1045	.num_channels = ARRAY_SIZE(axp22x_adc_channels),
1046	.channels = axp22x_adc_channels,
1047	.adc_en1 = AXP20X_ADC_EN1,
1048	.adc_en1_mask = AXP22X_ADC_EN1_MASK,
1049	.adc_rate = axp22x_adc_rate,
1050	.maps = axp22x_maps,
1051};
1052
1053static const struct axp_data axp717_data = {
1054	.iio_info = &axp717_adc_iio_info,
1055	.num_channels = ARRAY_SIZE(axp717_adc_channels),
1056	.channels = axp717_adc_channels,
1057	.adc_en1 = AXP717_ADC_CH_EN_CONTROL,
1058	.adc_en1_mask = AXP717_ADC_EN1_MASK,
1059	.maps = axp717_maps,
1060};
1061
1062static const struct axp_data axp813_data = {
1063	.iio_info = &axp813_adc_iio_info,
1064	.num_channels = ARRAY_SIZE(axp813_adc_channels),
1065	.channels = axp813_adc_channels,
1066	.adc_en1 = AXP20X_ADC_EN1,
1067	.adc_en1_mask = AXP22X_ADC_EN1_MASK,
1068	.adc_rate = axp813_adc_rate,
1069	.maps = axp22x_maps,
1070};
1071
1072static const struct of_device_id axp20x_adc_of_match[] = {
1073	{ .compatible = "x-powers,axp192-adc", .data = (void *)&axp192_data, },
1074	{ .compatible = "x-powers,axp209-adc", .data = (void *)&axp20x_data, },
1075	{ .compatible = "x-powers,axp221-adc", .data = (void *)&axp22x_data, },
1076	{ .compatible = "x-powers,axp717-adc", .data = (void *)&axp717_data, },
1077	{ .compatible = "x-powers,axp813-adc", .data = (void *)&axp813_data, },
1078	{ }
1079};
1080MODULE_DEVICE_TABLE(of, axp20x_adc_of_match);
1081
1082static const struct platform_device_id axp20x_adc_id_match[] = {
1083	{ .name = "axp192-adc", .driver_data = (kernel_ulong_t)&axp192_data, },
1084	{ .name = "axp20x-adc", .driver_data = (kernel_ulong_t)&axp20x_data, },
1085	{ .name = "axp22x-adc", .driver_data = (kernel_ulong_t)&axp22x_data, },
1086	{ .name = "axp717-adc", .driver_data = (kernel_ulong_t)&axp717_data, },
1087	{ .name = "axp813-adc", .driver_data = (kernel_ulong_t)&axp813_data, },
1088	{ }
1089};
1090MODULE_DEVICE_TABLE(platform, axp20x_adc_id_match);
1091
1092static int axp20x_probe(struct platform_device *pdev)
1093{
1094	struct axp20x_adc_iio *info;
1095	struct iio_dev *indio_dev;
1096	struct axp20x_dev *axp20x_dev;
1097	int ret;
1098
1099	axp20x_dev = dev_get_drvdata(pdev->dev.parent);
1100
1101	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
1102	if (!indio_dev)
1103		return -ENOMEM;
1104
1105	info = iio_priv(indio_dev);
1106	platform_set_drvdata(pdev, indio_dev);
1107
1108	info->regmap = axp20x_dev->regmap;
1109	indio_dev->modes = INDIO_DIRECT_MODE;
1110
1111	if (!dev_fwnode(&pdev->dev)) {
1112		const struct platform_device_id *id;
1113
1114		id = platform_get_device_id(pdev);
1115		info->data = (const struct axp_data *)id->driver_data;
1116	} else {
1117		struct device *dev = &pdev->dev;
1118
1119		info->data = device_get_match_data(dev);
1120	}
1121
1122	indio_dev->name = platform_get_device_id(pdev)->name;
1123	indio_dev->info = info->data->iio_info;
1124	indio_dev->num_channels = info->data->num_channels;
1125	indio_dev->channels = info->data->channels;
1126
1127	/* Enable the ADCs on IP */
1128	regmap_write(info->regmap, info->data->adc_en1,
1129		     info->data->adc_en1_mask);
1130
1131	if (info->data->adc_en2_mask)
1132		regmap_set_bits(info->regmap, info->data->adc_en2,
1133				info->data->adc_en2_mask);
1134
1135	/* Configure ADCs rate */
1136	if (info->data->adc_rate)
1137		info->data->adc_rate(info, 100);
1138
1139	ret = iio_map_array_register(indio_dev, info->data->maps);
1140	if (ret < 0) {
1141		dev_err(&pdev->dev, "failed to register IIO maps: %d\n", ret);
1142		goto fail_map;
1143	}
1144
1145	ret = iio_device_register(indio_dev);
1146	if (ret < 0) {
1147		dev_err(&pdev->dev, "could not register the device\n");
1148		goto fail_register;
1149	}
1150
1151	return 0;
1152
1153fail_register:
1154	iio_map_array_unregister(indio_dev);
1155
1156fail_map:
1157	regmap_write(info->regmap, info->data->adc_en1, 0);
1158
1159	if (info->data->adc_en2_mask)
1160		regmap_write(info->regmap, info->data->adc_en2, 0);
1161
1162	return ret;
1163}
1164
1165static void axp20x_remove(struct platform_device *pdev)
1166{
1167	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1168	struct axp20x_adc_iio *info = iio_priv(indio_dev);
1169
1170	iio_device_unregister(indio_dev);
1171	iio_map_array_unregister(indio_dev);
1172
1173	regmap_write(info->regmap, info->data->adc_en1, 0);
1174
1175	if (info->data->adc_en2_mask)
1176		regmap_write(info->regmap, info->data->adc_en2, 0);
1177}
1178
1179static struct platform_driver axp20x_adc_driver = {
1180	.driver = {
1181		.name = "axp20x-adc",
1182		.of_match_table = axp20x_adc_of_match,
1183	},
1184	.id_table = axp20x_adc_id_match,
1185	.probe = axp20x_probe,
1186	.remove = axp20x_remove,
1187};
1188
1189module_platform_driver(axp20x_adc_driver);
1190
1191MODULE_DESCRIPTION("ADC driver for AXP20X and AXP22X PMICs");
1192MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
1193MODULE_LICENSE("GPL");
~/ Read-only file preview.