ade9000.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/**
   3 * ADE9000 driver
   4 *
   5 * Copyright 2025 Analog Devices Inc.
   6 */
   7
   8#include <linux/bitfield.h>
   9#include <linux/clk.h>
  10#include <linux/clk-provider.h>
  11#include <linux/completion.h>
  12#include <linux/delay.h>
  13#include <linux/gpio/consumer.h>
  14#include <linux/iio/iio.h>
  15#include <linux/iio/buffer.h>
  16#include <linux/iio/kfifo_buf.h>
  17#include <linux/iio/events.h>
  18#include <linux/interrupt.h>
  19#include <linux/minmax.h>
  20#include <linux/module.h>
  21#include <linux/property.h>
  22#include <linux/regmap.h>
  23#include <linux/regulator/consumer.h>
  24#include <linux/spi/spi.h>
  25#include <linux/unaligned.h>
  26
  27/* Address of ADE9000 registers */
  28#define ADE9000_REG_AIGAIN		0x000
  29#define ADE9000_REG_AVGAIN		0x00B
  30#define ADE9000_REG_AIRMSOS		0x00C
  31#define ADE9000_REG_AVRMSOS		0x00D
  32#define ADE9000_REG_APGAIN		0x00E
  33#define ADE9000_REG_AWATTOS		0x00F
  34#define ADE9000_REG_AVAROS		0x010
  35#define ADE9000_REG_AFVAROS		0x012
  36#define ADE9000_REG_CONFIG0		0x060
  37#define ADE9000_REG_DICOEFF		0x072
  38#define ADE9000_REG_AI_PCF		0x20A
  39#define ADE9000_REG_AV_PCF		0x20B
  40#define ADE9000_REG_AIRMS		0x20C
  41#define ADE9000_REG_AVRMS		0x20D
  42#define ADE9000_REG_AWATT		0x210
  43#define ADE9000_REG_AVAR		0x211
  44#define ADE9000_REG_AVA			0x212
  45#define ADE9000_REG_AFVAR		0x214
  46#define ADE9000_REG_APF			0x216
  47#define ADE9000_REG_BI_PCF		0x22A
  48#define ADE9000_REG_BV_PCF		0x22B
  49#define ADE9000_REG_BIRMS		0x22C
  50#define ADE9000_REG_BVRMS		0x22D
  51#define ADE9000_REG_CI_PCF		0x24A
  52#define ADE9000_REG_CV_PCF		0x24B
  53#define ADE9000_REG_CIRMS		0x24C
  54#define ADE9000_REG_CVRMS		0x24D
  55#define ADE9000_REG_AWATT_ACC		0x2E5
  56#define ADE9000_REG_AWATTHR_LO		0x2E6
  57#define ADE9000_REG_AVAHR_LO		0x2FA
  58#define ADE9000_REG_AFVARHR_LO		0x30E
  59#define ADE9000_REG_BWATTHR_LO		0x322
  60#define ADE9000_REG_BVAHR_LO		0x336
  61#define ADE9000_REG_BFVARHR_LO		0x34A
  62#define ADE9000_REG_CWATTHR_LO		0x35E
  63#define ADE9000_REG_CVAHR_LO		0x372
  64#define ADE9000_REG_CFVARHR_LO		0x386
  65#define ADE9000_REG_STATUS0		0x402
  66#define ADE9000_REG_STATUS1		0x403
  67#define ADE9000_REG_MASK0		0x405
  68#define ADE9000_REG_MASK1		0x406
  69#define ADE9000_REG_EVENT_MASK		0x407
  70#define ADE9000_REG_VLEVEL		0x40F
  71#define ADE9000_REG_DIP_LVL		0x410
  72#define ADE9000_REG_DIPA		0x411
  73#define ADE9000_REG_DIPB		0x412
  74#define ADE9000_REG_DIPC		0x413
  75#define ADE9000_REG_SWELL_LVL		0x414
  76#define ADE9000_REG_SWELLA		0x415
  77#define ADE9000_REG_SWELLB		0x416
  78#define ADE9000_REG_SWELLC		0x417
  79#define ADE9000_REG_APERIOD		0x418
  80#define ADE9000_REG_BPERIOD		0x419
  81#define ADE9000_REG_CPERIOD		0x41A
  82#define ADE9000_REG_RUN			0x480
  83#define ADE9000_REG_CONFIG1		0x481
  84#define ADE9000_REG_ACCMODE		0x492
  85#define ADE9000_REG_CONFIG3		0x493
  86#define ADE9000_REG_ZXTOUT		0x498
  87#define ADE9000_REG_ZX_LP_SEL		0x49A
  88#define ADE9000_REG_WFB_CFG		0x4A0
  89#define ADE9000_REG_WFB_PG_IRQEN	0x4A1
  90#define ADE9000_REG_WFB_TRG_CFG		0x4A2
  91#define ADE9000_REG_WFB_TRG_STAT	0x4A3
  92#define ADE9000_REG_CONFIG2		0x4AF
  93#define ADE9000_REG_EP_CFG		0x4B0
  94#define ADE9000_REG_EGY_TIME		0x4B2
  95#define ADE9000_REG_PGA_GAIN		0x4B9
  96#define ADE9000_REG_VERSION		0x4FE
  97#define ADE9000_REG_WF_BUFF		0x800
  98#define ADE9000_REG_WF_HALF_BUFF	0xC00
  99
 100#define ADE9000_REG_ADDR_MASK		GENMASK(15, 4)
 101#define ADE9000_REG_READ_BIT_MASK	BIT(3)
 102
 103#define ADE9000_WF_CAP_EN_MASK		BIT(4)
 104#define ADE9000_WF_CAP_SEL_MASK		BIT(5)
 105#define ADE9000_WF_MODE_MASK		GENMASK(7, 6)
 106#define ADE9000_WF_SRC_MASK		GENMASK(9, 8)
 107#define ADE9000_WF_IN_EN_MASK		BIT(12)
 108
 109/* External reference selection bit in CONFIG1 */
 110#define ADE9000_EXT_REF_MASK		BIT(15)
 111
 112/*
 113 * Configuration registers
 114 */
 115#define ADE9000_PGA_GAIN		0x0000
 116
 117/* Default configuration */
 118
 119#define ADE9000_CONFIG0			0x00000000
 120
 121/* CF3/ZX pin outputs Zero crossing, CF4 = DREADY */
 122#define ADE9000_CONFIG1			0x000E
 123
 124/* Default High pass corner frequency of 1.25Hz */
 125#define ADE9000_CONFIG2			0x0A00
 126
 127/* Peak and overcurrent detection disabled */
 128#define ADE9000_CONFIG3			0x0000
 129
 130/*
 131 * 50Hz operation, 3P4W Wye configuration, signed accumulation
 132 * 3P4W Wye = 3-Phase 4-Wire star configuration (3 phases + neutral wire)
 133 * Clear bit 8 i.e. ACCMODE=0x00xx for 50Hz operation
 134 * ACCMODE=0x0x9x for 3Wire delta when phase B is used as reference
 135 * 3Wire delta = 3-Phase 3-Wire triangle configuration (3 phases, no neutral)
 136 */
 137#define ADE9000_ACCMODE			0x0000
 138#define ADE9000_ACCMODE_60HZ		0x0100
 139
 140/*Line period and zero crossing obtained from VA */
 141#define ADE9000_ZX_LP_SEL		0x0000
 142
 143/* Interrupt mask values for initialization */
 144#define ADE9000_MASK0_ALL_INT_DIS	0
 145#define ADE9000_MASK1_ALL_INT_DIS	0x00000000
 146
 147/* Events disabled */
 148#define ADE9000_EVENT_DISABLE		0x00000000
 149
 150/*
 151 * Assuming Vnom=1/2 of full scale.
 152 * Refer to Technical reference manual for detailed calculations.
 153 */
 154#define ADE9000_VLEVEL			0x0022EA28
 155
 156/* Set DICOEFF= 0xFFFFE000 when integrator is enabled */
 157#define ADE9000_DICOEFF			0x00000000
 158
 159/* DSP ON */
 160#define ADE9000_RUN_ON			0xFFFFFFFF
 161
 162/*
 163 * Energy Accumulation Settings
 164 * Enable energy accumulation, accumulate samples at 8ksps
 165 * latch energy accumulation after EGYRDY
 166 * If accumulation is changed to half line cycle mode, change EGY_TIME
 167 */
 168#define ADE9000_EP_CFG			0x0011
 169
 170/* Accumulate 4000 samples */
 171#define ADE9000_EGY_TIME		7999
 172
 173/*
 174 * Constant Definitions
 175 * ADE9000 FDSP: 8000sps, ADE9000 FDSP: 4000sps
 176 */
 177#define ADE9000_FDSP			4000
 178#define ADE9000_DEFAULT_CLK_FREQ_HZ	24576000
 179#define ADE9000_WFB_CFG			0x03E9
 180#define ADE9000_WFB_PAGE_SIZE		128
 181#define ADE9000_WFB_NR_OF_PAGES		16
 182#define ADE9000_WFB_MAX_CHANNELS	8
 183#define ADE9000_WFB_BYTES_IN_SAMPLE	4
 184#define ADE9000_WFB_SAMPLES_IN_PAGE	\
 185	(ADE9000_WFB_PAGE_SIZE / ADE9000_WFB_MAX_CHANNELS)
 186#define ADE9000_WFB_MAX_SAMPLES_CHAN	\
 187	(ADE9000_WFB_SAMPLES_IN_PAGE * ADE9000_WFB_NR_OF_PAGES)
 188#define ADE9000_WFB_FULL_BUFF_NR_SAMPLES \
 189	(ADE9000_WFB_PAGE_SIZE * ADE9000_WFB_NR_OF_PAGES)
 190#define ADE9000_WFB_FULL_BUFF_SIZE	\
 191	(ADE9000_WFB_FULL_BUFF_NR_SAMPLES * ADE9000_WFB_BYTES_IN_SAMPLE)
 192
 193#define ADE9000_SWRST_BIT		BIT(0)
 194
 195/* Status and Mask register bits*/
 196#define ADE9000_ST0_WFB_TRIG_BIT	BIT(16)
 197#define ADE9000_ST0_PAGE_FULL_BIT	BIT(17)
 198#define ADE9000_ST0_EGYRDY		BIT(0)
 199
 200#define ADE9000_ST1_ZXTOVA_BIT		BIT(6)
 201#define ADE9000_ST1_ZXTOVB_BIT		BIT(7)
 202#define ADE9000_ST1_ZXTOVC_BIT		BIT(8)
 203#define ADE9000_ST1_ZXVA_BIT		BIT(9)
 204#define ADE9000_ST1_ZXVB_BIT		BIT(10)
 205#define ADE9000_ST1_ZXVC_BIT		BIT(11)
 206#define ADE9000_ST1_ZXIA_BIT		BIT(13)
 207#define ADE9000_ST1_ZXIB_BIT		BIT(14)
 208#define ADE9000_ST1_ZXIC_BIT		BIT(15)
 209#define ADE9000_ST1_RSTDONE_BIT		BIT(16)
 210#define ADE9000_ST1_SEQERR_BIT		BIT(18)
 211#define ADE9000_ST1_SWELLA_BIT		BIT(20)
 212#define ADE9000_ST1_SWELLB_BIT		BIT(21)
 213#define ADE9000_ST1_SWELLC_BIT		BIT(22)
 214#define ADE9000_ST1_DIPA_BIT		BIT(23)
 215#define ADE9000_ST1_DIPB_BIT		BIT(24)
 216#define ADE9000_ST1_DIPC_BIT		BIT(25)
 217#define ADE9000_ST1_ERROR0_BIT		BIT(28)
 218#define ADE9000_ST1_ERROR1_BIT		BIT(29)
 219#define ADE9000_ST1_ERROR2_BIT		BIT(30)
 220#define ADE9000_ST1_ERROR3_BIT		BIT(31)
 221#define ADE9000_ST_ERROR \
 222	(ADE9000_ST1_ERROR0 | ADE9000_ST1_ERROR1 | \
 223	 ADE9000_ST1_ERROR2 | ADE9000_ST1_ERROR3)
 224#define ADE9000_ST1_CROSSING_FIRST	6
 225#define ADE9000_ST1_CROSSING_DEPTH	25
 226
 227#define ADE9000_WFB_TRG_DIP_BIT		BIT(0)
 228#define ADE9000_WFB_TRG_SWELL_BIT	BIT(1)
 229#define ADE9000_WFB_TRG_ZXIA_BIT	BIT(3)
 230#define ADE9000_WFB_TRG_ZXIB_BIT	BIT(4)
 231#define ADE9000_WFB_TRG_ZXIC_BIT	BIT(5)
 232#define ADE9000_WFB_TRG_ZXVA_BIT	BIT(6)
 233#define ADE9000_WFB_TRG_ZXVB_BIT	BIT(7)
 234#define ADE9000_WFB_TRG_ZXVC_BIT	BIT(8)
 235
 236/* Stop when waveform buffer is full */
 237#define ADE9000_WFB_FULL_MODE		0x0
 238/* Continuous fill—stop only on enabled trigger events */
 239#define ADE9000_WFB_EN_TRIG_MODE	0x1
 240/* Continuous filling—center capture around enabled trigger events */
 241#define ADE9000_WFB_C_EN_TRIG_MODE	0x2
 242/* Continuous fill—used as streaming mode for continuous data output */
 243#define ADE9000_WFB_STREAMING_MODE	0x3
 244
 245#define ADE9000_LAST_PAGE_BIT		BIT(15)
 246#define ADE9000_MIDDLE_PAGE_BIT		BIT(7)
 247
 248/*
 249 * Full scale Codes referred from Datasheet. Respective digital codes are
 250 * produced when ADC inputs are at full scale.
 251 */
 252#define ADE9000_RMS_FULL_SCALE_CODES	52866837
 253#define ADE9000_WATT_FULL_SCALE_CODES	20694066
 254#define ADE9000_PCF_FULL_SCALE_CODES	74770000
 255
 256/* Phase and channel definitions */
 257#define ADE9000_PHASE_A_NR		0
 258#define ADE9000_PHASE_B_NR		1
 259#define ADE9000_PHASE_C_NR		2
 260
 261#define ADE9000_SCAN_POS_IA		BIT(0)
 262#define ADE9000_SCAN_POS_VA		BIT(1)
 263#define ADE9000_SCAN_POS_IB		BIT(2)
 264#define ADE9000_SCAN_POS_VB		BIT(3)
 265#define ADE9000_SCAN_POS_IC		BIT(4)
 266#define ADE9000_SCAN_POS_VC		BIT(5)
 267
 268/* Waveform buffer configuration values */
 269enum ade9000_wfb_cfg {
 270	ADE9000_WFB_CFG_ALL_CHAN = 0x0,
 271	ADE9000_WFB_CFG_IA_VA = 0x1,
 272	ADE9000_WFB_CFG_IB_VB = 0x2,
 273	ADE9000_WFB_CFG_IC_VC = 0x3,
 274	ADE9000_WFB_CFG_IA = 0x8,
 275	ADE9000_WFB_CFG_VA = 0x9,
 276	ADE9000_WFB_CFG_IB = 0xA,
 277	ADE9000_WFB_CFG_VB = 0xB,
 278	ADE9000_WFB_CFG_IC = 0xC,
 279	ADE9000_WFB_CFG_VC = 0xD,
 280};
 281
 282#define ADE9000_PHASE_B_POS_BIT		BIT(5)
 283#define ADE9000_PHASE_C_POS_BIT		BIT(6)
 284
 285#define ADE9000_MAX_PHASE_NR		3
 286#define AD9000_CHANNELS_PER_PHASE	10
 287
 288/*
 289 * Calculate register address for multi-phase device.
 290 * Phase A (chan 0): base address + 0x00
 291 * Phase B (chan 1): base address + 0x20
 292 * Phase C (chan 2): base address + 0x40
 293 */
 294#define ADE9000_ADDR_ADJUST(addr, chan)					\
 295	(((chan) == 0 ? 0 : (chan) == 1 ? 2 : 4) << 4 | (addr))
 296
 297struct ade9000_state {
 298	struct completion reset_completion;
 299	struct mutex lock; /* Protects SPI transactions */
 300	u8 wf_src;
 301	u32 wfb_trg;
 302	u8 wfb_nr_activ_chan;
 303	u32 wfb_nr_samples;
 304	struct spi_device *spi;
 305	struct clk *clkin;
 306	struct spi_transfer xfer[2];
 307	struct spi_message spi_msg;
 308	struct regmap *regmap;
 309	union{
 310		u8 byte[ADE9000_WFB_FULL_BUFF_SIZE];
 311		__be32 word[ADE9000_WFB_FULL_BUFF_NR_SAMPLES];
 312	} rx_buff __aligned(IIO_DMA_MINALIGN);
 313	u8 tx_buff[2] __aligned(IIO_DMA_MINALIGN);
 314	unsigned int bulk_read_buf[2];
 315};
 316
 317struct ade9000_irq1_event {
 318	u32 bit_mask;
 319	enum iio_chan_type chan_type;
 320	u32 channel;
 321	enum iio_event_type event_type;
 322	enum iio_event_direction event_dir;
 323};
 324
 325static const struct ade9000_irq1_event ade9000_irq1_events[] = {
 326	{ ADE9000_ST1_ZXVA_BIT, IIO_VOLTAGE, ADE9000_PHASE_A_NR, IIO_EV_TYPE_THRESH, IIO_EV_DIR_EITHER },
 327	{ ADE9000_ST1_ZXIA_BIT, IIO_CURRENT, ADE9000_PHASE_A_NR, IIO_EV_TYPE_THRESH, IIO_EV_DIR_EITHER },
 328	{ ADE9000_ST1_ZXVB_BIT, IIO_VOLTAGE, ADE9000_PHASE_B_NR, IIO_EV_TYPE_THRESH, IIO_EV_DIR_EITHER },
 329	{ ADE9000_ST1_ZXIB_BIT, IIO_CURRENT, ADE9000_PHASE_B_NR, IIO_EV_TYPE_THRESH, IIO_EV_DIR_EITHER },
 330	{ ADE9000_ST1_ZXVC_BIT, IIO_VOLTAGE, ADE9000_PHASE_C_NR, IIO_EV_TYPE_THRESH, IIO_EV_DIR_EITHER },
 331	{ ADE9000_ST1_ZXIC_BIT, IIO_CURRENT, ADE9000_PHASE_C_NR, IIO_EV_TYPE_THRESH, IIO_EV_DIR_EITHER },
 332	{ ADE9000_ST1_SWELLA_BIT, IIO_ALTVOLTAGE, ADE9000_PHASE_A_NR, IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING },
 333	{ ADE9000_ST1_SWELLB_BIT, IIO_ALTVOLTAGE, ADE9000_PHASE_B_NR, IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING },
 334	{ ADE9000_ST1_SWELLC_BIT, IIO_ALTVOLTAGE, ADE9000_PHASE_C_NR, IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING },
 335	{ ADE9000_ST1_DIPA_BIT, IIO_ALTVOLTAGE, ADE9000_PHASE_A_NR, IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING },
 336	{ ADE9000_ST1_DIPB_BIT, IIO_ALTVOLTAGE, ADE9000_PHASE_B_NR, IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING },
 337	{ ADE9000_ST1_DIPC_BIT, IIO_ALTVOLTAGE, ADE9000_PHASE_C_NR, IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING },
 338};
 339
 340/* Voltage events (zero crossing on instantaneous voltage) */
 341static const struct iio_event_spec ade9000_voltage_events[] = {
 342	{
 343		/* Zero crossing detection - datasheet: ZXV interrupts */
 344		.type = IIO_EV_TYPE_THRESH,
 345		.dir = IIO_EV_DIR_EITHER,
 346		.mask_separate = BIT(IIO_EV_INFO_ENABLE),
 347	},
 348};
 349
 350/* Current events (zero crossing on instantaneous current) */
 351static const struct iio_event_spec ade9000_current_events[] = {
 352	{
 353		/* Zero crossing detection - datasheet: ZXI interrupts */
 354		.type = IIO_EV_TYPE_THRESH,
 355		.dir = IIO_EV_DIR_EITHER,
 356		.mask_separate = BIT(IIO_EV_INFO_ENABLE),
 357	},
 358};
 359
 360/* RMS voltage events (swell/sag detection on RMS values) */
 361static const struct iio_event_spec ade9000_rms_voltage_events[] = {
 362	{
 363		.type = IIO_EV_TYPE_THRESH,
 364		.dir = IIO_EV_DIR_RISING, /* RMS swell detection */
 365		.mask_separate = BIT(IIO_EV_INFO_ENABLE) | BIT(IIO_EV_INFO_VALUE),
 366	},
 367	{
 368		.type = IIO_EV_TYPE_THRESH,
 369		.dir = IIO_EV_DIR_FALLING, /* RMS sag/dip detection */
 370		.mask_separate = BIT(IIO_EV_INFO_ENABLE) | BIT(IIO_EV_INFO_VALUE),
 371	},
 372};
 373
 374static const char * const ade9000_filter_type_items[] = {
 375	"sinc4", "sinc4+lp",
 376};
 377
 378static const int ade9000_filter_type_values[] = {
 379	0, 2,
 380};
 381
 382static int ade9000_filter_type_get(struct iio_dev *indio_dev,
 383				   const struct iio_chan_spec *chan)
 384{
 385	struct ade9000_state *st = iio_priv(indio_dev);
 386	u32 val;
 387	int ret;
 388	unsigned int i;
 389
 390	ret = regmap_read(st->regmap, ADE9000_REG_WFB_CFG, &val);
 391	if (ret)
 392		return ret;
 393
 394	val = FIELD_GET(ADE9000_WF_SRC_MASK, val);
 395
 396	for (i = 0; i < ARRAY_SIZE(ade9000_filter_type_values); i++) {
 397		if (ade9000_filter_type_values[i] == val)
 398			return i;
 399	}
 400
 401	return -EINVAL;
 402}
 403
 404static int ade9000_filter_type_set(struct iio_dev *indio_dev,
 405				   const struct iio_chan_spec *chan,
 406				   unsigned int index)
 407{
 408	struct ade9000_state *st = iio_priv(indio_dev);
 409	int ret, val;
 410
 411	if (index >= ARRAY_SIZE(ade9000_filter_type_values))
 412		return -EINVAL;
 413
 414	val = ade9000_filter_type_values[index];
 415
 416	/* Update the WFB_CFG register with the new filter type */
 417	ret = regmap_update_bits(st->regmap, ADE9000_REG_WFB_CFG,
 418				 ADE9000_WF_SRC_MASK,
 419				 FIELD_PREP(ADE9000_WF_SRC_MASK, val));
 420	if (ret)
 421		return ret;
 422
 423	/* Update cached value */
 424	st->wf_src = val;
 425
 426	return 0;
 427}
 428
 429static const struct iio_enum ade9000_filter_type_enum = {
 430	.items = ade9000_filter_type_items,
 431	.num_items = ARRAY_SIZE(ade9000_filter_type_items),
 432	.get = ade9000_filter_type_get,
 433	.set = ade9000_filter_type_set,
 434};
 435
 436static const struct iio_chan_spec_ext_info ade9000_ext_info[] = {
 437	IIO_ENUM("filter_type", IIO_SHARED_BY_ALL, &ade9000_filter_type_enum),
 438	IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_ALL, &ade9000_filter_type_enum),
 439	{ }
 440};
 441
 442#define ADE9000_CURRENT_CHANNEL(num) {					\
 443	.type = IIO_CURRENT,						\
 444	.channel = num,							\
 445	.address = ADE9000_ADDR_ADJUST(ADE9000_REG_AI_PCF, num),	\
 446	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |			\
 447			      BIT(IIO_CHAN_INFO_SCALE) |		\
 448			      BIT(IIO_CHAN_INFO_CALIBSCALE),		\
 449	.event_spec = ade9000_current_events,				\
 450	.num_event_specs = ARRAY_SIZE(ade9000_current_events),		\
 451	.scan_index = num,						\
 452	.indexed = 1,							\
 453	.scan_type = {							\
 454		.sign = 's',						\
 455		.realbits = 32,						\
 456		.storagebits = 32,					\
 457		.endianness = IIO_BE,					\
 458	},								\
 459}
 460
 461#define ADE9000_VOLTAGE_CHANNEL(num) {					\
 462	.type = IIO_VOLTAGE,						\
 463	.channel = num,							\
 464	.address = ADE9000_ADDR_ADJUST(ADE9000_REG_AV_PCF, num),	\
 465	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |			\
 466			      BIT(IIO_CHAN_INFO_SCALE) |		\
 467			      BIT(IIO_CHAN_INFO_CALIBSCALE) |		\
 468			      BIT(IIO_CHAN_INFO_FREQUENCY),		\
 469	.event_spec = ade9000_voltage_events,				\
 470	.num_event_specs = ARRAY_SIZE(ade9000_voltage_events),		\
 471	.scan_index = num + 1,	/* interleave with current channels */	\
 472	.indexed = 1,							\
 473	.scan_type = {							\
 474		.sign = 's',						\
 475		.realbits = 32,						\
 476		.storagebits = 32,					\
 477		.endianness = IIO_BE,					\
 478	},								\
 479	.ext_info = ade9000_ext_info,					\
 480}
 481
 482#define ADE9000_ALTCURRENT_RMS_CHANNEL(num) {				\
 483	.type = IIO_ALTCURRENT,						\
 484	.channel = num,							\
 485	.address = ADE9000_ADDR_ADJUST(ADE9000_REG_AIRMS, num),		\
 486	.channel2 = IIO_MOD_RMS,					\
 487	.modified = 1,							\
 488	.indexed = 1,							\
 489	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |			\
 490			      BIT(IIO_CHAN_INFO_SCALE) |		\
 491			      BIT(IIO_CHAN_INFO_CALIBBIAS),		\
 492	.scan_index = -1						\
 493}
 494
 495#define ADE9000_ALTVOLTAGE_RMS_CHANNEL(num) {				\
 496	.type = IIO_ALTVOLTAGE,						\
 497	.channel = num,							\
 498	.address = ADE9000_ADDR_ADJUST(ADE9000_REG_AVRMS, num),		\
 499	.channel2 = IIO_MOD_RMS,					\
 500	.modified = 1,							\
 501	.indexed = 1,							\
 502	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |			\
 503			      BIT(IIO_CHAN_INFO_SCALE) |		\
 504			      BIT(IIO_CHAN_INFO_CALIBBIAS),		\
 505	.event_spec = ade9000_rms_voltage_events,			\
 506	.num_event_specs = ARRAY_SIZE(ade9000_rms_voltage_events),	\
 507	.scan_index = -1						\
 508}
 509
 510#define ADE9000_POWER_ACTIVE_CHANNEL(num) {				\
 511	.type = IIO_POWER,						\
 512	.channel = num,							\
 513	.address = ADE9000_ADDR_ADJUST(ADE9000_REG_AWATT, num),		\
 514	.channel2 = IIO_MOD_ACTIVE,					\
 515	.modified = 1,							\
 516	.indexed = 1,							\
 517	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |			\
 518			      BIT(IIO_CHAN_INFO_SCALE) |		\
 519			      BIT(IIO_CHAN_INFO_CALIBBIAS) |		\
 520			      BIT(IIO_CHAN_INFO_CALIBSCALE),		\
 521	.scan_index = -1						\
 522}
 523
 524#define ADE9000_POWER_REACTIVE_CHANNEL(num) {				\
 525	.type = IIO_POWER,						\
 526	.channel = num,							\
 527	.address = ADE9000_ADDR_ADJUST(ADE9000_REG_AVAR, num),		\
 528	.channel2 = IIO_MOD_REACTIVE,					\
 529	.modified = 1,							\
 530	.indexed = 1,							\
 531	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |			\
 532			      BIT(IIO_CHAN_INFO_SCALE) |		\
 533			      BIT(IIO_CHAN_INFO_CALIBBIAS),		\
 534	.scan_index = -1						\
 535}
 536
 537#define ADE9000_POWER_APPARENT_CHANNEL(num) {				\
 538	.type = IIO_POWER,						\
 539	.channel = num,							\
 540	.address = ADE9000_ADDR_ADJUST(ADE9000_REG_AVA, num),		\
 541	.channel2 = IIO_MOD_APPARENT,					\
 542	.modified = 1,							\
 543	.indexed = 1,							\
 544	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |			\
 545			      BIT(IIO_CHAN_INFO_SCALE),			\
 546	.scan_index = -1						\
 547}
 548
 549 #define ADE9000_ENERGY_ACTIVE_CHANNEL(num, addr) {			\
 550	.type = IIO_ENERGY,						\
 551	.channel = num,							\
 552	.address = addr,						\
 553	.channel2 = IIO_MOD_ACTIVE,					\
 554	.modified = 1,							\
 555	.indexed = 1,							\
 556	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),			\
 557	.scan_index = -1						\
 558}
 559
 560#define ADE9000_ENERGY_APPARENT_CHANNEL(num, addr) {			\
 561	.type = IIO_ENERGY,						\
 562	.channel = num,							\
 563	.address = addr,						\
 564	.channel2 = IIO_MOD_APPARENT,					\
 565	.modified = 1,							\
 566	.indexed = 1,							\
 567	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),			\
 568	.scan_index = -1						\
 569}
 570
 571#define ADE9000_ENERGY_REACTIVE_CHANNEL(num, addr) {			\
 572	.type = IIO_ENERGY,						\
 573	.channel = num,							\
 574	.address = addr,						\
 575	.channel2 = IIO_MOD_REACTIVE,					\
 576	.modified = 1,							\
 577	.indexed = 1,							\
 578	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),			\
 579	.scan_index = -1						\
 580}
 581
 582#define ADE9000_POWER_FACTOR_CHANNEL(num) {				\
 583	.type = IIO_POWER,						\
 584	.channel = num,							\
 585	.address = ADE9000_ADDR_ADJUST(ADE9000_REG_APF, num),		\
 586	.indexed = 1,							\
 587	.info_mask_separate = BIT(IIO_CHAN_INFO_POWERFACTOR),		\
 588	.scan_index = -1						\
 589}
 590
 591static const struct iio_chan_spec ade9000_channels[] = {
 592	/* Phase A channels */
 593	ADE9000_CURRENT_CHANNEL(ADE9000_PHASE_A_NR),
 594	ADE9000_VOLTAGE_CHANNEL(ADE9000_PHASE_A_NR),
 595	ADE9000_ALTCURRENT_RMS_CHANNEL(ADE9000_PHASE_A_NR),
 596	ADE9000_ALTVOLTAGE_RMS_CHANNEL(ADE9000_PHASE_A_NR),
 597	ADE9000_POWER_ACTIVE_CHANNEL(ADE9000_PHASE_A_NR),
 598	ADE9000_POWER_REACTIVE_CHANNEL(ADE9000_PHASE_A_NR),
 599	ADE9000_POWER_APPARENT_CHANNEL(ADE9000_PHASE_A_NR),
 600	ADE9000_ENERGY_ACTIVE_CHANNEL(ADE9000_PHASE_A_NR, ADE9000_REG_AWATTHR_LO),
 601	ADE9000_ENERGY_APPARENT_CHANNEL(ADE9000_PHASE_A_NR, ADE9000_REG_AVAHR_LO),
 602	ADE9000_ENERGY_REACTIVE_CHANNEL(ADE9000_PHASE_A_NR, ADE9000_REG_AFVARHR_LO),
 603	ADE9000_POWER_FACTOR_CHANNEL(ADE9000_PHASE_A_NR),
 604	/* Phase B channels */
 605	ADE9000_CURRENT_CHANNEL(ADE9000_PHASE_B_NR),
 606	ADE9000_VOLTAGE_CHANNEL(ADE9000_PHASE_B_NR),
 607	ADE9000_ALTCURRENT_RMS_CHANNEL(ADE9000_PHASE_B_NR),
 608	ADE9000_ALTVOLTAGE_RMS_CHANNEL(ADE9000_PHASE_B_NR),
 609	ADE9000_POWER_ACTIVE_CHANNEL(ADE9000_PHASE_B_NR),
 610	ADE9000_POWER_REACTIVE_CHANNEL(ADE9000_PHASE_B_NR),
 611	ADE9000_POWER_APPARENT_CHANNEL(ADE9000_PHASE_B_NR),
 612	ADE9000_ENERGY_ACTIVE_CHANNEL(ADE9000_PHASE_B_NR, ADE9000_REG_BWATTHR_LO),
 613	ADE9000_ENERGY_APPARENT_CHANNEL(ADE9000_PHASE_B_NR, ADE9000_REG_BVAHR_LO),
 614	ADE9000_ENERGY_REACTIVE_CHANNEL(ADE9000_PHASE_B_NR, ADE9000_REG_BFVARHR_LO),
 615	ADE9000_POWER_FACTOR_CHANNEL(ADE9000_PHASE_B_NR),
 616	/* Phase C channels */
 617	ADE9000_CURRENT_CHANNEL(ADE9000_PHASE_C_NR),
 618	ADE9000_VOLTAGE_CHANNEL(ADE9000_PHASE_C_NR),
 619	ADE9000_ALTCURRENT_RMS_CHANNEL(ADE9000_PHASE_C_NR),
 620	ADE9000_ALTVOLTAGE_RMS_CHANNEL(ADE9000_PHASE_C_NR),
 621	ADE9000_POWER_ACTIVE_CHANNEL(ADE9000_PHASE_C_NR),
 622	ADE9000_POWER_REACTIVE_CHANNEL(ADE9000_PHASE_C_NR),
 623	ADE9000_POWER_APPARENT_CHANNEL(ADE9000_PHASE_C_NR),
 624	ADE9000_ENERGY_ACTIVE_CHANNEL(ADE9000_PHASE_C_NR, ADE9000_REG_CWATTHR_LO),
 625	ADE9000_ENERGY_APPARENT_CHANNEL(ADE9000_PHASE_C_NR, ADE9000_REG_CVAHR_LO),
 626	ADE9000_ENERGY_REACTIVE_CHANNEL(ADE9000_PHASE_C_NR, ADE9000_REG_CFVARHR_LO),
 627	ADE9000_POWER_FACTOR_CHANNEL(ADE9000_PHASE_C_NR),
 628};
 629
 630static const struct reg_sequence ade9000_initialization_sequence[] = {
 631	{ ADE9000_REG_PGA_GAIN, ADE9000_PGA_GAIN },
 632	{ ADE9000_REG_CONFIG0, ADE9000_CONFIG0 },
 633	{ ADE9000_REG_CONFIG1, ADE9000_CONFIG1 },
 634	{ ADE9000_REG_CONFIG2, ADE9000_CONFIG2 },
 635	{ ADE9000_REG_CONFIG3, ADE9000_CONFIG3 },
 636	{ ADE9000_REG_ACCMODE, ADE9000_ACCMODE },
 637	{ ADE9000_REG_ZX_LP_SEL, ADE9000_ZX_LP_SEL },
 638	{ ADE9000_REG_MASK0, ADE9000_MASK0_ALL_INT_DIS },
 639	{ ADE9000_REG_MASK1, ADE9000_MASK1_ALL_INT_DIS },
 640	{ ADE9000_REG_EVENT_MASK, ADE9000_EVENT_DISABLE },
 641	{ ADE9000_REG_WFB_CFG, ADE9000_WFB_CFG },
 642	{ ADE9000_REG_VLEVEL, ADE9000_VLEVEL },
 643	{ ADE9000_REG_DICOEFF, ADE9000_DICOEFF },
 644	{ ADE9000_REG_EGY_TIME, ADE9000_EGY_TIME },
 645	{ ADE9000_REG_EP_CFG, ADE9000_EP_CFG },
 646	/* Clear all pending status bits by writing 1s */
 647	{ ADE9000_REG_STATUS0, GENMASK(31, 0) },
 648	{ ADE9000_REG_STATUS1, GENMASK(31, 0) },
 649	{ ADE9000_REG_RUN, ADE9000_RUN_ON }
 650};
 651
 652static int ade9000_spi_write_reg(void *context, unsigned int reg,
 653				 unsigned int val)
 654{
 655	struct ade9000_state *st = context;
 656	u8 tx_buf[6];
 657	u16 addr;
 658	int ret, len;
 659
 660	guard(mutex)(&st->lock);
 661
 662	addr = FIELD_PREP(ADE9000_REG_ADDR_MASK, reg);
 663	put_unaligned_be16(addr, tx_buf);
 664
 665	if (reg > ADE9000_REG_RUN && reg < ADE9000_REG_VERSION) {
 666		put_unaligned_be16(val, &tx_buf[2]);
 667		len = 4;
 668	} else {
 669		put_unaligned_be32(val, &tx_buf[2]);
 670		len = 6;
 671	}
 672
 673	ret = spi_write_then_read(st->spi, tx_buf, len, NULL, 0);
 674	if (ret)
 675		dev_err(&st->spi->dev, "problem when writing register 0x%x\n", reg);
 676
 677	return ret;
 678}
 679
 680static int ade9000_spi_read_reg(void *context, unsigned int reg,
 681				unsigned int *val)
 682{
 683	struct ade9000_state *st = context;
 684	u8 tx_buf[2];
 685	u8 rx_buf[4];
 686	u16 addr;
 687	int ret, rx_len;
 688
 689	guard(mutex)(&st->lock);
 690
 691	addr = FIELD_PREP(ADE9000_REG_ADDR_MASK, reg) |
 692	       ADE9000_REG_READ_BIT_MASK;
 693
 694	put_unaligned_be16(addr, tx_buf);
 695
 696	/* Skip CRC bytes - only read actual data */
 697	if (reg > ADE9000_REG_RUN && reg < ADE9000_REG_VERSION)
 698		rx_len = 2;
 699	else
 700		rx_len = 4;
 701
 702	ret = spi_write_then_read(st->spi, tx_buf, 2, rx_buf, rx_len);
 703	if (ret) {
 704		dev_err(&st->spi->dev, "error reading register 0x%x\n", reg);
 705		return ret;
 706	}
 707
 708	if (reg > ADE9000_REG_RUN && reg < ADE9000_REG_VERSION)
 709		*val = get_unaligned_be16(rx_buf);
 710	else
 711		*val = get_unaligned_be32(rx_buf);
 712
 713	return 0;
 714}
 715
 716static bool ade9000_is_volatile_reg(struct device *dev, unsigned int reg)
 717{
 718	switch (reg) {
 719	/* Interrupt/error status registers - volatile */
 720	case ADE9000_REG_STATUS0:
 721	case ADE9000_REG_STATUS1:
 722		return true;
 723	default:
 724		/* All other registers are non-volatile */
 725		return false;
 726	}
 727}
 728
 729static void ade9000_configure_scan(struct iio_dev *indio_dev, u32 wfb_addr)
 730{
 731	struct ade9000_state *st = iio_priv(indio_dev);
 732	u16 addr;
 733
 734	addr = FIELD_PREP(ADE9000_REG_ADDR_MASK, wfb_addr) |
 735	       ADE9000_REG_READ_BIT_MASK;
 736
 737	put_unaligned_be16(addr, st->tx_buff);
 738
 739	st->xfer[0].tx_buf = &st->tx_buff[0];
 740	st->xfer[0].len = 2;
 741
 742	st->xfer[1].rx_buf = st->rx_buff.byte;
 743
 744	/* Always use streaming mode */
 745	st->xfer[1].len = (st->wfb_nr_samples / 2) * 4;
 746
 747	spi_message_init_with_transfers(&st->spi_msg, st->xfer, ARRAY_SIZE(st->xfer));
 748}
 749
 750static int ade9000_iio_push_streaming(struct iio_dev *indio_dev)
 751{
 752	struct ade9000_state *st = iio_priv(indio_dev);
 753	struct device *dev = &st->spi->dev;
 754	u32 current_page, i;
 755	int ret;
 756
 757	guard(mutex)(&st->lock);
 758
 759	ret = spi_sync(st->spi, &st->spi_msg);
 760	if (ret) {
 761		dev_err_ratelimited(dev, "SPI fail in trigger handler\n");
 762		return ret;
 763	}
 764
 765	/* In streaming mode, only half the buffer is filled per interrupt */
 766	for (i = 0; i < st->wfb_nr_samples / 2; i += st->wfb_nr_activ_chan)
 767		iio_push_to_buffers(indio_dev, &st->rx_buff.word[i]);
 768
 769	ret = regmap_read(st->regmap, ADE9000_REG_WFB_PG_IRQEN, &current_page);
 770	if (ret) {
 771		dev_err_ratelimited(dev, "IRQ0 WFB read fail\n");
 772		return ret;
 773	}
 774
 775	if (current_page & ADE9000_MIDDLE_PAGE_BIT) {
 776		ret = regmap_write(st->regmap, ADE9000_REG_WFB_PG_IRQEN,
 777				   ADE9000_LAST_PAGE_BIT);
 778		if (ret) {
 779			dev_err_ratelimited(dev, "IRQ0 WFB write fail\n");
 780			return ret;
 781		}
 782
 783		ade9000_configure_scan(indio_dev,
 784				       ADE9000_REG_WF_HALF_BUFF);
 785	} else {
 786		ret = regmap_write(st->regmap, ADE9000_REG_WFB_PG_IRQEN,
 787				   ADE9000_MIDDLE_PAGE_BIT);
 788		if (ret) {
 789			dev_err_ratelimited(dev, "IRQ0 WFB write fail");
 790			return ret;
 791		}
 792
 793		ade9000_configure_scan(indio_dev, ADE9000_REG_WF_BUFF);
 794	}
 795
 796	return 0;
 797}
 798
 799static int ade9000_iio_push_buffer(struct iio_dev *indio_dev)
 800{
 801	struct ade9000_state *st = iio_priv(indio_dev);
 802	int ret;
 803	u32 i;
 804
 805	guard(mutex)(&st->lock);
 806
 807	ret = spi_sync(st->spi, &st->spi_msg);
 808	if (ret) {
 809		dev_err_ratelimited(&st->spi->dev,
 810				    "SPI fail in trigger handler\n");
 811		return ret;
 812	}
 813
 814	for (i = 0; i < st->wfb_nr_samples; i += st->wfb_nr_activ_chan)
 815		iio_push_to_buffers(indio_dev, &st->rx_buff.word[i]);
 816
 817	return 0;
 818}
 819
 820static irqreturn_t ade9000_irq0_thread(int irq, void *data)
 821{
 822	struct iio_dev *indio_dev = data;
 823	struct ade9000_state *st = iio_priv(indio_dev);
 824	struct device *dev = &st->spi->dev;
 825	u32 handled_irq = 0;
 826	u32 interrupts, status;
 827	int ret;
 828
 829	ret = regmap_read(st->regmap, ADE9000_REG_STATUS0, &status);
 830	if (ret) {
 831		dev_err_ratelimited(dev, "IRQ0 read status fail\n");
 832		return IRQ_HANDLED;
 833	}
 834
 835	ret = regmap_read(st->regmap, ADE9000_REG_MASK0, &interrupts);
 836	if (ret) {
 837		dev_err_ratelimited(dev, "IRQ0 read mask fail\n");
 838		return IRQ_HANDLED;
 839	}
 840
 841	if ((status & ADE9000_ST0_PAGE_FULL_BIT) &&
 842	    (interrupts & ADE9000_ST0_PAGE_FULL_BIT)) {
 843		/* Always use streaming mode */
 844		ret = ade9000_iio_push_streaming(indio_dev);
 845		if (ret) {
 846			dev_err_ratelimited(dev, "IRQ0 IIO push fail\n");
 847			return IRQ_HANDLED;
 848		}
 849
 850		handled_irq |= ADE9000_ST0_PAGE_FULL_BIT;
 851	}
 852
 853	if ((status & ADE9000_ST0_WFB_TRIG_BIT) &&
 854	    (interrupts & ADE9000_ST0_WFB_TRIG_BIT)) {
 855		ret = regmap_update_bits(st->regmap, ADE9000_REG_WFB_CFG,
 856					 ADE9000_WF_CAP_EN_MASK, 0);
 857		if (ret) {
 858			dev_err_ratelimited(dev, "IRQ0 WFB fail\n");
 859			return IRQ_HANDLED;
 860		}
 861
 862		if (iio_buffer_enabled(indio_dev)) {
 863			ret = ade9000_iio_push_buffer(indio_dev);
 864			if (ret) {
 865				dev_err_ratelimited(dev,
 866						    "IRQ0 IIO push fail @ WFB TRIG\n");
 867				return IRQ_HANDLED;
 868			}
 869		}
 870
 871		handled_irq |= ADE9000_ST0_WFB_TRIG_BIT;
 872	}
 873
 874	ret = regmap_write(st->regmap, ADE9000_REG_STATUS0, handled_irq);
 875	if (ret)
 876		dev_err_ratelimited(dev, "IRQ0 write status fail\n");
 877
 878	return IRQ_HANDLED;
 879}
 880
 881static irqreturn_t ade9000_irq1_thread(int irq, void *data)
 882{
 883	struct iio_dev *indio_dev = data;
 884	struct ade9000_state *st = iio_priv(indio_dev);
 885	unsigned int bit = ADE9000_ST1_CROSSING_FIRST;
 886	s64 timestamp = iio_get_time_ns(indio_dev);
 887	u32 handled_irq = 0;
 888	u32 interrupts, result, status, tmp;
 889	DECLARE_BITMAP(interrupt_bits, ADE9000_ST1_CROSSING_DEPTH);
 890	const struct ade9000_irq1_event *event;
 891	int ret, i;
 892
 893	if (!completion_done(&st->reset_completion)) {
 894		ret = regmap_read(st->regmap, ADE9000_REG_STATUS1, &result);
 895		if (ret) {
 896			dev_err_ratelimited(&st->spi->dev, "IRQ1 read status fail\n");
 897			return IRQ_HANDLED;
 898		}
 899
 900		if (result & ADE9000_ST1_RSTDONE_BIT) {
 901			complete(&st->reset_completion);
 902			/* Clear the reset done status bit */
 903			ret = regmap_write(st->regmap, ADE9000_REG_STATUS1, ADE9000_ST1_RSTDONE_BIT);
 904			if (ret)
 905				dev_err_ratelimited(&st->spi->dev,
 906						    "IRQ1 clear reset status fail\n");
 907		} else {
 908			dev_err_ratelimited(&st->spi->dev,
 909					    "Error testing reset done\n");
 910		}
 911
 912		return IRQ_HANDLED;
 913	}
 914
 915	ret = regmap_read(st->regmap, ADE9000_REG_STATUS1, &status);
 916	if (ret) {
 917		dev_err_ratelimited(&st->spi->dev, "IRQ1 read status fail\n");
 918		return IRQ_HANDLED;
 919	}
 920
 921	ret = regmap_read(st->regmap, ADE9000_REG_MASK1, &interrupts);
 922	if (ret) {
 923		dev_err_ratelimited(&st->spi->dev, "IRQ1 read mask fail\n");
 924		return IRQ_HANDLED;
 925	}
 926
 927	bitmap_from_arr32(interrupt_bits, &interrupts, ADE9000_ST1_CROSSING_DEPTH);
 928	for_each_set_bit_from(bit, interrupt_bits,
 929			      ADE9000_ST1_CROSSING_DEPTH) {
 930		tmp = status & BIT(bit);
 931		if (!tmp)
 932			continue;
 933
 934		event = NULL;
 935
 936		/* Find corresponding event in lookup table */
 937		for (i = 0; i < ARRAY_SIZE(ade9000_irq1_events); i++) {
 938			if (ade9000_irq1_events[i].bit_mask == tmp) {
 939				event = &ade9000_irq1_events[i];
 940				break;
 941			}
 942		}
 943
 944		if (event) {
 945			iio_push_event(indio_dev,
 946				       IIO_UNMOD_EVENT_CODE(event->chan_type,
 947							    event->channel,
 948							    event->event_type,
 949							    event->event_dir),
 950							    timestamp);
 951		}
 952		handled_irq |= tmp;
 953	}
 954
 955	ret = regmap_write(st->regmap, ADE9000_REG_STATUS1, handled_irq);
 956	if (ret)
 957		dev_err_ratelimited(&st->spi->dev, "IRQ1 write status fail\n");
 958
 959	return IRQ_HANDLED;
 960}
 961
 962static irqreturn_t ade9000_dready_thread(int irq, void *data)
 963{
 964	struct iio_dev *indio_dev = data;
 965
 966	/* Handle data ready interrupt from C4/EVENT/DREADY pin */
 967	if (!iio_device_claim_buffer_mode(indio_dev)) {
 968		ade9000_iio_push_buffer(indio_dev);
 969		iio_device_release_buffer_mode(indio_dev);
 970	}
 971
 972	return IRQ_HANDLED;
 973}
 974
 975static int ade9000_read_raw(struct iio_dev *indio_dev,
 976			    struct iio_chan_spec const *chan,
 977			    int *val,
 978			    int *val2,
 979			    long mask)
 980{
 981	struct ade9000_state *st = iio_priv(indio_dev);
 982	unsigned int measured;
 983	int ret;
 984
 985	switch (mask) {
 986	case IIO_CHAN_INFO_FREQUENCY:
 987		if (chan->type == IIO_VOLTAGE) {
 988			int period_reg;
 989			int period;
 990
 991			switch (chan->channel) {
 992			case ADE9000_PHASE_A_NR:
 993				period_reg = ADE9000_REG_APERIOD;
 994				break;
 995			case ADE9000_PHASE_B_NR:
 996				period_reg = ADE9000_REG_BPERIOD;
 997				break;
 998			case ADE9000_PHASE_C_NR:
 999				period_reg = ADE9000_REG_CPERIOD;
1000				break;
1001			default:
1002				return -EINVAL;
1003			}
1004			ret = regmap_read(st->regmap, period_reg, &period);
1005			if (ret)
1006				return ret;
1007			/*
1008			 * Frequency = (4MHz * 65536) / (PERIOD + 1)
1009			 * 4MHz = ADC sample rate, 65536 = 2^16 period register scaling
1010			 * See ADE9000 datasheet section on period measurement
1011			 */
1012			*val = 4000 * 65536;
1013			*val2 = period + 1;
1014			return IIO_VAL_FRACTIONAL;
1015		}
1016
1017		return -EINVAL;
1018	case IIO_CHAN_INFO_RAW:
1019		if (chan->type == IIO_ENERGY) {
1020			u16 lo_reg = chan->address;
1021
1022			ret = regmap_bulk_read(st->regmap, lo_reg,
1023					       st->bulk_read_buf, 2);
1024			if (ret)
1025				return ret;
1026
1027			*val = st->bulk_read_buf[0];  /* Lower 32 bits */
1028			*val2 = st->bulk_read_buf[1]; /* Upper 32 bits */
1029			return IIO_VAL_INT_64;
1030		}
1031
1032		if (!iio_device_claim_direct(indio_dev))
1033			return -EBUSY;
1034
1035		ret = regmap_read(st->regmap, chan->address, &measured);
1036		iio_device_release_direct(indio_dev);
1037		if (ret)
1038			return ret;
1039
1040		*val = measured;
1041
1042		return IIO_VAL_INT;
1043
1044	case IIO_CHAN_INFO_POWERFACTOR:
1045		if (!iio_device_claim_direct(indio_dev))
1046			return -EBUSY;
1047
1048		ret = regmap_read(st->regmap, chan->address, &measured);
1049		iio_device_release_direct(indio_dev);
1050		if (ret)
1051			return ret;
1052
1053		*val = measured;
1054
1055		return IIO_VAL_INT;
1056
1057	case IIO_CHAN_INFO_SCALE:
1058		switch (chan->type) {
1059		case IIO_CURRENT:
1060		case IIO_VOLTAGE:
1061		case IIO_ALTVOLTAGE:
1062		case IIO_ALTCURRENT:
1063			switch (chan->address) {
1064			case ADE9000_REG_AI_PCF:
1065			case ADE9000_REG_AV_PCF:
1066			case ADE9000_REG_BI_PCF:
1067			case ADE9000_REG_BV_PCF:
1068			case ADE9000_REG_CI_PCF:
1069			case ADE9000_REG_CV_PCF:
1070				*val = 1;
1071				*val2 = ADE9000_PCF_FULL_SCALE_CODES;
1072				return IIO_VAL_FRACTIONAL;
1073			case ADE9000_REG_AIRMS:
1074			case ADE9000_REG_AVRMS:
1075			case ADE9000_REG_BIRMS:
1076			case ADE9000_REG_BVRMS:
1077			case ADE9000_REG_CIRMS:
1078			case ADE9000_REG_CVRMS:
1079				*val = 1;
1080				*val2 = ADE9000_RMS_FULL_SCALE_CODES;
1081				return IIO_VAL_FRACTIONAL;
1082			default:
1083				return -EINVAL;
1084			}
1085		case IIO_POWER:
1086			*val = 1;
1087			*val2 = ADE9000_WATT_FULL_SCALE_CODES;
1088			return IIO_VAL_FRACTIONAL;
1089		default:
1090			break;
1091		}
1092
1093		return -EINVAL;
1094	default:
1095		return -EINVAL;
1096	}
1097}
1098
1099static int ade9000_write_raw(struct iio_dev *indio_dev,
1100			     struct iio_chan_spec const *chan,
1101			     int val,
1102			     int val2,
1103			     long mask)
1104{
1105	struct ade9000_state *st = iio_priv(indio_dev);
1106	u32 tmp;
1107
1108	switch (mask) {
1109	case IIO_CHAN_INFO_CALIBBIAS:
1110		switch (chan->type) {
1111		case IIO_CURRENT:
1112			return regmap_write(st->regmap,
1113					    ADE9000_ADDR_ADJUST(ADE9000_REG_AIRMSOS,
1114								chan->channel), val);
1115		case IIO_VOLTAGE:
1116		case IIO_ALTVOLTAGE:
1117			return regmap_write(st->regmap,
1118					    ADE9000_ADDR_ADJUST(ADE9000_REG_AVRMSOS,
1119								chan->channel), val);
1120		case IIO_POWER:
1121			tmp = chan->address;
1122			tmp &= ~ADE9000_PHASE_B_POS_BIT;
1123			tmp &= ~ADE9000_PHASE_C_POS_BIT;
1124
1125			switch (tmp) {
1126			case ADE9000_REG_AWATT:
1127				return regmap_write(st->regmap,
1128						    ADE9000_ADDR_ADJUST(ADE9000_REG_AWATTOS,
1129									chan->channel), val);
1130			case ADE9000_REG_AVAR:
1131				return regmap_write(st->regmap,
1132						    ADE9000_ADDR_ADJUST(ADE9000_REG_AVAROS,
1133									chan->channel), val);
1134			case ADE9000_REG_AFVAR:
1135				return regmap_write(st->regmap,
1136						    ADE9000_ADDR_ADJUST(ADE9000_REG_AFVAROS,
1137									chan->channel), val);
1138			default:
1139				return -EINVAL;
1140			}
1141		default:
1142			return -EINVAL;
1143		}
1144	case IIO_CHAN_INFO_CALIBSCALE:
1145		/*
1146		 * Calibration gain registers for fine-tuning measurements.
1147		 * These are separate from PGA gain and applied in the digital domain.
1148		 */
1149		switch (chan->type) {
1150		case IIO_CURRENT:
1151			return regmap_write(st->regmap,
1152					    ADE9000_ADDR_ADJUST(ADE9000_REG_AIGAIN,
1153								chan->channel), val);
1154		case IIO_VOLTAGE:
1155			return regmap_write(st->regmap,
1156					    ADE9000_ADDR_ADJUST(ADE9000_REG_AVGAIN,
1157								chan->channel), val);
1158		case IIO_POWER:
1159			return regmap_write(st->regmap,
1160					    ADE9000_ADDR_ADJUST(ADE9000_REG_APGAIN,
1161								chan->channel), val);
1162		default:
1163			return -EINVAL;
1164		}
1165	case IIO_CHAN_INFO_SCALE:
1166		/* Per-channel scales are read-only */
1167		return -EINVAL;
1168	default:
1169		return -EINVAL;
1170	}
1171}
1172
1173static int ade9000_reg_access(struct iio_dev *indio_dev,
1174			      unsigned int reg,
1175			      unsigned int tx_val,
1176			      unsigned int *rx_val)
1177{
1178	struct ade9000_state *st = iio_priv(indio_dev);
1179
1180	if (rx_val)
1181		return regmap_read(st->regmap, reg, rx_val);
1182
1183	return regmap_write(st->regmap, reg, tx_val);
1184}
1185
1186static int ade9000_read_event_config(struct iio_dev *indio_dev,
1187				     const struct iio_chan_spec *chan,
1188				     enum iio_event_type type,
1189				     enum iio_event_direction dir)
1190{
1191	struct ade9000_state *st = iio_priv(indio_dev);
1192	u32 interrupts1;
1193	int ret;
1194
1195	/* All events use MASK1 register */
1196	ret = regmap_read(st->regmap, ADE9000_REG_MASK1, &interrupts1);
1197	if (ret)
1198		return ret;
1199
1200	switch (chan->channel) {
1201	case ADE9000_PHASE_A_NR:
1202		if (chan->type == IIO_VOLTAGE && dir == IIO_EV_DIR_EITHER)
1203			return !!(interrupts1 & ADE9000_ST1_ZXVA_BIT);
1204		else if (chan->type == IIO_CURRENT && dir == IIO_EV_DIR_EITHER)
1205			return !!(interrupts1 & ADE9000_ST1_ZXIA_BIT);
1206		else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_RISING)
1207			return !!(interrupts1 & ADE9000_ST1_SWELLA_BIT);
1208		else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_FALLING)
1209			return !!(interrupts1 & ADE9000_ST1_DIPA_BIT);
1210		dev_err_ratelimited(&indio_dev->dev,
1211				    "Invalid channel type %d or direction %d for phase A\n", chan->type, dir);
1212		return -EINVAL;
1213	case ADE9000_PHASE_B_NR:
1214		if (chan->type == IIO_VOLTAGE && dir == IIO_EV_DIR_EITHER)
1215			return !!(interrupts1 & ADE9000_ST1_ZXVB_BIT);
1216		else if (chan->type == IIO_CURRENT && dir == IIO_EV_DIR_EITHER)
1217			return !!(interrupts1 & ADE9000_ST1_ZXIB_BIT);
1218		else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_RISING)
1219			return !!(interrupts1 & ADE9000_ST1_SWELLB_BIT);
1220		else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_FALLING)
1221			return !!(interrupts1 & ADE9000_ST1_DIPB_BIT);
1222		dev_err_ratelimited(&indio_dev->dev,
1223				    "Invalid channel type %d or direction %d for phase B\n", chan->type, dir);
1224		return -EINVAL;
1225	case ADE9000_PHASE_C_NR:
1226		if (chan->type == IIO_VOLTAGE && dir == IIO_EV_DIR_EITHER)
1227			return !!(interrupts1 & ADE9000_ST1_ZXVC_BIT);
1228		else if (chan->type == IIO_CURRENT && dir == IIO_EV_DIR_EITHER)
1229			return !!(interrupts1 & ADE9000_ST1_ZXIC_BIT);
1230		else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_RISING)
1231			return !!(interrupts1 & ADE9000_ST1_SWELLC_BIT);
1232		else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_FALLING)
1233			return !!(interrupts1 & ADE9000_ST1_DIPC_BIT);
1234		dev_err_ratelimited(&indio_dev->dev,
1235				    "Invalid channel type %d or direction %d for phase C\n", chan->type, dir);
1236		return -EINVAL;
1237	default:
1238		return -EINVAL;
1239	}
1240}
1241
1242static int ade9000_write_event_config(struct iio_dev *indio_dev,
1243				      const struct iio_chan_spec *chan,
1244				      enum iio_event_type type,
1245				      enum iio_event_direction dir,
1246				      bool state)
1247{
1248	struct ade9000_state *st = iio_priv(indio_dev);
1249	u32 bit_mask;
1250	int ret;
1251
1252	/* Clear all pending events in STATUS1 register (write 1 to clear) */
1253	ret = regmap_write(st->regmap, ADE9000_REG_STATUS1, GENMASK(31, 0));
1254	if (ret)
1255		return ret;
1256
1257	/* Determine which interrupt bit to enable/disable */
1258	switch (chan->channel) {
1259	case ADE9000_PHASE_A_NR:
1260		if (chan->type == IIO_VOLTAGE && dir == IIO_EV_DIR_EITHER) {
1261			bit_mask = ADE9000_ST1_ZXVA_BIT;
1262			if (state)
1263				st->wfb_trg |= ADE9000_WFB_TRG_ZXVA_BIT;
1264			else
1265				st->wfb_trg &= ~ADE9000_WFB_TRG_ZXVA_BIT;
1266		} else if (chan->type == IIO_CURRENT && dir == IIO_EV_DIR_EITHER) {
1267			bit_mask = ADE9000_ST1_ZXIA_BIT;
1268			if (state)
1269				st->wfb_trg |= ADE9000_WFB_TRG_ZXIA_BIT;
1270			else
1271				st->wfb_trg &= ~ADE9000_WFB_TRG_ZXIA_BIT;
1272		} else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_RISING) {
1273			bit_mask = ADE9000_ST1_SWELLA_BIT;
1274			if (state)
1275				st->wfb_trg |= ADE9000_WFB_TRG_SWELL_BIT;
1276			else
1277				st->wfb_trg &= ~ADE9000_WFB_TRG_SWELL_BIT;
1278		} else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_FALLING) {
1279			bit_mask = ADE9000_ST1_DIPA_BIT;
1280			if (state)
1281				st->wfb_trg |= ADE9000_WFB_TRG_DIP_BIT;
1282			else
1283				st->wfb_trg &= ~ADE9000_WFB_TRG_DIP_BIT;
1284		} else {
1285			dev_err_ratelimited(&indio_dev->dev, "Invalid channel type %d or direction %d for phase A\n",
1286					    chan->type, dir);
1287			return -EINVAL;
1288		}
1289		break;
1290	case ADE9000_PHASE_B_NR:
1291		if (chan->type == IIO_VOLTAGE && dir == IIO_EV_DIR_EITHER) {
1292			bit_mask = ADE9000_ST1_ZXVB_BIT;
1293			if (state)
1294				st->wfb_trg |= ADE9000_WFB_TRG_ZXVB_BIT;
1295			else
1296				st->wfb_trg &= ~ADE9000_WFB_TRG_ZXVB_BIT;
1297		} else if (chan->type == IIO_CURRENT && dir == IIO_EV_DIR_EITHER) {
1298			bit_mask = ADE9000_ST1_ZXIB_BIT;
1299			if (state)
1300				st->wfb_trg |= ADE9000_WFB_TRG_ZXIB_BIT;
1301			else
1302				st->wfb_trg &= ~ADE9000_WFB_TRG_ZXIB_BIT;
1303		} else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_RISING) {
1304			bit_mask = ADE9000_ST1_SWELLB_BIT;
1305			if (state)
1306				st->wfb_trg |= ADE9000_WFB_TRG_SWELL_BIT;
1307			else
1308				st->wfb_trg &= ~ADE9000_WFB_TRG_SWELL_BIT;
1309		} else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_FALLING) {
1310			bit_mask = ADE9000_ST1_DIPB_BIT;
1311			if (state)
1312				st->wfb_trg |= ADE9000_WFB_TRG_DIP_BIT;
1313			else
1314				st->wfb_trg &= ~ADE9000_WFB_TRG_DIP_BIT;
1315		} else {
1316			dev_err_ratelimited(&indio_dev->dev,
1317					    "Invalid channel type %d or direction %d for phase B\n",
1318					    chan->type, dir);
1319			return -EINVAL;
1320		}
1321		break;
1322	case ADE9000_PHASE_C_NR:
1323		if (chan->type == IIO_VOLTAGE && dir == IIO_EV_DIR_EITHER) {
1324			bit_mask = ADE9000_ST1_ZXVC_BIT;
1325			if (state)
1326				st->wfb_trg |= ADE9000_WFB_TRG_ZXVC_BIT;
1327			else
1328				st->wfb_trg &= ~ADE9000_WFB_TRG_ZXVC_BIT;
1329		} else if (chan->type == IIO_CURRENT && dir == IIO_EV_DIR_EITHER) {
1330			bit_mask = ADE9000_ST1_ZXIC_BIT;
1331			if (state)
1332				st->wfb_trg |= ADE9000_WFB_TRG_ZXIC_BIT;
1333			else
1334				st->wfb_trg &= ~ADE9000_WFB_TRG_ZXIC_BIT;
1335		} else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_RISING) {
1336			bit_mask = ADE9000_ST1_SWELLC_BIT;
1337			if (state)
1338				st->wfb_trg |= ADE9000_WFB_TRG_SWELL_BIT;
1339			else
1340				st->wfb_trg &= ~ADE9000_WFB_TRG_SWELL_BIT;
1341		} else if (chan->type == IIO_ALTVOLTAGE && dir == IIO_EV_DIR_FALLING) {
1342			bit_mask = ADE9000_ST1_DIPC_BIT;
1343			if (state)
1344				st->wfb_trg |= ADE9000_WFB_TRG_DIP_BIT;
1345			else
1346				st->wfb_trg &= ~ADE9000_WFB_TRG_DIP_BIT;
1347		} else {
1348			dev_err_ratelimited(&indio_dev->dev,
1349					    "Invalid channel type %d or direction %d for phase C\n",
1350					    chan->type, dir);
1351			return -EINVAL;
1352		}
1353		break;
1354	default:
1355		return -EINVAL;
1356	}
1357
1358	/* Set bits if enabling event, clear bits if disabling */
1359	return regmap_assign_bits(st->regmap, ADE9000_REG_MASK1, bit_mask, state ? bit_mask : 0);
1360}
1361
1362static int ade9000_write_event_value(struct iio_dev *indio_dev,
1363				     const struct iio_chan_spec *chan,
1364				     enum iio_event_type type,
1365				     enum iio_event_direction dir,
1366				     enum iio_event_info info,
1367				     int val, int val2)
1368{
1369	struct ade9000_state *st = iio_priv(indio_dev);
1370
1371	switch (info) {
1372	case IIO_EV_INFO_VALUE:
1373		switch (dir) {
1374		case IIO_EV_DIR_FALLING:
1375			return regmap_write(st->regmap, ADE9000_REG_DIP_LVL, val);
1376		case IIO_EV_DIR_RISING:
1377			return regmap_write(st->regmap, ADE9000_REG_SWELL_LVL, val);
1378		default:
1379			return -EINVAL;
1380		}
1381	default:
1382		return -EINVAL;
1383	}
1384}
1385
1386static int ade9000_read_event_value(struct iio_dev *indio_dev,
1387				    const struct iio_chan_spec *chan,
1388				    enum iio_event_type type,
1389				    enum iio_event_direction dir,
1390				    enum iio_event_info info,
1391				    int *val, int *val2)
1392{
1393	struct ade9000_state *st = iio_priv(indio_dev);
1394	unsigned int data;
1395	int ret;
1396
1397	switch (info) {
1398	case IIO_EV_INFO_VALUE:
1399		switch (dir) {
1400		case IIO_EV_DIR_FALLING:
1401			ret = regmap_read(st->regmap, ADE9000_REG_DIP_LVL, &data);
1402			if (ret)
1403				return ret;
1404			*val = data;
1405			return IIO_VAL_INT;
1406		case IIO_EV_DIR_RISING:
1407			ret = regmap_read(st->regmap, ADE9000_REG_SWELL_LVL, &data);
1408			if (ret)
1409				return ret;
1410			*val = data;
1411			return IIO_VAL_INT;
1412		default:
1413			return -EINVAL;
1414		}
1415	default:
1416		return -EINVAL;
1417	}
1418}
1419
1420static int ade9000_waveform_buffer_config(struct iio_dev *indio_dev)
1421{
1422	struct ade9000_state *st = iio_priv(indio_dev);
1423	u32 wfb_cfg_val;
1424	u32 active_scans;
1425
1426	bitmap_to_arr32(&active_scans, indio_dev->active_scan_mask,
1427			iio_get_masklength(indio_dev));
1428
1429	switch (active_scans) {
1430	case ADE9000_SCAN_POS_IA | ADE9000_SCAN_POS_VA:
1431		wfb_cfg_val = ADE9000_WFB_CFG_IA_VA;
1432		st->wfb_nr_activ_chan = 2;
1433		break;
1434	case ADE9000_SCAN_POS_IB | ADE9000_SCAN_POS_VB:
1435		wfb_cfg_val = ADE9000_WFB_CFG_IB_VB;
1436		st->wfb_nr_activ_chan = 2;
1437		break;
1438	case ADE9000_SCAN_POS_IC | ADE9000_SCAN_POS_VC:
1439		wfb_cfg_val = ADE9000_WFB_CFG_IC_VC;
1440		st->wfb_nr_activ_chan = 2;
1441		break;
1442	case ADE9000_SCAN_POS_IA:
1443		wfb_cfg_val = ADE9000_WFB_CFG_IA;
1444		st->wfb_nr_activ_chan = 1;
1445		break;
1446	case ADE9000_SCAN_POS_VA:
1447		wfb_cfg_val = ADE9000_WFB_CFG_VA;
1448		st->wfb_nr_activ_chan = 1;
1449		break;
1450	case ADE9000_SCAN_POS_IB:
1451		wfb_cfg_val = ADE9000_WFB_CFG_IB;
1452		st->wfb_nr_activ_chan = 1;
1453		break;
1454	case ADE9000_SCAN_POS_VB:
1455		wfb_cfg_val = ADE9000_WFB_CFG_VB;
1456		st->wfb_nr_activ_chan = 1;
1457		break;
1458	case ADE9000_SCAN_POS_IC:
1459		wfb_cfg_val = ADE9000_WFB_CFG_IC;
1460		st->wfb_nr_activ_chan = 1;
1461		break;
1462	case ADE9000_SCAN_POS_VC:
1463		wfb_cfg_val = ADE9000_WFB_CFG_VC;
1464		st->wfb_nr_activ_chan = 1;
1465		break;
1466	case (ADE9000_SCAN_POS_IA | ADE9000_SCAN_POS_VA | ADE9000_SCAN_POS_IB |
1467	      ADE9000_SCAN_POS_VB | ADE9000_SCAN_POS_IC | ADE9000_SCAN_POS_VC):
1468		wfb_cfg_val = ADE9000_WFB_CFG_ALL_CHAN;
1469		st->wfb_nr_activ_chan = 6;
1470		break;
1471	default:
1472		dev_err(&st->spi->dev, "Unsupported combination of scans\n");
1473		return -EINVAL;
1474	}
1475
1476	wfb_cfg_val |= FIELD_PREP(ADE9000_WF_SRC_MASK, st->wf_src);
1477
1478	return regmap_write(st->regmap, ADE9000_REG_WFB_CFG, wfb_cfg_val);
1479}
1480
1481static int ade9000_waveform_buffer_interrupt_setup(struct ade9000_state *st)
1482{
1483	int ret;
1484
1485	ret = regmap_write(st->regmap, ADE9000_REG_WFB_TRG_CFG, 0x0);
1486	if (ret)
1487		return ret;
1488
1489	/* Always use streaming mode setup */
1490	ret = regmap_write(st->regmap, ADE9000_REG_WFB_PG_IRQEN,
1491			   ADE9000_MIDDLE_PAGE_BIT);
1492	if (ret)
1493		return ret;
1494
1495	ret = regmap_write(st->regmap, ADE9000_REG_STATUS0, GENMASK(31, 0));
1496	if (ret)
1497		return ret;
1498
1499	return regmap_set_bits(st->regmap, ADE9000_REG_MASK0,
1500			       ADE9000_ST0_PAGE_FULL_BIT);
1501}
1502
1503static int ade9000_buffer_preenable(struct iio_dev *indio_dev)
1504{
1505	struct ade9000_state *st = iio_priv(indio_dev);
1506	int ret;
1507
1508	ret = ade9000_waveform_buffer_config(indio_dev);
1509	if (ret)
1510		return ret;
1511
1512	st->wfb_nr_samples = ADE9000_WFB_MAX_SAMPLES_CHAN * st->wfb_nr_activ_chan;
1513
1514	ade9000_configure_scan(indio_dev, ADE9000_REG_WF_BUFF);
1515
1516	ret = ade9000_waveform_buffer_interrupt_setup(st);
1517	if (ret)
1518		return ret;
1519
1520	ret = regmap_set_bits(st->regmap, ADE9000_REG_WFB_CFG,
1521			      ADE9000_WF_CAP_EN_MASK);
1522	if (ret) {
1523		dev_err(&st->spi->dev, "Post-enable waveform buffer enable fail\n");
1524		return ret;
1525	}
1526
1527	return 0;
1528}
1529
1530static int ade9000_buffer_postdisable(struct iio_dev *indio_dev)
1531{
1532	struct ade9000_state *st = iio_priv(indio_dev);
1533	struct device *dev = &st->spi->dev;
1534	u32 interrupts;
1535	int ret;
1536
1537	ret = regmap_clear_bits(st->regmap, ADE9000_REG_WFB_CFG,
1538				ADE9000_WF_CAP_EN_MASK);
1539	if (ret) {
1540		dev_err(dev, "Post-disable waveform buffer disable fail\n");
1541		return ret;
1542	}
1543
1544	ret = regmap_write(st->regmap, ADE9000_REG_WFB_TRG_CFG, 0x0);
1545	if (ret)
1546		return ret;
1547
1548	interrupts = ADE9000_ST0_WFB_TRIG_BIT | ADE9000_ST0_PAGE_FULL_BIT;
1549
1550	ret = regmap_clear_bits(st->regmap, ADE9000_REG_MASK0, interrupts);
1551	if (ret) {
1552		dev_err(dev, "Post-disable update maks0 fail\n");
1553		return ret;
1554	}
1555
1556	return regmap_write(st->regmap, ADE9000_REG_STATUS0, GENMASK(31, 0));
1557}
1558
1559static const struct iio_buffer_setup_ops ade9000_buffer_ops = {
1560	.preenable = &ade9000_buffer_preenable,
1561	.postdisable = &ade9000_buffer_postdisable,
1562};
1563
1564static int ade9000_reset(struct ade9000_state *st)
1565{
1566	struct device *dev = &st->spi->dev;
1567	struct gpio_desc *gpio_reset;
1568	int ret;
1569
1570	gpio_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
1571	if (IS_ERR(gpio_reset))
1572		return PTR_ERR(gpio_reset);
1573
1574	/* Software reset via register if no GPIO available */
1575	if (!gpio_reset) {
1576		ret = regmap_set_bits(st->regmap, ADE9000_REG_CONFIG1,
1577				      ADE9000_SWRST_BIT);
1578		if (ret)
1579			return ret;
1580		fsleep(90);
1581		return 0;
1582	}
1583
1584	/* Hardware reset via GPIO */
1585	fsleep(10);
1586	gpiod_set_value_cansleep(gpio_reset, 0);
1587	fsleep(50000);
1588
1589	/* Only wait for completion if IRQ1 is available to signal reset done */
1590	if (fwnode_irq_get_byname(dev_fwnode(dev), "irq1") >= 0) {
1591		if (!wait_for_completion_timeout(&st->reset_completion,
1592						 msecs_to_jiffies(1000))) {
1593			dev_err(dev, "Reset timeout after 1s\n");
1594			return -ETIMEDOUT;
1595		}
1596	}
1597	/* If no IRQ available, reset is already complete after the 50ms delay above */
1598
1599	return 0;
1600}
1601
1602static int ade9000_setup(struct ade9000_state *st)
1603{
1604	struct device *dev = &st->spi->dev;
1605	int ret;
1606
1607	ret = regmap_multi_reg_write(st->regmap, ade9000_initialization_sequence,
1608				     ARRAY_SIZE(ade9000_initialization_sequence));
1609	if (ret)
1610		return dev_err_probe(dev, ret, "Failed to write register sequence");
1611
1612	fsleep(2000);
1613
1614	return 0;
1615}
1616
1617static const struct iio_info ade9000_info = {
1618	.read_raw = ade9000_read_raw,
1619	.write_raw = ade9000_write_raw,
1620	.debugfs_reg_access = ade9000_reg_access,
1621	.write_event_config = ade9000_write_event_config,
1622	.read_event_config = ade9000_read_event_config,
1623	.write_event_value = ade9000_write_event_value,
1624	.read_event_value = ade9000_read_event_value,
1625};
1626
1627static const struct regmap_config ade9000_regmap_config = {
1628	.reg_bits = 16,
1629	.val_bits = 32,
1630	.max_register = 0x6bc,
1631	.zero_flag_mask = true,
1632	.cache_type = REGCACHE_MAPLE,
1633	.reg_read = ade9000_spi_read_reg,
1634	.reg_write = ade9000_spi_write_reg,
1635	.volatile_reg = ade9000_is_volatile_reg,
1636};
1637
1638static int ade9000_setup_clkout(struct device *dev, struct ade9000_state *st)
1639{
1640	struct clk_hw *clkout_hw;
1641	int ret;
1642
1643	if (!IS_ENABLED(CONFIG_COMMON_CLK))
1644		return 0;
1645
1646	/*
1647	 * Only provide clock output when using external CMOS clock.
1648	 * When using crystal, CLKOUT is connected to crystal and shouldn't
1649	 * be used as clock provider for other devices.
1650	 */
1651	if (!device_property_present(dev, "#clock-cells") || !st->clkin)
1652		return 0;
1653
1654	/* CLKOUT passes through CLKIN with divider of 1 */
1655	clkout_hw = devm_clk_hw_register_divider(dev, "clkout", __clk_get_name(st->clkin),
1656						 CLK_SET_RATE_PARENT, NULL, 0, 1, 0, NULL);
1657	if (IS_ERR(clkout_hw))
1658		return dev_err_probe(dev, PTR_ERR(clkout_hw), "Failed to register clkout");
1659
1660	ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, clkout_hw);
1661	if (ret)
1662		return dev_err_probe(dev, ret, "Failed to add clock provider");
1663
1664	return 0;
1665}
1666
1667static int ade9000_request_irq(struct device *dev, const char *name,
1668			       irq_handler_t handler, void *dev_id)
1669{
1670	int irq, ret;
1671
1672	irq = fwnode_irq_get_byname(dev_fwnode(dev), name);
1673	if (irq == -EINVAL)
1674		return 0; /* interrupts are optional */
1675	if (irq < 0)
1676		return dev_err_probe(dev, irq, "Failed to get %s irq", name);
1677
1678	ret = devm_request_threaded_irq(dev, irq, NULL, handler,
1679					IRQF_ONESHOT, KBUILD_MODNAME, dev_id);
1680	if (ret)
1681		return dev_err_probe(dev, ret, "Failed to request %s irq", name);
1682
1683	return 0;
1684}
1685
1686static int ade9000_probe(struct spi_device *spi)
1687{
1688	struct device *dev = &spi->dev;
1689	struct iio_dev *indio_dev;
1690	struct ade9000_state *st;
1691	struct regmap *regmap;
1692	int ret;
1693
1694	indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1695	if (!indio_dev)
1696		return -ENOMEM;
1697
1698	st = iio_priv(indio_dev);
1699
1700	regmap = devm_regmap_init(dev, NULL, st, &ade9000_regmap_config);
1701	if (IS_ERR(regmap))
1702		return dev_err_probe(dev, PTR_ERR(regmap), "Unable to allocate ADE9000 regmap");
1703
1704	st->regmap = regmap;
1705	st->spi = spi;
1706
1707	init_completion(&st->reset_completion);
1708
1709	ret = devm_mutex_init(dev, &st->lock);
1710	if (ret)
1711		return ret;
1712
1713	ret = ade9000_request_irq(dev, "irq0", ade9000_irq0_thread, indio_dev);
1714	if (ret)
1715		return ret;
1716
1717	ret = ade9000_request_irq(dev, "irq1", ade9000_irq1_thread, indio_dev);
1718	if (ret)
1719		return ret;
1720
1721	ret = ade9000_request_irq(dev, "dready", ade9000_dready_thread, indio_dev);
1722	if (ret)
1723		return ret;
1724
1725	/* External CMOS clock input (optional - crystal can be used instead) */
1726	st->clkin = devm_clk_get_optional_enabled(dev, NULL);
1727	if (IS_ERR(st->clkin))
1728		return dev_err_probe(dev, PTR_ERR(st->clkin), "Failed to get and enable clkin");
1729
1730	ret = ade9000_setup_clkout(dev, st);
1731	if (ret)
1732		return ret;
1733
1734	indio_dev->name = "ade9000";
1735	indio_dev->info = &ade9000_info;
1736	indio_dev->modes = INDIO_DIRECT_MODE;
1737	indio_dev->setup_ops = &ade9000_buffer_ops;
1738
1739	ret = devm_regulator_get_enable(&spi->dev, "vdd");
1740	if (ret)
1741		return dev_err_probe(&spi->dev, ret,
1742				     "Failed to get and enable vdd regulator\n");
1743
1744	indio_dev->channels = ade9000_channels;
1745	indio_dev->num_channels = ARRAY_SIZE(ade9000_channels);
1746
1747	ret = devm_iio_kfifo_buffer_setup(dev, indio_dev,
1748					  &ade9000_buffer_ops);
1749	if (ret)
1750		return dev_err_probe(dev, ret, "Failed to setup IIO buffer");
1751
1752	ret = ade9000_reset(st);
1753	if (ret)
1754		return ret;
1755
1756	/* Configure reference selection if vref regulator is available */
1757	ret = devm_regulator_get_enable_optional(dev, "vref");
1758	if (ret != -ENODEV && ret >= 0) {
1759		ret = regmap_set_bits(st->regmap, ADE9000_REG_CONFIG1,
1760				      ADE9000_EXT_REF_MASK);
1761		if (ret)
1762			return ret;
1763	} else if (ret < 0 && ret != -ENODEV) {
1764		return dev_err_probe(dev, ret,
1765				     "Failed to get and enable vref regulator\n");
1766	}
1767
1768	ret = ade9000_setup(st);
1769	if (ret)
1770		return ret;
1771
1772	return devm_iio_device_register(dev, indio_dev);
1773};
1774
1775static const struct spi_device_id ade9000_id[] = {
1776	{ "ade9000", 0 },
1777	{ }
1778};
1779MODULE_DEVICE_TABLE(spi, ade9000_id);
1780
1781static const struct of_device_id ade9000_of_match[] = {
1782	{ .compatible = "adi,ade9000" },
1783	{ }
1784};
1785MODULE_DEVICE_TABLE(of, ade9000_of_match);
1786
1787static struct spi_driver ade9000_driver = {
1788	.driver = {
1789		.name = "ade9000",
1790		.of_match_table = ade9000_of_match,
1791	},
1792	.probe = ade9000_probe,
1793	.id_table = ade9000_id,
1794};
1795module_spi_driver(ade9000_driver);
1796
1797MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com>");
1798MODULE_DESCRIPTION("Analog Devices ADE9000");
1799MODULE_LICENSE("GPL");