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ad9467.c
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linux-6.19.14/drivers/iio/adc/ad9467.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Analog Devices AD9467 SPI ADC driver 4 * 5 * Copyright 2012-2020 Analog Devices Inc. 6 */ 7 8#include <linux/bitmap.h> 9#include <linux/bitops.h> 10#include <linux/cleanup.h> 11#include <linux/debugfs.h> 12#include <linux/module.h> 13#include <linux/mutex.h> 14#include <linux/device.h> 15#include <linux/kernel.h> 16#include <linux/slab.h> 17#include <linux/spi/spi.h> 18#include <linux/seq_file.h> 19#include <linux/err.h> 20#include <linux/delay.h> 21#include <linux/gpio/consumer.h> 22#include <linux/of.h> 23 24 25#include <linux/iio/backend.h> 26#include <linux/iio/iio.h> 27#include <linux/iio/sysfs.h> 28 29#include <linux/clk.h> 30 31/* 32 * ADI High-Speed ADC common spi interface registers 33 * See Application-Note AN-877: 34 * https://www.analog.com/media/en/technical-documentation/application-notes/AN-877.pdf 35 */ 36 37#define AN877_ADC_REG_CHIP_PORT_CONF 0x00 38#define AN877_ADC_REG_CHIP_ID 0x01 39#define AN877_ADC_REG_CHIP_GRADE 0x02 40#define AN877_ADC_REG_CHAN_INDEX 0x05 41#define AN877_ADC_REG_TRANSFER 0xFF 42#define AN877_ADC_REG_MODES 0x08 43#define AN877_ADC_REG_TEST_IO 0x0D 44#define AN877_ADC_REG_ADC_INPUT 0x0F 45#define AN877_ADC_REG_OFFSET 0x10 46#define AN877_ADC_REG_OUTPUT_MODE 0x14 47#define AN877_ADC_REG_OUTPUT_ADJUST 0x15 48#define AN877_ADC_REG_OUTPUT_PHASE 0x16 49#define AN877_ADC_REG_OUTPUT_DELAY 0x17 50#define AN877_ADC_REG_VREF 0x18 51#define AN877_ADC_REG_ANALOG_INPUT 0x2C 52 53/* AN877_ADC_REG_TEST_IO */ 54#define AN877_ADC_TESTMODE_OFF 0x0 55#define AN877_ADC_TESTMODE_MIDSCALE_SHORT 0x1 56#define AN877_ADC_TESTMODE_POS_FULLSCALE 0x2 57#define AN877_ADC_TESTMODE_NEG_FULLSCALE 0x3 58#define AN877_ADC_TESTMODE_ALT_CHECKERBOARD 0x4 59#define AN877_ADC_TESTMODE_PN23_SEQ 0x5 60#define AN877_ADC_TESTMODE_PN9_SEQ 0x6 61#define AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE 0x7 62#define AN877_ADC_TESTMODE_USER 0x8 63#define AN877_ADC_TESTMODE_BIT_TOGGLE 0x9 64#define AN877_ADC_TESTMODE_SYNC 0xA 65#define AN877_ADC_TESTMODE_ONE_BIT_HIGH 0xB 66#define AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY 0xC 67#define AN877_ADC_TESTMODE_RAMP 0xF 68 69/* AN877_ADC_REG_TRANSFER */ 70#define AN877_ADC_TRANSFER_SYNC 0x1 71 72/* AN877_ADC_REG_OUTPUT_MODE */ 73#define AN877_ADC_OUTPUT_MODE_OFFSET_BINARY 0x0 74#define AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT 0x1 75#define AN877_ADC_OUTPUT_MODE_GRAY_CODE 0x2 76 77/* AN877_ADC_REG_OUTPUT_PHASE */ 78#define AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN 0x20 79#define AN877_ADC_INVERT_DCO_CLK 0x80 80 81/* AN877_ADC_REG_OUTPUT_DELAY */ 82#define AN877_ADC_DCO_DELAY_ENABLE 0x80 83 84/* 85 * Analog Devices AD9265 16-Bit, 125/105/80 MSPS ADC 86 */ 87 88#define CHIPID_AD9265 0x64 89#define AD9265_DEF_OUTPUT_MODE 0x40 90#define AD9265_REG_VREF_MASK 0xC0 91 92/* 93 * Analog Devices AD9434 12-Bit, 370/500 MSPS ADC 94 */ 95 96#define CHIPID_AD9434 0x6A 97#define AD9434_DEF_OUTPUT_MODE 0x00 98#define AD9434_REG_VREF_MASK GENMASK(4, 0) 99 100/* 101 * Analog Devices AD9467 16-Bit, 200/250 MSPS ADC 102 */ 103 104#define CHIPID_AD9467 0x50 105#define AD9467_DEF_OUTPUT_MODE 0x08 106#define AD9467_REG_VREF_MASK 0x0F 107 108/* 109 * Analog Devices AD9643 14-Bit, 170/210/250 MSPS ADC 110 */ 111 112#define CHIPID_AD9643 0x82 113#define AD9643_REG_VREF_MASK 0x1F 114 115/* 116 * Analog Devices AD9652 16-bit 310 MSPS ADC 117 */ 118 119#define CHIPID_AD9652 0xC1 120#define AD9652_REG_VREF_MASK 0xC0 121 122/* 123 * Analog Devices AD9649 14-bit 20/40/65/80 MSPS ADC 124 */ 125 126#define CHIPID_AD9649 0x6F 127#define AD9649_TEST_POINTS 8 128 129#define AD9647_MAX_TEST_POINTS 32 130#define AD9467_CAN_INVERT(st) \ 131 (!(st)->info->has_dco || (st)->info->has_dco_invert) 132 133struct ad9467_chip_info { 134 const char *name; 135 unsigned int id; 136 const struct iio_chan_spec *channels; 137 unsigned int num_channels; 138 const unsigned int (*scale_table)[2]; 139 int num_scales; 140 unsigned long test_mask; 141 unsigned int test_mask_len; 142 unsigned long max_rate; 143 unsigned int default_output_mode; 144 unsigned int vref_mask; 145 unsigned int num_lanes; 146 unsigned int dco_en; 147 unsigned int test_points; 148 /* data clock output */ 149 bool has_dco; 150 bool has_dco_invert; 151}; 152 153struct ad9467_chan_test_mode { 154 struct ad9467_state *st; 155 unsigned int idx; 156 u8 mode; 157}; 158 159struct ad9467_state { 160 const struct ad9467_chip_info *info; 161 struct iio_backend *back; 162 struct spi_device *spi; 163 struct clk *clk; 164 /* used for debugfs */ 165 struct ad9467_chan_test_mode *chan_test; 166 unsigned int output_mode; 167 unsigned int (*scales)[2]; 168 /* 169 * Times 2 because we may also invert the signal polarity and run the 170 * calibration again. For some reference on the test points (ad9265) see: 171 * https://www.analog.com/media/en/technical-documentation/data-sheets/ad9265.pdf 172 * at page 38 for the dco output delay. On devices as ad9467, the 173 * calibration is done at the backend level. For the ADI axi-adc: 174 * https://wiki.analog.com/resources/fpga/docs/axi_adc_ip 175 * at the io delay control section. 176 */ 177 DECLARE_BITMAP(calib_map, AD9647_MAX_TEST_POINTS * 2); 178 /* number of bits of the map */ 179 unsigned int calib_map_size; 180 struct gpio_desc *pwrdown_gpio; 181 /* ensure consistent state obtained on multiple related accesses */ 182 struct mutex lock; 183 u8 buf[3] __aligned(IIO_DMA_MINALIGN); 184}; 185 186static int ad9467_spi_read(struct ad9467_state *st, unsigned int reg) 187{ 188 unsigned char tbuf[2], rbuf[1]; 189 int ret; 190 191 tbuf[0] = 0x80 | (reg >> 8); 192 tbuf[1] = reg & 0xFF; 193 194 ret = spi_write_then_read(st->spi, 195 tbuf, ARRAY_SIZE(tbuf), 196 rbuf, ARRAY_SIZE(rbuf)); 197 198 if (ret < 0) 199 return ret; 200 201 return rbuf[0]; 202} 203 204static int ad9467_spi_write(struct ad9467_state *st, unsigned int reg, 205 unsigned int val) 206{ 207 st->buf[0] = reg >> 8; 208 st->buf[1] = reg & 0xFF; 209 st->buf[2] = val; 210 211 return spi_write(st->spi, st->buf, ARRAY_SIZE(st->buf)); 212} 213 214static int ad9467_reg_access(struct iio_dev *indio_dev, unsigned int reg, 215 unsigned int writeval, unsigned int *readval) 216{ 217 struct ad9467_state *st = iio_priv(indio_dev); 218 int ret; 219 220 if (!readval) { 221 guard(mutex)(&st->lock); 222 ret = ad9467_spi_write(st, reg, writeval); 223 if (ret) 224 return ret; 225 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER, 226 AN877_ADC_TRANSFER_SYNC); 227 } 228 229 ret = ad9467_spi_read(st, reg); 230 if (ret < 0) 231 return ret; 232 *readval = ret; 233 234 return 0; 235} 236 237static const unsigned int ad9265_scale_table[][2] = { 238 {1250, 0x00}, {1500, 0x40}, {1750, 0x80}, {2000, 0xC0}, 239}; 240 241static const unsigned int ad9434_scale_table[][2] = { 242 {1600, 0x1C}, {1580, 0x1D}, {1550, 0x1E}, {1520, 0x1F}, {1500, 0x00}, 243 {1470, 0x01}, {1440, 0x02}, {1420, 0x03}, {1390, 0x04}, {1360, 0x05}, 244 {1340, 0x06}, {1310, 0x07}, {1280, 0x08}, {1260, 0x09}, {1230, 0x0A}, 245 {1200, 0x0B}, {1180, 0x0C}, 246}; 247 248static const unsigned int ad9467_scale_table[][2] = { 249 {2000, 0}, {2100, 6}, {2200, 7}, 250 {2300, 8}, {2400, 9}, {2500, 10}, 251}; 252 253static const unsigned int ad9643_scale_table[][2] = { 254 {2087, 0x0F}, {2065, 0x0E}, {2042, 0x0D}, {2020, 0x0C}, {1997, 0x0B}, 255 {1975, 0x0A}, {1952, 0x09}, {1930, 0x08}, {1907, 0x07}, {1885, 0x06}, 256 {1862, 0x05}, {1840, 0x04}, {1817, 0x03}, {1795, 0x02}, {1772, 0x01}, 257 {1750, 0x00}, {1727, 0x1F}, {1704, 0x1E}, {1681, 0x1D}, {1658, 0x1C}, 258 {1635, 0x1B}, {1612, 0x1A}, {1589, 0x19}, {1567, 0x18}, {1544, 0x17}, 259 {1521, 0x16}, {1498, 0x15}, {1475, 0x14}, {1452, 0x13}, {1429, 0x12}, 260 {1406, 0x11}, {1383, 0x10}, 261}; 262 263static const unsigned int ad9649_scale_table[][2] = { 264 {2000, 0}, 265}; 266 267static const unsigned int ad9652_scale_table[][2] = { 268 {1250, 0}, {1125, 1}, {1200, 2}, {1250, 3}, {1000, 5}, 269}; 270 271static void __ad9467_get_scale(struct ad9467_state *st, int index, 272 unsigned int *val, unsigned int *val2) 273{ 274 const struct ad9467_chip_info *info = st->info; 275 const struct iio_chan_spec *chan = &info->channels[0]; 276 unsigned int tmp; 277 278 tmp = (info->scale_table[index][0] * 1000000ULL) >> 279 chan->scan_type.realbits; 280 *val = tmp / 1000000; 281 *val2 = tmp % 1000000; 282} 283 284#define AD9467_CHAN(_chan, avai_mask, _si, _bits, _sign) \ 285{ \ 286 .type = IIO_VOLTAGE, \ 287 .indexed = 1, \ 288 .channel = _chan, \ 289 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 290 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 291 .info_mask_shared_by_type_available = avai_mask, \ 292 .scan_index = _si, \ 293 .scan_type = { \ 294 .sign = _sign, \ 295 .realbits = _bits, \ 296 .storagebits = 16, \ 297 }, \ 298} 299 300static const struct iio_chan_spec ad9434_channels[] = { 301 AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 0, 12, 's'), 302}; 303 304static const struct iio_chan_spec ad9467_channels[] = { 305 AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 0, 16, 's'), 306}; 307 308static const struct iio_chan_spec ad9643_channels[] = { 309 AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 0, 14, 's'), 310 AD9467_CHAN(1, BIT(IIO_CHAN_INFO_SCALE), 1, 14, 's'), 311}; 312 313static const struct iio_chan_spec ad9649_channels[] = { 314 AD9467_CHAN(0, 0, 0, 14, 's'), 315}; 316 317static const struct iio_chan_spec ad9652_channels[] = { 318 AD9467_CHAN(0, BIT(IIO_CHAN_INFO_SCALE), 0, 16, 's'), 319 AD9467_CHAN(1, BIT(IIO_CHAN_INFO_SCALE), 1, 16, 's'), 320}; 321 322static const char * const ad9467_test_modes[] = { 323 [AN877_ADC_TESTMODE_OFF] = "off", 324 [AN877_ADC_TESTMODE_MIDSCALE_SHORT] = "midscale_short", 325 [AN877_ADC_TESTMODE_POS_FULLSCALE] = "pos_fullscale", 326 [AN877_ADC_TESTMODE_NEG_FULLSCALE] = "neg_fullscale", 327 [AN877_ADC_TESTMODE_ALT_CHECKERBOARD] = "checkerboard", 328 [AN877_ADC_TESTMODE_PN23_SEQ] = "prbs23", 329 [AN877_ADC_TESTMODE_PN9_SEQ] = "prbs9", 330 [AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE] = "one_zero_toggle", 331 [AN877_ADC_TESTMODE_USER] = "user", 332 [AN877_ADC_TESTMODE_BIT_TOGGLE] = "bit_toggle", 333 [AN877_ADC_TESTMODE_SYNC] = "sync", 334 [AN877_ADC_TESTMODE_ONE_BIT_HIGH] = "one_bit_high", 335 [AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY] = "mixed_bit_frequency", 336 [AN877_ADC_TESTMODE_RAMP] = "ramp", 337}; 338 339static const struct ad9467_chip_info ad9467_chip_tbl = { 340 .name = "ad9467", 341 .id = CHIPID_AD9467, 342 .max_rate = 250000000UL, 343 .scale_table = ad9467_scale_table, 344 .num_scales = ARRAY_SIZE(ad9467_scale_table), 345 .channels = ad9467_channels, 346 .num_channels = ARRAY_SIZE(ad9467_channels), 347 .test_points = AD9647_MAX_TEST_POINTS, 348 .test_mask = GENMASK(AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE, 349 AN877_ADC_TESTMODE_OFF), 350 .test_mask_len = AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE + 1, 351 .default_output_mode = AD9467_DEF_OUTPUT_MODE, 352 .vref_mask = AD9467_REG_VREF_MASK, 353 .num_lanes = 8, 354}; 355 356static const struct ad9467_chip_info ad9434_chip_tbl = { 357 .name = "ad9434", 358 .id = CHIPID_AD9434, 359 .max_rate = 500000000UL, 360 .scale_table = ad9434_scale_table, 361 .num_scales = ARRAY_SIZE(ad9434_scale_table), 362 .channels = ad9434_channels, 363 .num_channels = ARRAY_SIZE(ad9434_channels), 364 .test_points = AD9647_MAX_TEST_POINTS, 365 .test_mask = GENMASK(AN877_ADC_TESTMODE_USER, AN877_ADC_TESTMODE_OFF), 366 .test_mask_len = AN877_ADC_TESTMODE_USER + 1, 367 .default_output_mode = AD9434_DEF_OUTPUT_MODE, 368 .vref_mask = AD9434_REG_VREF_MASK, 369 .num_lanes = 6, 370}; 371 372static const struct ad9467_chip_info ad9265_chip_tbl = { 373 .name = "ad9265", 374 .id = CHIPID_AD9265, 375 .max_rate = 125000000UL, 376 .scale_table = ad9265_scale_table, 377 .num_scales = ARRAY_SIZE(ad9265_scale_table), 378 .channels = ad9467_channels, 379 .num_channels = ARRAY_SIZE(ad9467_channels), 380 .test_points = AD9647_MAX_TEST_POINTS, 381 .test_mask = GENMASK(AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE, 382 AN877_ADC_TESTMODE_OFF), 383 .test_mask_len = AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE + 1, 384 .default_output_mode = AD9265_DEF_OUTPUT_MODE, 385 .vref_mask = AD9265_REG_VREF_MASK, 386 .has_dco = true, 387 .has_dco_invert = true, 388}; 389 390static const struct ad9467_chip_info ad9643_chip_tbl = { 391 .name = "ad9643", 392 .id = CHIPID_AD9643, 393 .max_rate = 250000000UL, 394 .scale_table = ad9643_scale_table, 395 .num_scales = ARRAY_SIZE(ad9643_scale_table), 396 .channels = ad9643_channels, 397 .num_channels = ARRAY_SIZE(ad9643_channels), 398 .test_points = AD9647_MAX_TEST_POINTS, 399 .test_mask = BIT(AN877_ADC_TESTMODE_RAMP) | 400 GENMASK(AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY, AN877_ADC_TESTMODE_OFF), 401 .test_mask_len = AN877_ADC_TESTMODE_RAMP + 1, 402 .vref_mask = AD9643_REG_VREF_MASK, 403 .has_dco = true, 404 .has_dco_invert = true, 405 .dco_en = AN877_ADC_DCO_DELAY_ENABLE, 406}; 407 408static const struct ad9467_chip_info ad9649_chip_tbl = { 409 .name = "ad9649", 410 .id = CHIPID_AD9649, 411 .max_rate = 80000000UL, 412 .scale_table = ad9649_scale_table, 413 .num_scales = ARRAY_SIZE(ad9649_scale_table), 414 .channels = ad9649_channels, 415 .num_channels = ARRAY_SIZE(ad9649_channels), 416 .test_points = AD9649_TEST_POINTS, 417 .test_mask = GENMASK(AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY, 418 AN877_ADC_TESTMODE_OFF), 419 .test_mask_len = AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY + 1, 420 .has_dco = true, 421 .has_dco_invert = true, 422 .dco_en = AN877_ADC_DCO_DELAY_ENABLE, 423}; 424 425static const struct ad9467_chip_info ad9652_chip_tbl = { 426 .name = "ad9652", 427 .id = CHIPID_AD9652, 428 .max_rate = 310000000UL, 429 .scale_table = ad9652_scale_table, 430 .num_scales = ARRAY_SIZE(ad9652_scale_table), 431 .channels = ad9652_channels, 432 .num_channels = ARRAY_SIZE(ad9652_channels), 433 .test_points = AD9647_MAX_TEST_POINTS, 434 .test_mask = GENMASK(AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE, 435 AN877_ADC_TESTMODE_OFF), 436 .test_mask_len = AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE + 1, 437 .vref_mask = AD9652_REG_VREF_MASK, 438 .has_dco = true, 439}; 440 441static int ad9467_get_scale(struct ad9467_state *st, int *val, int *val2) 442{ 443 const struct ad9467_chip_info *info = st->info; 444 unsigned int vref_val; 445 unsigned int i = 0; 446 int ret; 447 448 /* nothing to read if we only have one possible scale */ 449 if (info->num_scales == 1) 450 goto out_get_scale; 451 452 ret = ad9467_spi_read(st, AN877_ADC_REG_VREF); 453 if (ret < 0) 454 return ret; 455 456 vref_val = ret & info->vref_mask; 457 458 for (i = 0; i < info->num_scales; i++) { 459 if (vref_val == info->scale_table[i][1]) 460 break; 461 } 462 463 if (i == info->num_scales) 464 return -ERANGE; 465 466out_get_scale: 467 __ad9467_get_scale(st, i, val, val2); 468 469 return IIO_VAL_INT_PLUS_MICRO; 470} 471 472static int ad9467_set_scale(struct ad9467_state *st, int val, int val2) 473{ 474 const struct ad9467_chip_info *info = st->info; 475 unsigned int scale_val[2]; 476 unsigned int i; 477 int ret; 478 479 if (val != 0) 480 return -EINVAL; 481 if (info->num_scales == 1) 482 return -EOPNOTSUPP; 483 484 for (i = 0; i < info->num_scales; i++) { 485 __ad9467_get_scale(st, i, &scale_val[0], &scale_val[1]); 486 if (scale_val[0] != val || scale_val[1] != val2) 487 continue; 488 489 guard(mutex)(&st->lock); 490 ret = ad9467_spi_write(st, AN877_ADC_REG_VREF, 491 info->scale_table[i][1]); 492 if (ret < 0) 493 return ret; 494 495 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER, 496 AN877_ADC_TRANSFER_SYNC); 497 } 498 499 return -EINVAL; 500} 501 502static int ad9467_outputmode_set(struct ad9467_state *st, unsigned int mode) 503{ 504 int ret; 505 506 ret = ad9467_spi_write(st, AN877_ADC_REG_OUTPUT_MODE, mode); 507 if (ret < 0) 508 return ret; 509 510 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER, 511 AN877_ADC_TRANSFER_SYNC); 512} 513 514static int ad9467_testmode_set(struct ad9467_state *st, unsigned int chan, 515 unsigned int test_mode) 516{ 517 int ret; 518 519 if (st->info->num_channels > 1) { 520 /* so that the test mode is only applied to one channel */ 521 ret = ad9467_spi_write(st, AN877_ADC_REG_CHAN_INDEX, BIT(chan)); 522 if (ret) 523 return ret; 524 } 525 526 ret = ad9467_spi_write(st, AN877_ADC_REG_TEST_IO, test_mode); 527 if (ret) 528 return ret; 529 530 if (st->info->num_channels > 1) { 531 /* go to default state where all channels get write commands */ 532 ret = ad9467_spi_write(st, AN877_ADC_REG_CHAN_INDEX, 533 GENMASK(st->info->num_channels - 1, 0)); 534 if (ret) 535 return ret; 536 } 537 538 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER, 539 AN877_ADC_TRANSFER_SYNC); 540} 541 542static int ad9467_backend_testmode_on(struct ad9467_state *st, 543 unsigned int chan, 544 enum iio_backend_test_pattern pattern) 545{ 546 struct iio_backend_data_fmt data = { 547 .enable = false, 548 }; 549 int ret; 550 551 ret = iio_backend_data_format_set(st->back, chan, &data); 552 if (ret) 553 return ret; 554 555 ret = iio_backend_test_pattern_set(st->back, chan, pattern); 556 if (ret) 557 return ret; 558 559 return iio_backend_chan_enable(st->back, chan); 560} 561 562static int ad9467_backend_testmode_off(struct ad9467_state *st, 563 unsigned int chan) 564{ 565 struct iio_backend_data_fmt data = { 566 .enable = true, 567 .sign_extend = true, 568 }; 569 int ret; 570 571 ret = iio_backend_chan_disable(st->back, chan); 572 if (ret) 573 return ret; 574 575 ret = iio_backend_test_pattern_set(st->back, chan, 576 IIO_BACKEND_NO_TEST_PATTERN); 577 if (ret) 578 return ret; 579 580 return iio_backend_data_format_set(st->back, chan, &data); 581} 582 583static int ad9647_calibrate_prepare(struct ad9467_state *st) 584{ 585 unsigned int c; 586 int ret; 587 588 ret = ad9467_outputmode_set(st, st->info->default_output_mode); 589 if (ret) 590 return ret; 591 592 for (c = 0; c < st->info->num_channels; c++) { 593 ret = ad9467_testmode_set(st, c, AN877_ADC_TESTMODE_PN9_SEQ); 594 if (ret) 595 return ret; 596 597 ret = ad9467_backend_testmode_on(st, c, 598 IIO_BACKEND_ADI_PRBS_9A); 599 if (ret) 600 return ret; 601 } 602 603 return 0; 604} 605 606static int ad9647_calibrate_polarity_set(struct ad9467_state *st, 607 bool invert) 608{ 609 enum iio_backend_sample_trigger trigger; 610 611 if (st->info->has_dco) { 612 unsigned int phase = AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN; 613 614 if (invert) 615 phase |= AN877_ADC_INVERT_DCO_CLK; 616 617 return ad9467_spi_write(st, AN877_ADC_REG_OUTPUT_PHASE, 618 phase); 619 } 620 621 if (invert) 622 trigger = IIO_BACKEND_SAMPLE_TRIGGER_EDGE_FALLING; 623 else 624 trigger = IIO_BACKEND_SAMPLE_TRIGGER_EDGE_RISING; 625 626 return iio_backend_data_sample_trigger(st->back, trigger); 627} 628 629/* 630 * The idea is pretty simple. Find the max number of successful points in a row 631 * and get the one in the middle. 632 */ 633static unsigned int ad9467_find_optimal_point(const unsigned long *calib_map, 634 unsigned int start, 635 unsigned int nbits, 636 unsigned int *val) 637{ 638 unsigned int bit = start, end, start_cnt, cnt = 0; 639 640 for_each_clear_bitrange_from(bit, end, calib_map, nbits + start) { 641 if (end - bit > cnt) { 642 cnt = end - bit; 643 start_cnt = bit; 644 } 645 } 646 647 if (cnt) 648 *val = start_cnt + cnt / 2; 649 650 return cnt; 651} 652 653static int ad9467_calibrate_apply(struct ad9467_state *st, unsigned int val) 654{ 655 unsigned int lane; 656 int ret; 657 658 if (st->info->has_dco) { 659 ret = ad9467_spi_write(st, AN877_ADC_REG_OUTPUT_DELAY, 660 val | st->info->dco_en); 661 if (ret) 662 return ret; 663 664 return ad9467_spi_write(st, AN877_ADC_REG_TRANSFER, 665 AN877_ADC_TRANSFER_SYNC); 666 } 667 668 for (lane = 0; lane < st->info->num_lanes; lane++) { 669 ret = iio_backend_iodelay_set(st->back, lane, val); 670 if (ret) 671 return ret; 672 } 673 674 return 0; 675} 676 677static int ad9647_calibrate_stop(struct ad9467_state *st) 678{ 679 unsigned int c, mode; 680 int ret; 681 682 for (c = 0; c < st->info->num_channels; c++) { 683 ret = ad9467_backend_testmode_off(st, c); 684 if (ret) 685 return ret; 686 687 ret = ad9467_testmode_set(st, c, AN877_ADC_TESTMODE_OFF); 688 if (ret) 689 return ret; 690 } 691 692 mode = st->info->default_output_mode | AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT; 693 return ad9467_outputmode_set(st, mode); 694} 695 696static int ad9467_calibrate(struct ad9467_state *st) 697{ 698 unsigned int point, val, inv_val, cnt, inv_cnt = 0, c; 699 /* 700 * Half of the bitmap is for the inverted signal. The number of test 701 * points is the same though... 702 */ 703 unsigned int test_points = st->info->test_points; 704 unsigned long sample_rate = clk_get_rate(st->clk); 705 struct device *dev = &st->spi->dev; 706 bool invert = false, stat; 707 int ret; 708 709 /* all points invalid */ 710 bitmap_fill(st->calib_map, st->calib_map_size); 711 712 ret = ad9647_calibrate_prepare(st); 713 if (ret) 714 return ret; 715retune: 716 ret = ad9647_calibrate_polarity_set(st, invert); 717 if (ret) 718 return ret; 719 720 for (point = 0; point < st->info->test_points; point++) { 721 ret = ad9467_calibrate_apply(st, point); 722 if (ret) 723 return ret; 724 725 for (c = 0; c < st->info->num_channels; c++) { 726 ret = iio_backend_chan_status(st->back, c, &stat); 727 if (ret) 728 return ret; 729 730 /* 731 * A point is considered valid if all channels report no 732 * error. If one reports an error, then we consider the 733 * point as invalid and we can break the loop right away. 734 */ 735 if (stat) { 736 dev_dbg(dev, "Invalid point(%u, inv:%u) for CH:%u\n", 737 point, invert, c); 738 break; 739 } 740 741 if (c == st->info->num_channels - 1) 742 __clear_bit(point + invert * test_points, 743 st->calib_map); 744 } 745 } 746 747 if (!invert) { 748 cnt = ad9467_find_optimal_point(st->calib_map, 0, test_points, 749 &val); 750 /* 751 * We're happy if we find, at least, three good test points in 752 * a row. 753 */ 754 if (cnt < 3) { 755 if (AD9467_CAN_INVERT(st)) { 756 invert = true; 757 goto retune; 758 } 759 760 if (!cnt) 761 return -EIO; 762 } 763 } else { 764 inv_cnt = ad9467_find_optimal_point(st->calib_map, test_points, 765 test_points, &inv_val); 766 if (!inv_cnt && !cnt) 767 return -EIO; 768 } 769 770 if (inv_cnt < cnt) { 771 ret = ad9647_calibrate_polarity_set(st, false); 772 if (ret) 773 return ret; 774 } else { 775 /* 776 * polarity inverted is the last test to run. Hence, there's no 777 * need to re-do any configuration. We just need to "normalize" 778 * the selected value. 779 */ 780 val = inv_val - test_points; 781 } 782 783 if (st->info->has_dco) 784 dev_dbg(dev, "%sDCO 0x%X CLK %lu Hz\n", inv_cnt >= cnt ? "INVERT " : "", 785 val, sample_rate); 786 else 787 dev_dbg(dev, "%sIDELAY 0x%x\n", inv_cnt >= cnt ? "INVERT " : "", 788 val); 789 790 ret = ad9467_calibrate_apply(st, val); 791 if (ret) 792 return ret; 793 794 /* finally apply the optimal value */ 795 return ad9647_calibrate_stop(st); 796} 797 798static int ad9467_read_raw(struct iio_dev *indio_dev, 799 struct iio_chan_spec const *chan, 800 int *val, int *val2, long m) 801{ 802 struct ad9467_state *st = iio_priv(indio_dev); 803 804 switch (m) { 805 case IIO_CHAN_INFO_SCALE: 806 return ad9467_get_scale(st, val, val2); 807 case IIO_CHAN_INFO_SAMP_FREQ: 808 *val = clk_get_rate(st->clk); 809 810 return IIO_VAL_INT; 811 default: 812 return -EINVAL; 813 } 814} 815 816static int __ad9467_update_clock(struct ad9467_state *st, long r_clk) 817{ 818 int ret; 819 820 ret = clk_set_rate(st->clk, r_clk); 821 if (ret) 822 return ret; 823 824 guard(mutex)(&st->lock); 825 return ad9467_calibrate(st); 826} 827 828static int ad9467_write_raw(struct iio_dev *indio_dev, 829 struct iio_chan_spec const *chan, 830 int val, int val2, long mask) 831{ 832 struct ad9467_state *st = iio_priv(indio_dev); 833 const struct ad9467_chip_info *info = st->info; 834 unsigned long sample_rate; 835 long r_clk; 836 int ret; 837 838 switch (mask) { 839 case IIO_CHAN_INFO_SCALE: 840 return ad9467_set_scale(st, val, val2); 841 case IIO_CHAN_INFO_SAMP_FREQ: 842 r_clk = clk_round_rate(st->clk, val); 843 if (r_clk < 0 || r_clk > info->max_rate) { 844 dev_warn(&st->spi->dev, 845 "Error setting ADC sample rate %ld", r_clk); 846 return -EINVAL; 847 } 848 849 sample_rate = clk_get_rate(st->clk); 850 /* 851 * clk_set_rate() would also do this but since we would still 852 * need it for avoiding an unnecessary calibration, do it now. 853 */ 854 if (sample_rate == r_clk) 855 return 0; 856 857 if (!iio_device_claim_direct(indio_dev)) 858 return -EBUSY; 859 860 ret = __ad9467_update_clock(st, r_clk); 861 iio_device_release_direct(indio_dev); 862 return ret; 863 default: 864 return -EINVAL; 865 } 866} 867 868static int ad9467_read_avail(struct iio_dev *indio_dev, 869 struct iio_chan_spec const *chan, 870 const int **vals, int *type, int *length, 871 long mask) 872{ 873 struct ad9467_state *st = iio_priv(indio_dev); 874 const struct ad9467_chip_info *info = st->info; 875 876 switch (mask) { 877 case IIO_CHAN_INFO_SCALE: 878 *vals = (const int *)st->scales; 879 *type = IIO_VAL_INT_PLUS_MICRO; 880 /* Values are stored in a 2D matrix */ 881 *length = info->num_scales * 2; 882 return IIO_AVAIL_LIST; 883 default: 884 return -EINVAL; 885 } 886} 887 888static int ad9467_update_scan_mode(struct iio_dev *indio_dev, 889 const unsigned long *scan_mask) 890{ 891 struct ad9467_state *st = iio_priv(indio_dev); 892 unsigned int c; 893 int ret; 894 895 for (c = 0; c < st->info->num_channels; c++) { 896 if (test_bit(c, scan_mask)) 897 ret = iio_backend_chan_enable(st->back, c); 898 else 899 ret = iio_backend_chan_disable(st->back, c); 900 if (ret) 901 return ret; 902 } 903 904 return 0; 905} 906 907static const struct iio_info ad9467_info = { 908 .read_raw = ad9467_read_raw, 909 .write_raw = ad9467_write_raw, 910 .update_scan_mode = ad9467_update_scan_mode, 911 .debugfs_reg_access = ad9467_reg_access, 912 .read_avail = ad9467_read_avail, 913}; 914 915/* Same as above, but without .read_avail */ 916static const struct iio_info ad9467_info_no_read_avail = { 917 .read_raw = ad9467_read_raw, 918 .write_raw = ad9467_write_raw, 919 .update_scan_mode = ad9467_update_scan_mode, 920 .debugfs_reg_access = ad9467_reg_access, 921}; 922 923static int ad9467_scale_fill(struct ad9467_state *st) 924{ 925 const struct ad9467_chip_info *info = st->info; 926 unsigned int i, val1, val2; 927 928 st->scales = devm_kmalloc_array(&st->spi->dev, info->num_scales, 929 sizeof(*st->scales), GFP_KERNEL); 930 if (!st->scales) 931 return -ENOMEM; 932 933 for (i = 0; i < info->num_scales; i++) { 934 __ad9467_get_scale(st, i, &val1, &val2); 935 st->scales[i][0] = val1; 936 st->scales[i][1] = val2; 937 } 938 939 return 0; 940} 941 942static int ad9467_reset(struct device *dev) 943{ 944 struct gpio_desc *gpio; 945 946 gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); 947 if (IS_ERR_OR_NULL(gpio)) 948 return PTR_ERR_OR_ZERO(gpio); 949 950 fsleep(1); 951 gpiod_set_value_cansleep(gpio, 0); 952 fsleep(10 * USEC_PER_MSEC); 953 954 return 0; 955} 956 957static int ad9467_iio_backend_get(struct ad9467_state *st) 958{ 959 struct device *dev = &st->spi->dev; 960 struct device_node *__back; 961 962 st->back = devm_iio_backend_get(dev, NULL); 963 if (!IS_ERR(st->back)) 964 return 0; 965 /* If not found, don't error out as we might have legacy DT property */ 966 if (PTR_ERR(st->back) != -ENOENT) 967 return PTR_ERR(st->back); 968 969 /* 970 * if we don't get the backend using the normal API's, use the legacy 971 * 'adi,adc-dev' property. So we get all nodes with that property, and 972 * look for the one pointing at us. Then we directly lookup that fwnode 973 * on the backend list of registered devices. This is done so we don't 974 * make io-backends mandatory which would break DT ABI. 975 */ 976 for_each_node_with_property(__back, "adi,adc-dev") { 977 struct device_node *__me; 978 979 __me = of_parse_phandle(__back, "adi,adc-dev", 0); 980 if (!__me) 981 continue; 982 983 if (!device_match_of_node(dev, __me)) { 984 of_node_put(__me); 985 continue; 986 } 987 988 of_node_put(__me); 989 st->back = __devm_iio_backend_get_from_fwnode_lookup(dev, 990 of_fwnode_handle(__back)); 991 of_node_put(__back); 992 return PTR_ERR_OR_ZERO(st->back); 993 } 994 995 return -ENODEV; 996} 997 998static int ad9467_test_mode_available_show(struct seq_file *s, void *ignored) 999{ 1000 struct ad9467_state *st = s->private; 1001 unsigned int bit; 1002 1003 for_each_set_bit(bit, &st->info->test_mask, st->info->test_mask_len) 1004 seq_printf(s, "%s\n", ad9467_test_modes[bit]); 1005 1006 return 0; 1007} 1008DEFINE_SHOW_ATTRIBUTE(ad9467_test_mode_available); 1009 1010static ssize_t ad9467_chan_test_mode_read(struct file *file, 1011 char __user *userbuf, size_t count, 1012 loff_t *ppos) 1013{ 1014 struct ad9467_chan_test_mode *chan = file->private_data; 1015 struct ad9467_state *st = chan->st; 1016 char buf[128] = {0}; 1017 size_t len; 1018 int ret; 1019 1020 if (chan->mode == AN877_ADC_TESTMODE_PN9_SEQ || 1021 chan->mode == AN877_ADC_TESTMODE_PN23_SEQ) { 1022 len = scnprintf(buf, sizeof(buf), "Running \"%s\" Test:\n\t", 1023 ad9467_test_modes[chan->mode]); 1024 1025 ret = iio_backend_debugfs_print_chan_status(st->back, chan->idx, 1026 buf + len, 1027 sizeof(buf) - len); 1028 if (ret < 0) 1029 return ret; 1030 len += ret; 1031 } else if (chan->mode == AN877_ADC_TESTMODE_OFF) { 1032 len = scnprintf(buf, sizeof(buf), "No test Running...\n"); 1033 } else { 1034 len = scnprintf(buf, sizeof(buf), "Running \"%s\" Test on CH:%u\n", 1035 ad9467_test_modes[chan->mode], chan->idx); 1036 } 1037 1038 return simple_read_from_buffer(userbuf, count, ppos, buf, len); 1039} 1040 1041static ssize_t ad9467_chan_test_mode_write(struct file *file, 1042 const char __user *userbuf, 1043 size_t count, loff_t *ppos) 1044{ 1045 struct ad9467_chan_test_mode *chan = file->private_data; 1046 struct ad9467_state *st = chan->st; 1047 char test_mode[32] = {0}; 1048 unsigned int mode; 1049 int ret; 1050 1051 ret = simple_write_to_buffer(test_mode, sizeof(test_mode) - 1, ppos, 1052 userbuf, count); 1053 if (ret < 0) 1054 return ret; 1055 1056 for_each_set_bit(mode, &st->info->test_mask, st->info->test_mask_len) { 1057 if (sysfs_streq(test_mode, ad9467_test_modes[mode])) 1058 break; 1059 } 1060 1061 if (mode == st->info->test_mask_len) 1062 return -EINVAL; 1063 1064 guard(mutex)(&st->lock); 1065 1066 if (mode == AN877_ADC_TESTMODE_OFF) { 1067 unsigned int out_mode; 1068 1069 if (chan->mode == AN877_ADC_TESTMODE_PN9_SEQ || 1070 chan->mode == AN877_ADC_TESTMODE_PN23_SEQ) { 1071 ret = ad9467_backend_testmode_off(st, chan->idx); 1072 if (ret) 1073 return ret; 1074 } 1075 1076 ret = ad9467_testmode_set(st, chan->idx, mode); 1077 if (ret) 1078 return ret; 1079 1080 out_mode = st->info->default_output_mode | AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT; 1081 ret = ad9467_outputmode_set(st, out_mode); 1082 if (ret) 1083 return ret; 1084 } else { 1085 ret = ad9467_outputmode_set(st, st->info->default_output_mode); 1086 if (ret) 1087 return ret; 1088 1089 ret = ad9467_testmode_set(st, chan->idx, mode); 1090 if (ret) 1091 return ret; 1092 1093 /* some patterns have a backend matching monitoring block */ 1094 if (mode == AN877_ADC_TESTMODE_PN9_SEQ) { 1095 ret = ad9467_backend_testmode_on(st, chan->idx, 1096 IIO_BACKEND_ADI_PRBS_9A); 1097 if (ret) 1098 return ret; 1099 } else if (mode == AN877_ADC_TESTMODE_PN23_SEQ) { 1100 ret = ad9467_backend_testmode_on(st, chan->idx, 1101 IIO_BACKEND_ADI_PRBS_23A); 1102 if (ret) 1103 return ret; 1104 } 1105 } 1106 1107 chan->mode = mode; 1108 1109 return count; 1110} 1111 1112static const struct file_operations ad9467_chan_test_mode_fops = { 1113 .open = simple_open, 1114 .read = ad9467_chan_test_mode_read, 1115 .write = ad9467_chan_test_mode_write, 1116 .llseek = default_llseek, 1117 .owner = THIS_MODULE, 1118}; 1119 1120static ssize_t ad9467_dump_calib_table(struct file *file, 1121 char __user *userbuf, 1122 size_t count, loff_t *ppos) 1123{ 1124 struct ad9467_state *st = file->private_data; 1125 unsigned int bit; 1126 /* +2 for the newline and +1 for the string termination */ 1127 unsigned char map[AD9647_MAX_TEST_POINTS * 2 + 3]; 1128 ssize_t len = 0; 1129 1130 guard(mutex)(&st->lock); 1131 if (*ppos) 1132 goto out_read; 1133 1134 for (bit = 0; bit < st->calib_map_size; bit++) { 1135 if (AD9467_CAN_INVERT(st) && bit == st->calib_map_size / 2) 1136 len += scnprintf(map + len, sizeof(map) - len, "\n"); 1137 1138 len += scnprintf(map + len, sizeof(map) - len, "%c", 1139 test_bit(bit, st->calib_map) ? 'x' : 'o'); 1140 } 1141 1142 len += scnprintf(map + len, sizeof(map) - len, "\n"); 1143out_read: 1144 return simple_read_from_buffer(userbuf, count, ppos, map, len); 1145} 1146 1147static const struct file_operations ad9467_calib_table_fops = { 1148 .open = simple_open, 1149 .read = ad9467_dump_calib_table, 1150 .llseek = default_llseek, 1151 .owner = THIS_MODULE, 1152}; 1153 1154static void ad9467_debugfs_init(struct iio_dev *indio_dev) 1155{ 1156 struct dentry *d = iio_get_debugfs_dentry(indio_dev); 1157 struct ad9467_state *st = iio_priv(indio_dev); 1158 char attr_name[32]; 1159 unsigned int chan; 1160 1161 if (!IS_ENABLED(CONFIG_DEBUG_FS)) 1162 return; 1163 1164 st->chan_test = devm_kcalloc(&st->spi->dev, st->info->num_channels, 1165 sizeof(*st->chan_test), GFP_KERNEL); 1166 if (!st->chan_test) 1167 return; 1168 1169 debugfs_create_file("calibration_table_dump", 0400, d, st, 1170 &ad9467_calib_table_fops); 1171 1172 for (chan = 0; chan < st->info->num_channels; chan++) { 1173 snprintf(attr_name, sizeof(attr_name), "in_voltage%u_test_mode", 1174 chan); 1175 st->chan_test[chan].idx = chan; 1176 st->chan_test[chan].st = st; 1177 debugfs_create_file(attr_name, 0600, d, &st->chan_test[chan], 1178 &ad9467_chan_test_mode_fops); 1179 } 1180 1181 debugfs_create_file("in_voltage_test_mode_available", 0400, d, st, 1182 &ad9467_test_mode_available_fops); 1183 1184 iio_backend_debugfs_add(st->back, indio_dev); 1185} 1186 1187static int ad9467_probe(struct spi_device *spi) 1188{ 1189 struct iio_dev *indio_dev; 1190 struct ad9467_state *st; 1191 unsigned int id; 1192 int ret; 1193 1194 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 1195 if (!indio_dev) 1196 return -ENOMEM; 1197 1198 st = iio_priv(indio_dev); 1199 st->spi = spi; 1200 1201 st->info = spi_get_device_match_data(spi); 1202 if (!st->info) 1203 return -ENODEV; 1204 1205 st->calib_map_size = st->info->test_points; 1206 if (AD9467_CAN_INVERT(st)) 1207 st->calib_map_size *= 2; 1208 1209 st->clk = devm_clk_get_enabled(&spi->dev, "adc-clk"); 1210 if (IS_ERR(st->clk)) 1211 return PTR_ERR(st->clk); 1212 1213 st->pwrdown_gpio = devm_gpiod_get_optional(&spi->dev, "powerdown", 1214 GPIOD_OUT_LOW); 1215 if (IS_ERR(st->pwrdown_gpio)) 1216 return PTR_ERR(st->pwrdown_gpio); 1217 1218 ret = ad9467_reset(&spi->dev); 1219 if (ret) 1220 return ret; 1221 1222 ret = ad9467_scale_fill(st); 1223 if (ret) 1224 return ret; 1225 1226 id = ad9467_spi_read(st, AN877_ADC_REG_CHIP_ID); 1227 if (id != st->info->id) { 1228 dev_err(&spi->dev, "Mismatch CHIP_ID, got 0x%X, expected 0x%X\n", 1229 id, st->info->id); 1230 return -ENODEV; 1231 } 1232 1233 if (st->info->num_scales > 1) 1234 indio_dev->info = &ad9467_info; 1235 else 1236 indio_dev->info = &ad9467_info_no_read_avail; 1237 indio_dev->name = st->info->name; 1238 indio_dev->channels = st->info->channels; 1239 indio_dev->num_channels = st->info->num_channels; 1240 1241 ret = ad9467_iio_backend_get(st); 1242 if (ret) 1243 return ret; 1244 1245 ret = devm_iio_backend_request_buffer(&spi->dev, st->back, indio_dev); 1246 if (ret) 1247 return ret; 1248 1249 ret = devm_iio_backend_enable(&spi->dev, st->back); 1250 if (ret) 1251 return ret; 1252 1253 ret = ad9467_calibrate(st); 1254 if (ret) 1255 return ret; 1256 1257 ret = devm_iio_device_register(&spi->dev, indio_dev); 1258 if (ret) 1259 return ret; 1260 1261 ad9467_debugfs_init(indio_dev); 1262 1263 return 0; 1264} 1265 1266static const struct of_device_id ad9467_of_match[] = { 1267 { .compatible = "adi,ad9265", .data = &ad9265_chip_tbl, }, 1268 { .compatible = "adi,ad9434", .data = &ad9434_chip_tbl, }, 1269 { .compatible = "adi,ad9467", .data = &ad9467_chip_tbl, }, 1270 { .compatible = "adi,ad9643", .data = &ad9643_chip_tbl, }, 1271 { .compatible = "adi,ad9649", .data = &ad9649_chip_tbl, }, 1272 { .compatible = "adi,ad9652", .data = &ad9652_chip_tbl, }, 1273 { } 1274}; 1275MODULE_DEVICE_TABLE(of, ad9467_of_match); 1276 1277static const struct spi_device_id ad9467_ids[] = { 1278 { "ad9265", (kernel_ulong_t)&ad9265_chip_tbl }, 1279 { "ad9434", (kernel_ulong_t)&ad9434_chip_tbl }, 1280 { "ad9467", (kernel_ulong_t)&ad9467_chip_tbl }, 1281 { "ad9643", (kernel_ulong_t)&ad9643_chip_tbl }, 1282 { "ad9649", (kernel_ulong_t)&ad9649_chip_tbl, }, 1283 { "ad9652", (kernel_ulong_t)&ad9652_chip_tbl, }, 1284 { } 1285}; 1286MODULE_DEVICE_TABLE(spi, ad9467_ids); 1287 1288static struct spi_driver ad9467_driver = { 1289 .driver = { 1290 .name = "ad9467", 1291 .of_match_table = ad9467_of_match, 1292 }, 1293 .probe = ad9467_probe, 1294 .id_table = ad9467_ids, 1295}; 1296module_spi_driver(ad9467_driver); 1297 1298MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 1299MODULE_DESCRIPTION("Analog Devices AD9467 ADC driver"); 1300MODULE_LICENSE("GPL v2"); 1301MODULE_IMPORT_NS("IIO_BACKEND");
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