ad7191.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * AD7191 ADC driver
  4 *
  5 * Copyright 2025 Analog Devices Inc.
  6 */
  7
  8#include <linux/bitfield.h>
  9#include <linux/clk.h>
 10#include <linux/device.h>
 11#include <linux/err.h>
 12#include <linux/gpio/consumer.h>
 13#include <linux/interrupt.h>
 14#include <linux/mod_devicetable.h>
 15#include <linux/mutex.h>
 16#include <linux/property.h>
 17#include <linux/regulator/consumer.h>
 18#include <linux/spi/spi.h>
 19#include <linux/types.h>
 20#include <linux/units.h>
 21
 22#include <linux/iio/adc/ad_sigma_delta.h>
 23#include <linux/iio/iio.h>
 24
 25#define ad_sigma_delta_to_ad7191(sigmad)	\
 26	container_of((sigmad), struct ad7191_state, sd)
 27
 28#define AD7191_TEMP_CODES_PER_DEGREE	2815
 29
 30#define AD7191_CHAN_MASK		BIT(0)
 31#define AD7191_TEMP_MASK		BIT(1)
 32
 33enum ad7191_channel {
 34	AD7191_CH_AIN1_AIN2,
 35	AD7191_CH_AIN3_AIN4,
 36	AD7191_CH_TEMP,
 37};
 38
 39/*
 40 * NOTE:
 41 * The AD7191 features a dual-use data out ready DOUT/RDY output.
 42 * In order to avoid contentions on the SPI bus, it's therefore necessary
 43 * to use SPI bus locking.
 44 *
 45 * The DOUT/RDY output must also be wired to an interrupt-capable GPIO.
 46 *
 47 * The SPI controller's chip select must be connected to the PDOWN pin
 48 * of the ADC. When CS (PDOWN) is high, it powers down the device and
 49 * resets the internal circuitry.
 50 */
 51
 52struct ad7191_state {
 53	struct ad_sigma_delta		sd;
 54	struct mutex			lock; /* Protect device state */
 55
 56	struct gpio_descs		*odr_gpios;
 57	struct gpio_descs		*pga_gpios;
 58	struct gpio_desc		*temp_gpio;
 59	struct gpio_desc		*chan_gpio;
 60
 61	u16				int_vref_mv;
 62	const u32			(*scale_avail)[2];
 63	size_t				scale_avail_size;
 64	u32				scale_index;
 65	const u32			*samp_freq_avail;
 66	size_t				samp_freq_avail_size;
 67	u32				samp_freq_index;
 68
 69	struct clk			*mclk;
 70};
 71
 72static int ad7191_set_channel(struct ad_sigma_delta *sd, unsigned int address)
 73{
 74	struct ad7191_state *st = ad_sigma_delta_to_ad7191(sd);
 75	u8 temp_gpio_val, chan_gpio_val;
 76
 77	if (!FIELD_FIT(AD7191_CHAN_MASK | AD7191_TEMP_MASK, address))
 78		return -EINVAL;
 79
 80	chan_gpio_val = FIELD_GET(AD7191_CHAN_MASK, address);
 81	temp_gpio_val = FIELD_GET(AD7191_TEMP_MASK, address);
 82
 83	gpiod_set_value(st->chan_gpio, chan_gpio_val);
 84	gpiod_set_value(st->temp_gpio, temp_gpio_val);
 85
 86	return 0;
 87}
 88
 89static int ad7191_set_cs(struct ad_sigma_delta *sigma_delta, int assert)
 90{
 91	struct spi_transfer t = {
 92		.len = 0,
 93		.cs_change = assert,
 94	};
 95	struct spi_message m;
 96
 97	spi_message_init_with_transfers(&m, &t, 1);
 98
 99	return spi_sync_locked(sigma_delta->spi, &m);
100}
101
102static int ad7191_set_mode(struct ad_sigma_delta *sd,
103			   enum ad_sigma_delta_mode mode)
104{
105	struct ad7191_state *st = ad_sigma_delta_to_ad7191(sd);
106
107	switch (mode) {
108	case AD_SD_MODE_CONTINUOUS:
109	case AD_SD_MODE_SINGLE:
110		return ad7191_set_cs(&st->sd, 1);
111	case AD_SD_MODE_IDLE:
112		return ad7191_set_cs(&st->sd, 0);
113	default:
114		return -EINVAL;
115	}
116}
117
118static const struct ad_sigma_delta_info ad7191_sigma_delta_info = {
119	.set_channel = ad7191_set_channel,
120	.set_mode = ad7191_set_mode,
121	.has_registers = false,
122};
123
124static int ad7191_init_regulators(struct iio_dev *indio_dev)
125{
126	struct ad7191_state *st = iio_priv(indio_dev);
127	struct device *dev = &st->sd.spi->dev;
128	int ret;
129
130	ret = devm_regulator_get_enable(dev, "avdd");
131	if (ret)
132		return dev_err_probe(dev, ret, "Failed to enable specified AVdd supply\n");
133
134	ret = devm_regulator_get_enable(dev, "dvdd");
135	if (ret)
136		return dev_err_probe(dev, ret, "Failed to enable specified DVdd supply\n");
137
138	ret = devm_regulator_get_enable_read_voltage(dev, "vref");
139	if (ret < 0)
140		return dev_err_probe(dev, ret, "Failed to get Vref voltage\n");
141
142	st->int_vref_mv = ret / 1000;
143
144	return 0;
145}
146
147static int ad7191_config_setup(struct iio_dev *indio_dev)
148{
149	struct ad7191_state *st = iio_priv(indio_dev);
150	struct device *dev = &st->sd.spi->dev;
151	/* Sampling frequencies in Hz, see Table 5 */
152	static const u32 samp_freq[4] = { 120, 60, 50, 10 };
153	/* Gain options, see Table 7 */
154	const u32 gain[4] = { 1, 8, 64, 128 };
155	static u32 scale_buffer[4][2];
156	int odr_value, odr_index = 0, pga_value, pga_index = 0, i, ret;
157	u64 scale_uv;
158
159	st->samp_freq_index = 0;
160	st->scale_index = 0;
161
162	ret = device_property_read_u32(dev, "adi,odr-value", &odr_value);
163	if (ret && ret != -EINVAL)
164		return dev_err_probe(dev, ret, "Failed to get odr value.\n");
165
166	if (ret == -EINVAL) {
167		st->odr_gpios = devm_gpiod_get_array(dev, "odr", GPIOD_OUT_LOW);
168		if (IS_ERR(st->odr_gpios))
169			return dev_err_probe(dev, PTR_ERR(st->odr_gpios),
170					     "Failed to get odr gpios.\n");
171
172		if (st->odr_gpios->ndescs != 2)
173			return dev_err_probe(dev, -EINVAL, "Expected 2 odr gpio pins.\n");
174
175		st->samp_freq_avail = samp_freq;
176		st->samp_freq_avail_size = ARRAY_SIZE(samp_freq);
177	} else {
178		for (i = 0; i < ARRAY_SIZE(samp_freq); i++) {
179			if (odr_value != samp_freq[i])
180				continue;
181			odr_index = i;
182			break;
183		}
184
185		st->samp_freq_avail = &samp_freq[odr_index];
186		st->samp_freq_avail_size = 1;
187
188		st->odr_gpios = NULL;
189	}
190
191	mutex_lock(&st->lock);
192
193	for (i = 0; i < ARRAY_SIZE(scale_buffer); i++) {
194		scale_uv = ((u64)st->int_vref_mv * NANO) >>
195			(indio_dev->channels[0].scan_type.realbits - 1);
196		do_div(scale_uv, gain[i]);
197		scale_buffer[i][1] = do_div(scale_uv, NANO);
198		scale_buffer[i][0] = scale_uv;
199	}
200
201	mutex_unlock(&st->lock);
202
203	ret = device_property_read_u32(dev, "adi,pga-value", &pga_value);
204	if (ret && ret != -EINVAL)
205		return dev_err_probe(dev, ret, "Failed to get pga value.\n");
206
207	if (ret == -EINVAL) {
208		st->pga_gpios = devm_gpiod_get_array(dev, "pga", GPIOD_OUT_LOW);
209		if (IS_ERR(st->pga_gpios))
210			return dev_err_probe(dev, PTR_ERR(st->pga_gpios),
211					     "Failed to get pga gpios.\n");
212
213		if (st->pga_gpios->ndescs != 2)
214			return dev_err_probe(dev, -EINVAL, "Expected 2 pga gpio pins.\n");
215
216		st->scale_avail = scale_buffer;
217		st->scale_avail_size = ARRAY_SIZE(scale_buffer);
218	} else {
219		for (i = 0; i < ARRAY_SIZE(gain); i++) {
220			if (pga_value != gain[i])
221				continue;
222			pga_index = i;
223			break;
224		}
225
226		st->scale_avail = &scale_buffer[pga_index];
227		st->scale_avail_size = 1;
228
229		st->pga_gpios = NULL;
230	}
231
232	st->temp_gpio = devm_gpiod_get(dev, "temp", GPIOD_OUT_LOW);
233	if (IS_ERR(st->temp_gpio))
234		return dev_err_probe(dev, PTR_ERR(st->temp_gpio),
235				     "Failed to get temp gpio.\n");
236
237	st->chan_gpio = devm_gpiod_get(dev, "chan", GPIOD_OUT_LOW);
238	if (IS_ERR(st->chan_gpio))
239		return dev_err_probe(dev, PTR_ERR(st->chan_gpio),
240				     "Failed to get chan gpio.\n");
241
242	return 0;
243}
244
245static int ad7191_clock_setup(struct ad7191_state *st)
246{
247	struct device *dev = &st->sd.spi->dev;
248
249	st->mclk = devm_clk_get_optional_enabled(dev, "mclk");
250	if (IS_ERR(st->mclk))
251		return dev_err_probe(dev, PTR_ERR(st->mclk),
252				     "Failed to get mclk.\n");
253
254	return 0;
255}
256
257static int ad7191_setup(struct iio_dev *indio_dev)
258{
259	struct ad7191_state *st = iio_priv(indio_dev);
260	int ret;
261
262	ret = ad7191_init_regulators(indio_dev);
263	if (ret)
264		return ret;
265
266	ret = ad7191_config_setup(indio_dev);
267	if (ret)
268		return ret;
269
270	return ad7191_clock_setup(st);
271}
272
273static int ad7191_read_raw(struct iio_dev *indio_dev,
274			   struct iio_chan_spec const *chan, int *val,
275			   int *val2, long m)
276{
277	struct ad7191_state *st = iio_priv(indio_dev);
278
279	switch (m) {
280	case IIO_CHAN_INFO_RAW:
281		return ad_sigma_delta_single_conversion(indio_dev, chan, val);
282	case IIO_CHAN_INFO_SCALE:
283		switch (chan->type) {
284		case IIO_VOLTAGE: {
285			guard(mutex)(&st->lock);
286			*val = st->scale_avail[st->scale_index][0];
287			*val2 = st->scale_avail[st->scale_index][1];
288			return IIO_VAL_INT_PLUS_NANO;
289		}
290		case IIO_TEMP:
291			*val = 0;
292			*val2 = NANO / AD7191_TEMP_CODES_PER_DEGREE;
293			return IIO_VAL_INT_PLUS_NANO;
294		default:
295			return -EINVAL;
296		}
297	case IIO_CHAN_INFO_OFFSET:
298		*val = -(1 << (chan->scan_type.realbits - 1));
299		switch (chan->type) {
300		case IIO_VOLTAGE:
301			return IIO_VAL_INT;
302		case IIO_TEMP:
303			*val -= 273 * AD7191_TEMP_CODES_PER_DEGREE;
304			return IIO_VAL_INT;
305		default:
306			return -EINVAL;
307		}
308	case IIO_CHAN_INFO_SAMP_FREQ:
309		*val = st->samp_freq_avail[st->samp_freq_index];
310		return IIO_VAL_INT;
311	default:
312		return -EINVAL;
313	}
314}
315
316static int ad7191_set_gain(struct ad7191_state *st, int gain_index)
317{
318	DECLARE_BITMAP(bitmap, 2) = { };
319
320	st->scale_index = gain_index;
321
322	bitmap_write(bitmap, gain_index, 0, 2);
323
324	return gpiod_multi_set_value_cansleep(st->pga_gpios, bitmap);
325}
326
327static int ad7191_set_samp_freq(struct ad7191_state *st, int samp_freq_index)
328{
329	DECLARE_BITMAP(bitmap, 2) = {};
330
331	st->samp_freq_index = samp_freq_index;
332
333	bitmap_write(bitmap, samp_freq_index, 0, 2);
334
335	return gpiod_multi_set_value_cansleep(st->odr_gpios, bitmap);
336}
337
338static int __ad7191_write_raw(struct ad7191_state *st,
339			      struct iio_chan_spec const *chan,
340			      int val, int val2, long mask)
341{
342	int i;
343
344	switch (mask) {
345	case IIO_CHAN_INFO_SCALE: {
346		if (!st->pga_gpios)
347			return -EPERM;
348		guard(mutex)(&st->lock);
349		for (i = 0; i < st->scale_avail_size; i++) {
350			if (val2 == st->scale_avail[i][1])
351				return ad7191_set_gain(st, i);
352		}
353		return -EINVAL;
354	}
355	case IIO_CHAN_INFO_SAMP_FREQ: {
356		if (!st->odr_gpios)
357			return -EPERM;
358		guard(mutex)(&st->lock);
359		for (i = 0; i < st->samp_freq_avail_size; i++) {
360			if (val == st->samp_freq_avail[i])
361				return ad7191_set_samp_freq(st, i);
362		}
363		return -EINVAL;
364	}
365	default:
366		return -EINVAL;
367	}
368}
369
370static int ad7191_write_raw(struct iio_dev *indio_dev,
371			    struct iio_chan_spec const *chan, int val, int val2,
372			    long mask)
373{
374	struct ad7191_state *st = iio_priv(indio_dev);
375	int ret;
376
377	if (!iio_device_claim_direct(indio_dev))
378		return -EBUSY;
379
380	ret = __ad7191_write_raw(st, chan, val, val2, mask);
381
382	iio_device_release_direct(indio_dev);
383
384	return ret;
385}
386
387static int ad7191_write_raw_get_fmt(struct iio_dev *indio_dev,
388				    struct iio_chan_spec const *chan, long mask)
389{
390	switch (mask) {
391	case IIO_CHAN_INFO_SCALE:
392		return IIO_VAL_INT_PLUS_NANO;
393	case IIO_CHAN_INFO_SAMP_FREQ:
394		return IIO_VAL_INT;
395	default:
396		return -EINVAL;
397	}
398}
399
400static int ad7191_read_avail(struct iio_dev *indio_dev,
401			     struct iio_chan_spec const *chan, const int **vals,
402			     int *type, int *length, long mask)
403{
404	struct ad7191_state *st = iio_priv(indio_dev);
405
406	switch (mask) {
407	case IIO_CHAN_INFO_SCALE:
408		*vals = (int *)st->scale_avail;
409		*type = IIO_VAL_INT_PLUS_NANO;
410		*length = st->scale_avail_size * 2;
411		return IIO_AVAIL_LIST;
412	case IIO_CHAN_INFO_SAMP_FREQ:
413		*vals = (int *)st->samp_freq_avail;
414		*type = IIO_VAL_INT;
415		*length = st->samp_freq_avail_size;
416		return IIO_AVAIL_LIST;
417	}
418
419	return -EINVAL;
420}
421
422static const struct iio_info ad7191_info = {
423	.read_raw = ad7191_read_raw,
424	.write_raw = ad7191_write_raw,
425	.write_raw_get_fmt = ad7191_write_raw_get_fmt,
426	.read_avail = ad7191_read_avail,
427	.validate_trigger = ad_sd_validate_trigger,
428};
429
430static const struct iio_chan_spec ad7191_channels[] = {
431	{
432		.type = IIO_TEMP,
433		.address = AD7191_CH_TEMP,
434		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
435				      BIT(IIO_CHAN_INFO_OFFSET) |
436				      BIT(IIO_CHAN_INFO_SAMP_FREQ),
437		.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
438		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
439		.scan_type = {
440			.sign = 'u',
441			.realbits = 24,
442			.storagebits = 32,
443			.endianness = IIO_BE,
444		},
445	},
446	{
447		.type = IIO_VOLTAGE,
448		.differential = 1,
449		.indexed = 1,
450		.channel = 1,
451		.channel2 = 2,
452		.address = AD7191_CH_AIN1_AIN2,
453		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
454				      BIT(IIO_CHAN_INFO_OFFSET) |
455				      BIT(IIO_CHAN_INFO_SAMP_FREQ),
456		.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
457		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
458		.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE),
459		.scan_index = 1,
460		.scan_type = {
461			.sign = 'u',
462			.realbits = 24,
463			.storagebits = 32,
464			.endianness = IIO_BE,
465		},
466	},
467	{
468		.type = IIO_VOLTAGE,
469		.differential = 1,
470		.indexed = 1,
471		.channel = 3,
472		.channel2 = 4,
473		.address = AD7191_CH_AIN3_AIN4,
474		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
475				      BIT(IIO_CHAN_INFO_OFFSET) |
476				      BIT(IIO_CHAN_INFO_SAMP_FREQ),
477		.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
478		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
479		.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE),
480		.scan_index = 2,
481		.scan_type = {
482			.sign = 'u',
483			.realbits = 24,
484			.storagebits = 32,
485			.endianness = IIO_BE,
486		},
487	},
488	IIO_CHAN_SOFT_TIMESTAMP(3),
489};
490
491static int ad7191_probe(struct spi_device *spi)
492{
493	struct device *dev = &spi->dev;
494	struct ad7191_state *st;
495	struct iio_dev *indio_dev;
496	int ret;
497
498	indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
499	if (!indio_dev)
500		return -ENOMEM;
501
502	st = iio_priv(indio_dev);
503
504	ret = devm_mutex_init(dev, &st->lock);
505	if (ret)
506		return ret;
507
508	indio_dev->name = "ad7191";
509	indio_dev->modes = INDIO_DIRECT_MODE;
510	indio_dev->channels = ad7191_channels;
511	indio_dev->num_channels = ARRAY_SIZE(ad7191_channels);
512	indio_dev->info = &ad7191_info;
513
514	ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7191_sigma_delta_info);
515	if (ret)
516		return ret;
517
518	ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev);
519	if (ret)
520		return ret;
521
522	ret = ad7191_setup(indio_dev);
523	if (ret)
524		return ret;
525
526	return devm_iio_device_register(dev, indio_dev);
527}
528
529static const struct of_device_id ad7191_of_match[] = {
530	{ .compatible = "adi,ad7191", },
531	{ }
532};
533MODULE_DEVICE_TABLE(of, ad7191_of_match);
534
535static const struct spi_device_id ad7191_id_table[] = {
536	{ "ad7191" },
537	{ }
538};
539MODULE_DEVICE_TABLE(spi, ad7191_id_table);
540
541static struct spi_driver ad7191_driver = {
542	.driver = {
543		.name = "ad7191",
544		.of_match_table = ad7191_of_match,
545	},
546	.probe = ad7191_probe,
547	.id_table = ad7191_id_table,
548};
549module_spi_driver(ad7191_driver);
550
551MODULE_AUTHOR("Alisa-Dariana Roman <alisa.roman@analog.com>");
552MODULE_DESCRIPTION("Analog Devices AD7191 ADC");
553MODULE_LICENSE("GPL");
554MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA");