ad7173.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * AD717x and AD411x family SPI ADC driver
   4 *
   5 * Supported devices:
   6 *  AD4111/AD4112/AD4113/AD4114/AD4115/AD4116
   7 *  AD7172-2/AD7172-4/AD7173-8/AD7175-2
   8 *  AD7175-8/AD7176-2/AD7177-2
   9 *
  10 * Copyright (C) 2015, 2024 Analog Devices, Inc.
  11 * Copyright (C) 2025 BayLibre, SAS
  12 */
  13
  14#include <linux/array_size.h>
  15#include <linux/bitfield.h>
  16#include <linux/bitmap.h>
  17#include <linux/container_of.h>
  18#include <linux/clk.h>
  19#include <linux/clk-provider.h>
  20#include <linux/delay.h>
  21#include <linux/device.h>
  22#include <linux/err.h>
  23#include <linux/gpio/driver.h>
  24#include <linux/gpio/regmap.h>
  25#include <linux/idr.h>
  26#include <linux/interrupt.h>
  27#include <linux/math64.h>
  28#include <linux/module.h>
  29#include <linux/mod_devicetable.h>
  30#include <linux/property.h>
  31#include <linux/regmap.h>
  32#include <linux/regulator/consumer.h>
  33#include <linux/slab.h>
  34#include <linux/spi/spi.h>
  35#include <linux/types.h>
  36#include <linux/units.h>
  37
  38#include <linux/iio/buffer.h>
  39#include <linux/iio/events.h>
  40#include <linux/iio/iio.h>
  41#include <linux/iio/trigger_consumer.h>
  42#include <linux/iio/triggered_buffer.h>
  43
  44#include <linux/iio/adc/ad_sigma_delta.h>
  45
  46#define AD7173_REG_COMMS		0x00
  47#define AD7173_REG_ADC_MODE		0x01
  48#define AD7173_REG_INTERFACE_MODE	0x02
  49#define AD7173_REG_CRC			0x03
  50#define AD7173_REG_DATA			0x04
  51#define AD7173_REG_GPIO			0x06
  52#define AD7173_REG_ID			0x07
  53#define AD7173_REG_CH(x)		(0x10 + (x))
  54#define AD7173_REG_SETUP(x)		(0x20 + (x))
  55#define AD7173_REG_FILTER(x)		(0x28 + (x))
  56#define AD7173_REG_OFFSET(x)		(0x30 + (x))
  57#define AD7173_REG_GAIN(x)		(0x38 + (x))
  58
  59#define AD7173_RESET_LENGTH		BITS_TO_BYTES(64)
  60
  61#define AD7173_CH_ENABLE		BIT(15)
  62#define AD7173_CH_SETUP_SEL_MASK	GENMASK(14, 12)
  63#define AD7173_CH_SETUP_AINPOS_MASK	GENMASK(9, 5)
  64#define AD7173_CH_SETUP_AINNEG_MASK	GENMASK(4, 0)
  65
  66#define AD7173_NO_AINS_PER_CHANNEL	2
  67#define AD7173_CH_ADDRESS(pos, neg) \
  68	(FIELD_PREP(AD7173_CH_SETUP_AINPOS_MASK, pos) | \
  69	 FIELD_PREP(AD7173_CH_SETUP_AINNEG_MASK, neg))
  70#define AD7173_AIN_TEMP_POS	17
  71#define AD7173_AIN_TEMP_NEG	18
  72#define AD7173_AIN_POW_MON_POS	19
  73#define AD7173_AIN_POW_MON_NEG	20
  74#define AD7173_AIN_REF_POS	21
  75#define AD7173_AIN_REF_NEG	22
  76
  77#define AD7173_IS_REF_INPUT(x)		((x) == AD7173_AIN_REF_POS || \
  78					(x) == AD7173_AIN_REF_NEG)
  79
  80#define AD7172_2_ID			0x00d0
  81#define AD7176_ID			0x0c90
  82#define AD7175_ID			0x0cd0
  83#define AD7175_2_ID			0x0cd0
  84#define AD7172_4_ID			0x2050
  85#define AD7173_ID			0x30d0
  86#define AD4111_ID			AD7173_ID
  87#define AD4112_ID			AD7173_ID
  88#define AD4114_ID			AD7173_ID
  89#define AD4113_ID			0x31d0
  90#define AD4116_ID			0x34d0
  91#define AD4115_ID			0x38d0
  92#define AD7175_8_ID			0x3cd0
  93#define AD7177_ID			0x4fd0
  94#define AD7173_ID_MASK			GENMASK(15, 4)
  95
  96#define AD7173_ADC_MODE_REF_EN		BIT(15)
  97#define AD7173_ADC_MODE_SING_CYC	BIT(13)
  98#define AD7173_ADC_MODE_MODE_MASK	GENMASK(6, 4)
  99#define AD7173_ADC_MODE_CLOCKSEL_MASK	GENMASK(3, 2)
 100#define AD7173_ADC_MODE_CLOCKSEL_INT		0x0
 101#define AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT	0x1
 102#define AD7173_ADC_MODE_CLOCKSEL_EXT		0x2
 103#define AD7173_ADC_MODE_CLOCKSEL_XTAL		0x3
 104
 105#define AD7173_GPIO_PDSW	BIT(14)
 106#define AD7173_GPIO_OP_EN2_3	BIT(13)
 107#define AD4111_GPIO_GP_OW_EN	BIT(12)
 108#define AD7173_GPIO_MUX_IO	BIT(12)
 109#define AD7173_GPIO_SYNC_EN	BIT(11)
 110#define AD7173_GPIO_ERR_EN	BIT(10)
 111#define AD7173_GPIO_ERR_DAT	BIT(9)
 112#define AD7173_GPIO_GP_DATA3	BIT(7)
 113#define AD7173_GPIO_GP_DATA2	BIT(6)
 114#define AD7173_GPIO_IP_EN1	BIT(5)
 115#define AD7173_GPIO_IP_EN0	BIT(4)
 116#define AD7173_GPIO_OP_EN1	BIT(3)
 117#define AD7173_GPIO_OP_EN0	BIT(2)
 118#define AD7173_GPIO_GP_DATA1	BIT(1)
 119#define AD7173_GPIO_GP_DATA0	BIT(0)
 120
 121#define AD7173_GPO12_DATA(x)	BIT((x) + 0)
 122#define AD7173_GPO23_DATA(x)	BIT((x) + 4)
 123#define AD4111_GPO01_DATA(x)	BIT((x) + 6)
 124#define AD7173_GPO_DATA(x)	((x) < 2 ? AD7173_GPO12_DATA(x) : AD7173_GPO23_DATA(x))
 125
 126#define AD7173_INTERFACE_DATA_STAT	BIT(6)
 127#define AD7173_INTERFACE_DATA_STAT_EN(x) \
 128	FIELD_PREP(AD7173_INTERFACE_DATA_STAT, x)
 129
 130#define AD7173_SETUP_BIPOLAR		BIT(12)
 131#define AD7173_SETUP_AREF_BUF_MASK	GENMASK(11, 10)
 132#define AD7173_SETUP_AIN_BUF_MASK	GENMASK(9, 8)
 133
 134#define AD7173_SETUP_REF_SEL_MASK	GENMASK(5, 4)
 135#define AD7173_SETUP_REF_SEL_AVDD1_AVSS	0x3
 136#define AD7173_SETUP_REF_SEL_INT_REF	0x2
 137#define AD7173_SETUP_REF_SEL_EXT_REF2	0x1
 138#define AD7173_SETUP_REF_SEL_EXT_REF	0x0
 139#define AD7173_VOLTAGE_INT_REF_uV	2500000
 140#define AD7173_TEMP_SENSIIVITY_uV_per_C	477
 141#define AD7177_ODR_START_VALUE		0x07
 142#define AD4111_SHUNT_RESISTOR_OHM	50
 143#define AD4111_DIVIDER_RATIO		10
 144#define AD4111_CURRENT_CHAN_CUTOFF	16
 145#define AD4111_VINCOM_INPUT		0x10
 146
 147/* pin <  num_voltage_in is a normal voltage input */
 148/* pin >= num_voltage_in_div is a voltage input without a divider */
 149#define AD4111_IS_VINCOM_MISMATCH(pin1, pin2) ((pin1) == AD4111_VINCOM_INPUT && \
 150					       (pin2) < st->info->num_voltage_in && \
 151					       (pin2) >= st->info->num_voltage_in_div)
 152
 153#define AD7173_FILTER_SINC3_MAP		BIT(15)
 154#define AD7173_FILTER_SINC3_MAP_DIV	GENMASK(14, 0)
 155#define AD7173_FILTER_ENHFILTEN		BIT(11)
 156#define AD7173_FILTER_ENHFILT_MASK	GENMASK(10, 8)
 157#define AD7173_FILTER_ORDER		BIT(6)
 158#define AD7173_FILTER_ODR_MASK		GENMASK(5, 0)
 159#define AD7173_MAX_CONFIGS		8
 160#define AD4111_OW_DET_THRSH_MV		300
 161
 162#define AD7173_MODE_CAL_INT_ZERO		0x4 /* Internal Zero-Scale Calibration */
 163#define AD7173_MODE_CAL_INT_FULL		0x5 /* Internal Full-Scale Calibration */
 164#define AD7173_MODE_CAL_SYS_ZERO		0x6 /* System Zero-Scale Calibration */
 165#define AD7173_MODE_CAL_SYS_FULL		0x7 /* System Full-Scale Calibration */
 166
 167struct ad7173_device_info {
 168	const unsigned int *sinc5_data_rates;
 169	unsigned int num_sinc5_data_rates;
 170	unsigned int odr_start_value;
 171	/*
 172	 * AD4116 has both inputs with a voltage divider and without.
 173	 * These inputs cannot be mixed in the channel configuration.
 174	 * Does not include the VINCOM input.
 175	 */
 176	unsigned int num_voltage_in_div;
 177	unsigned int num_channels;
 178	unsigned int num_configs;
 179	unsigned int num_voltage_in;
 180	unsigned int clock;
 181	unsigned int id;
 182	char *name;
 183	const struct ad_sigma_delta_info *sd_info;
 184	bool has_current_inputs;
 185	bool has_vincom_input;
 186	bool has_temp;
 187	/* ((AVDD1 − AVSS)/5) */
 188	bool has_pow_supply_monitoring;
 189	bool data_reg_only_16bit;
 190	bool has_input_buf;
 191	bool has_int_ref;
 192	bool has_ref2;
 193	bool has_internal_fs_calibration;
 194	bool has_openwire_det;
 195	bool higher_gpio_bits;
 196	u8 num_gpios;
 197};
 198
 199enum ad7173_filter_type {
 200	AD7173_FILTER_SINC3,
 201	AD7173_FILTER_SINC5_SINC1,
 202	AD7173_FILTER_SINC5_SINC1_PF1,
 203	AD7173_FILTER_SINC5_SINC1_PF2,
 204	AD7173_FILTER_SINC5_SINC1_PF3,
 205	AD7173_FILTER_SINC5_SINC1_PF4,
 206};
 207
 208struct ad7173_channel_config {
 209	/* Openwire detection threshold */
 210	unsigned int openwire_thrsh_raw;
 211	int openwire_comp_chan;
 212	u8 cfg_slot;
 213	bool live;
 214
 215	/*
 216	 * Following fields are used to compare equality. If you
 217	 * make adaptations in it, you most likely also have to adapt
 218	 * ad7173_is_setup_equal(), too.
 219	 */
 220	struct_group(config_props,
 221		bool bipolar;
 222		bool input_buf;
 223		u16 sinc3_odr_div;
 224		u8 sinc5_odr_index;
 225		u8 ref_sel;
 226		enum ad7173_filter_type filter_type;
 227	);
 228};
 229
 230struct ad7173_channel {
 231	unsigned int ain;
 232	struct ad7173_channel_config cfg;
 233	u8 syscalib_mode;
 234	bool openwire_det_en;
 235};
 236
 237struct ad7173_state {
 238	struct ad_sigma_delta sd;
 239	const struct ad7173_device_info *info;
 240	struct ad7173_channel *channels;
 241	struct regulator_bulk_data regulators[3];
 242	unsigned int adc_mode;
 243	unsigned int interface_mode;
 244	unsigned int num_channels;
 245	struct ida cfg_slots_status;
 246	unsigned long long config_usage_counter;
 247	unsigned long long *config_cnts;
 248	struct clk_hw int_clk_hw;
 249	struct regmap *reg_gpiocon_regmap;
 250	struct gpio_regmap *gpio_regmap;
 251};
 252
 253static unsigned int ad4115_sinc5_data_rates[] = {
 254	24845000, 24845000, 20725000, 20725000,	/*  0-3  */
 255	15564000, 13841000, 10390000, 10390000,	/*  4-7  */
 256	4994000,  2499000,  1000000,  500000,	/*  8-11 */
 257	395500,   200000,   100000,   59890,	/* 12-15 */
 258	49920,    20000,    16660,    10000,	/* 16-19 */
 259	5000,	  2500,     2500,		/* 20-22 */
 260};
 261
 262static unsigned int ad4116_sinc5_data_rates[] = {
 263	12422360, 12422360, 12422360, 12422360,	/*  0-3  */
 264	10362690, 10362690, 7782100,  6290530,	/*  4-7  */
 265	5194800,  2496900,  1007600,  499900,	/*  8-11 */
 266	390600,	  200300,   100000,   59750,	/* 12-15 */
 267	49840,	  20000,    16650,    10000,	/* 16-19 */
 268	5000,	  2500,	    1250,		/* 20-22 */
 269};
 270
 271static const unsigned int ad7173_sinc5_data_rates[] = {
 272	6211000, 6211000, 6211000, 6211000, 6211000, 6211000, 5181000, 4444000,	/*  0-7  */
 273	3115000, 2597000, 1007000, 503800,  381000,  200300,  100500,  59520,	/*  8-15 */
 274	49680,	 20010,	  16333,   10000,   5000,    2500,    1250,		/* 16-22 */
 275};
 276
 277static const unsigned int ad7175_sinc5_data_rates[] = {
 278	50000000, 41667000, 31250000, 27778000,	/*  0-3  */
 279	20833000, 17857000, 12500000, 10000000,	/*  4-7  */
 280	5000000,  2500000,  1000000,  500000,	/*  8-11 */
 281	397500,   200000,   100000,   59920,	/* 12-15 */
 282	49960,    20000,    16666,    10000,	/* 16-19 */
 283	5000,					/* 20    */
 284};
 285
 286/**
 287 * ad7173_sinc3_odr_div_from_odr() - Convert ODR to divider value
 288 * @odr_millihz: ODR (sampling_frequency) in milliHz
 289 * Returns: Divider value for SINC3 filter to pass.
 290 */
 291static u16 ad7173_sinc3_odr_div_from_odr(u32 odr_millihz)
 292{
 293	/*
 294	 * Divider is f_MOD (1 MHz) / 32 / ODR. ODR freq is in milliHz, so
 295	 * we need to convert f_MOD to the same units. When SING_CYC=1 or
 296	 * multiple channels are enabled (currently always the case), there
 297	 * is an additional factor of 3.
 298	 */
 299	u32 div = DIV_ROUND_CLOSEST(MEGA * MILLI, odr_millihz * 32 * 3);
 300	/* Avoid divide by 0 and limit to register field size. */
 301	return clamp(div, 1U, AD7173_FILTER_SINC3_MAP_DIV);
 302}
 303
 304static unsigned int ad4111_current_channel_config[] = {
 305	/* Ain sel: pos        neg    */
 306	0x1E8, /* 15:IIN0+    8:IIN0− */
 307	0x1C9, /* 14:IIN1+    9:IIN1− */
 308	0x1AA, /* 13:IIN2+   10:IIN2− */
 309	0x18B, /* 12:IIN3+   11:IIN3− */
 310};
 311
 312static const char *const ad7173_ref_sel_str[] = {
 313	[AD7173_SETUP_REF_SEL_EXT_REF]    = "vref",
 314	[AD7173_SETUP_REF_SEL_EXT_REF2]   = "vref2",
 315	[AD7173_SETUP_REF_SEL_INT_REF]    = "refout-avss",
 316	[AD7173_SETUP_REF_SEL_AVDD1_AVSS] = "avdd",
 317};
 318
 319static const char *const ad7173_clk_sel[] = {
 320	"ext-clk", "xtal"
 321};
 322
 323static const struct regmap_range ad7173_range_gpio[] = {
 324	regmap_reg_range(AD7173_REG_GPIO, AD7173_REG_GPIO),
 325};
 326
 327static const struct regmap_access_table ad7173_access_table = {
 328	.yes_ranges = ad7173_range_gpio,
 329	.n_yes_ranges = ARRAY_SIZE(ad7173_range_gpio),
 330};
 331
 332static const struct regmap_config ad7173_regmap_config = {
 333	.reg_bits = 8,
 334	.val_bits = 16,
 335	.rd_table = &ad7173_access_table,
 336	.wr_table = &ad7173_access_table,
 337	.read_flag_mask = BIT(6),
 338};
 339
 340enum {
 341	AD7173_SYSCALIB_ZERO_SCALE,
 342	AD7173_SYSCALIB_FULL_SCALE,
 343};
 344
 345static const char * const ad7173_syscalib_modes[] = {
 346	[AD7173_SYSCALIB_ZERO_SCALE] = "zero_scale",
 347	[AD7173_SYSCALIB_FULL_SCALE] = "full_scale",
 348};
 349
 350static int ad7173_set_syscalib_mode(struct iio_dev *indio_dev,
 351				    const struct iio_chan_spec *chan,
 352				    unsigned int mode)
 353{
 354	struct ad7173_state *st = iio_priv(indio_dev);
 355
 356	st->channels[chan->address].syscalib_mode = mode;
 357
 358	return 0;
 359}
 360
 361static int ad7173_get_syscalib_mode(struct iio_dev *indio_dev,
 362				    const struct iio_chan_spec *chan)
 363{
 364	struct ad7173_state *st = iio_priv(indio_dev);
 365
 366	return st->channels[chan->address].syscalib_mode;
 367}
 368
 369static ssize_t ad7173_write_syscalib(struct iio_dev *indio_dev,
 370				     uintptr_t private,
 371				     const struct iio_chan_spec *chan,
 372				     const char *buf, size_t len)
 373{
 374	struct ad7173_state *st = iio_priv(indio_dev);
 375	bool sys_calib;
 376	int ret, mode;
 377
 378	ret = kstrtobool(buf, &sys_calib);
 379	if (ret)
 380		return ret;
 381
 382	if (!iio_device_claim_direct(indio_dev))
 383		return -EBUSY;
 384
 385	mode = st->channels[chan->address].syscalib_mode;
 386	if (sys_calib) {
 387		if (mode == AD7173_SYSCALIB_ZERO_SCALE)
 388			ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_SYS_ZERO,
 389					      chan->address);
 390		else
 391			ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_SYS_FULL,
 392					      chan->address);
 393	}
 394
 395	iio_device_release_direct(indio_dev);
 396
 397	return ret ? : len;
 398}
 399
 400static const struct iio_enum ad7173_syscalib_mode_enum = {
 401	.items = ad7173_syscalib_modes,
 402	.num_items = ARRAY_SIZE(ad7173_syscalib_modes),
 403	.set = ad7173_set_syscalib_mode,
 404	.get = ad7173_get_syscalib_mode
 405};
 406
 407static const char * const ad7173_filter_types_str[] = {
 408	[AD7173_FILTER_SINC3] = "sinc3",
 409	[AD7173_FILTER_SINC5_SINC1] = "sinc5+sinc1",
 410	[AD7173_FILTER_SINC5_SINC1_PF1] = "sinc5+sinc1+pf1",
 411	[AD7173_FILTER_SINC5_SINC1_PF2] = "sinc5+sinc1+pf2",
 412	[AD7173_FILTER_SINC5_SINC1_PF3] = "sinc5+sinc1+pf3",
 413	[AD7173_FILTER_SINC5_SINC1_PF4] = "sinc5+sinc1+pf4",
 414};
 415
 416static int ad7173_set_filter_type(struct iio_dev *indio_dev,
 417				  const struct iio_chan_spec *chan,
 418				  unsigned int val)
 419{
 420	struct ad7173_state *st = iio_priv(indio_dev);
 421
 422	if (!iio_device_claim_direct(indio_dev))
 423		return -EBUSY;
 424
 425	st->channels[chan->address].cfg.filter_type = val;
 426	st->channels[chan->address].cfg.live = false;
 427
 428	iio_device_release_direct(indio_dev);
 429
 430	return 0;
 431}
 432
 433static int ad7173_get_filter_type(struct iio_dev *indio_dev,
 434				  const struct iio_chan_spec *chan)
 435{
 436	struct ad7173_state *st = iio_priv(indio_dev);
 437
 438	return st->channels[chan->address].cfg.filter_type;
 439}
 440
 441static const struct iio_enum ad7173_filter_type_enum = {
 442	.items = ad7173_filter_types_str,
 443	.num_items = ARRAY_SIZE(ad7173_filter_types_str),
 444	.set = ad7173_set_filter_type,
 445	.get = ad7173_get_filter_type,
 446};
 447
 448static const struct iio_chan_spec_ext_info ad7173_chan_spec_ext_info[] = {
 449	{
 450		.name = "sys_calibration",
 451		.write = ad7173_write_syscalib,
 452		.shared = IIO_SEPARATE,
 453	},
 454	IIO_ENUM("sys_calibration_mode", IIO_SEPARATE,
 455		 &ad7173_syscalib_mode_enum),
 456	IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE,
 457			   &ad7173_syscalib_mode_enum),
 458	IIO_ENUM("filter_type", IIO_SEPARATE, &ad7173_filter_type_enum),
 459	IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_TYPE,
 460			   &ad7173_filter_type_enum),
 461	{ }
 462};
 463
 464static const struct iio_chan_spec_ext_info ad7173_temp_chan_spec_ext_info[] = {
 465	IIO_ENUM("filter_type", IIO_SEPARATE, &ad7173_filter_type_enum),
 466	IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_TYPE,
 467			   &ad7173_filter_type_enum),
 468	{ }
 469};
 470
 471static int ad7173_calibrate_all(struct ad7173_state *st, struct iio_dev *indio_dev)
 472{
 473	int ret;
 474	int i;
 475
 476	for (i = 0; i < st->num_channels; i++) {
 477		if (indio_dev->channels[i].type != IIO_VOLTAGE)
 478			continue;
 479
 480		ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_INT_ZERO, i);
 481		if (ret < 0)
 482			return ret;
 483
 484		if (st->info->has_internal_fs_calibration) {
 485			ret = ad_sd_calibrate(&st->sd, AD7173_MODE_CAL_INT_FULL, i);
 486			if (ret < 0)
 487				return ret;
 488		}
 489	}
 490
 491	return 0;
 492}
 493
 494/*
 495 * Associative array of channel pairs for open wire detection
 496 * The array is indexed by ain and gives the associated channel pair
 497 * to perform the open wire detection with
 498 * the channel pair [0] is for non differential and pair [1]
 499 * is for differential inputs
 500 */
 501static int openwire_ain_to_channel_pair[][2][2] = {
 502/*	AIN      Single      Differential */
 503	[0] = { { 0, 15 },  { 1, 2 }   },
 504	[1] = { { 1, 2 },   { 2, 1 }   },
 505	[2] = { { 3, 4 },   { 5, 6 }   },
 506	[3] = { { 5, 6 },   { 6, 5 }   },
 507	[4] = { { 7, 8 },   { 9, 10 }  },
 508	[5] = { { 9, 10 },  { 10, 9 }  },
 509	[6] = { { 11, 12 }, { 13, 14 } },
 510	[7] = { { 13, 14 }, { 14, 13 } },
 511};
 512
 513/*
 514 * Openwire detection on ad4111 works by running the same input measurement
 515 * on two different channels and compare if the difference between the two
 516 * measurements exceeds a certain value (typical 300mV)
 517 */
 518static int ad4111_openwire_event(struct iio_dev *indio_dev,
 519				 const struct iio_chan_spec *chan)
 520{
 521	struct ad7173_state *st = iio_priv(indio_dev);
 522	struct ad7173_channel *adchan = &st->channels[chan->address];
 523	struct ad7173_channel_config *cfg = &adchan->cfg;
 524	int ret, val1, val2;
 525
 526	ret = regmap_set_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO,
 527			      AD4111_GPIO_GP_OW_EN);
 528	if (ret)
 529		return ret;
 530
 531	adchan->cfg.openwire_comp_chan =
 532		openwire_ain_to_channel_pair[chan->channel][chan->differential][0];
 533
 534	ret = ad_sigma_delta_single_conversion(indio_dev, chan, &val1);
 535	if (ret < 0) {
 536		dev_err(&indio_dev->dev,
 537			"Error running ad_sigma_delta single conversion: %d", ret);
 538		goto out;
 539	}
 540
 541	adchan->cfg.openwire_comp_chan =
 542		openwire_ain_to_channel_pair[chan->channel][chan->differential][1];
 543
 544	ret = ad_sigma_delta_single_conversion(indio_dev, chan, &val2);
 545	if (ret < 0) {
 546		dev_err(&indio_dev->dev,
 547			"Error running ad_sigma_delta single conversion: %d", ret);
 548		goto out;
 549	}
 550
 551	if (abs(val1 - val2) > cfg->openwire_thrsh_raw)
 552		iio_push_event(indio_dev,
 553			       IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, chan->address,
 554						    IIO_EV_TYPE_FAULT, IIO_EV_DIR_FAULT_OPENWIRE),
 555			       iio_get_time_ns(indio_dev));
 556
 557out:
 558	adchan->cfg.openwire_comp_chan = -1;
 559	regmap_clear_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO,
 560			  AD4111_GPIO_GP_OW_EN);
 561	return ret;
 562}
 563
 564static int ad7173_mask_xlate(struct gpio_regmap *gpio, unsigned int base,
 565			     unsigned int offset, unsigned int *reg,
 566			     unsigned int *mask)
 567{
 568	*mask = AD7173_GPO_DATA(offset);
 569	*reg = base;
 570	return 0;
 571}
 572
 573static int ad4111_mask_xlate(struct gpio_regmap *gpio, unsigned int base,
 574			     unsigned int offset, unsigned int *reg,
 575			     unsigned int *mask)
 576{
 577	*mask = AD4111_GPO01_DATA(offset);
 578	*reg = base;
 579	return 0;
 580}
 581
 582static void ad7173_gpio_disable(void *data)
 583{
 584	struct ad7173_state *st = data;
 585	unsigned int mask;
 586
 587	mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3;
 588	regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, ~mask);
 589}
 590
 591static int ad7173_gpio_init(struct ad7173_state *st)
 592{
 593	struct gpio_regmap_config gpio_regmap = {};
 594	struct device *dev = &st->sd.spi->dev;
 595	unsigned int mask;
 596	int ret;
 597
 598	st->reg_gpiocon_regmap = devm_regmap_init_spi(st->sd.spi, &ad7173_regmap_config);
 599	ret = PTR_ERR_OR_ZERO(st->reg_gpiocon_regmap);
 600	if (ret)
 601		return dev_err_probe(dev, ret, "Unable to init regmap\n");
 602
 603	mask = AD7173_GPIO_OP_EN0 | AD7173_GPIO_OP_EN1 | AD7173_GPIO_OP_EN2_3;
 604	regmap_update_bits(st->reg_gpiocon_regmap, AD7173_REG_GPIO, mask, mask);
 605
 606	ret = devm_add_action_or_reset(dev, ad7173_gpio_disable, st);
 607	if (ret)
 608		return ret;
 609
 610	gpio_regmap.parent = dev;
 611	gpio_regmap.regmap = st->reg_gpiocon_regmap;
 612	gpio_regmap.ngpio = st->info->num_gpios;
 613	gpio_regmap.reg_set_base = AD7173_REG_GPIO;
 614	if (st->info->higher_gpio_bits)
 615		gpio_regmap.reg_mask_xlate = ad4111_mask_xlate;
 616	else
 617		gpio_regmap.reg_mask_xlate = ad7173_mask_xlate;
 618
 619	st->gpio_regmap = devm_gpio_regmap_register(dev, &gpio_regmap);
 620	ret = PTR_ERR_OR_ZERO(st->gpio_regmap);
 621	if (ret)
 622		return dev_err_probe(dev, ret, "Unable to init gpio-regmap\n");
 623
 624	return 0;
 625}
 626
 627static struct ad7173_state *ad_sigma_delta_to_ad7173(struct ad_sigma_delta *sd)
 628{
 629	return container_of(sd, struct ad7173_state, sd);
 630}
 631
 632static struct ad7173_state *clk_hw_to_ad7173(struct clk_hw *hw)
 633{
 634	return container_of(hw, struct ad7173_state, int_clk_hw);
 635}
 636
 637static void ad7173_ida_destroy(void *data)
 638{
 639	struct ad7173_state *st = data;
 640
 641	ida_destroy(&st->cfg_slots_status);
 642}
 643
 644static void ad7173_reset_usage_cnts(struct ad7173_state *st)
 645{
 646	memset64(st->config_cnts, 0, st->info->num_configs);
 647	st->config_usage_counter = 0;
 648}
 649
 650/**
 651 * ad7173_is_setup_equal - Compare two channel setups
 652 * @cfg1: First channel configuration
 653 * @cfg2: Second channel configuration
 654 *
 655 * Compares all configuration options that affect the registers connected to
 656 * SETUP_SEL, namely CONFIGx, FILTERx, GAINx and OFFSETx.
 657 *
 658 * Returns: true if the setups are identical, false otherwise
 659 */
 660static bool ad7173_is_setup_equal(const struct ad7173_channel_config *cfg1,
 661				  const struct ad7173_channel_config *cfg2)
 662{
 663	/*
 664	 * This is just to make sure that the comparison is adapted after
 665	 * struct ad7173_channel_config was changed.
 666	 */
 667	static_assert(sizeof_field(struct ad7173_channel_config, config_props) ==
 668		      sizeof(struct {
 669				     bool bipolar;
 670				     bool input_buf;
 671				     u16 sinc3_odr_div;
 672				     u8 sinc5_odr_index;
 673				     u8 ref_sel;
 674				     enum ad7173_filter_type filter_type;
 675			     }));
 676
 677	return cfg1->bipolar == cfg2->bipolar &&
 678	       cfg1->input_buf == cfg2->input_buf &&
 679	       cfg1->sinc3_odr_div == cfg2->sinc3_odr_div &&
 680	       cfg1->sinc5_odr_index == cfg2->sinc5_odr_index &&
 681	       cfg1->ref_sel == cfg2->ref_sel &&
 682	       cfg1->filter_type == cfg2->filter_type;
 683}
 684
 685static struct ad7173_channel_config *
 686ad7173_find_live_config(struct ad7173_state *st, struct ad7173_channel_config *cfg)
 687{
 688	struct ad7173_channel_config *cfg_aux;
 689	int i;
 690
 691	for (i = 0; i < st->num_channels; i++) {
 692		cfg_aux = &st->channels[i].cfg;
 693
 694		if (cfg_aux->live && ad7173_is_setup_equal(cfg, cfg_aux))
 695			return cfg_aux;
 696	}
 697	return NULL;
 698}
 699
 700/* Could be replaced with a generic LRU implementation */
 701static int ad7173_free_config_slot_lru(struct ad7173_state *st)
 702{
 703	int i, lru_position = 0;
 704
 705	for (i = 1; i < st->info->num_configs; i++)
 706		if (st->config_cnts[i] < st->config_cnts[lru_position])
 707			lru_position = i;
 708
 709	for (i = 0; i < st->num_channels; i++)
 710		if (st->channels[i].cfg.cfg_slot == lru_position)
 711			st->channels[i].cfg.live = false;
 712
 713	ida_free(&st->cfg_slots_status, lru_position);
 714	return ida_alloc(&st->cfg_slots_status, GFP_KERNEL);
 715}
 716
 717/* Could be replaced with a generic LRU implementation */
 718static int ad7173_load_config(struct ad7173_state *st,
 719			      struct ad7173_channel_config *cfg)
 720{
 721	unsigned int config;
 722	int free_cfg_slot, ret;
 723	u8 post_filter_enable, post_filter_select;
 724
 725	free_cfg_slot = ida_alloc_range(&st->cfg_slots_status, 0,
 726					st->info->num_configs - 1, GFP_KERNEL);
 727	if (free_cfg_slot < 0)
 728		free_cfg_slot = ad7173_free_config_slot_lru(st);
 729
 730	cfg->cfg_slot = free_cfg_slot;
 731	config = FIELD_PREP(AD7173_SETUP_REF_SEL_MASK, cfg->ref_sel);
 732
 733	if (cfg->bipolar)
 734		config |= AD7173_SETUP_BIPOLAR;
 735
 736	if (cfg->input_buf)
 737		config |= AD7173_SETUP_AIN_BUF_MASK;
 738
 739	ret = ad_sd_write_reg(&st->sd, AD7173_REG_SETUP(free_cfg_slot), 2, config);
 740	if (ret)
 741		return ret;
 742
 743	/*
 744	 * When SINC3_MAP flag is enabled, the rest of the register has a
 745	 * different meaning. We are using this option to allow the most
 746	 * possible sampling frequencies with SINC3 filter.
 747	 */
 748	if (cfg->filter_type == AD7173_FILTER_SINC3)
 749		return ad_sd_write_reg(&st->sd, AD7173_REG_FILTER(free_cfg_slot), 2,
 750				       FIELD_PREP(AD7173_FILTER_SINC3_MAP, 1) |
 751				       FIELD_PREP(AD7173_FILTER_SINC3_MAP_DIV,
 752						  cfg->sinc3_odr_div));
 753
 754	switch (cfg->filter_type) {
 755	case AD7173_FILTER_SINC5_SINC1_PF1:
 756		post_filter_enable = 1;
 757		post_filter_select = 2;
 758		break;
 759	case AD7173_FILTER_SINC5_SINC1_PF2:
 760		post_filter_enable = 1;
 761		post_filter_select = 3;
 762		break;
 763	case AD7173_FILTER_SINC5_SINC1_PF3:
 764		post_filter_enable = 1;
 765		post_filter_select = 5;
 766		break;
 767	case AD7173_FILTER_SINC5_SINC1_PF4:
 768		post_filter_enable = 1;
 769		post_filter_select = 6;
 770		break;
 771	default:
 772		post_filter_enable = 0;
 773		post_filter_select = 0;
 774		break;
 775	}
 776
 777	return ad_sd_write_reg(&st->sd, AD7173_REG_FILTER(free_cfg_slot), 2,
 778			       FIELD_PREP(AD7173_FILTER_SINC3_MAP, 0) |
 779			       FIELD_PREP(AD7173_FILTER_ENHFILT_MASK,
 780					  post_filter_enable) |
 781			       FIELD_PREP(AD7173_FILTER_ENHFILTEN,
 782					  post_filter_select) |
 783			       FIELD_PREP(AD7173_FILTER_ORDER, 0) |
 784			       FIELD_PREP(AD7173_FILTER_ODR_MASK,
 785					  cfg->sinc5_odr_index));
 786}
 787
 788static int ad7173_config_channel(struct ad7173_state *st, int addr)
 789{
 790	struct ad7173_channel_config *cfg = &st->channels[addr].cfg;
 791	struct ad7173_channel_config *live_cfg;
 792	int ret;
 793
 794	if (!cfg->live) {
 795		live_cfg = ad7173_find_live_config(st, cfg);
 796		if (live_cfg) {
 797			cfg->cfg_slot = live_cfg->cfg_slot;
 798		} else {
 799			ret = ad7173_load_config(st, cfg);
 800			if (ret)
 801				return ret;
 802			cfg->live = true;
 803		}
 804	}
 805
 806	if (st->config_usage_counter == U64_MAX)
 807		ad7173_reset_usage_cnts(st);
 808
 809	st->config_usage_counter++;
 810	st->config_cnts[cfg->cfg_slot] = st->config_usage_counter;
 811
 812	return 0;
 813}
 814
 815static int ad7173_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
 816{
 817	struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
 818	unsigned int val;
 819	int ret;
 820
 821	ret = ad7173_config_channel(st, channel);
 822	if (ret)
 823		return ret;
 824
 825	val = AD7173_CH_ENABLE |
 826	      FIELD_PREP(AD7173_CH_SETUP_SEL_MASK, st->channels[channel].cfg.cfg_slot) |
 827	      st->channels[channel].ain;
 828
 829	if (st->channels[channel].cfg.openwire_comp_chan >= 0)
 830		channel = st->channels[channel].cfg.openwire_comp_chan;
 831
 832	return ad_sd_write_reg(&st->sd, AD7173_REG_CH(channel), 2, val);
 833}
 834
 835static int ad7173_set_mode(struct ad_sigma_delta *sd,
 836			   enum ad_sigma_delta_mode mode)
 837{
 838	struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
 839
 840	st->adc_mode &= ~AD7173_ADC_MODE_MODE_MASK;
 841	st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_MODE_MASK, mode);
 842
 843	return ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 2, st->adc_mode);
 844}
 845
 846static int ad7173_append_status(struct ad_sigma_delta *sd, bool append)
 847{
 848	struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
 849	unsigned int interface_mode = st->interface_mode;
 850	int ret;
 851
 852	interface_mode &= ~AD7173_INTERFACE_DATA_STAT;
 853	interface_mode |= AD7173_INTERFACE_DATA_STAT_EN(append);
 854	ret = ad_sd_write_reg(&st->sd, AD7173_REG_INTERFACE_MODE, 2, interface_mode);
 855	if (ret)
 856		return ret;
 857
 858	st->interface_mode = interface_mode;
 859
 860	return 0;
 861}
 862
 863static int ad7173_disable_all(struct ad_sigma_delta *sd)
 864{
 865	struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
 866	int ret;
 867	int i;
 868
 869	for (i = 0; i < st->num_channels; i++) {
 870		ret = ad_sd_write_reg(sd, AD7173_REG_CH(i), 2, 0);
 871		if (ret < 0)
 872			return ret;
 873	}
 874
 875	return 0;
 876}
 877
 878static int ad7173_disable_one(struct ad_sigma_delta *sd, unsigned int chan)
 879{
 880	struct ad7173_state *st = ad_sigma_delta_to_ad7173(sd);
 881
 882	if (st->channels[chan].cfg.openwire_comp_chan >= 0)
 883		chan = st->channels[chan].cfg.openwire_comp_chan;
 884
 885	return ad_sd_write_reg(sd, AD7173_REG_CH(chan), 2, 0);
 886}
 887
 888static const struct ad_sigma_delta_info ad7173_sigma_delta_info_4_slots = {
 889	.set_channel = ad7173_set_channel,
 890	.append_status = ad7173_append_status,
 891	.disable_all = ad7173_disable_all,
 892	.disable_one = ad7173_disable_one,
 893	.set_mode = ad7173_set_mode,
 894	.has_registers = true,
 895	.has_named_irqs = true,
 896	.supports_spi_offload = true,
 897	.addr_shift = 0,
 898	.read_mask = BIT(6),
 899	.status_ch_mask = GENMASK(3, 0),
 900	.data_reg = AD7173_REG_DATA,
 901	.num_resetclks = 64,
 902	.num_slots = 4,
 903};
 904
 905static const struct ad_sigma_delta_info ad7173_sigma_delta_info_8_slots = {
 906	.set_channel = ad7173_set_channel,
 907	.append_status = ad7173_append_status,
 908	.disable_all = ad7173_disable_all,
 909	.disable_one = ad7173_disable_one,
 910	.set_mode = ad7173_set_mode,
 911	.has_registers = true,
 912	.has_named_irqs = true,
 913	.supports_spi_offload = true,
 914	.addr_shift = 0,
 915	.read_mask = BIT(6),
 916	.status_ch_mask = GENMASK(3, 0),
 917	.data_reg = AD7173_REG_DATA,
 918	.num_resetclks = 64,
 919	.num_slots = 8,
 920};
 921
 922static const struct ad_sigma_delta_info ad7173_sigma_delta_info_16_slots = {
 923	.set_channel = ad7173_set_channel,
 924	.append_status = ad7173_append_status,
 925	.disable_all = ad7173_disable_all,
 926	.disable_one = ad7173_disable_one,
 927	.set_mode = ad7173_set_mode,
 928	.has_registers = true,
 929	.has_named_irqs = true,
 930	.supports_spi_offload = true,
 931	.addr_shift = 0,
 932	.read_mask = BIT(6),
 933	.status_ch_mask = GENMASK(3, 0),
 934	.data_reg = AD7173_REG_DATA,
 935	.num_resetclks = 64,
 936	.num_slots = 16,
 937};
 938
 939static const struct ad7173_device_info ad4111_device_info = {
 940	.name = "ad4111",
 941	.id = AD4111_ID,
 942	.sd_info = &ad7173_sigma_delta_info_16_slots,
 943	.num_voltage_in_div = 8,
 944	.num_channels = 16,
 945	.num_configs = 8,
 946	.num_voltage_in = 8,
 947	.num_gpios = 2,
 948	.higher_gpio_bits = true,
 949	.has_temp = true,
 950	.has_vincom_input = true,
 951	.has_input_buf = true,
 952	.has_current_inputs = true,
 953	.has_int_ref = true,
 954	.has_internal_fs_calibration = true,
 955	.has_openwire_det = true,
 956	.clock = 2 * HZ_PER_MHZ,
 957	.sinc5_data_rates = ad7173_sinc5_data_rates,
 958	.num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
 959};
 960
 961static const struct ad7173_device_info ad4112_device_info = {
 962	.name = "ad4112",
 963	.id = AD4112_ID,
 964	.sd_info = &ad7173_sigma_delta_info_16_slots,
 965	.num_voltage_in_div = 8,
 966	.num_channels = 16,
 967	.num_configs = 8,
 968	.num_voltage_in = 8,
 969	.num_gpios = 2,
 970	.higher_gpio_bits = true,
 971	.has_vincom_input = true,
 972	.has_temp = true,
 973	.has_input_buf = true,
 974	.has_current_inputs = true,
 975	.has_int_ref = true,
 976	.has_internal_fs_calibration = true,
 977	.clock = 2 * HZ_PER_MHZ,
 978	.sinc5_data_rates = ad7173_sinc5_data_rates,
 979	.num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
 980};
 981
 982static const struct ad7173_device_info ad4113_device_info = {
 983	.name = "ad4113",
 984	.id = AD4113_ID,
 985	.sd_info = &ad7173_sigma_delta_info_16_slots,
 986	.num_voltage_in_div = 8,
 987	.num_channels = 16,
 988	.num_configs = 8,
 989	.num_voltage_in = 8,
 990	.num_gpios = 2,
 991	.data_reg_only_16bit = true,
 992	.higher_gpio_bits = true,
 993	.has_vincom_input = true,
 994	.has_input_buf = true,
 995	.has_int_ref = true,
 996	.clock = 2 * HZ_PER_MHZ,
 997	.sinc5_data_rates = ad7173_sinc5_data_rates,
 998	.num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
 999};
1000
1001static const struct ad7173_device_info ad4114_device_info = {
1002	.name = "ad4114",
1003	.id = AD4114_ID,
1004	.sd_info = &ad7173_sigma_delta_info_16_slots,
1005	.num_voltage_in_div = 16,
1006	.num_channels = 16,
1007	.num_configs = 8,
1008	.num_voltage_in = 16,
1009	.num_gpios = 4,
1010	.has_vincom_input = true,
1011	.has_temp = true,
1012	.has_input_buf = true,
1013	.has_int_ref = true,
1014	.has_internal_fs_calibration = true,
1015	.clock = 2 * HZ_PER_MHZ,
1016	.sinc5_data_rates = ad7173_sinc5_data_rates,
1017	.num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
1018};
1019
1020static const struct ad7173_device_info ad4115_device_info = {
1021	.name = "ad4115",
1022	.id = AD4115_ID,
1023	.sd_info = &ad7173_sigma_delta_info_16_slots,
1024	.num_voltage_in_div = 16,
1025	.num_channels = 16,
1026	.num_configs = 8,
1027	.num_voltage_in = 16,
1028	.num_gpios = 4,
1029	.has_vincom_input = true,
1030	.has_temp = true,
1031	.has_input_buf = true,
1032	.has_int_ref = true,
1033	.has_internal_fs_calibration = true,
1034	.clock = 8 * HZ_PER_MHZ,
1035	.sinc5_data_rates = ad4115_sinc5_data_rates,
1036	.num_sinc5_data_rates = ARRAY_SIZE(ad4115_sinc5_data_rates),
1037};
1038
1039static const struct ad7173_device_info ad4116_device_info = {
1040	.name = "ad4116",
1041	.id = AD4116_ID,
1042	.sd_info = &ad7173_sigma_delta_info_16_slots,
1043	.num_voltage_in_div = 11,
1044	.num_channels = 16,
1045	.num_configs = 8,
1046	.num_voltage_in = 16,
1047	.num_gpios = 4,
1048	.has_vincom_input = true,
1049	.has_temp = true,
1050	.has_input_buf = true,
1051	.has_int_ref = true,
1052	.has_internal_fs_calibration = true,
1053	.clock = 4 * HZ_PER_MHZ,
1054	.sinc5_data_rates = ad4116_sinc5_data_rates,
1055	.num_sinc5_data_rates = ARRAY_SIZE(ad4116_sinc5_data_rates),
1056};
1057
1058static const struct ad7173_device_info ad7172_2_device_info = {
1059	.name = "ad7172-2",
1060	.id = AD7172_2_ID,
1061	.sd_info = &ad7173_sigma_delta_info_4_slots,
1062	.num_voltage_in = 5,
1063	.num_channels = 4,
1064	.num_configs = 4,
1065	.num_gpios = 2,
1066	.has_temp = true,
1067	.has_input_buf = true,
1068	.has_int_ref = true,
1069	.has_pow_supply_monitoring = true,
1070	.clock = 2 * HZ_PER_MHZ,
1071	.sinc5_data_rates = ad7173_sinc5_data_rates,
1072	.num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
1073};
1074
1075static const struct ad7173_device_info ad7172_4_device_info = {
1076	.name = "ad7172-4",
1077	.id = AD7172_4_ID,
1078	.sd_info = &ad7173_sigma_delta_info_8_slots,
1079	.num_voltage_in = 9,
1080	.num_channels = 8,
1081	.num_configs = 8,
1082	.num_gpios = 4,
1083	.has_input_buf = true,
1084	.has_ref2 = true,
1085	.has_pow_supply_monitoring = true,
1086	.clock = 2 * HZ_PER_MHZ,
1087	.sinc5_data_rates = ad7173_sinc5_data_rates,
1088	.num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
1089};
1090
1091static const struct ad7173_device_info ad7173_8_device_info = {
1092	.name = "ad7173-8",
1093	.id = AD7173_ID,
1094	.sd_info = &ad7173_sigma_delta_info_16_slots,
1095	.num_voltage_in = 17,
1096	.num_channels = 16,
1097	.num_configs = 8,
1098	.num_gpios = 4,
1099	.has_temp = true,
1100	.has_input_buf = true,
1101	.has_int_ref = true,
1102	.has_ref2 = true,
1103	.clock = 2 * HZ_PER_MHZ,
1104	.sinc5_data_rates = ad7173_sinc5_data_rates,
1105	.num_sinc5_data_rates = ARRAY_SIZE(ad7173_sinc5_data_rates),
1106};
1107
1108static const struct ad7173_device_info ad7175_2_device_info = {
1109	.name = "ad7175-2",
1110	.id = AD7175_2_ID,
1111	.sd_info = &ad7173_sigma_delta_info_4_slots,
1112	.num_voltage_in = 5,
1113	.num_channels = 4,
1114	.num_configs = 4,
1115	.num_gpios = 2,
1116	.has_temp = true,
1117	.has_input_buf = true,
1118	.has_int_ref = true,
1119	.has_pow_supply_monitoring = true,
1120	.clock = 16 * HZ_PER_MHZ,
1121	.sinc5_data_rates = ad7175_sinc5_data_rates,
1122	.num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates),
1123};
1124
1125static const struct ad7173_device_info ad7175_8_device_info = {
1126	.name = "ad7175-8",
1127	.id = AD7175_8_ID,
1128	.sd_info = &ad7173_sigma_delta_info_16_slots,
1129	.num_voltage_in = 17,
1130	.num_channels = 16,
1131	.num_configs = 8,
1132	.num_gpios = 4,
1133	.has_temp = true,
1134	.has_input_buf = true,
1135	.has_int_ref = true,
1136	.has_ref2 = true,
1137	.has_pow_supply_monitoring = true,
1138	.clock = 16 * HZ_PER_MHZ,
1139	.sinc5_data_rates = ad7175_sinc5_data_rates,
1140	.num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates),
1141};
1142
1143static const struct ad7173_device_info ad7176_2_device_info = {
1144	.name = "ad7176-2",
1145	.id = AD7176_ID,
1146	.sd_info = &ad7173_sigma_delta_info_4_slots,
1147	.num_voltage_in = 5,
1148	.num_channels = 4,
1149	.num_configs = 4,
1150	.num_gpios = 2,
1151	.has_int_ref = true,
1152	.clock = 16 * HZ_PER_MHZ,
1153	.sinc5_data_rates = ad7175_sinc5_data_rates,
1154	.num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates),
1155};
1156
1157static const struct ad7173_device_info ad7177_2_device_info = {
1158	.name = "ad7177-2",
1159	.id = AD7177_ID,
1160	.sd_info = &ad7173_sigma_delta_info_4_slots,
1161	.num_voltage_in = 5,
1162	.num_channels = 4,
1163	.num_configs = 4,
1164	.num_gpios = 2,
1165	.has_temp = true,
1166	.has_input_buf = true,
1167	.has_int_ref = true,
1168	.has_pow_supply_monitoring = true,
1169	.clock = 16 * HZ_PER_MHZ,
1170	.odr_start_value = AD7177_ODR_START_VALUE,
1171	.sinc5_data_rates = ad7175_sinc5_data_rates,
1172	.num_sinc5_data_rates = ARRAY_SIZE(ad7175_sinc5_data_rates),
1173};
1174
1175static int ad7173_setup(struct iio_dev *indio_dev)
1176{
1177	struct ad7173_state *st = iio_priv(indio_dev);
1178	struct device *dev = &st->sd.spi->dev;
1179	u8 buf[AD7173_RESET_LENGTH];
1180	unsigned int id;
1181	int ret;
1182
1183	/* reset the serial interface */
1184	memset(buf, 0xff, AD7173_RESET_LENGTH);
1185	ret = spi_write_then_read(st->sd.spi, buf, sizeof(buf), NULL, 0);
1186	if (ret < 0)
1187		return ret;
1188
1189	/* datasheet recommends a delay of at least 500us after reset */
1190	fsleep(500);
1191
1192	ret = ad_sd_read_reg(&st->sd, AD7173_REG_ID, 2, &id);
1193	if (ret)
1194		return ret;
1195
1196	id &= AD7173_ID_MASK;
1197	if (id != st->info->id)
1198		dev_warn(dev, "Unexpected device id: 0x%04X, expected: 0x%04X\n",
1199			 id, st->info->id);
1200
1201	st->adc_mode |= AD7173_ADC_MODE_SING_CYC;
1202	st->interface_mode = 0x0;
1203
1204	st->config_usage_counter = 0;
1205	st->config_cnts = devm_kcalloc(dev, st->info->num_configs,
1206				       sizeof(*st->config_cnts), GFP_KERNEL);
1207	if (!st->config_cnts)
1208		return -ENOMEM;
1209
1210	ret = ad7173_calibrate_all(st, indio_dev);
1211	if (ret)
1212		return ret;
1213
1214	/* All channels are enabled by default after a reset */
1215	return ad7173_disable_all(&st->sd);
1216}
1217
1218static unsigned int ad7173_get_ref_voltage_milli(struct ad7173_state *st,
1219						 u8 reference_select)
1220{
1221	int vref;
1222
1223	switch (reference_select) {
1224	case AD7173_SETUP_REF_SEL_EXT_REF:
1225		vref = regulator_get_voltage(st->regulators[0].consumer);
1226		break;
1227
1228	case AD7173_SETUP_REF_SEL_EXT_REF2:
1229		vref = regulator_get_voltage(st->regulators[1].consumer);
1230		break;
1231
1232	case AD7173_SETUP_REF_SEL_INT_REF:
1233		vref = AD7173_VOLTAGE_INT_REF_uV;
1234		break;
1235
1236	case AD7173_SETUP_REF_SEL_AVDD1_AVSS:
1237		vref = regulator_get_voltage(st->regulators[2].consumer);
1238		break;
1239
1240	default:
1241		return -EINVAL;
1242	}
1243
1244	if (vref < 0)
1245		return vref;
1246
1247	return vref / (MICRO / MILLI);
1248}
1249
1250static int ad7173_read_raw(struct iio_dev *indio_dev,
1251			   struct iio_chan_spec const *chan,
1252			   int *val, int *val2, long info)
1253{
1254	struct ad7173_state *st = iio_priv(indio_dev);
1255	struct ad7173_channel *ch = &st->channels[chan->address];
1256	unsigned int reg;
1257	u64 temp;
1258	int ret;
1259
1260	switch (info) {
1261	case IIO_CHAN_INFO_RAW:
1262		ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
1263		if (ret < 0)
1264			return ret;
1265
1266		if (ch->openwire_det_en) {
1267			ret = ad4111_openwire_event(indio_dev, chan);
1268			if (ret < 0)
1269				return ret;
1270		}
1271
1272		return IIO_VAL_INT;
1273	case IIO_CHAN_INFO_SCALE:
1274
1275		switch (chan->type) {
1276		case IIO_TEMP:
1277			temp = AD7173_VOLTAGE_INT_REF_uV * MILLI;
1278			temp /= AD7173_TEMP_SENSIIVITY_uV_per_C;
1279			*val = temp;
1280			*val2 = chan->scan_type.realbits;
1281			return IIO_VAL_FRACTIONAL_LOG2;
1282		case IIO_VOLTAGE:
1283			*val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel);
1284			*val2 = chan->scan_type.realbits - !!(ch->cfg.bipolar);
1285
1286			if (chan->channel < st->info->num_voltage_in_div)
1287				*val *= AD4111_DIVIDER_RATIO;
1288			return IIO_VAL_FRACTIONAL_LOG2;
1289		case IIO_CURRENT:
1290			*val = ad7173_get_ref_voltage_milli(st, ch->cfg.ref_sel);
1291			*val /= AD4111_SHUNT_RESISTOR_OHM;
1292			*val2 = chan->scan_type.realbits - ch->cfg.bipolar;
1293			return IIO_VAL_FRACTIONAL_LOG2;
1294		default:
1295			return -EINVAL;
1296		}
1297	case IIO_CHAN_INFO_OFFSET:
1298
1299		switch (chan->type) {
1300		case IIO_TEMP:
1301			/* 0 Kelvin -> raw sample */
1302			temp   = -ABSOLUTE_ZERO_MILLICELSIUS;
1303			temp  *= AD7173_TEMP_SENSIIVITY_uV_per_C;
1304			temp <<= chan->scan_type.realbits;
1305			temp   = DIV_U64_ROUND_CLOSEST(temp,
1306						       AD7173_VOLTAGE_INT_REF_uV *
1307						       MILLI);
1308			*val   = -temp;
1309			return IIO_VAL_INT;
1310		case IIO_VOLTAGE:
1311		case IIO_CURRENT:
1312			*val = -BIT(chan->scan_type.realbits - 1);
1313			return IIO_VAL_INT;
1314		default:
1315			return -EINVAL;
1316		}
1317	case IIO_CHAN_INFO_SAMP_FREQ:
1318		if (st->channels[chan->address].cfg.filter_type == AD7173_FILTER_SINC3) {
1319			/* Inverse operation of ad7173_sinc3_odr_div_from_odr() */
1320			*val = MEGA;
1321			*val2 = 3 * 32 * st->channels[chan->address].cfg.sinc3_odr_div;
1322			return IIO_VAL_FRACTIONAL;
1323		}
1324
1325		reg = st->channels[chan->address].cfg.sinc5_odr_index;
1326
1327		*val = st->info->sinc5_data_rates[reg] / MILLI;
1328		*val2 = (st->info->sinc5_data_rates[reg] % MILLI) * (MICRO / MILLI);
1329
1330		return IIO_VAL_INT_PLUS_MICRO;
1331	default:
1332		return -EINVAL;
1333	}
1334}
1335
1336static int ad7173_write_raw(struct iio_dev *indio_dev,
1337			    struct iio_chan_spec const *chan,
1338			    int val, int val2, long info)
1339{
1340	struct ad7173_state *st = iio_priv(indio_dev);
1341	struct ad7173_channel_config *cfg;
1342	unsigned int freq, i;
1343	int ret = 0;
1344
1345	if (!iio_device_claim_direct(indio_dev))
1346		return -EBUSY;
1347
1348	switch (info) {
1349	/*
1350	 * This attribute sets the sampling frequency for each channel individually.
1351	 * There are no issues for raw or buffered reads of an individual channel.
1352	 *
1353	 * When multiple channels are enabled in buffered mode, the effective
1354	 * sampling rate of a channel is lowered in correlation to the number
1355	 * of channels enabled and the sampling rate of the other channels.
1356	 *
1357	 * Example: 3 channels enabled with rates CH1:6211sps CH2,CH3:10sps
1358	 * While the reading of CH1 takes only 0.16ms, the reading of CH2 and CH3
1359	 * will take 100ms each.
1360	 *
1361	 * This will cause the reading of CH1 to be actually done once every
1362	 * 200.16ms, an effective rate of 4.99sps.
1363	 *
1364	 * Both the sinc5 and sinc3 rates are set here so that if the filter
1365	 * type is changed, the requested rate will still be set (aside from
1366	 * rounding differences).
1367	 */
1368	case IIO_CHAN_INFO_SAMP_FREQ:
1369		freq = val * MILLI + val2 / MILLI;
1370		for (i = st->info->odr_start_value; i < st->info->num_sinc5_data_rates - 1; i++)
1371			if (freq >= st->info->sinc5_data_rates[i])
1372				break;
1373
1374		cfg = &st->channels[chan->address].cfg;
1375		cfg->sinc5_odr_index = i;
1376		cfg->sinc3_odr_div = ad7173_sinc3_odr_div_from_odr(freq);
1377		cfg->live = false;
1378		break;
1379
1380	default:
1381		ret = -EINVAL;
1382		break;
1383	}
1384
1385	iio_device_release_direct(indio_dev);
1386	return ret;
1387}
1388
1389static int ad7173_update_scan_mode(struct iio_dev *indio_dev,
1390				   const unsigned long *scan_mask)
1391{
1392	struct ad7173_state *st = iio_priv(indio_dev);
1393	u16 sinc3_count = 0;
1394	u16 sinc3_div = 0;
1395	int i, j, k, ret;
1396
1397	for (i = 0; i < indio_dev->num_channels; i++) {
1398		const struct ad7173_channel_config *cfg = &st->channels[i].cfg;
1399
1400		if (test_bit(i, scan_mask)) {
1401			if (cfg->filter_type == AD7173_FILTER_SINC3) {
1402				sinc3_count++;
1403
1404				if (sinc3_div == 0) {
1405					sinc3_div = cfg->sinc3_odr_div;
1406				} else if (sinc3_div != cfg->sinc3_odr_div) {
1407					dev_err(&st->sd.spi->dev,
1408						"All enabled channels must have the same sampling_frequency for sinc3 filter_type\n");
1409					return -EINVAL;
1410				}
1411			}
1412
1413			ret = ad7173_set_channel(&st->sd, i);
1414		} else {
1415			ret = ad_sd_write_reg(&st->sd, AD7173_REG_CH(i), 2, 0);
1416		}
1417		if (ret < 0)
1418			return ret;
1419	}
1420
1421	if (sinc3_count && sinc3_count < bitmap_weight(scan_mask, indio_dev->num_channels)) {
1422		dev_err(&st->sd.spi->dev,
1423			"All enabled channels must have sinc3 filter_type\n");
1424		return -EINVAL;
1425	}
1426
1427	/*
1428	 * On some chips, there are more channels that setups, so if there were
1429	 * more unique setups requested than the number of available slots,
1430	 * ad7173_set_channel() will have written over some of the slots. We
1431	 * can detect this by making sure each assigned cfg_slot matches the
1432	 * requested configuration. If it doesn't, we know that the slot was
1433	 * overwritten by a different channel.
1434	 */
1435	for_each_set_bit(i, scan_mask, indio_dev->num_channels) {
1436		const struct ad7173_channel_config *cfg1, *cfg2;
1437
1438		cfg1 = &st->channels[i].cfg;
1439
1440		for_each_set_bit(j, scan_mask, indio_dev->num_channels) {
1441			cfg2 = &st->channels[j].cfg;
1442
1443			/*
1444			 * Only compare configs that are assigned to the same
1445			 * SETUP_SEL slot and don't compare channel to itself.
1446			 */
1447			if (i == j || cfg1->cfg_slot != cfg2->cfg_slot)
1448				continue;
1449
1450			/*
1451			 * If we find two different configs trying to use the
1452			 * same SETUP_SEL slot, then we know that the that we
1453			 * have too many unique configurations requested for
1454			 * the available slots and at least one was overwritten.
1455			 */
1456			if (!ad7173_is_setup_equal(cfg1, cfg2)) {
1457				/*
1458				 * At this point, there isn't a way to tell
1459				 * which setups are actually programmed in the
1460				 * ADC anymore, so we could read them back to
1461				 * see, but it is simpler to just turn off all
1462				 * of the live flags so that everything gets
1463				 * reprogramed on the next attempt read a sample.
1464				 */
1465				for (k = 0; k < st->num_channels; k++)
1466					st->channels[k].cfg.live = false;
1467
1468				dev_err(&st->sd.spi->dev,
1469					"Too many unique channel configurations requested for scan\n");
1470				return -EINVAL;
1471			}
1472		}
1473	}
1474
1475	return 0;
1476}
1477
1478static int ad7173_debug_reg_access(struct iio_dev *indio_dev, unsigned int reg,
1479				   unsigned int writeval, unsigned int *readval)
1480{
1481	struct ad7173_state *st = iio_priv(indio_dev);
1482	u8 reg_size;
1483
1484	if (reg == AD7173_REG_COMMS)
1485		reg_size = 1;
1486	else if (reg == AD7173_REG_CRC || reg == AD7173_REG_DATA ||
1487		 reg >= AD7173_REG_OFFSET(0))
1488		reg_size = 3;
1489	else
1490		reg_size = 2;
1491
1492	if (readval)
1493		return ad_sd_read_reg(&st->sd, reg, reg_size, readval);
1494
1495	return ad_sd_write_reg(&st->sd, reg, reg_size, writeval);
1496}
1497
1498static int ad7173_write_event_config(struct iio_dev *indio_dev,
1499				     const struct iio_chan_spec *chan,
1500				     enum iio_event_type type,
1501				     enum iio_event_direction dir,
1502				     bool state)
1503{
1504	struct ad7173_state *st = iio_priv(indio_dev);
1505	struct ad7173_channel *adchan = &st->channels[chan->address];
1506
1507	switch (type) {
1508	case IIO_EV_TYPE_FAULT:
1509		adchan->openwire_det_en = state;
1510		return 0;
1511	default:
1512		return -EINVAL;
1513	}
1514}
1515
1516static int ad7173_read_event_config(struct iio_dev *indio_dev,
1517				    const struct iio_chan_spec *chan,
1518				    enum iio_event_type type,
1519				    enum iio_event_direction dir)
1520{
1521	struct ad7173_state *st = iio_priv(indio_dev);
1522	struct ad7173_channel *adchan = &st->channels[chan->address];
1523
1524	switch (type) {
1525	case IIO_EV_TYPE_FAULT:
1526		return adchan->openwire_det_en;
1527	default:
1528		return -EINVAL;
1529	}
1530}
1531
1532static const struct iio_event_spec ad4111_events[] = {
1533	{
1534		.type = IIO_EV_TYPE_FAULT,
1535		.dir = IIO_EV_DIR_FAULT_OPENWIRE,
1536		.mask_separate = BIT(IIO_EV_INFO_VALUE),
1537		.mask_shared_by_all = BIT(IIO_EV_INFO_ENABLE),
1538	},
1539};
1540
1541static const struct iio_info ad7173_info = {
1542	.read_raw = &ad7173_read_raw,
1543	.write_raw = &ad7173_write_raw,
1544	.debugfs_reg_access = &ad7173_debug_reg_access,
1545	.validate_trigger = ad_sd_validate_trigger,
1546	.update_scan_mode = ad7173_update_scan_mode,
1547	.write_event_config = ad7173_write_event_config,
1548	.read_event_config = ad7173_read_event_config,
1549};
1550
1551static const struct iio_scan_type ad4113_scan_type = {
1552	.sign = 'u',
1553	.realbits = 16,
1554	.storagebits = 16,
1555	.endianness = IIO_BE,
1556};
1557
1558static const struct iio_chan_spec ad7173_channel_template = {
1559	.type = IIO_VOLTAGE,
1560	.indexed = 1,
1561	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1562		BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_SAMP_FREQ),
1563	.scan_type = {
1564		.sign = 'u',
1565		.realbits = 24,
1566		.storagebits = 32,
1567		.endianness = IIO_BE,
1568	},
1569	.ext_info = ad7173_chan_spec_ext_info,
1570};
1571
1572static const struct iio_chan_spec ad7173_temp_iio_channel_template = {
1573	.type = IIO_TEMP,
1574	.channel = AD7173_AIN_TEMP_POS,
1575	.channel2 = AD7173_AIN_TEMP_NEG,
1576	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1577		BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET) |
1578		BIT(IIO_CHAN_INFO_SAMP_FREQ),
1579	.scan_type = {
1580		.sign = 'u',
1581		.realbits = 24,
1582		.storagebits = 32,
1583		.endianness = IIO_BE,
1584	},
1585	.ext_info = ad7173_temp_chan_spec_ext_info,
1586};
1587
1588static void ad7173_disable_regulators(void *data)
1589{
1590	struct ad7173_state *st = data;
1591
1592	regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators);
1593}
1594
1595static unsigned long ad7173_sel_clk(struct ad7173_state *st,
1596				    unsigned int clk_sel)
1597{
1598	int ret;
1599
1600	st->adc_mode &= ~AD7173_ADC_MODE_CLOCKSEL_MASK;
1601	st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK, clk_sel);
1602	ret = ad_sd_write_reg(&st->sd, AD7173_REG_ADC_MODE, 0x2, st->adc_mode);
1603
1604	return ret;
1605}
1606
1607static unsigned long ad7173_clk_recalc_rate(struct clk_hw *hw,
1608					    unsigned long parent_rate)
1609{
1610	struct ad7173_state *st = clk_hw_to_ad7173(hw);
1611
1612	return st->info->clock / HZ_PER_KHZ;
1613}
1614
1615static int ad7173_clk_output_is_enabled(struct clk_hw *hw)
1616{
1617	struct ad7173_state *st = clk_hw_to_ad7173(hw);
1618	u32 clk_sel;
1619
1620	clk_sel = FIELD_GET(AD7173_ADC_MODE_CLOCKSEL_MASK, st->adc_mode);
1621	return clk_sel == AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT;
1622}
1623
1624static int ad7173_clk_output_prepare(struct clk_hw *hw)
1625{
1626	struct ad7173_state *st = clk_hw_to_ad7173(hw);
1627
1628	return ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT_OUTPUT);
1629}
1630
1631static void ad7173_clk_output_unprepare(struct clk_hw *hw)
1632{
1633	struct ad7173_state *st = clk_hw_to_ad7173(hw);
1634
1635	ad7173_sel_clk(st, AD7173_ADC_MODE_CLOCKSEL_INT);
1636}
1637
1638static const struct clk_ops ad7173_int_clk_ops = {
1639	.recalc_rate = ad7173_clk_recalc_rate,
1640	.is_enabled = ad7173_clk_output_is_enabled,
1641	.prepare = ad7173_clk_output_prepare,
1642	.unprepare = ad7173_clk_output_unprepare,
1643};
1644
1645static int ad7173_register_clk_provider(struct iio_dev *indio_dev)
1646{
1647	struct ad7173_state *st = iio_priv(indio_dev);
1648	struct device *dev = indio_dev->dev.parent;
1649	struct fwnode_handle *fwnode = dev_fwnode(dev);
1650	struct clk_init_data init = {};
1651	int ret;
1652
1653	if (!IS_ENABLED(CONFIG_COMMON_CLK))
1654		return 0;
1655
1656	init.name = fwnode_get_name(fwnode);
1657	init.ops = &ad7173_int_clk_ops;
1658
1659	st->int_clk_hw.init = &init;
1660	ret = devm_clk_hw_register(dev, &st->int_clk_hw);
1661	if (ret)
1662		return ret;
1663
1664	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
1665					   &st->int_clk_hw);
1666}
1667
1668static int ad4111_validate_current_ain(struct ad7173_state *st,
1669				       const unsigned int ain[AD7173_NO_AINS_PER_CHANNEL])
1670{
1671	struct device *dev = &st->sd.spi->dev;
1672
1673	if (!st->info->has_current_inputs)
1674		return dev_err_probe(dev, -EINVAL,
1675			"Model %s does not support current channels\n",
1676			st->info->name);
1677
1678	if (ain[0] >= ARRAY_SIZE(ad4111_current_channel_config))
1679		return dev_err_probe(dev, -EINVAL,
1680			"For current channels single-channel must be <[0-3]>\n");
1681
1682	return 0;
1683}
1684
1685static int ad7173_validate_voltage_ain_inputs(struct ad7173_state *st,
1686					      unsigned int ain0, unsigned int ain1)
1687{
1688	struct device *dev = &st->sd.spi->dev;
1689	bool special_input0, special_input1;
1690
1691	/* (AVDD1-AVSS)/5 power supply monitoring */
1692	if (ain0 == AD7173_AIN_POW_MON_POS && ain1 == AD7173_AIN_POW_MON_NEG &&
1693	    st->info->has_pow_supply_monitoring)
1694		return 0;
1695
1696	special_input0 = AD7173_IS_REF_INPUT(ain0) ||
1697			 (ain0 == AD4111_VINCOM_INPUT && st->info->has_vincom_input);
1698	special_input1 = AD7173_IS_REF_INPUT(ain1) ||
1699			 (ain1 == AD4111_VINCOM_INPUT && st->info->has_vincom_input);
1700
1701	if ((ain0 >= st->info->num_voltage_in && !special_input0) ||
1702	    (ain1 >= st->info->num_voltage_in && !special_input1)) {
1703		if (ain0 == AD4111_VINCOM_INPUT || ain1 == AD4111_VINCOM_INPUT)
1704			return dev_err_probe(dev, -EINVAL,
1705				"VINCOM not supported for %s\n", st->info->name);
1706
1707		return dev_err_probe(dev, -EINVAL,
1708				     "Input pin number out of range for pair (%d %d).\n",
1709				     ain0, ain1);
1710	}
1711
1712	if (AD4111_IS_VINCOM_MISMATCH(ain0, ain1) ||
1713	    AD4111_IS_VINCOM_MISMATCH(ain1, ain0))
1714		return dev_err_probe(dev, -EINVAL,
1715			"VINCOM must be paired with inputs having divider.\n");
1716
1717	if (!special_input0 && !special_input1 &&
1718	    ((ain0 >= st->info->num_voltage_in_div) !=
1719	     (ain1 >= st->info->num_voltage_in_div)))
1720		return dev_err_probe(dev, -EINVAL,
1721			"Both inputs must either have a voltage divider or not have: (%d %d).\n",
1722			ain0, ain1);
1723
1724	return 0;
1725}
1726
1727static int ad7173_validate_reference(struct ad7173_state *st, int ref_sel)
1728{
1729	struct device *dev = &st->sd.spi->dev;
1730	int ret;
1731
1732	if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF && !st->info->has_int_ref)
1733		return dev_err_probe(dev, -EINVAL,
1734			"Internal reference is not available on current model.\n");
1735
1736	if (ref_sel == AD7173_SETUP_REF_SEL_EXT_REF2 && !st->info->has_ref2)
1737		return dev_err_probe(dev, -EINVAL,
1738			"External reference 2 is not available on current model.\n");
1739
1740	ret = ad7173_get_ref_voltage_milli(st, ref_sel);
1741	if (ret < 0)
1742		return dev_err_probe(dev, ret, "Cannot use reference %u\n",
1743				     ref_sel);
1744
1745	return 0;
1746}
1747
1748static int ad7173_validate_openwire_ain_inputs(struct ad7173_state *st,
1749					       bool differential,
1750					       unsigned int ain0,
1751					       unsigned int ain1)
1752{
1753	/*
1754	 * If the channel is configured as differential,
1755	 * the ad4111 requires specific ains to be used together
1756	 */
1757	if (differential)
1758		return (ain0 % 2) ? (ain0 - 1) == ain1 : (ain0 + 1) == ain1;
1759
1760	return ain1 == AD4111_VINCOM_INPUT;
1761}
1762
1763static unsigned int ad7173_calc_openwire_thrsh_raw(struct ad7173_state *st,
1764						   struct iio_chan_spec *chan,
1765						   struct ad7173_channel *chan_st_priv,
1766						   unsigned int thrsh_mv) {
1767	unsigned int thrsh_raw;
1768
1769	thrsh_raw =
1770		BIT(chan->scan_type.realbits - !!(chan_st_priv->cfg.bipolar))
1771		* thrsh_mv
1772		/ ad7173_get_ref_voltage_milli(st, chan_st_priv->cfg.ref_sel);
1773	if (chan->channel < st->info->num_voltage_in_div)
1774		thrsh_raw /= AD4111_DIVIDER_RATIO;
1775
1776	return thrsh_raw;
1777}
1778
1779static int ad7173_fw_parse_channel_config(struct iio_dev *indio_dev)
1780{
1781	struct ad7173_channel *chans_st_arr, *chan_st_priv;
1782	struct ad7173_state *st = iio_priv(indio_dev);
1783	struct device *dev = indio_dev->dev.parent;
1784	struct iio_chan_spec *chan_arr, *chan;
1785	unsigned int ain[AD7173_NO_AINS_PER_CHANNEL], chan_index = 0;
1786	int ref_sel, ret, num_channels;
1787
1788	num_channels = device_get_child_node_count(dev);
1789
1790	if (st->info->has_temp)
1791		num_channels++;
1792
1793	if (num_channels == 0)
1794		return dev_err_probe(dev, -ENODATA, "No channels specified\n");
1795
1796	if (num_channels > st->info->num_channels)
1797		return dev_err_probe(dev, -EINVAL,
1798			"Too many channels specified. Maximum is %d, not including temperature channel if supported.\n",
1799			st->info->num_channels);
1800
1801	indio_dev->num_channels = num_channels;
1802	st->num_channels = num_channels;
1803
1804	chan_arr = devm_kcalloc(dev, sizeof(*indio_dev->channels),
1805				st->num_channels, GFP_KERNEL);
1806	if (!chan_arr)
1807		return -ENOMEM;
1808
1809	chans_st_arr = devm_kcalloc(dev, st->num_channels, sizeof(*st->channels),
1810				    GFP_KERNEL);
1811	if (!chans_st_arr)
1812		return -ENOMEM;
1813
1814	indio_dev->channels = chan_arr;
1815	st->channels = chans_st_arr;
1816
1817	if (st->info->has_temp) {
1818		chan_arr[chan_index] = ad7173_temp_iio_channel_template;
1819		chan_st_priv = &chans_st_arr[chan_index];
1820		chan_st_priv->ain =
1821			AD7173_CH_ADDRESS(chan_arr[chan_index].channel,
1822					  chan_arr[chan_index].channel2);
1823		chan_st_priv->cfg.bipolar = false;
1824		chan_st_priv->cfg.input_buf = st->info->has_input_buf;
1825		chan_st_priv->cfg.ref_sel = AD7173_SETUP_REF_SEL_INT_REF;
1826		chan_st_priv->cfg.sinc3_odr_div = ad7173_sinc3_odr_div_from_odr(
1827			st->info->sinc5_data_rates[st->info->odr_start_value]
1828		);
1829		chan_st_priv->cfg.sinc5_odr_index = st->info->odr_start_value;
1830		chan_st_priv->cfg.filter_type = AD7173_FILTER_SINC5_SINC1;
1831		chan_st_priv->cfg.openwire_comp_chan = -1;
1832		st->adc_mode |= AD7173_ADC_MODE_REF_EN;
1833		if (st->info->data_reg_only_16bit)
1834			chan_arr[chan_index].scan_type = ad4113_scan_type;
1835
1836		if (ad_sigma_delta_has_spi_offload(&st->sd)) {
1837			chan_arr[chan_index].scan_type.storagebits = 32;
1838			chan_arr[chan_index].scan_type.endianness = IIO_CPU;
1839		}
1840
1841		chan_index++;
1842	}
1843
1844	device_for_each_child_node_scoped(dev, child) {
1845		bool is_current_chan = false;
1846
1847		chan = &chan_arr[chan_index];
1848		*chan = ad7173_channel_template;
1849		chan_st_priv = &chans_st_arr[chan_index];
1850		ret = fwnode_property_read_u32_array(child, "diff-channels",
1851						     ain, ARRAY_SIZE(ain));
1852		if (ret) {
1853			ret = fwnode_property_read_u32(child, "single-channel",
1854						       ain);
1855			if (ret)
1856				return dev_err_probe(dev, ret,
1857					"Channel must define one of diff-channels or single-channel.\n");
1858
1859			is_current_chan = fwnode_property_read_bool(child, "adi,current-channel");
1860		} else {
1861			chan->differential = true;
1862		}
1863
1864		if (is_current_chan) {
1865			ret = ad4111_validate_current_ain(st, ain);
1866			if (ret)
1867				return ret;
1868		} else {
1869			if (!chan->differential) {
1870				ret = fwnode_property_read_u32(child,
1871					"common-mode-channel", ain + 1);
1872				if (ret)
1873					return dev_err_probe(dev, ret,
1874						"common-mode-channel must be defined for single-ended channels.\n");
1875			}
1876			ret = ad7173_validate_voltage_ain_inputs(st, ain[0], ain[1]);
1877			if (ret)
1878				return ret;
1879		}
1880
1881		ret = fwnode_property_match_property_string(child,
1882							    "adi,reference-select",
1883							    ad7173_ref_sel_str,
1884							    ARRAY_SIZE(ad7173_ref_sel_str));
1885		if (ret < 0)
1886			ref_sel = AD7173_SETUP_REF_SEL_INT_REF;
1887		else
1888			ref_sel = ret;
1889
1890		ret = ad7173_validate_reference(st, ref_sel);
1891		if (ret)
1892			return ret;
1893
1894		if (ref_sel == AD7173_SETUP_REF_SEL_INT_REF)
1895			st->adc_mode |= AD7173_ADC_MODE_REF_EN;
1896		chan_st_priv->cfg.ref_sel = ref_sel;
1897
1898		chan->address = chan_index;
1899		chan->scan_index = chan_index;
1900		chan->channel = ain[0];
1901		chan_st_priv->cfg.input_buf = st->info->has_input_buf;
1902		chan_st_priv->cfg.sinc3_odr_div = ad7173_sinc3_odr_div_from_odr(
1903			st->info->sinc5_data_rates[st->info->odr_start_value]
1904		);
1905		chan_st_priv->cfg.sinc5_odr_index = st->info->odr_start_value;
1906		chan_st_priv->cfg.filter_type = AD7173_FILTER_SINC5_SINC1;
1907		chan_st_priv->cfg.openwire_comp_chan = -1;
1908
1909		chan_st_priv->cfg.bipolar = fwnode_property_read_bool(child, "bipolar");
1910		if (chan_st_priv->cfg.bipolar)
1911			chan->info_mask_separate |= BIT(IIO_CHAN_INFO_OFFSET);
1912
1913		if (is_current_chan) {
1914			chan->type = IIO_CURRENT;
1915			chan->differential = false;
1916			chan->channel2 = 0;
1917			chan_st_priv->ain = ad4111_current_channel_config[ain[0]];
1918		} else {
1919			chan_st_priv->cfg.input_buf = st->info->has_input_buf;
1920			chan->channel2 = ain[1];
1921			chan_st_priv->ain = AD7173_CH_ADDRESS(ain[0], ain[1]);
1922			if (st->info->has_openwire_det &&
1923			    ad7173_validate_openwire_ain_inputs(st, chan->differential, ain[0], ain[1])) {
1924				chan->event_spec = ad4111_events;
1925				chan->num_event_specs = ARRAY_SIZE(ad4111_events);
1926				chan_st_priv->cfg.openwire_thrsh_raw =
1927					ad7173_calc_openwire_thrsh_raw(st, chan, chan_st_priv,
1928								       AD4111_OW_DET_THRSH_MV);
1929			}
1930		}
1931
1932		if (st->info->data_reg_only_16bit)
1933			chan_arr[chan_index].scan_type = ad4113_scan_type;
1934
1935		/* Assuming SPI offload is ad411x_ad717x HDL project. */
1936		if (ad_sigma_delta_has_spi_offload(&st->sd)) {
1937			chan_arr[chan_index].scan_type.storagebits = 32;
1938			chan_arr[chan_index].scan_type.endianness = IIO_CPU;
1939		}
1940
1941		chan_index++;
1942	}
1943	return 0;
1944}
1945
1946static int ad7173_fw_parse_device_config(struct iio_dev *indio_dev)
1947{
1948	struct ad7173_state *st = iio_priv(indio_dev);
1949	struct device *dev = indio_dev->dev.parent;
1950	int ret;
1951
1952	st->regulators[0].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF];
1953	st->regulators[1].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_EXT_REF2];
1954	st->regulators[2].supply = ad7173_ref_sel_str[AD7173_SETUP_REF_SEL_AVDD1_AVSS];
1955
1956	/*
1957	 * If a regulator is not available, it will be set to a dummy regulator.
1958	 * Each channel reference is checked with regulator_get_voltage() before
1959	 * setting attributes so if any channel uses a dummy supply the driver
1960	 * probe will fail.
1961	 */
1962	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators),
1963				      st->regulators);
1964	if (ret)
1965		return dev_err_probe(dev, ret, "Failed to get regulators\n");
1966
1967	ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators);
1968	if (ret)
1969		return dev_err_probe(dev, ret, "Failed to enable regulators\n");
1970
1971	ret = devm_add_action_or_reset(dev, ad7173_disable_regulators, st);
1972	if (ret)
1973		return ret;
1974
1975	ret = device_property_match_property_string(dev, "clock-names",
1976						    ad7173_clk_sel,
1977						    ARRAY_SIZE(ad7173_clk_sel));
1978	if (ret < 0) {
1979		st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK,
1980					   AD7173_ADC_MODE_CLOCKSEL_INT);
1981		ad7173_register_clk_provider(indio_dev);
1982	} else {
1983		struct clk *clk;
1984
1985		st->adc_mode |= FIELD_PREP(AD7173_ADC_MODE_CLOCKSEL_MASK,
1986					   AD7173_ADC_MODE_CLOCKSEL_EXT + ret);
1987		clk = devm_clk_get_enabled(dev, ad7173_clk_sel[ret]);
1988		if (IS_ERR(clk))
1989			return dev_err_probe(dev, PTR_ERR(clk),
1990					     "Failed to get external clock\n");
1991	}
1992
1993	return ad7173_fw_parse_channel_config(indio_dev);
1994}
1995
1996static int ad7173_probe(struct spi_device *spi)
1997{
1998	struct device *dev = &spi->dev;
1999	struct ad7173_state *st;
2000	struct iio_dev *indio_dev;
2001	int ret;
2002
2003	indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
2004	if (!indio_dev)
2005		return -ENOMEM;
2006
2007	st = iio_priv(indio_dev);
2008	st->info = spi_get_device_match_data(spi);
2009	if (!st->info)
2010		return -ENODEV;
2011
2012	ida_init(&st->cfg_slots_status);
2013	ret = devm_add_action_or_reset(dev, ad7173_ida_destroy, st);
2014	if (ret)
2015		return ret;
2016
2017	indio_dev->name = st->info->name;
2018	indio_dev->modes = INDIO_DIRECT_MODE;
2019	indio_dev->info = &ad7173_info;
2020
2021	spi->mode = SPI_MODE_3;
2022	ret = spi_setup(spi);
2023	if (ret)
2024		return ret;
2025
2026	ret = ad_sd_init(&st->sd, indio_dev, spi, st->info->sd_info);
2027	if (ret)
2028		return ret;
2029
2030	ret = ad7173_fw_parse_device_config(indio_dev);
2031	if (ret)
2032		return ret;
2033
2034	ret = devm_ad_sd_setup_buffer_and_trigger(dev, indio_dev);
2035	if (ret)
2036		return ret;
2037
2038	ret = ad7173_setup(indio_dev);
2039	if (ret)
2040		return ret;
2041
2042	ret = devm_iio_device_register(dev, indio_dev);
2043	if (ret)
2044		return ret;
2045
2046	return ad7173_gpio_init(st);
2047}
2048
2049static const struct of_device_id ad7173_of_match[] = {
2050	{ .compatible = "adi,ad4111",	.data = &ad4111_device_info },
2051	{ .compatible = "adi,ad4112",	.data = &ad4112_device_info },
2052	{ .compatible = "adi,ad4113",	.data = &ad4113_device_info },
2053	{ .compatible = "adi,ad4114",	.data = &ad4114_device_info },
2054	{ .compatible = "adi,ad4115",	.data = &ad4115_device_info },
2055	{ .compatible = "adi,ad4116",	.data = &ad4116_device_info },
2056	{ .compatible = "adi,ad7172-2", .data = &ad7172_2_device_info },
2057	{ .compatible = "adi,ad7172-4", .data = &ad7172_4_device_info },
2058	{ .compatible = "adi,ad7173-8", .data = &ad7173_8_device_info },
2059	{ .compatible = "adi,ad7175-2", .data = &ad7175_2_device_info },
2060	{ .compatible = "adi,ad7175-8", .data = &ad7175_8_device_info },
2061	{ .compatible = "adi,ad7176-2", .data = &ad7176_2_device_info },
2062	{ .compatible = "adi,ad7177-2", .data = &ad7177_2_device_info },
2063	{ }
2064};
2065MODULE_DEVICE_TABLE(of, ad7173_of_match);
2066
2067static const struct spi_device_id ad7173_id_table[] = {
2068	{ "ad4111",   (kernel_ulong_t)&ad4111_device_info },
2069	{ "ad4112",   (kernel_ulong_t)&ad4112_device_info },
2070	{ "ad4113",   (kernel_ulong_t)&ad4113_device_info },
2071	{ "ad4114",   (kernel_ulong_t)&ad4114_device_info },
2072	{ "ad4115",   (kernel_ulong_t)&ad4115_device_info },
2073	{ "ad4116",   (kernel_ulong_t)&ad4116_device_info },
2074	{ "ad7172-2", (kernel_ulong_t)&ad7172_2_device_info },
2075	{ "ad7172-4", (kernel_ulong_t)&ad7172_4_device_info },
2076	{ "ad7173-8", (kernel_ulong_t)&ad7173_8_device_info },
2077	{ "ad7175-2", (kernel_ulong_t)&ad7175_2_device_info },
2078	{ "ad7175-8", (kernel_ulong_t)&ad7175_8_device_info },
2079	{ "ad7176-2", (kernel_ulong_t)&ad7176_2_device_info },
2080	{ "ad7177-2", (kernel_ulong_t)&ad7177_2_device_info },
2081	{ }
2082};
2083MODULE_DEVICE_TABLE(spi, ad7173_id_table);
2084
2085static struct spi_driver ad7173_driver = {
2086	.driver = {
2087		.name	= "ad7173",
2088		.of_match_table = ad7173_of_match,
2089	},
2090	.probe		= ad7173_probe,
2091	.id_table	= ad7173_id_table,
2092};
2093module_spi_driver(ad7173_driver);
2094
2095MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA");
2096MODULE_AUTHOR("Lars-Peter Clausen <lars@metafo.de>");
2097MODULE_AUTHOR("Dumitru Ceclan <dumitru.ceclan@analog.com>");
2098MODULE_DESCRIPTION("Analog Devices AD7173 and similar ADC driver");
2099MODULE_LICENSE("GPL");