ad4080.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Analog Devices AD4080 SPI ADC driver
  4 *
  5 * Copyright 2025 Analog Devices Inc.
  6 */
  7
  8#include <linux/array_size.h>
  9#include <linux/bitfield.h>
 10#include <linux/bits.h>
 11#include <linux/clk.h>
 12#include <linux/device.h>
 13#include <linux/err.h>
 14#include <linux/iio/backend.h>
 15#include <linux/iio/iio.h>
 16#include <linux/mod_devicetable.h>
 17#include <linux/module.h>
 18#include <linux/mutex.h>
 19#include <linux/regmap.h>
 20#include <linux/regulator/consumer.h>
 21#include <linux/spi/spi.h>
 22#include <linux/types.h>
 23#include <linux/unaligned.h>
 24#include <linux/units.h>
 25
 26/* Register Definition */
 27#define AD4080_REG_INTERFACE_CONFIG_A				0x00
 28#define AD4080_REG_INTERFACE_CONFIG_B				0x01
 29#define AD4080_REG_DEVICE_CONFIG				0x02
 30#define AD4080_REG_CHIP_TYPE					0x03
 31#define AD4080_REG_PRODUCT_ID_L					0x04
 32#define AD4080_REG_PRODUCT_ID_H					0x05
 33#define AD4080_REG_CHIP_GRADE					0x06
 34#define AD4080_REG_SCRATCH_PAD					0x0A
 35#define AD4080_REG_SPI_REVISION					0x0B
 36#define AD4080_REG_VENDOR_L					0x0C
 37#define AD4080_REG_VENDOR_H					0x0D
 38#define AD4080_REG_STREAM_MODE					0x0E
 39#define AD4080_REG_TRANSFER_CONFIG				0x0F
 40#define AD4080_REG_INTERFACE_CONFIG_C				0x10
 41#define AD4080_REG_INTERFACE_STATUS_A				0x11
 42#define AD4080_REG_DEVICE_STATUS				0x14
 43#define AD4080_REG_ADC_DATA_INTF_CONFIG_A			0x15
 44#define AD4080_REG_ADC_DATA_INTF_CONFIG_B			0x16
 45#define AD4080_REG_ADC_DATA_INTF_CONFIG_C			0x17
 46#define AD4080_REG_PWR_CTRL					0x18
 47#define AD4080_REG_GPIO_CONFIG_A				0x19
 48#define AD4080_REG_GPIO_CONFIG_B				0x1A
 49#define AD4080_REG_GPIO_CONFIG_C				0x1B
 50#define AD4080_REG_GENERAL_CONFIG				0x1C
 51#define AD4080_REG_FIFO_WATERMARK_LSB				0x1D
 52#define AD4080_REG_FIFO_WATERMARK_MSB				0x1E
 53#define AD4080_REG_EVENT_HYSTERESIS_LSB				0x1F
 54#define AD4080_REG_EVENT_HYSTERESIS_MSB				0x20
 55#define AD4080_REG_EVENT_DETECTION_HI_LSB			0x21
 56#define AD4080_REG_EVENT_DETECTION_HI_MSB			0x22
 57#define AD4080_REG_EVENT_DETECTION_LO_LSB			0x23
 58#define AD4080_REG_EVENT_DETECTION_LO_MSB			0x24
 59#define AD4080_REG_OFFSET_LSB					0x25
 60#define AD4080_REG_OFFSET_MSB					0x26
 61#define AD4080_REG_GAIN_LSB					0x27
 62#define AD4080_REG_GAIN_MSB					0x28
 63#define AD4080_REG_FILTER_CONFIG				0x29
 64
 65/* AD4080_REG_INTERFACE_CONFIG_A Bit Definition */
 66#define AD4080_INTERFACE_CONFIG_A_SW_RESET			(BIT(7) | BIT(0))
 67#define AD4080_INTERFACE_CONFIG_A_ADDR_ASC			BIT(5)
 68#define AD4080_INTERFACE_CONFIG_A_SDO_ENABLE			BIT(4)
 69
 70/* AD4080_REG_INTERFACE_CONFIG_B Bit Definition */
 71#define AD4080_INTERFACE_CONFIG_B_SINGLE_INST			BIT(7)
 72#define AD4080_INTERFACE_CONFIG_B_SHORT_INST			BIT(3)
 73
 74/* AD4080_REG_DEVICE_CONFIG Bit Definition */
 75#define AD4080_DEVICE_CONFIG_OPERATING_MODES_MSK		GENMASK(1, 0)
 76
 77/* AD4080_REG_TRANSFER_CONFIG Bit Definition */
 78#define AD4080_TRANSFER_CONFIG_KEEP_STREAM_LENGTH_VAL		BIT(2)
 79
 80/* AD4080_REG_INTERFACE_CONFIG_C Bit Definition */
 81#define AD4080_INTERFACE_CONFIG_C_STRICT_REG_ACCESS		BIT(5)
 82
 83/* AD4080_REG_ADC_DATA_INTF_CONFIG_A Bit Definition */
 84#define AD4080_ADC_DATA_INTF_CONFIG_A_RESERVED_CONFIG_A		BIT(6)
 85#define AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN		BIT(4)
 86#define AD4080_ADC_DATA_INTF_CONFIG_A_SPI_LVDS_LANES		BIT(2)
 87#define AD4080_ADC_DATA_INTF_CONFIG_A_DATA_INTF_MODE		BIT(0)
 88
 89/* AD4080_REG_ADC_DATA_INTF_CONFIG_B Bit Definition */
 90#define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK	GENMASK(7, 4)
 91#define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_SELF_CLK_MODE	BIT(3)
 92#define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_EN		BIT(0)
 93
 94/* AD4080_REG_ADC_DATA_INTF_CONFIG_C Bit Definition */
 95#define AD4080_ADC_DATA_INTF_CONFIG_C_LVDS_VOD_MSK		GENMASK(6, 4)
 96
 97/* AD4080_REG_PWR_CTRL Bit Definition */
 98#define AD4080_PWR_CTRL_ANA_DIG_LDO_PD				BIT(1)
 99#define AD4080_PWR_CTRL_INTF_LDO_PD				BIT(0)
100
101/* AD4080_REG_GPIO_CONFIG_A Bit Definition */
102#define AD4080_GPIO_CONFIG_A_GPO_1_EN				BIT(1)
103#define AD4080_GPIO_CONFIG_A_GPO_0_EN				BIT(0)
104
105/* AD4080_REG_GPIO_CONFIG_B Bit Definition */
106#define AD4080_GPIO_CONFIG_B_GPIO_1_SEL_MSK			GENMASK(7, 4)
107#define AD4080_GPIO_CONFIG_B_GPIO_0_SEL_MSK			GENMASK(3, 0)
108#define AD4080_GPIO_CONFIG_B_GPIO_SPI_SDO			0
109#define AD4080_GPIO_CONFIG_B_GPIO_FIFO_FULL			1
110#define AD4080_GPIO_CONFIG_B_GPIO_FIFO_READ_DONE		2
111#define AD4080_GPIO_CONFIG_B_GPIO_FILTER_RES_RDY		3
112#define AD4080_GPIO_CONFIG_B_GPIO_H_THRESH			4
113#define AD4080_GPIO_CONFIG_B_GPIO_L_THRESH			5
114#define AD4080_GPIO_CONFIG_B_GPIO_STATUS_ALERT			6
115#define AD4080_GPIO_CONFIG_B_GPIO_GPIO_DATA			7
116#define AD4080_GPIO_CONFIG_B_GPIO_FILTER_SYNC			8
117#define AD4080_GPIO_CONFIG_B_GPIO_EXTERNAL_EVENT		9
118
119/* AD4080_REG_FIFO_CONFIG Bit Definition */
120#define AD4080_FIFO_CONFIG_FIFO_MODE_MSK			GENMASK(1, 0)
121
122/* AD4080_REG_FILTER_CONFIG Bit Definition */
123#define AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK			GENMASK(6, 3)
124#define AD4080_FILTER_CONFIG_FILTER_SEL_MSK			GENMASK(1, 0)
125
126/* Miscellaneous Definitions */
127#define AD4080_SPI_READ						BIT(7)
128#define AD4080_CHIP_ID						0x0050
129#define AD4081_CHIP_ID						0x0051
130#define AD4083_CHIP_ID						0x0053
131#define AD4084_CHIP_ID						0x0054
132#define AD4086_CHIP_ID						0x0056
133#define AD4087_CHIP_ID						0x0057
134
135#define AD4080_LVDS_CNV_CLK_CNT_MAX				7
136
137#define AD4080_MAX_SAMP_FREQ					40000000
138#define AD4080_MIN_SAMP_FREQ					1250000
139
140enum ad4080_filter_type {
141	FILTER_NONE,
142	SINC_1,
143	SINC_5,
144	SINC_5_COMP
145};
146
147static const unsigned int ad4080_scale_table[][2] = {
148	{ 6000, 0 },
149};
150
151static const char *const ad4080_filter_type_iio_enum[] = {
152	[FILTER_NONE]      = "none",
153	[SINC_1]           = "sinc1",
154	[SINC_5]           = "sinc5",
155	[SINC_5_COMP]      = "sinc5+pf1",
156};
157
158static const int ad4080_dec_rate_avail[] = {
159	2, 4, 8, 16, 32, 64, 128, 256, 512, 1024,
160};
161
162static const int ad4080_dec_rate_none[] = { 1 };
163
164static const char * const ad4080_power_supplies[] = {
165	"vdd33", "vdd11", "vddldo", "iovdd", "vrefin",
166};
167
168struct ad4080_chip_info {
169	const char *name;
170	unsigned int product_id;
171	int num_scales;
172	const unsigned int (*scale_table)[2];
173	const struct iio_chan_spec *channels;
174	unsigned int num_channels;
175	unsigned int lvds_cnv_clk_cnt_max;
176};
177
178struct ad4080_state {
179	struct regmap			*regmap;
180	struct iio_backend		*back;
181	const struct ad4080_chip_info	*info;
182	/*
183	 * Synchronize access to members the of driver state, and ensure
184	 * atomicity of consecutive regmap operations.
185	 */
186	struct mutex			lock;
187	unsigned int			num_lanes;
188	unsigned int			dec_rate;
189	unsigned long			clk_rate;
190	enum ad4080_filter_type		filter_type;
191	bool				lvds_cnv_en;
192};
193
194static const struct regmap_config ad4080_regmap_config = {
195	.reg_bits = 16,
196	.val_bits = 8,
197	.read_flag_mask = BIT(7),
198	.max_register = 0x29,
199};
200
201static int ad4080_reg_access(struct iio_dev *indio_dev, unsigned int reg,
202			     unsigned int writeval, unsigned int *readval)
203{
204	struct ad4080_state *st = iio_priv(indio_dev);
205
206	if (readval)
207		return regmap_read(st->regmap, reg, readval);
208
209	return regmap_write(st->regmap, reg, writeval);
210}
211
212static int ad4080_get_scale(struct ad4080_state *st, int *val, int *val2)
213{
214	unsigned int tmp;
215
216	tmp = (st->info->scale_table[0][0] * 1000000ULL) >>
217		    st->info->channels[0].scan_type.realbits;
218	*val = tmp / 1000000;
219	*val2 = tmp % 1000000;
220
221	return IIO_VAL_INT_PLUS_NANO;
222}
223
224static unsigned int ad4080_get_dec_rate(struct iio_dev *dev,
225					const struct iio_chan_spec *chan)
226{
227	struct ad4080_state *st = iio_priv(dev);
228	int ret;
229	unsigned int data;
230
231	ret = regmap_read(st->regmap, AD4080_REG_FILTER_CONFIG, &data);
232	if (ret)
233		return ret;
234
235	return 1 << (FIELD_GET(AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK, data) + 1);
236}
237
238static int ad4080_set_dec_rate(struct iio_dev *dev,
239			       const struct iio_chan_spec *chan,
240			       unsigned int mode)
241{
242	struct ad4080_state *st = iio_priv(dev);
243
244	guard(mutex)(&st->lock);
245
246	if ((st->filter_type >= SINC_5 && mode >= 512) || mode < 2)
247		return -EINVAL;
248
249	return regmap_update_bits(st->regmap, AD4080_REG_FILTER_CONFIG,
250				  AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK,
251				  FIELD_PREP(AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK,
252					     (ilog2(mode) - 1)));
253}
254
255static int ad4080_read_raw(struct iio_dev *indio_dev,
256			   struct iio_chan_spec const *chan,
257			   int *val, int *val2, long m)
258{
259	struct ad4080_state *st = iio_priv(indio_dev);
260	int dec_rate;
261
262	switch (m) {
263	case IIO_CHAN_INFO_SCALE:
264		return ad4080_get_scale(st, val, val2);
265	case IIO_CHAN_INFO_SAMP_FREQ:
266		dec_rate = ad4080_get_dec_rate(indio_dev, chan);
267		if (dec_rate < 0)
268			return dec_rate;
269		if (st->filter_type == SINC_5_COMP)
270			dec_rate *= 2;
271		if (st->filter_type)
272			*val = DIV_ROUND_CLOSEST(st->clk_rate, dec_rate);
273		else
274			*val = st->clk_rate;
275		return IIO_VAL_INT;
276	case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
277		if (st->filter_type == FILTER_NONE) {
278			*val = 1;
279		} else {
280			*val = ad4080_get_dec_rate(indio_dev, chan);
281			if (*val < 0)
282				return *val;
283		}
284		return IIO_VAL_INT;
285	default:
286		return -EINVAL;
287	}
288}
289
290static int ad4080_write_raw(struct iio_dev *indio_dev,
291			    struct iio_chan_spec const *chan,
292			    int val, int val2, long mask)
293{
294	struct ad4080_state *st = iio_priv(indio_dev);
295
296	switch (mask) {
297	case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
298		if (st->filter_type == FILTER_NONE && val > 1)
299			return -EINVAL;
300
301		return ad4080_set_dec_rate(indio_dev, chan, val);
302	default:
303		return -EINVAL;
304	}
305}
306
307static int ad4080_lvds_sync_write(struct ad4080_state *st)
308{
309	struct device *dev = regmap_get_device(st->regmap);
310	int ret;
311
312	ret = regmap_set_bits(st->regmap, AD4080_REG_ADC_DATA_INTF_CONFIG_A,
313			      AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN);
314	if (ret)
315		return ret;
316
317	ret = iio_backend_interface_data_align(st->back, 10000);
318	if (ret)
319		return dev_err_probe(dev, ret,
320				     "Data alignment process failed\n");
321
322	dev_dbg(dev, "Success: Pattern correct and Locked!\n");
323	return regmap_clear_bits(st->regmap, AD4080_REG_ADC_DATA_INTF_CONFIG_A,
324				 AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN);
325}
326
327static int ad4080_get_filter_type(struct iio_dev *dev,
328				  const struct iio_chan_spec *chan)
329{
330	struct ad4080_state *st = iio_priv(dev);
331	unsigned int data;
332	int ret;
333
334	ret = regmap_read(st->regmap, AD4080_REG_FILTER_CONFIG, &data);
335	if (ret)
336		return ret;
337
338	return FIELD_GET(AD4080_FILTER_CONFIG_FILTER_SEL_MSK, data);
339}
340
341static int ad4080_set_filter_type(struct iio_dev *dev,
342				  const struct iio_chan_spec *chan,
343				  unsigned int mode)
344{
345	struct ad4080_state *st = iio_priv(dev);
346	int dec_rate;
347	int ret;
348
349	guard(mutex)(&st->lock);
350
351	dec_rate = ad4080_get_dec_rate(dev, chan);
352	if (dec_rate < 0)
353		return dec_rate;
354
355	if (mode >= SINC_5 && dec_rate >= 512)
356		return -EINVAL;
357
358	ret = iio_backend_filter_type_set(st->back, mode);
359	if (ret)
360		return ret;
361
362	ret = regmap_update_bits(st->regmap, AD4080_REG_FILTER_CONFIG,
363				 AD4080_FILTER_CONFIG_FILTER_SEL_MSK,
364				 FIELD_PREP(AD4080_FILTER_CONFIG_FILTER_SEL_MSK,
365					    mode));
366	if (ret)
367		return ret;
368
369	st->filter_type = mode;
370
371	return 0;
372}
373
374static int ad4080_read_avail(struct iio_dev *indio_dev,
375			     struct iio_chan_spec const *chan,
376			     const int **vals, int *type, int *length,
377			     long mask)
378{
379	struct ad4080_state *st = iio_priv(indio_dev);
380
381	switch (mask) {
382	case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
383		switch (st->filter_type) {
384		case FILTER_NONE:
385			*vals = ad4080_dec_rate_none;
386			*length = ARRAY_SIZE(ad4080_dec_rate_none);
387			break;
388		default:
389			*vals = ad4080_dec_rate_avail;
390			*length = st->filter_type >= SINC_5 ?
391				  (ARRAY_SIZE(ad4080_dec_rate_avail) - 2) :
392				  ARRAY_SIZE(ad4080_dec_rate_avail);
393			break;
394		}
395		*type = IIO_VAL_INT;
396		return IIO_AVAIL_LIST;
397	default:
398		return -EINVAL;
399	}
400}
401
402static const struct iio_info ad4080_iio_info = {
403	.debugfs_reg_access = ad4080_reg_access,
404	.read_raw = ad4080_read_raw,
405	.write_raw = ad4080_write_raw,
406	.read_avail = ad4080_read_avail,
407};
408
409static const struct iio_enum ad4080_filter_type_enum = {
410	.items = ad4080_filter_type_iio_enum,
411	.num_items = ARRAY_SIZE(ad4080_filter_type_iio_enum),
412	.set = ad4080_set_filter_type,
413	.get = ad4080_get_filter_type,
414};
415
416static struct iio_chan_spec_ext_info ad4080_ext_info[] = {
417	IIO_ENUM("filter_type", IIO_SHARED_BY_ALL, &ad4080_filter_type_enum),
418	IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_ALL,
419			   &ad4080_filter_type_enum),
420	{ }
421};
422
423#define AD4080_CHANNEL_DEFINE(bits, storage) {				\
424	.type = IIO_VOLTAGE,						\
425	.indexed = 1,							\
426	.channel = 0,							\
427	.info_mask_separate = BIT(IIO_CHAN_INFO_SCALE),			\
428	.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) |	\
429			BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),		\
430	.info_mask_shared_by_all_available =				\
431			BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),		\
432	.ext_info = ad4080_ext_info,					\
433	.scan_index = 0,						\
434	.scan_type = {							\
435		.sign = 's',						\
436		.realbits = (bits),					\
437		.storagebits = (storage),				\
438	},								\
439}
440
441static const struct iio_chan_spec ad4080_channel = AD4080_CHANNEL_DEFINE(20, 32);
442
443static const struct iio_chan_spec ad4081_channel = AD4080_CHANNEL_DEFINE(20, 32);
444
445static const struct iio_chan_spec ad4083_channel = AD4080_CHANNEL_DEFINE(16, 16);
446
447static const struct iio_chan_spec ad4084_channel = AD4080_CHANNEL_DEFINE(16, 16);
448
449static const struct iio_chan_spec ad4086_channel = AD4080_CHANNEL_DEFINE(14, 16);
450
451static const struct iio_chan_spec ad4087_channel = AD4080_CHANNEL_DEFINE(14, 16);
452
453static const struct ad4080_chip_info ad4080_chip_info = {
454	.name = "ad4080",
455	.product_id = AD4080_CHIP_ID,
456	.scale_table = ad4080_scale_table,
457	.num_scales = ARRAY_SIZE(ad4080_scale_table),
458	.num_channels = 1,
459	.channels = &ad4080_channel,
460	.lvds_cnv_clk_cnt_max = AD4080_LVDS_CNV_CLK_CNT_MAX,
461};
462
463static const struct ad4080_chip_info ad4081_chip_info = {
464	.name = "ad4081",
465	.product_id = AD4081_CHIP_ID,
466	.scale_table = ad4080_scale_table,
467	.num_scales = ARRAY_SIZE(ad4080_scale_table),
468	.num_channels = 1,
469	.channels = &ad4081_channel,
470	.lvds_cnv_clk_cnt_max = 2,
471};
472
473static const struct ad4080_chip_info ad4083_chip_info = {
474	.name = "ad4083",
475	.product_id = AD4083_CHIP_ID,
476	.scale_table = ad4080_scale_table,
477	.num_scales = ARRAY_SIZE(ad4080_scale_table),
478	.num_channels = 1,
479	.channels = &ad4083_channel,
480	.lvds_cnv_clk_cnt_max = 5,
481};
482
483static const struct ad4080_chip_info ad4084_chip_info = {
484	.name = "ad4084",
485	.product_id = AD4084_CHIP_ID,
486	.scale_table = ad4080_scale_table,
487	.num_scales = ARRAY_SIZE(ad4080_scale_table),
488	.num_channels = 1,
489	.channels = &ad4084_channel,
490	.lvds_cnv_clk_cnt_max = 2,
491};
492
493static const struct ad4080_chip_info ad4086_chip_info = {
494	.name = "ad4086",
495	.product_id = AD4086_CHIP_ID,
496	.scale_table = ad4080_scale_table,
497	.num_scales = ARRAY_SIZE(ad4080_scale_table),
498	.num_channels = 1,
499	.channels = &ad4086_channel,
500	.lvds_cnv_clk_cnt_max = 4,
501};
502
503static const struct ad4080_chip_info ad4087_chip_info = {
504	.name = "ad4087",
505	.product_id = AD4087_CHIP_ID,
506	.scale_table = ad4080_scale_table,
507	.num_scales = ARRAY_SIZE(ad4080_scale_table),
508	.num_channels = 1,
509	.channels = &ad4087_channel,
510	.lvds_cnv_clk_cnt_max = 1,
511};
512
513static int ad4080_setup(struct iio_dev *indio_dev)
514{
515	struct ad4080_state *st = iio_priv(indio_dev);
516	struct device *dev = regmap_get_device(st->regmap);
517	__le16 id_le;
518	u16 id;
519	int ret;
520
521	ret = regmap_write(st->regmap, AD4080_REG_INTERFACE_CONFIG_A,
522			   AD4080_INTERFACE_CONFIG_A_SW_RESET);
523	if (ret)
524		return ret;
525
526	ret = regmap_write(st->regmap, AD4080_REG_INTERFACE_CONFIG_A,
527			   AD4080_INTERFACE_CONFIG_A_SDO_ENABLE);
528	if (ret)
529		return ret;
530
531	ret = regmap_bulk_read(st->regmap, AD4080_REG_PRODUCT_ID_L, &id_le,
532			       sizeof(id_le));
533	if (ret)
534		return ret;
535
536	id = le16_to_cpu(id_le);
537	if (id != st->info->product_id)
538		dev_info(dev, "Unrecognized CHIP_ID 0x%X\n", id);
539
540	ret = regmap_set_bits(st->regmap, AD4080_REG_GPIO_CONFIG_A,
541			      AD4080_GPIO_CONFIG_A_GPO_1_EN);
542	if (ret)
543		return ret;
544
545	ret = regmap_write(st->regmap, AD4080_REG_GPIO_CONFIG_B,
546			   FIELD_PREP(AD4080_GPIO_CONFIG_B_GPIO_1_SEL_MSK,
547				      AD4080_GPIO_CONFIG_B_GPIO_FILTER_RES_RDY));
548	if (ret)
549		return ret;
550
551	ret = iio_backend_num_lanes_set(st->back, st->num_lanes);
552	if (ret)
553		return ret;
554
555	if (!st->lvds_cnv_en)
556		return 0;
557
558	/* Set maximum LVDS Data Transfer Latency */
559	ret = regmap_update_bits(st->regmap,
560				 AD4080_REG_ADC_DATA_INTF_CONFIG_B,
561				 AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK,
562				 FIELD_PREP(AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK,
563					    st->info->lvds_cnv_clk_cnt_max));
564	if (ret)
565		return ret;
566
567	if (st->num_lanes > 1) {
568		ret = regmap_set_bits(st->regmap, AD4080_REG_ADC_DATA_INTF_CONFIG_A,
569				      AD4080_ADC_DATA_INTF_CONFIG_A_SPI_LVDS_LANES);
570		if (ret)
571			return ret;
572	}
573
574	ret = regmap_set_bits(st->regmap,
575			      AD4080_REG_ADC_DATA_INTF_CONFIG_B,
576			      AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_EN);
577	if (ret)
578		return ret;
579
580	return ad4080_lvds_sync_write(st);
581}
582
583static int ad4080_properties_parse(struct ad4080_state *st)
584{
585	struct device *dev = regmap_get_device(st->regmap);
586
587	st->lvds_cnv_en = device_property_read_bool(dev, "adi,lvds-cnv-enable");
588
589	st->num_lanes = 1;
590	device_property_read_u32(dev, "adi,num-lanes", &st->num_lanes);
591	if (!st->num_lanes || st->num_lanes > 2)
592		return dev_err_probe(dev, -EINVAL,
593				     "Invalid 'adi,num-lanes' value: %u",
594				     st->num_lanes);
595
596	return 0;
597}
598
599static int ad4080_probe(struct spi_device *spi)
600{
601	struct iio_dev *indio_dev;
602	struct device *dev = &spi->dev;
603	struct ad4080_state *st;
604	struct clk *clk;
605	int ret;
606
607	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
608	if (!indio_dev)
609		return -ENOMEM;
610
611	st = iio_priv(indio_dev);
612
613	ret = devm_regulator_bulk_get_enable(dev,
614					     ARRAY_SIZE(ad4080_power_supplies),
615					     ad4080_power_supplies);
616	if (ret)
617		return dev_err_probe(dev, ret,
618				     "failed to get and enable supplies\n");
619
620	st->regmap = devm_regmap_init_spi(spi, &ad4080_regmap_config);
621	if (IS_ERR(st->regmap))
622		return PTR_ERR(st->regmap);
623
624	st->info = spi_get_device_match_data(spi);
625	if (!st->info)
626		return -ENODEV;
627
628	ret = devm_mutex_init(dev, &st->lock);
629	if (ret)
630		return ret;
631
632	indio_dev->name = st->info->name;
633	indio_dev->channels = st->info->channels;
634	indio_dev->num_channels = st->info->num_channels;
635	indio_dev->info = &ad4080_iio_info;
636
637	ret = ad4080_properties_parse(st);
638	if (ret)
639		return ret;
640
641	clk = devm_clk_get_enabled(&spi->dev, "cnv");
642	if (IS_ERR(clk))
643		return PTR_ERR(clk);
644
645	st->clk_rate = clk_get_rate(clk);
646
647	st->back = devm_iio_backend_get(dev, NULL);
648	if (IS_ERR(st->back))
649		return PTR_ERR(st->back);
650
651	ret = devm_iio_backend_request_buffer(dev, st->back, indio_dev);
652	if (ret)
653		return ret;
654
655	ret = devm_iio_backend_enable(dev, st->back);
656	if (ret)
657		return ret;
658
659	ret = ad4080_setup(indio_dev);
660	if (ret)
661		return ret;
662
663	return devm_iio_device_register(&spi->dev, indio_dev);
664}
665
666static const struct spi_device_id ad4080_id[] = {
667	{ "ad4080", (kernel_ulong_t)&ad4080_chip_info },
668	{ "ad4081", (kernel_ulong_t)&ad4081_chip_info },
669	{ "ad4083", (kernel_ulong_t)&ad4083_chip_info },
670	{ "ad4084", (kernel_ulong_t)&ad4084_chip_info },
671	{ "ad4086", (kernel_ulong_t)&ad4086_chip_info },
672	{ "ad4087", (kernel_ulong_t)&ad4087_chip_info },
673	{ }
674};
675MODULE_DEVICE_TABLE(spi, ad4080_id);
676
677static const struct of_device_id ad4080_of_match[] = {
678	{ .compatible = "adi,ad4080", &ad4080_chip_info },
679	{ .compatible = "adi,ad4081", &ad4081_chip_info },
680	{ .compatible = "adi,ad4083", &ad4083_chip_info },
681	{ .compatible = "adi,ad4084", &ad4084_chip_info },
682	{ .compatible = "adi,ad4086", &ad4086_chip_info },
683	{ .compatible = "adi,ad4087", &ad4087_chip_info },
684	{ }
685};
686MODULE_DEVICE_TABLE(of, ad4080_of_match);
687
688static struct spi_driver ad4080_driver = {
689	.driver = {
690		.name = "ad4080",
691		.of_match_table = ad4080_of_match,
692	},
693	.probe = ad4080_probe,
694	.id_table = ad4080_id,
695};
696module_spi_driver(ad4080_driver);
697
698MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com");
699MODULE_DESCRIPTION("Analog Devices AD4080");
700MODULE_LICENSE("GPL");
701MODULE_IMPORT_NS("IIO_BACKEND");