ad4030.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Analog Devices AD4030 and AD4630 ADC family driver.
   4 *
   5 * Copyright 2024 Analog Devices, Inc.
   6 * Copyright 2024 BayLibre, SAS
   7 *
   8 * based on code from:
   9 *	Analog Devices, Inc.
  10 *	  Sergiu Cuciurean <sergiu.cuciurean@analog.com>
  11 *	  Nuno Sa <nuno.sa@analog.com>
  12 *	  Marcelo Schmitt <marcelo.schmitt@analog.com>
  13 *	  Liviu Adace <liviu.adace@analog.com>
  14 */
  15
  16#include <linux/bitfield.h>
  17#include <linux/clk.h>
  18#include <linux/iio/iio.h>
  19#include <linux/iio/trigger_consumer.h>
  20#include <linux/iio/triggered_buffer.h>
  21#include <linux/regmap.h>
  22#include <linux/regulator/consumer.h>
  23#include <linux/spi/spi.h>
  24#include <linux/unaligned.h>
  25#include <linux/units.h>
  26
  27#define AD4030_REG_INTERFACE_CONFIG_A			0x00
  28#define     AD4030_REG_INTERFACE_CONFIG_A_SW_RESET	(BIT(0) | BIT(7))
  29#define AD4030_REG_INTERFACE_CONFIG_B			0x01
  30#define AD4030_REG_DEVICE_CONFIG			0x02
  31#define AD4030_REG_CHIP_TYPE				0x03
  32#define AD4030_REG_PRODUCT_ID_L				0x04
  33#define AD4030_REG_PRODUCT_ID_H				0x05
  34#define AD4030_REG_CHIP_GRADE				0x06
  35#define     AD4030_REG_CHIP_GRADE_AD4030_24_GRADE	0x10
  36#define     AD4030_REG_CHIP_GRADE_AD4630_16_GRADE	0x03
  37#define     AD4030_REG_CHIP_GRADE_AD4630_24_GRADE	0x00
  38#define     AD4030_REG_CHIP_GRADE_AD4632_16_GRADE	0x05
  39#define     AD4030_REG_CHIP_GRADE_AD4632_24_GRADE	0x02
  40#define     AD4030_REG_CHIP_GRADE_MASK_CHIP_GRADE	GENMASK(7, 3)
  41#define AD4030_REG_SCRATCH_PAD			0x0A
  42#define AD4030_REG_SPI_REVISION			0x0B
  43#define AD4030_REG_VENDOR_L			0x0C
  44#define AD4030_REG_VENDOR_H			0x0D
  45#define AD4030_REG_STREAM_MODE			0x0E
  46#define AD4030_REG_INTERFACE_CONFIG_C		0x10
  47#define AD4030_REG_INTERFACE_STATUS_A		0x11
  48#define AD4030_REG_EXIT_CFG_MODE		0x14
  49#define     AD4030_REG_EXIT_CFG_MODE_EXIT_MSK	BIT(0)
  50#define AD4030_REG_AVG				0x15
  51#define     AD4030_REG_AVG_MASK_AVG_SYNC	BIT(7)
  52#define     AD4030_REG_AVG_MASK_AVG_VAL		GENMASK(4, 0)
  53#define AD4030_REG_OFFSET_X0_0			0x16
  54#define AD4030_REG_OFFSET_X0_1			0x17
  55#define AD4030_REG_OFFSET_X0_2			0x18
  56#define AD4030_REG_OFFSET_X1_0			0x19
  57#define AD4030_REG_OFFSET_X1_1			0x1A
  58#define AD4030_REG_OFFSET_X1_2			0x1B
  59#define     AD4030_REG_OFFSET_BYTES_NB		3
  60#define     AD4030_REG_OFFSET_CHAN(ch)		\
  61	(AD4030_REG_OFFSET_X0_2 + (AD4030_REG_OFFSET_BYTES_NB * (ch)))
  62#define AD4030_REG_GAIN_X0_LSB			0x1C
  63#define AD4030_REG_GAIN_X0_MSB			0x1D
  64#define AD4030_REG_GAIN_X1_LSB			0x1E
  65#define AD4030_REG_GAIN_X1_MSB			0x1F
  66#define     AD4030_REG_GAIN_MAX_GAIN		1999970
  67#define     AD4030_REG_GAIN_BYTES_NB		2
  68#define     AD4030_REG_GAIN_CHAN(ch)		\
  69	(AD4030_REG_GAIN_X0_MSB + (AD4030_REG_GAIN_BYTES_NB * (ch)))
  70#define AD4030_REG_MODES			0x20
  71#define     AD4030_REG_MODES_MASK_OUT_DATA_MODE	GENMASK(2, 0)
  72#define     AD4030_REG_MODES_MASK_LANE_MODE	GENMASK(7, 6)
  73#define AD4030_REG_OSCILATOR			0x21
  74#define AD4030_REG_IO				0x22
  75#define     AD4030_REG_IO_MASK_IO2X		BIT(1)
  76#define AD4030_REG_PAT0				0x23
  77#define AD4030_REG_PAT1				0x24
  78#define AD4030_REG_PAT2				0x25
  79#define AD4030_REG_PAT3				0x26
  80#define AD4030_REG_DIG_DIAG			0x34
  81#define AD4030_REG_DIG_ERR			0x35
  82
  83/* Sequence starting with "1 0 1" to enable reg access */
  84#define AD4030_REG_ACCESS			0xA0
  85
  86#define AD4030_MAX_IIO_SAMPLE_SIZE_BUFFERED	BITS_TO_BYTES(64)
  87#define AD4030_MAX_HARDWARE_CHANNEL_NB		2
  88#define AD4030_MAX_IIO_CHANNEL_NB		5
  89#define AD4030_SINGLE_COMMON_BYTE_CHANNELS_MASK	0b10
  90#define AD4030_DUAL_COMMON_BYTE_CHANNELS_MASK	0b1100
  91#define AD4030_GAIN_MIDLE_POINT			0x8000
  92/*
  93 * This accounts for 1 sample per channel plus one s64 for the timestamp,
  94 * aligned on a s64 boundary
  95 */
  96#define AD4030_MAXIMUM_RX_BUFFER_SIZE			\
  97	(ALIGN(AD4030_MAX_IIO_SAMPLE_SIZE_BUFFERED *	\
  98	      AD4030_MAX_HARDWARE_CHANNEL_NB,		\
  99	      sizeof(s64)) + sizeof(s64))
 100
 101#define AD4030_VREF_MIN_UV		(4096 * MILLI)
 102#define AD4030_VREF_MAX_UV		(5000 * MILLI)
 103#define AD4030_VIO_THRESHOLD_UV		(1400 * MILLI)
 104#define AD4030_SPI_MAX_XFER_LEN		8
 105#define AD4030_SPI_MAX_REG_XFER_SPEED	(80 * MEGA)
 106#define AD4030_TCNVH_NS			10
 107#define AD4030_TCNVL_NS			20
 108#define AD4030_TCYC_NS			500
 109#define AD4030_TCYC_ADJUSTED_NS		(AD4030_TCYC_NS - AD4030_TCNVL_NS)
 110#define AD4030_TRESET_PW_NS		50
 111#define AD4632_TCYC_NS			2000
 112#define AD4632_TCYC_ADJUSTED_NS		(AD4632_TCYC_NS - AD4030_TCNVL_NS)
 113#define AD4030_TRESET_COM_DELAY_MS	750
 114
 115enum ad4030_out_mode {
 116	AD4030_OUT_DATA_MD_DIFF,
 117	AD4030_OUT_DATA_MD_16_DIFF_8_COM,
 118	AD4030_OUT_DATA_MD_24_DIFF_8_COM,
 119	AD4030_OUT_DATA_MD_30_AVERAGED_DIFF,
 120	AD4030_OUT_DATA_MD_32_PATTERN,
 121};
 122
 123enum {
 124	AD4030_LANE_MD_1_PER_CH,
 125	AD4030_LANE_MD_2_PER_CH,
 126	AD4030_LANE_MD_4_PER_CH,
 127	AD4030_LANE_MD_INTERLEAVED,
 128};
 129
 130enum {
 131	AD4030_SCAN_TYPE_NORMAL,
 132	AD4030_SCAN_TYPE_AVG,
 133};
 134
 135struct ad4030_chip_info {
 136	const char *name;
 137	const unsigned long *available_masks;
 138	const struct iio_chan_spec channels[AD4030_MAX_IIO_CHANNEL_NB];
 139	u8 grade;
 140	u8 precision_bits;
 141	/* Number of hardware channels */
 142	int num_voltage_inputs;
 143	unsigned int tcyc_ns;
 144};
 145
 146struct ad4030_state {
 147	struct spi_device *spi;
 148	struct regmap *regmap;
 149	const struct ad4030_chip_info *chip;
 150	struct gpio_desc *cnv_gpio;
 151	int vref_uv;
 152	int vio_uv;
 153	int offset_avail[3];
 154	unsigned int avg_log2;
 155	enum ad4030_out_mode mode;
 156
 157	/*
 158	 * DMA (thus cache coherency maintenance) requires the transfer buffers
 159	 * to live in their own cache lines.
 160	 */
 161	u8 tx_data[AD4030_SPI_MAX_XFER_LEN] __aligned(IIO_DMA_MINALIGN);
 162	union {
 163		u8 raw[AD4030_MAXIMUM_RX_BUFFER_SIZE];
 164		struct {
 165			s32 diff;
 166			u8 common;
 167		} single;
 168		struct {
 169			s32 diff[2];
 170			u8 common[2];
 171		} dual;
 172	} rx_data;
 173};
 174
 175/*
 176 * For a chip with 2 hardware channel this will be used to create 2 common-mode
 177 * channels:
 178 * - voltage4
 179 * - voltage5
 180 * As the common-mode channels are after the differential ones, we compute the
 181 * channel number like this:
 182 * - _idx is the scan_index (the order in the output buffer)
 183 * - _ch is the hardware channel number this common-mode channel is related
 184 * - _idx - _ch gives us the number of channel in the chip
 185 * - _idx - _ch * 2 is the starting number of the common-mode channels, since
 186 *   for each differential channel there is a common-mode channel
 187 * - _idx - _ch * 2 + _ch gives the channel number for this specific common-mode
 188 *   channel
 189 */
 190#define AD4030_CHAN_CMO(_idx, _ch)  {					\
 191	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |			\
 192		BIT(IIO_CHAN_INFO_SCALE),				\
 193	.type = IIO_VOLTAGE,						\
 194	.indexed = 1,							\
 195	.address = (_ch),						\
 196	.channel = ((_idx) - (_ch)) * 2 + (_ch),			\
 197	.scan_index = (_idx),						\
 198	.scan_type = {							\
 199		.sign = 'u',						\
 200		.storagebits = 8,					\
 201		.realbits = 8,						\
 202		.endianness = IIO_BE,					\
 203	},								\
 204}
 205
 206/*
 207 * For a chip with 2 hardware channel this will be used to create 2 differential
 208 * channels:
 209 * - voltage0-voltage1
 210 * - voltage2-voltage3
 211 */
 212#define AD4030_CHAN_DIFF(_idx, _scan_type) {				\
 213	.info_mask_shared_by_all =					\
 214		BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),			\
 215	.info_mask_shared_by_all_available =				\
 216		BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),			\
 217	.info_mask_separate = BIT(IIO_CHAN_INFO_SCALE) |		\
 218		BIT(IIO_CHAN_INFO_CALIBSCALE) |				\
 219		BIT(IIO_CHAN_INFO_CALIBBIAS) |				\
 220		BIT(IIO_CHAN_INFO_RAW),					\
 221	.info_mask_separate_available = BIT(IIO_CHAN_INFO_CALIBBIAS) |	\
 222		BIT(IIO_CHAN_INFO_CALIBSCALE),				\
 223	.type = IIO_VOLTAGE,						\
 224	.indexed = 1,							\
 225	.address = (_idx),						\
 226	.channel = (_idx) * 2,						\
 227	.channel2 = (_idx) * 2 + 1,					\
 228	.scan_index = (_idx),						\
 229	.differential = true,						\
 230	.has_ext_scan_type = 1,						\
 231	.ext_scan_type = _scan_type,					\
 232	.num_ext_scan_type = ARRAY_SIZE(_scan_type),			\
 233}
 234
 235static const int ad4030_average_modes[] = {
 236	1, 2, 4, 8, 16, 32, 64, 128,
 237	256, 512, 1024, 2048, 4096, 8192, 16384, 32768,
 238	65536,
 239};
 240
 241static int ad4030_enter_config_mode(struct ad4030_state *st)
 242{
 243	st->tx_data[0] = AD4030_REG_ACCESS;
 244
 245	struct spi_transfer xfer = {
 246		.tx_buf = st->tx_data,
 247		.len = 1,
 248		.speed_hz = AD4030_SPI_MAX_REG_XFER_SPEED,
 249	};
 250
 251	return spi_sync_transfer(st->spi, &xfer, 1);
 252}
 253
 254static int ad4030_exit_config_mode(struct ad4030_state *st)
 255{
 256	st->tx_data[0] = 0;
 257	st->tx_data[1] = AD4030_REG_EXIT_CFG_MODE;
 258	st->tx_data[2] = AD4030_REG_EXIT_CFG_MODE_EXIT_MSK;
 259
 260	struct spi_transfer xfer = {
 261		.tx_buf = st->tx_data,
 262		.len = 3,
 263		.speed_hz = AD4030_SPI_MAX_REG_XFER_SPEED,
 264	};
 265
 266	return spi_sync_transfer(st->spi, &xfer, 1);
 267}
 268
 269static int ad4030_spi_read(void *context, const void *reg, size_t reg_size,
 270			   void *val, size_t val_size)
 271{
 272	int ret;
 273	struct ad4030_state *st = context;
 274	struct spi_transfer xfer = {
 275		.tx_buf = st->tx_data,
 276		.rx_buf = st->rx_data.raw,
 277		.len = reg_size + val_size,
 278		.speed_hz = AD4030_SPI_MAX_REG_XFER_SPEED,
 279	};
 280
 281	if (xfer.len > sizeof(st->tx_data) ||
 282	    xfer.len > sizeof(st->rx_data.raw))
 283		return  -EINVAL;
 284
 285	ret = ad4030_enter_config_mode(st);
 286	if (ret)
 287		return ret;
 288
 289	memset(st->tx_data, 0, sizeof(st->tx_data));
 290	memcpy(st->tx_data, reg, reg_size);
 291
 292	ret = spi_sync_transfer(st->spi, &xfer, 1);
 293	if (ret)
 294		return ret;
 295
 296	memcpy(val, &st->rx_data.raw[reg_size], val_size);
 297
 298	return ad4030_exit_config_mode(st);
 299}
 300
 301static int ad4030_spi_write(void *context, const void *data, size_t count)
 302{
 303	int ret;
 304	struct ad4030_state *st = context;
 305	bool is_reset = count >= 3 &&
 306			((u8 *)data)[0] == 0 &&
 307			((u8 *)data)[1] == 0 &&
 308			((u8 *)data)[2] == 0x81;
 309	struct spi_transfer xfer = {
 310		.tx_buf = st->tx_data,
 311		.len = count,
 312		.speed_hz = AD4030_SPI_MAX_REG_XFER_SPEED,
 313	};
 314
 315	if (count > sizeof(st->tx_data))
 316		return  -EINVAL;
 317
 318	ret = ad4030_enter_config_mode(st);
 319	if (ret)
 320		return ret;
 321
 322	memcpy(st->tx_data, data, count);
 323
 324	ret = spi_sync_transfer(st->spi, &xfer, 1);
 325	if (ret)
 326		return ret;
 327
 328	/*
 329	 * From datasheet: "After a [...] reset, no SPI commands or conversions
 330	 * can be started for 750us"
 331	 *  After a reset we are in conversion mode, no need to exit config mode
 332	 */
 333	if (is_reset) {
 334		fsleep(750);
 335		return 0;
 336	}
 337
 338	return ad4030_exit_config_mode(st);
 339}
 340
 341static const struct regmap_bus ad4030_regmap_bus = {
 342	.read = ad4030_spi_read,
 343	.write = ad4030_spi_write,
 344	.reg_format_endian_default = REGMAP_ENDIAN_BIG,
 345};
 346
 347static const struct regmap_range ad4030_regmap_rd_range[] = {
 348	regmap_reg_range(AD4030_REG_INTERFACE_CONFIG_A, AD4030_REG_CHIP_GRADE),
 349	regmap_reg_range(AD4030_REG_SCRATCH_PAD, AD4030_REG_STREAM_MODE),
 350	regmap_reg_range(AD4030_REG_INTERFACE_CONFIG_C,
 351			 AD4030_REG_INTERFACE_STATUS_A),
 352	regmap_reg_range(AD4030_REG_EXIT_CFG_MODE, AD4030_REG_PAT3),
 353	regmap_reg_range(AD4030_REG_DIG_DIAG, AD4030_REG_DIG_ERR),
 354};
 355
 356static const struct regmap_range ad4030_regmap_wr_range[] = {
 357	regmap_reg_range(AD4030_REG_CHIP_TYPE, AD4030_REG_CHIP_GRADE),
 358	regmap_reg_range(AD4030_REG_SPI_REVISION, AD4030_REG_VENDOR_H),
 359};
 360
 361static const struct regmap_access_table ad4030_regmap_rd_table = {
 362	.yes_ranges = ad4030_regmap_rd_range,
 363	.n_yes_ranges = ARRAY_SIZE(ad4030_regmap_rd_range),
 364};
 365
 366static const struct regmap_access_table ad4030_regmap_wr_table = {
 367	.no_ranges = ad4030_regmap_wr_range,
 368	.n_no_ranges = ARRAY_SIZE(ad4030_regmap_wr_range),
 369};
 370
 371static const struct regmap_config ad4030_regmap_config = {
 372	.reg_bits = 16,
 373	.val_bits = 8,
 374	.read_flag_mask = 0x80,
 375	.rd_table = &ad4030_regmap_rd_table,
 376	.wr_table = &ad4030_regmap_wr_table,
 377	.max_register = AD4030_REG_DIG_ERR,
 378};
 379
 380static int ad4030_get_chan_scale(struct iio_dev *indio_dev,
 381				 struct iio_chan_spec const *chan,
 382				 int *val,
 383				 int *val2)
 384{
 385	struct ad4030_state *st = iio_priv(indio_dev);
 386	const struct iio_scan_type *scan_type;
 387
 388	scan_type = iio_get_current_scan_type(indio_dev, chan);
 389	if (IS_ERR(scan_type))
 390		return PTR_ERR(scan_type);
 391
 392	if (chan->differential)
 393		*val = (st->vref_uv * 2) / MILLI;
 394	else
 395		*val = st->vref_uv / MILLI;
 396
 397	*val2 = scan_type->realbits;
 398
 399	return IIO_VAL_FRACTIONAL_LOG2;
 400}
 401
 402static int ad4030_get_chan_calibscale(struct iio_dev *indio_dev,
 403				      struct iio_chan_spec const *chan,
 404				      int *val,
 405				      int *val2)
 406{
 407	struct ad4030_state *st = iio_priv(indio_dev);
 408	u16 gain;
 409	int ret;
 410
 411	ret = regmap_bulk_read(st->regmap, AD4030_REG_GAIN_CHAN(chan->address),
 412			       st->rx_data.raw, AD4030_REG_GAIN_BYTES_NB);
 413	if (ret)
 414		return ret;
 415
 416	gain = get_unaligned_be16(st->rx_data.raw);
 417
 418	/* From datasheet: multiplied output = input × gain word/0x8000 */
 419	*val = gain / AD4030_GAIN_MIDLE_POINT;
 420	*val2 = mul_u64_u32_div(gain % AD4030_GAIN_MIDLE_POINT, NANO,
 421				AD4030_GAIN_MIDLE_POINT);
 422
 423	return IIO_VAL_INT_PLUS_NANO;
 424}
 425
 426/* Returns the offset where 1 LSB = (VREF/2^precision_bits - 1)/gain */
 427static int ad4030_get_chan_calibbias(struct iio_dev *indio_dev,
 428				     struct iio_chan_spec const *chan,
 429				     int *val)
 430{
 431	struct ad4030_state *st = iio_priv(indio_dev);
 432	int ret;
 433
 434	ret = regmap_bulk_read(st->regmap,
 435			       AD4030_REG_OFFSET_CHAN(chan->address),
 436			       st->rx_data.raw, AD4030_REG_OFFSET_BYTES_NB);
 437	if (ret)
 438		return ret;
 439
 440	switch (st->chip->precision_bits) {
 441	case 16:
 442		*val = sign_extend32(get_unaligned_be16(st->rx_data.raw), 15);
 443		return IIO_VAL_INT;
 444
 445	case 24:
 446		*val = sign_extend32(get_unaligned_be24(st->rx_data.raw), 23);
 447		return IIO_VAL_INT;
 448
 449	default:
 450		return -EINVAL;
 451	}
 452}
 453
 454static int ad4030_set_chan_calibscale(struct iio_dev *indio_dev,
 455				      struct iio_chan_spec const *chan,
 456				      int gain_int,
 457				      int gain_frac)
 458{
 459	struct ad4030_state *st = iio_priv(indio_dev);
 460	u64 gain;
 461
 462	if (gain_int < 0 || gain_frac < 0)
 463		return -EINVAL;
 464
 465	gain = mul_u32_u32(gain_int, MICRO) + gain_frac;
 466
 467	if (gain > AD4030_REG_GAIN_MAX_GAIN)
 468		return -EINVAL;
 469
 470	put_unaligned_be16(DIV_ROUND_CLOSEST_ULL(gain * AD4030_GAIN_MIDLE_POINT,
 471						 MICRO),
 472			   st->tx_data);
 473
 474	return regmap_bulk_write(st->regmap,
 475				 AD4030_REG_GAIN_CHAN(chan->address),
 476				 st->tx_data, AD4030_REG_GAIN_BYTES_NB);
 477}
 478
 479static int ad4030_set_chan_calibbias(struct iio_dev *indio_dev,
 480				     struct iio_chan_spec const *chan,
 481				     int offset)
 482{
 483	struct ad4030_state *st = iio_priv(indio_dev);
 484
 485	if (offset < st->offset_avail[0] || offset > st->offset_avail[2])
 486		return -EINVAL;
 487
 488	st->tx_data[2] = 0;
 489
 490	switch (st->chip->precision_bits) {
 491	case 16:
 492		put_unaligned_be16(offset, st->tx_data);
 493		break;
 494
 495	case 24:
 496		put_unaligned_be24(offset, st->tx_data);
 497		break;
 498
 499	default:
 500		return -EINVAL;
 501	}
 502
 503	return regmap_bulk_write(st->regmap,
 504				 AD4030_REG_OFFSET_CHAN(chan->address),
 505				 st->tx_data, AD4030_REG_OFFSET_BYTES_NB);
 506}
 507
 508static int ad4030_set_avg_frame_len(struct iio_dev *dev, int avg_val)
 509{
 510	struct ad4030_state *st = iio_priv(dev);
 511	unsigned int avg_log2 = ilog2(avg_val);
 512	unsigned int last_avg_idx = ARRAY_SIZE(ad4030_average_modes) - 1;
 513	int ret;
 514
 515	if (avg_val < 0 || avg_val > ad4030_average_modes[last_avg_idx])
 516		return -EINVAL;
 517
 518	ret = regmap_write(st->regmap, AD4030_REG_AVG,
 519			   AD4030_REG_AVG_MASK_AVG_SYNC |
 520			   FIELD_PREP(AD4030_REG_AVG_MASK_AVG_VAL, avg_log2));
 521	if (ret)
 522		return ret;
 523
 524	st->avg_log2 = avg_log2;
 525
 526	return 0;
 527}
 528
 529static bool ad4030_is_common_byte_asked(struct ad4030_state *st,
 530					unsigned int mask)
 531{
 532	return mask & (st->chip->num_voltage_inputs == 1 ?
 533		AD4030_SINGLE_COMMON_BYTE_CHANNELS_MASK :
 534		AD4030_DUAL_COMMON_BYTE_CHANNELS_MASK);
 535}
 536
 537static int ad4030_set_mode(struct iio_dev *indio_dev, unsigned long mask)
 538{
 539	struct ad4030_state *st = iio_priv(indio_dev);
 540
 541	if (st->avg_log2 > 0) {
 542		st->mode = AD4030_OUT_DATA_MD_30_AVERAGED_DIFF;
 543	} else if (ad4030_is_common_byte_asked(st, mask)) {
 544		switch (st->chip->precision_bits) {
 545		case 16:
 546			st->mode = AD4030_OUT_DATA_MD_16_DIFF_8_COM;
 547			break;
 548
 549		case 24:
 550			st->mode = AD4030_OUT_DATA_MD_24_DIFF_8_COM;
 551			break;
 552
 553		default:
 554			return -EINVAL;
 555		}
 556	} else {
 557		st->mode = AD4030_OUT_DATA_MD_DIFF;
 558	}
 559
 560	return regmap_update_bits(st->regmap, AD4030_REG_MODES,
 561				  AD4030_REG_MODES_MASK_OUT_DATA_MODE,
 562				  st->mode);
 563}
 564
 565/*
 566 * Descramble 2 32bits numbers out of a 64bits. The bits are interleaved:
 567 * 1 bit for first number, 1 bit for the second, and so on...
 568 */
 569static void ad4030_extract_interleaved(u8 *src, u32 *ch0, u32 *ch1)
 570{
 571	u8 h0, h1, l0, l1;
 572	u32 out0, out1;
 573	u8 *out0_raw = (u8 *)&out0;
 574	u8 *out1_raw = (u8 *)&out1;
 575
 576	for (int i = 0; i < 4; i++) {
 577		h0 = src[i * 2];
 578		l1 = src[i * 2 + 1];
 579		h1 = h0 << 1;
 580		l0 = l1 >> 1;
 581
 582		h0 &= 0xAA;
 583		l0 &= 0x55;
 584		h1 &= 0xAA;
 585		l1 &= 0x55;
 586
 587		h0 = (h0 | h0 << 001) & 0xCC;
 588		h1 = (h1 | h1 << 001) & 0xCC;
 589		l0 = (l0 | l0 >> 001) & 0x33;
 590		l1 = (l1 | l1 >> 001) & 0x33;
 591		h0 = (h0 | h0 << 002) & 0xF0;
 592		h1 = (h1 | h1 << 002) & 0xF0;
 593		l0 = (l0 | l0 >> 002) & 0x0F;
 594		l1 = (l1 | l1 >> 002) & 0x0F;
 595
 596		out0_raw[i] = h0 | l0;
 597		out1_raw[i] = h1 | l1;
 598	}
 599
 600	*ch0 = out0;
 601	*ch1 = out1;
 602}
 603
 604static int ad4030_conversion(struct iio_dev *indio_dev)
 605{
 606	struct ad4030_state *st = iio_priv(indio_dev);
 607	const struct iio_scan_type *scan_type;
 608	unsigned char diff_realbytes, diff_storagebytes;
 609	unsigned int bytes_to_read;
 610	unsigned long cnv_nb = BIT(st->avg_log2);
 611	unsigned int i;
 612	int ret;
 613
 614	scan_type = iio_get_current_scan_type(indio_dev, st->chip->channels);
 615	if (IS_ERR(scan_type))
 616		return PTR_ERR(scan_type);
 617
 618	diff_realbytes = BITS_TO_BYTES(scan_type->realbits);
 619	diff_storagebytes = BITS_TO_BYTES(scan_type->storagebits);
 620
 621	/* Number of bytes for one differential channel */
 622	bytes_to_read = diff_realbytes;
 623	/* Add one byte if we are using a differential + common byte mode */
 624	bytes_to_read += (st->mode == AD4030_OUT_DATA_MD_24_DIFF_8_COM ||
 625			st->mode == AD4030_OUT_DATA_MD_16_DIFF_8_COM) ? 1 : 0;
 626	/* Mulitiply by the number of hardware channels */
 627	bytes_to_read *= st->chip->num_voltage_inputs;
 628
 629	for (i = 0; i < cnv_nb; i++) {
 630		gpiod_set_value_cansleep(st->cnv_gpio, 1);
 631		ndelay(AD4030_TCNVH_NS);
 632		gpiod_set_value_cansleep(st->cnv_gpio, 0);
 633		ndelay(st->chip->tcyc_ns);
 634	}
 635
 636	ret = spi_read(st->spi, st->rx_data.raw, bytes_to_read);
 637	if (ret)
 638		return ret;
 639
 640	if (st->chip->num_voltage_inputs == 2)
 641		ad4030_extract_interleaved(st->rx_data.raw,
 642					   &st->rx_data.dual.diff[0],
 643					   &st->rx_data.dual.diff[1]);
 644
 645	/*
 646	 * If no common mode voltage channel is enabled, we can use the raw
 647	 * data as is. Otherwise, we need to rearrange the data a bit to match
 648	 * the natural alignment of the IIO buffer.
 649	 */
 650
 651	if (st->mode != AD4030_OUT_DATA_MD_16_DIFF_8_COM &&
 652	    st->mode != AD4030_OUT_DATA_MD_24_DIFF_8_COM)
 653		return 0;
 654
 655	if (st->chip->num_voltage_inputs == 1) {
 656		st->rx_data.single.common = st->rx_data.raw[diff_realbytes];
 657		return 0;
 658	}
 659
 660	for (i = 0; i < st->chip->num_voltage_inputs; i++)
 661		st->rx_data.dual.common[i] =
 662			st->rx_data.raw[diff_storagebytes * i + diff_realbytes];
 663
 664	return 0;
 665}
 666
 667static int ad4030_single_conversion(struct iio_dev *indio_dev,
 668				    const struct iio_chan_spec *chan, int *val)
 669{
 670	struct ad4030_state *st = iio_priv(indio_dev);
 671	int ret;
 672
 673	ret = ad4030_set_mode(indio_dev, BIT(chan->scan_index));
 674	if (ret)
 675		return ret;
 676
 677	ret = ad4030_conversion(indio_dev);
 678	if (ret)
 679		return ret;
 680
 681	if (chan->differential)
 682		if (st->chip->num_voltage_inputs == 1)
 683			*val = st->rx_data.single.diff;
 684		else
 685			*val = st->rx_data.dual.diff[chan->address];
 686	else
 687		if (st->chip->num_voltage_inputs == 1)
 688			*val = st->rx_data.single.common;
 689		else
 690			*val = st->rx_data.dual.common[chan->address];
 691
 692	return IIO_VAL_INT;
 693}
 694
 695static irqreturn_t ad4030_trigger_handler(int irq, void *p)
 696{
 697	struct iio_poll_func *pf = p;
 698	struct iio_dev *indio_dev = pf->indio_dev;
 699	struct ad4030_state *st = iio_priv(indio_dev);
 700	int ret;
 701
 702	ret = ad4030_conversion(indio_dev);
 703	if (ret)
 704		goto out;
 705
 706	iio_push_to_buffers_with_ts(indio_dev, &st->rx_data, sizeof(st->rx_data),
 707				    pf->timestamp);
 708
 709out:
 710	iio_trigger_notify_done(indio_dev->trig);
 711
 712	return IRQ_HANDLED;
 713}
 714
 715static const int ad4030_gain_avail[3][2] = {
 716	{ 0, 0 },
 717	{ 0, 30518 },
 718	{ 1, 999969482 },
 719};
 720
 721static int ad4030_read_avail(struct iio_dev *indio_dev,
 722			     struct iio_chan_spec const *channel,
 723			     const int **vals, int *type,
 724			     int *length, long mask)
 725{
 726	struct ad4030_state *st = iio_priv(indio_dev);
 727
 728	switch (mask) {
 729	case IIO_CHAN_INFO_CALIBBIAS:
 730		*vals = st->offset_avail;
 731		*type = IIO_VAL_INT;
 732		return IIO_AVAIL_RANGE;
 733
 734	case IIO_CHAN_INFO_CALIBSCALE:
 735		*vals = (void *)ad4030_gain_avail;
 736		*type = IIO_VAL_INT_PLUS_NANO;
 737		return IIO_AVAIL_RANGE;
 738
 739	case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
 740		*vals = ad4030_average_modes;
 741		*type = IIO_VAL_INT;
 742		*length = ARRAY_SIZE(ad4030_average_modes);
 743		return IIO_AVAIL_LIST;
 744
 745	default:
 746		return -EINVAL;
 747	}
 748}
 749
 750static int ad4030_read_raw_dispatch(struct iio_dev *indio_dev,
 751				    struct iio_chan_spec const *chan, int *val,
 752				    int *val2, long info)
 753{
 754	struct ad4030_state *st = iio_priv(indio_dev);
 755
 756	switch (info) {
 757	case IIO_CHAN_INFO_RAW:
 758		return ad4030_single_conversion(indio_dev, chan, val);
 759
 760	case IIO_CHAN_INFO_CALIBSCALE:
 761		return ad4030_get_chan_calibscale(indio_dev, chan, val, val2);
 762
 763	case IIO_CHAN_INFO_CALIBBIAS:
 764		return ad4030_get_chan_calibbias(indio_dev, chan, val);
 765
 766	case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
 767		*val = BIT(st->avg_log2);
 768		return IIO_VAL_INT;
 769
 770	default:
 771		return -EINVAL;
 772	}
 773}
 774
 775static int ad4030_read_raw(struct iio_dev *indio_dev,
 776			   struct iio_chan_spec const *chan, int *val,
 777			   int *val2, long info)
 778{
 779	int ret;
 780
 781	if (info == IIO_CHAN_INFO_SCALE)
 782		return ad4030_get_chan_scale(indio_dev, chan, val, val2);
 783
 784	if (!iio_device_claim_direct(indio_dev))
 785		return -EBUSY;
 786
 787	ret = ad4030_read_raw_dispatch(indio_dev, chan, val, val2, info);
 788
 789	iio_device_release_direct(indio_dev);
 790
 791	return ret;
 792}
 793
 794static int ad4030_write_raw_dispatch(struct iio_dev *indio_dev,
 795				     struct iio_chan_spec const *chan, int val,
 796				     int val2, long info)
 797{
 798	switch (info) {
 799	case IIO_CHAN_INFO_CALIBSCALE:
 800		return ad4030_set_chan_calibscale(indio_dev, chan, val, val2);
 801
 802	case IIO_CHAN_INFO_CALIBBIAS:
 803		if (val2 != 0)
 804			return -EINVAL;
 805		return ad4030_set_chan_calibbias(indio_dev, chan, val);
 806
 807	case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
 808		return ad4030_set_avg_frame_len(indio_dev, val);
 809
 810	default:
 811		return -EINVAL;
 812	}
 813}
 814
 815static int ad4030_write_raw(struct iio_dev *indio_dev,
 816			    struct iio_chan_spec const *chan, int val,
 817			    int val2, long info)
 818{
 819	int ret;
 820
 821	if (!iio_device_claim_direct(indio_dev))
 822		return -EBUSY;
 823
 824	ret = ad4030_write_raw_dispatch(indio_dev, chan, val, val2, info);
 825
 826	iio_device_release_direct(indio_dev);
 827
 828	return ret;
 829}
 830
 831static int ad4030_reg_access(struct iio_dev *indio_dev, unsigned int reg,
 832			     unsigned int writeval, unsigned int *readval)
 833{
 834	const struct ad4030_state *st = iio_priv(indio_dev);
 835	int ret;
 836
 837	if (!iio_device_claim_direct(indio_dev))
 838		return -EBUSY;
 839
 840	if (readval)
 841		ret = regmap_read(st->regmap, reg, readval);
 842	else
 843		ret = regmap_write(st->regmap, reg, writeval);
 844
 845	iio_device_release_direct(indio_dev);
 846
 847	return ret;
 848}
 849
 850static int ad4030_read_label(struct iio_dev *indio_dev,
 851			     struct iio_chan_spec const *chan,
 852			     char *label)
 853{
 854	if (chan->differential)
 855		return sysfs_emit(label, "differential%lu\n", chan->address);
 856	return sysfs_emit(label, "common-mode%lu\n", chan->address);
 857}
 858
 859static int ad4030_get_current_scan_type(const struct iio_dev *indio_dev,
 860					const struct iio_chan_spec *chan)
 861{
 862	struct ad4030_state *st = iio_priv(indio_dev);
 863
 864	return st->avg_log2 ? AD4030_SCAN_TYPE_AVG : AD4030_SCAN_TYPE_NORMAL;
 865}
 866
 867static int ad4030_update_scan_mode(struct iio_dev *indio_dev,
 868				   const unsigned long *scan_mask)
 869{
 870	return ad4030_set_mode(indio_dev, *scan_mask);
 871}
 872
 873static const struct iio_info ad4030_iio_info = {
 874	.read_avail = ad4030_read_avail,
 875	.read_raw = ad4030_read_raw,
 876	.write_raw = ad4030_write_raw,
 877	.debugfs_reg_access = ad4030_reg_access,
 878	.read_label = ad4030_read_label,
 879	.get_current_scan_type = ad4030_get_current_scan_type,
 880	.update_scan_mode  = ad4030_update_scan_mode,
 881};
 882
 883static bool ad4030_validate_scan_mask(struct iio_dev *indio_dev,
 884				      const unsigned long *scan_mask)
 885{
 886	struct ad4030_state *st = iio_priv(indio_dev);
 887
 888	/* Asking for both common channels and averaging */
 889	if (st->avg_log2 && ad4030_is_common_byte_asked(st, *scan_mask))
 890		return false;
 891
 892	return true;
 893}
 894
 895static const struct iio_buffer_setup_ops ad4030_buffer_setup_ops = {
 896	.validate_scan_mask = ad4030_validate_scan_mask,
 897};
 898
 899static int ad4030_regulators_get(struct ad4030_state *st)
 900{
 901	struct device *dev = &st->spi->dev;
 902	static const char * const ids[] = { "vdd-5v", "vdd-1v8" };
 903	int ret;
 904
 905	ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ids), ids);
 906	if (ret)
 907		return dev_err_probe(dev, ret, "Failed to enable regulators\n");
 908
 909	st->vio_uv = devm_regulator_get_enable_read_voltage(dev, "vio");
 910	if (st->vio_uv < 0)
 911		return dev_err_probe(dev, st->vio_uv,
 912				     "Failed to enable and read vio voltage\n");
 913
 914	st->vref_uv = devm_regulator_get_enable_read_voltage(dev, "ref");
 915	if (st->vref_uv < 0) {
 916		if (st->vref_uv != -ENODEV)
 917			return dev_err_probe(dev, st->vref_uv,
 918					     "Failed to read ref voltage\n");
 919
 920		/* if not using optional REF, the REFIN must be used */
 921		st->vref_uv = devm_regulator_get_enable_read_voltage(dev,
 922								     "refin");
 923		if (st->vref_uv < 0)
 924			return dev_err_probe(dev, st->vref_uv,
 925					     "Failed to read refin voltage\n");
 926	}
 927
 928	return 0;
 929}
 930
 931static int ad4030_reset(struct ad4030_state *st)
 932{
 933	struct device *dev = &st->spi->dev;
 934	struct gpio_desc *reset;
 935
 936	reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
 937	if (IS_ERR(reset))
 938		return dev_err_probe(dev, PTR_ERR(reset),
 939				     "Failed to get reset GPIO\n");
 940
 941	if (reset) {
 942		ndelay(50);
 943		gpiod_set_value_cansleep(reset, 0);
 944		return 0;
 945	}
 946
 947	return regmap_write(st->regmap, AD4030_REG_INTERFACE_CONFIG_A,
 948			   AD4030_REG_INTERFACE_CONFIG_A_SW_RESET);
 949}
 950
 951static int ad4030_detect_chip_info(const struct ad4030_state *st)
 952{
 953	unsigned int grade;
 954	int ret;
 955
 956	ret = regmap_read(st->regmap, AD4030_REG_CHIP_GRADE, &grade);
 957	if (ret)
 958		return ret;
 959
 960	grade = FIELD_GET(AD4030_REG_CHIP_GRADE_MASK_CHIP_GRADE, grade);
 961	if (grade != st->chip->grade)
 962		dev_warn(&st->spi->dev, "Unknown grade(0x%x) for %s\n", grade,
 963			 st->chip->name);
 964
 965	return 0;
 966}
 967
 968static int ad4030_config(struct ad4030_state *st)
 969{
 970	int ret;
 971	u8 reg_modes;
 972
 973	st->offset_avail[0] = (int)BIT(st->chip->precision_bits - 1) * -1;
 974	st->offset_avail[1] = 1;
 975	st->offset_avail[2] = BIT(st->chip->precision_bits - 1) - 1;
 976
 977	if (st->chip->num_voltage_inputs > 1)
 978		reg_modes = FIELD_PREP(AD4030_REG_MODES_MASK_LANE_MODE,
 979				       AD4030_LANE_MD_INTERLEAVED);
 980	else
 981		reg_modes = FIELD_PREP(AD4030_REG_MODES_MASK_LANE_MODE,
 982				       AD4030_LANE_MD_1_PER_CH);
 983
 984	ret = regmap_write(st->regmap, AD4030_REG_MODES, reg_modes);
 985	if (ret)
 986		return ret;
 987
 988	if (st->vio_uv < AD4030_VIO_THRESHOLD_UV)
 989		return regmap_write(st->regmap, AD4030_REG_IO,
 990				    AD4030_REG_IO_MASK_IO2X);
 991
 992	return 0;
 993}
 994
 995static int ad4030_probe(struct spi_device *spi)
 996{
 997	struct device *dev = &spi->dev;
 998	struct iio_dev *indio_dev;
 999	struct ad4030_state *st;
1000	int ret;
1001
1002	indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
1003	if (!indio_dev)
1004		return -ENOMEM;
1005
1006	st = iio_priv(indio_dev);
1007	st->spi = spi;
1008
1009	st->regmap = devm_regmap_init(dev, &ad4030_regmap_bus, st,
1010				      &ad4030_regmap_config);
1011	if (IS_ERR(st->regmap))
1012		return dev_err_probe(dev, PTR_ERR(st->regmap),
1013				     "Failed to initialize regmap\n");
1014
1015	st->chip = spi_get_device_match_data(spi);
1016	if (!st->chip)
1017		return -EINVAL;
1018
1019	ret = ad4030_regulators_get(st);
1020	if (ret)
1021		return ret;
1022
1023	/*
1024	 * From datasheet: "Perform a reset no sooner than 3ms after the power
1025	 * supplies are valid and stable"
1026	 */
1027	fsleep(3000);
1028
1029	ret = ad4030_reset(st);
1030	if (ret)
1031		return ret;
1032
1033	ret = ad4030_detect_chip_info(st);
1034	if (ret)
1035		return ret;
1036
1037	ret = ad4030_config(st);
1038	if (ret)
1039		return ret;
1040
1041	st->cnv_gpio = devm_gpiod_get(dev, "cnv", GPIOD_OUT_LOW);
1042	if (IS_ERR(st->cnv_gpio))
1043		return dev_err_probe(dev, PTR_ERR(st->cnv_gpio),
1044				     "Failed to get cnv gpio\n");
1045
1046	/*
1047	 * One hardware channel is split in two software channels when using
1048	 * common byte mode. Add one more channel for the timestamp.
1049	 */
1050	indio_dev->num_channels = 2 * st->chip->num_voltage_inputs + 1;
1051	indio_dev->name = st->chip->name;
1052	indio_dev->modes = INDIO_DIRECT_MODE;
1053	indio_dev->info = &ad4030_iio_info;
1054	indio_dev->channels = st->chip->channels;
1055	indio_dev->available_scan_masks = st->chip->available_masks;
1056
1057	ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
1058					      iio_pollfunc_store_time,
1059					      ad4030_trigger_handler,
1060					      &ad4030_buffer_setup_ops);
1061	if (ret)
1062		return dev_err_probe(dev, ret,
1063				     "Failed to setup triggered buffer\n");
1064
1065	return devm_iio_device_register(dev, indio_dev);
1066}
1067
1068static const unsigned long ad4030_channel_masks[] = {
1069	/* Differential only */
1070	BIT(0),
1071	/* Differential and common-mode voltage */
1072	GENMASK(1, 0),
1073	0,
1074};
1075
1076static const unsigned long ad4630_channel_masks[] = {
1077	/* Differential only */
1078	BIT(1) | BIT(0),
1079	/* Differential with common byte */
1080	GENMASK(3, 0),
1081	0,
1082};
1083
1084static const struct iio_scan_type ad4030_24_scan_types[] = {
1085	[AD4030_SCAN_TYPE_NORMAL] = {
1086		.sign = 's',
1087		.storagebits = 32,
1088		.realbits = 24,
1089		.shift = 8,
1090		.endianness = IIO_BE,
1091	},
1092	[AD4030_SCAN_TYPE_AVG] = {
1093		.sign = 's',
1094		.storagebits = 32,
1095		.realbits = 30,
1096		.shift = 2,
1097		.endianness = IIO_BE,
1098	},
1099};
1100
1101static const struct iio_scan_type ad4030_16_scan_types[] = {
1102	[AD4030_SCAN_TYPE_NORMAL] = {
1103		.sign = 's',
1104		.storagebits = 32,
1105		.realbits = 16,
1106		.shift = 16,
1107		.endianness = IIO_BE,
1108	},
1109	[AD4030_SCAN_TYPE_AVG] = {
1110		.sign = 's',
1111		.storagebits = 32,
1112		.realbits = 30,
1113		.shift = 2,
1114		.endianness = IIO_BE,
1115	}
1116};
1117
1118static const struct ad4030_chip_info ad4030_24_chip_info = {
1119	.name = "ad4030-24",
1120	.available_masks = ad4030_channel_masks,
1121	.channels = {
1122		AD4030_CHAN_DIFF(0, ad4030_24_scan_types),
1123		AD4030_CHAN_CMO(1, 0),
1124		IIO_CHAN_SOFT_TIMESTAMP(2),
1125	},
1126	.grade = AD4030_REG_CHIP_GRADE_AD4030_24_GRADE,
1127	.precision_bits = 24,
1128	.num_voltage_inputs = 1,
1129	.tcyc_ns = AD4030_TCYC_ADJUSTED_NS,
1130};
1131
1132static const struct ad4030_chip_info ad4630_16_chip_info = {
1133	.name = "ad4630-16",
1134	.available_masks = ad4630_channel_masks,
1135	.channels = {
1136		AD4030_CHAN_DIFF(0, ad4030_16_scan_types),
1137		AD4030_CHAN_DIFF(1, ad4030_16_scan_types),
1138		AD4030_CHAN_CMO(2, 0),
1139		AD4030_CHAN_CMO(3, 1),
1140		IIO_CHAN_SOFT_TIMESTAMP(4),
1141	},
1142	.grade = AD4030_REG_CHIP_GRADE_AD4630_16_GRADE,
1143	.precision_bits = 16,
1144	.num_voltage_inputs = 2,
1145	.tcyc_ns = AD4030_TCYC_ADJUSTED_NS,
1146};
1147
1148static const struct ad4030_chip_info ad4630_24_chip_info = {
1149	.name = "ad4630-24",
1150	.available_masks = ad4630_channel_masks,
1151	.channels = {
1152		AD4030_CHAN_DIFF(0, ad4030_24_scan_types),
1153		AD4030_CHAN_DIFF(1, ad4030_24_scan_types),
1154		AD4030_CHAN_CMO(2, 0),
1155		AD4030_CHAN_CMO(3, 1),
1156		IIO_CHAN_SOFT_TIMESTAMP(4),
1157	},
1158	.grade = AD4030_REG_CHIP_GRADE_AD4630_24_GRADE,
1159	.precision_bits = 24,
1160	.num_voltage_inputs = 2,
1161	.tcyc_ns = AD4030_TCYC_ADJUSTED_NS,
1162};
1163
1164static const struct ad4030_chip_info ad4632_16_chip_info = {
1165	.name = "ad4632-16",
1166	.available_masks = ad4630_channel_masks,
1167	.channels = {
1168		AD4030_CHAN_DIFF(0, ad4030_16_scan_types),
1169		AD4030_CHAN_DIFF(1, ad4030_16_scan_types),
1170		AD4030_CHAN_CMO(2, 0),
1171		AD4030_CHAN_CMO(3, 1),
1172		IIO_CHAN_SOFT_TIMESTAMP(4),
1173	},
1174	.grade = AD4030_REG_CHIP_GRADE_AD4632_16_GRADE,
1175	.precision_bits = 16,
1176	.num_voltage_inputs = 2,
1177	.tcyc_ns = AD4632_TCYC_ADJUSTED_NS,
1178};
1179
1180static const struct ad4030_chip_info ad4632_24_chip_info = {
1181	.name = "ad4632-24",
1182	.available_masks = ad4630_channel_masks,
1183	.channels = {
1184		AD4030_CHAN_DIFF(0, ad4030_24_scan_types),
1185		AD4030_CHAN_DIFF(1, ad4030_24_scan_types),
1186		AD4030_CHAN_CMO(2, 0),
1187		AD4030_CHAN_CMO(3, 1),
1188		IIO_CHAN_SOFT_TIMESTAMP(4),
1189	},
1190	.grade = AD4030_REG_CHIP_GRADE_AD4632_24_GRADE,
1191	.precision_bits = 24,
1192	.num_voltage_inputs = 2,
1193	.tcyc_ns = AD4632_TCYC_ADJUSTED_NS,
1194};
1195
1196static const struct spi_device_id ad4030_id_table[] = {
1197	{ "ad4030-24", (kernel_ulong_t)&ad4030_24_chip_info },
1198	{ "ad4630-16", (kernel_ulong_t)&ad4630_16_chip_info },
1199	{ "ad4630-24", (kernel_ulong_t)&ad4630_24_chip_info },
1200	{ "ad4632-16", (kernel_ulong_t)&ad4632_16_chip_info },
1201	{ "ad4632-24", (kernel_ulong_t)&ad4632_24_chip_info },
1202	{ }
1203};
1204MODULE_DEVICE_TABLE(spi, ad4030_id_table);
1205
1206static const struct of_device_id ad4030_of_match[] = {
1207	{ .compatible = "adi,ad4030-24", .data = &ad4030_24_chip_info },
1208	{ .compatible = "adi,ad4630-16", .data = &ad4630_16_chip_info },
1209	{ .compatible = "adi,ad4630-24", .data = &ad4630_24_chip_info },
1210	{ .compatible = "adi,ad4632-16", .data = &ad4632_16_chip_info },
1211	{ .compatible = "adi,ad4632-24", .data = &ad4632_24_chip_info },
1212	{ }
1213};
1214MODULE_DEVICE_TABLE(of, ad4030_of_match);
1215
1216static struct spi_driver ad4030_driver = {
1217	.driver = {
1218		.name = "ad4030",
1219		.of_match_table = ad4030_of_match,
1220	},
1221	.probe = ad4030_probe,
1222	.id_table = ad4030_id_table,
1223};
1224module_spi_driver(ad4030_driver);
1225
1226MODULE_AUTHOR("Esteban Blanc <eblanc@baylibre.com>");
1227MODULE_DESCRIPTION("Analog Devices AD4630 ADC family driver");
1228MODULE_LICENSE("GPL");