sca3000.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * sca3000_core.c -- support VTI sca3000 series accelerometers via SPI
   4 *
   5 * Copyright (c) 2009 Jonathan Cameron <jic23@kernel.org>
   6 *
   7 * See industrialio/accels/sca3000.h for comments.
   8 */
   9
  10#include <linux/interrupt.h>
  11#include <linux/fs.h>
  12#include <linux/device.h>
  13#include <linux/slab.h>
  14#include <linux/kernel.h>
  15#include <linux/spi/spi.h>
  16#include <linux/sysfs.h>
  17#include <linux/module.h>
  18#include <linux/uaccess.h>
  19#include <linux/iio/iio.h>
  20#include <linux/iio/sysfs.h>
  21#include <linux/iio/events.h>
  22#include <linux/iio/buffer.h>
  23#include <linux/iio/kfifo_buf.h>
  24
  25#define SCA3000_WRITE_REG(a) (((a) << 2) | 0x02)
  26#define SCA3000_READ_REG(a) ((a) << 2)
  27
  28#define SCA3000_REG_REVID_ADDR				0x00
  29#define   SCA3000_REG_REVID_MAJOR_MASK			GENMASK(8, 4)
  30#define   SCA3000_REG_REVID_MINOR_MASK			GENMASK(3, 0)
  31
  32#define SCA3000_REG_STATUS_ADDR				0x02
  33#define   SCA3000_LOCKED				BIT(5)
  34#define   SCA3000_EEPROM_CS_ERROR			BIT(1)
  35#define   SCA3000_SPI_FRAME_ERROR			BIT(0)
  36
  37/* All reads done using register decrement so no need to directly access LSBs */
  38#define SCA3000_REG_X_MSB_ADDR				0x05
  39#define SCA3000_REG_Y_MSB_ADDR				0x07
  40#define SCA3000_REG_Z_MSB_ADDR				0x09
  41
  42#define SCA3000_REG_RING_OUT_ADDR			0x0f
  43
  44/* Temp read untested - the e05 doesn't have the sensor */
  45#define SCA3000_REG_TEMP_MSB_ADDR			0x13
  46
  47#define SCA3000_REG_MODE_ADDR				0x14
  48#define SCA3000_MODE_PROT_MASK				0x28
  49#define   SCA3000_REG_MODE_RING_BUF_ENABLE		BIT(7)
  50#define   SCA3000_REG_MODE_RING_BUF_8BIT		BIT(6)
  51
  52/*
  53 * Free fall detection triggers an interrupt if the acceleration
  54 * is below a threshold for equivalent of 25cm drop
  55 */
  56#define   SCA3000_REG_MODE_FREE_FALL_DETECT		BIT(4)
  57#define   SCA3000_REG_MODE_MEAS_MODE_NORMAL		0x00
  58#define   SCA3000_REG_MODE_MEAS_MODE_OP_1		0x01
  59#define   SCA3000_REG_MODE_MEAS_MODE_OP_2		0x02
  60
  61/*
  62 * In motion detection mode the accelerations are band pass filtered
  63 * (approx 1 - 25Hz) and then a programmable threshold used to trigger
  64 * and interrupt.
  65 */
  66#define   SCA3000_REG_MODE_MEAS_MODE_MOT_DET		0x03
  67#define   SCA3000_REG_MODE_MODE_MASK			0x03
  68
  69#define SCA3000_REG_BUF_COUNT_ADDR			0x15
  70
  71#define SCA3000_REG_INT_STATUS_ADDR			0x16
  72#define   SCA3000_REG_INT_STATUS_THREE_QUARTERS		BIT(7)
  73#define   SCA3000_REG_INT_STATUS_HALF			BIT(6)
  74
  75#define SCA3000_INT_STATUS_FREE_FALL			BIT(3)
  76#define SCA3000_INT_STATUS_Y_TRIGGER			BIT(2)
  77#define SCA3000_INT_STATUS_X_TRIGGER			BIT(1)
  78#define SCA3000_INT_STATUS_Z_TRIGGER			BIT(0)
  79
  80/* Used to allow access to multiplexed registers */
  81#define SCA3000_REG_CTRL_SEL_ADDR			0x18
  82/* Only available for SCA3000-D03 and SCA3000-D01 */
  83#define   SCA3000_REG_CTRL_SEL_I2C_DISABLE		0x01
  84#define   SCA3000_REG_CTRL_SEL_MD_CTRL			0x02
  85#define   SCA3000_REG_CTRL_SEL_MD_Y_TH			0x03
  86#define   SCA3000_REG_CTRL_SEL_MD_X_TH			0x04
  87#define   SCA3000_REG_CTRL_SEL_MD_Z_TH			0x05
  88/*
  89 * BE VERY CAREFUL WITH THIS, IF 3 BITS ARE NOT SET the device
  90 * will not function
  91 */
  92#define   SCA3000_REG_CTRL_SEL_OUT_CTRL			0x0B
  93
  94#define     SCA3000_REG_OUT_CTRL_PROT_MASK		0xE0
  95#define     SCA3000_REG_OUT_CTRL_BUF_X_EN		0x10
  96#define     SCA3000_REG_OUT_CTRL_BUF_Y_EN		0x08
  97#define     SCA3000_REG_OUT_CTRL_BUF_Z_EN		0x04
  98#define     SCA3000_REG_OUT_CTRL_BUF_DIV_MASK		0x03
  99#define     SCA3000_REG_OUT_CTRL_BUF_DIV_4		0x02
 100#define     SCA3000_REG_OUT_CTRL_BUF_DIV_2		0x01
 101
 102
 103/*
 104 * Control which motion detector interrupts are on.
 105 * For now only OR combinations are supported.
 106 */
 107#define SCA3000_MD_CTRL_PROT_MASK			0xC0
 108#define SCA3000_MD_CTRL_OR_Y				BIT(0)
 109#define SCA3000_MD_CTRL_OR_X				BIT(1)
 110#define SCA3000_MD_CTRL_OR_Z				BIT(2)
 111/* Currently unsupported */
 112#define SCA3000_MD_CTRL_AND_Y				BIT(3)
 113#define SCA3000_MD_CTRL_AND_X				BIT(4)
 114#define SCA3000_MD_CTRL_AND_Z				BIT(5)
 115
 116/*
 117 * Some control registers of complex access methods requiring this register to
 118 * be used to remove a lock.
 119 */
 120#define SCA3000_REG_UNLOCK_ADDR				0x1e
 121
 122#define SCA3000_REG_INT_MASK_ADDR			0x21
 123#define   SCA3000_REG_INT_MASK_PROT_MASK		0x1C
 124
 125#define   SCA3000_REG_INT_MASK_RING_THREE_QUARTER	BIT(7)
 126#define   SCA3000_REG_INT_MASK_RING_HALF		BIT(6)
 127
 128#define SCA3000_REG_INT_MASK_ALL_INTS			0x02
 129#define SCA3000_REG_INT_MASK_ACTIVE_HIGH		0x01
 130#define SCA3000_REG_INT_MASK_ACTIVE_LOW			0x00
 131/* Values of multiplexed registers (write to ctrl_data after select) */
 132#define SCA3000_REG_CTRL_DATA_ADDR			0x22
 133
 134/*
 135 * Measurement modes available on some sca3000 series chips. Code assumes others
 136 * may become available in the future.
 137 *
 138 * Bypass - Bypass the low-pass filter in the signal channel so as to increase
 139 *          signal bandwidth.
 140 *
 141 * Narrow - Narrow low-pass filtering of the signal channel and half output
 142 *          data rate by decimation.
 143 *
 144 * Wide - Widen low-pass filtering of signal channel to increase bandwidth
 145 */
 146#define SCA3000_OP_MODE_BYPASS				0x01
 147#define SCA3000_OP_MODE_NARROW				0x02
 148#define SCA3000_OP_MODE_WIDE				0x04
 149#define SCA3000_MAX_TX 6
 150#define SCA3000_MAX_RX 2
 151
 152/**
 153 * struct sca3000_state - device instance state information
 154 * @us:			the associated spi device
 155 * @info:			chip variant information
 156 * @last_timestamp:		the timestamp of the last event
 157 * @mo_det_use_count:		reference counter for the motion detection unit
 158 * @lock:			lock used to protect elements of sca3000_state
 159 *				and the underlying device state.
 160 * @tx:			dma-able transmit buffer
 161 * @rx:			dma-able receive buffer
 162 **/
 163struct sca3000_state {
 164	struct spi_device		*us;
 165	const struct sca3000_chip_info	*info;
 166	s64				last_timestamp;
 167	int				mo_det_use_count;
 168	struct mutex			lock;
 169	/* Can these share a cacheline ? */
 170	u8				rx[384] __aligned(IIO_DMA_MINALIGN);
 171	u8				tx[6] __aligned(IIO_DMA_MINALIGN);
 172};
 173
 174/**
 175 * struct sca3000_chip_info - model dependent parameters
 176 * @scale:			scale * 10^-6
 177 * @temp_output:		some devices have temperature sensors.
 178 * @measurement_mode_freq:	normal mode sampling frequency
 179 * @measurement_mode_3db_freq:	3db cutoff frequency of the low pass filter for
 180 * the normal measurement mode.
 181 * @option_mode_1:		first optional mode. Not all models have one
 182 * @option_mode_1_freq:		option mode 1 sampling frequency
 183 * @option_mode_1_3db_freq:	3db cutoff frequency of the low pass filter for
 184 * the first option mode.
 185 * @option_mode_2:		second optional mode. Not all chips have one
 186 * @option_mode_2_freq:		option mode 2 sampling frequency
 187 * @option_mode_2_3db_freq:	3db cutoff frequency of the low pass filter for
 188 * the second option mode.
 189 * @mot_det_mult_xz:		Bit wise multipliers to calculate the threshold
 190 * for motion detection in the x and z axis.
 191 * @mot_det_mult_y:		Bit wise multipliers to calculate the threshold
 192 * for motion detection in the y axis.
 193 *
 194 * This structure is used to hold information about the functionality of a given
 195 * sca3000 variant.
 196 **/
 197struct sca3000_chip_info {
 198	unsigned int		scale;
 199	bool			temp_output;
 200	int			measurement_mode_freq;
 201	int			measurement_mode_3db_freq;
 202	int			option_mode_1;
 203	int			option_mode_1_freq;
 204	int			option_mode_1_3db_freq;
 205	int			option_mode_2;
 206	int			option_mode_2_freq;
 207	int			option_mode_2_3db_freq;
 208	int			mot_det_mult_xz[6];
 209	int			mot_det_mult_y[7];
 210};
 211
 212enum sca3000_variant {
 213	d01,
 214	e02,
 215	e04,
 216	e05,
 217};
 218
 219/*
 220 * Note where option modes are not defined, the chip simply does not
 221 * support any.
 222 * Other chips in the sca3000 series use i2c and are not included here.
 223 *
 224 * Some of these devices are only listed in the family data sheet and
 225 * do not actually appear to be available.
 226 */
 227static const struct sca3000_chip_info sca3000_spi_chip_info_tbl[] = {
 228	[d01] = {
 229		.scale = 7357,
 230		.temp_output = true,
 231		.measurement_mode_freq = 250,
 232		.measurement_mode_3db_freq = 45,
 233		.option_mode_1 = SCA3000_OP_MODE_BYPASS,
 234		.option_mode_1_freq = 250,
 235		.option_mode_1_3db_freq = 70,
 236		.mot_det_mult_xz = {50, 100, 200, 350, 650, 1300},
 237		.mot_det_mult_y = {50, 100, 150, 250, 450, 850, 1750},
 238	},
 239	[e02] = {
 240		.scale = 9810,
 241		.measurement_mode_freq = 125,
 242		.measurement_mode_3db_freq = 40,
 243		.option_mode_1 = SCA3000_OP_MODE_NARROW,
 244		.option_mode_1_freq = 63,
 245		.option_mode_1_3db_freq = 11,
 246		.mot_det_mult_xz = {100, 150, 300, 550, 1050, 2050},
 247		.mot_det_mult_y = {50, 100, 200, 350, 700, 1350, 2700},
 248	},
 249	[e04] = {
 250		.scale = 19620,
 251		.measurement_mode_freq = 100,
 252		.measurement_mode_3db_freq = 38,
 253		.option_mode_1 = SCA3000_OP_MODE_NARROW,
 254		.option_mode_1_freq = 50,
 255		.option_mode_1_3db_freq = 9,
 256		.option_mode_2 = SCA3000_OP_MODE_WIDE,
 257		.option_mode_2_freq = 400,
 258		.option_mode_2_3db_freq = 70,
 259		.mot_det_mult_xz = {200, 300, 600, 1100, 2100, 4100},
 260		.mot_det_mult_y = {100, 200, 400, 7000, 1400, 2700, 54000},
 261	},
 262	[e05] = {
 263		.scale = 61313,
 264		.measurement_mode_freq = 200,
 265		.measurement_mode_3db_freq = 60,
 266		.option_mode_1 = SCA3000_OP_MODE_NARROW,
 267		.option_mode_1_freq = 50,
 268		.option_mode_1_3db_freq = 9,
 269		.option_mode_2 = SCA3000_OP_MODE_WIDE,
 270		.option_mode_2_freq = 400,
 271		.option_mode_2_3db_freq = 75,
 272		.mot_det_mult_xz = {600, 900, 1700, 3200, 6100, 11900},
 273		.mot_det_mult_y = {300, 600, 1200, 2000, 4100, 7800, 15600},
 274	},
 275};
 276
 277static int sca3000_write_reg(struct sca3000_state *st, u8 address, u8 val)
 278{
 279	st->tx[0] = SCA3000_WRITE_REG(address);
 280	st->tx[1] = val;
 281	return spi_write(st->us, st->tx, 2);
 282}
 283
 284static int sca3000_read_data_short(struct sca3000_state *st,
 285				   u8 reg_address_high,
 286				   int len)
 287{
 288	struct spi_transfer xfer[2] = {
 289		{
 290			.len = 1,
 291			.tx_buf = st->tx,
 292		}, {
 293			.len = len,
 294			.rx_buf = st->rx,
 295		}
 296	};
 297	st->tx[0] = SCA3000_READ_REG(reg_address_high);
 298
 299	return spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer));
 300}
 301
 302/**
 303 * sca3000_reg_lock_on() - test if the ctrl register lock is on
 304 * @st: Driver specific device instance data.
 305 *
 306 * Lock must be held.
 307 **/
 308static int sca3000_reg_lock_on(struct sca3000_state *st)
 309{
 310	int ret;
 311
 312	ret = sca3000_read_data_short(st, SCA3000_REG_STATUS_ADDR, 1);
 313	if (ret < 0)
 314		return ret;
 315
 316	return !(st->rx[0] & SCA3000_LOCKED);
 317}
 318
 319/**
 320 * __sca3000_unlock_reg_lock() - unlock the control registers
 321 * @st: Driver specific device instance data.
 322 *
 323 * Note the device does not appear to support doing this in a single transfer.
 324 * This should only ever be used as part of ctrl reg read.
 325 * Lock must be held before calling this
 326 */
 327static int __sca3000_unlock_reg_lock(struct sca3000_state *st)
 328{
 329	struct spi_transfer xfer[3] = {
 330		{
 331			.len = 2,
 332			.cs_change = 1,
 333			.tx_buf = st->tx,
 334		}, {
 335			.len = 2,
 336			.cs_change = 1,
 337			.tx_buf = st->tx + 2,
 338		}, {
 339			.len = 2,
 340			.tx_buf = st->tx + 4,
 341		},
 342	};
 343	st->tx[0] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR);
 344	st->tx[1] = 0x00;
 345	st->tx[2] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR);
 346	st->tx[3] = 0x50;
 347	st->tx[4] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR);
 348	st->tx[5] = 0xA0;
 349
 350	return spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer));
 351}
 352
 353/**
 354 * sca3000_write_ctrl_reg() - write to a lock protect ctrl register
 355 * @st: Driver specific device instance data.
 356 * @sel: selects which registers we wish to write to
 357 * @val: the value to be written
 358 *
 359 * Certain control registers are protected against overwriting by the lock
 360 * register and use a shared write address. This function allows writing of
 361 * these registers.
 362 * Lock must be held.
 363 */
 364static int sca3000_write_ctrl_reg(struct sca3000_state *st,
 365				  u8 sel,
 366				  uint8_t val)
 367{
 368	int ret;
 369
 370	ret = sca3000_reg_lock_on(st);
 371	if (ret < 0)
 372		return ret;
 373	if (ret) {
 374		ret = __sca3000_unlock_reg_lock(st);
 375		if (ret)
 376			return ret;
 377	}
 378
 379	/* Set the control select register */
 380	ret = sca3000_write_reg(st, SCA3000_REG_CTRL_SEL_ADDR, sel);
 381	if (ret)
 382		return ret;
 383
 384	/* Write the actual value into the register */
 385	return sca3000_write_reg(st, SCA3000_REG_CTRL_DATA_ADDR, val);
 386}
 387
 388/**
 389 * sca3000_read_ctrl_reg() - read from lock protected control register.
 390 * @st: Driver specific device instance data.
 391 * @ctrl_reg: Which ctrl register do we want to read.
 392 *
 393 * Lock must be held.
 394 */
 395static int sca3000_read_ctrl_reg(struct sca3000_state *st,
 396				 u8 ctrl_reg)
 397{
 398	int ret;
 399
 400	ret = sca3000_reg_lock_on(st);
 401	if (ret < 0)
 402		return ret;
 403	if (ret) {
 404		ret = __sca3000_unlock_reg_lock(st);
 405		if (ret)
 406			return ret;
 407	}
 408	/* Set the control select register */
 409	ret = sca3000_write_reg(st, SCA3000_REG_CTRL_SEL_ADDR, ctrl_reg);
 410	if (ret)
 411		return ret;
 412	ret = sca3000_read_data_short(st, SCA3000_REG_CTRL_DATA_ADDR, 1);
 413	if (ret)
 414		return ret;
 415	return st->rx[0];
 416}
 417
 418/**
 419 * sca3000_print_rev() - sysfs interface to read the chip revision number
 420 * @indio_dev: Device instance specific generic IIO data.
 421 * Driver specific device instance data can be obtained via
 422 * iio_priv(indio_dev)
 423 */
 424static int sca3000_print_rev(struct iio_dev *indio_dev)
 425{
 426	int ret;
 427	struct sca3000_state *st = iio_priv(indio_dev);
 428
 429	mutex_lock(&st->lock);
 430	ret = sca3000_read_data_short(st, SCA3000_REG_REVID_ADDR, 1);
 431	if (ret < 0)
 432		goto error_ret;
 433	dev_info(&indio_dev->dev,
 434		 "sca3000 revision major=%lu, minor=%lu\n",
 435		 st->rx[0] & SCA3000_REG_REVID_MAJOR_MASK,
 436		 st->rx[0] & SCA3000_REG_REVID_MINOR_MASK);
 437error_ret:
 438	mutex_unlock(&st->lock);
 439
 440	return ret;
 441}
 442
 443static ssize_t
 444sca3000_show_available_3db_freqs(struct device *dev,
 445				 struct device_attribute *attr,
 446				 char *buf)
 447{
 448	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 449	struct sca3000_state *st = iio_priv(indio_dev);
 450	int len;
 451
 452	len = sprintf(buf, "%d", st->info->measurement_mode_3db_freq);
 453	if (st->info->option_mode_1)
 454		len += sprintf(buf + len, " %d",
 455			       st->info->option_mode_1_3db_freq);
 456	if (st->info->option_mode_2)
 457		len += sprintf(buf + len, " %d",
 458			       st->info->option_mode_2_3db_freq);
 459	len += sprintf(buf + len, "\n");
 460
 461	return len;
 462}
 463
 464static IIO_DEVICE_ATTR(in_accel_filter_low_pass_3db_frequency_available,
 465		       S_IRUGO, sca3000_show_available_3db_freqs,
 466		       NULL, 0);
 467
 468static const struct iio_event_spec sca3000_event = {
 469	.type = IIO_EV_TYPE_MAG,
 470	.dir = IIO_EV_DIR_RISING,
 471	.mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT(IIO_EV_INFO_ENABLE),
 472};
 473
 474/*
 475 * Note the hack in the number of bits to pretend we have 2 more than
 476 * we do in the fifo.
 477 */
 478#define SCA3000_CHAN(index, mod)				\
 479	{							\
 480		.type = IIO_ACCEL,				\
 481		.modified = 1,					\
 482		.channel2 = mod,				\
 483		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),	\
 484		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |\
 485			BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),\
 486		.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
 487		.address = index,				\
 488		.scan_index = index,				\
 489		.scan_type = {					\
 490			.sign = 's',				\
 491			.realbits = 13,				\
 492			.storagebits = 16,			\
 493			.shift = 3,				\
 494			.endianness = IIO_BE,			\
 495		},						\
 496		.event_spec = &sca3000_event,			\
 497		.num_event_specs = 1,				\
 498	}
 499
 500static const struct iio_event_spec sca3000_freefall_event_spec = {
 501	.type = IIO_EV_TYPE_MAG,
 502	.dir = IIO_EV_DIR_FALLING,
 503	.mask_separate = BIT(IIO_EV_INFO_ENABLE) |
 504		BIT(IIO_EV_INFO_PERIOD),
 505};
 506
 507static const struct iio_chan_spec sca3000_channels[] = {
 508	SCA3000_CHAN(0, IIO_MOD_X),
 509	SCA3000_CHAN(1, IIO_MOD_Y),
 510	SCA3000_CHAN(2, IIO_MOD_Z),
 511	{
 512		.type = IIO_ACCEL,
 513		.modified = 1,
 514		.channel2 = IIO_MOD_X_AND_Y_AND_Z,
 515		.scan_index = -1, /* Fake channel */
 516		.event_spec = &sca3000_freefall_event_spec,
 517		.num_event_specs = 1,
 518	},
 519};
 520
 521static const struct iio_chan_spec sca3000_channels_with_temp[] = {
 522	SCA3000_CHAN(0, IIO_MOD_X),
 523	SCA3000_CHAN(1, IIO_MOD_Y),
 524	SCA3000_CHAN(2, IIO_MOD_Z),
 525	{
 526		.type = IIO_TEMP,
 527		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
 528		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
 529			BIT(IIO_CHAN_INFO_OFFSET),
 530		/* No buffer support */
 531		.scan_index = -1,
 532		.scan_type = {
 533			.sign = 'u',
 534			.realbits = 9,
 535			.storagebits = 16,
 536			.shift = 5,
 537			.endianness = IIO_BE,
 538		},
 539	},
 540	{
 541		.type = IIO_ACCEL,
 542		.modified = 1,
 543		.channel2 = IIO_MOD_X_AND_Y_AND_Z,
 544		.scan_index = -1, /* Fake channel */
 545		.event_spec = &sca3000_freefall_event_spec,
 546		.num_event_specs = 1,
 547	},
 548};
 549
 550static u8 sca3000_addresses[3][3] = {
 551	[0] = {SCA3000_REG_X_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_X_TH,
 552	       SCA3000_MD_CTRL_OR_X},
 553	[1] = {SCA3000_REG_Y_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_Y_TH,
 554	       SCA3000_MD_CTRL_OR_Y},
 555	[2] = {SCA3000_REG_Z_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_Z_TH,
 556	       SCA3000_MD_CTRL_OR_Z},
 557};
 558
 559/**
 560 * __sca3000_get_base_freq() - obtain mode specific base frequency
 561 * @st: Private driver specific device instance specific state.
 562 * @info: chip type specific information.
 563 * @base_freq: Base frequency for the current measurement mode.
 564 *
 565 * lock must be held
 566 */
 567static inline int __sca3000_get_base_freq(struct sca3000_state *st,
 568					  const struct sca3000_chip_info *info,
 569					  int *base_freq)
 570{
 571	int ret;
 572
 573	ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
 574	if (ret)
 575		return ret;
 576
 577	switch (SCA3000_REG_MODE_MODE_MASK & st->rx[0]) {
 578	case SCA3000_REG_MODE_MEAS_MODE_NORMAL:
 579		*base_freq = info->measurement_mode_freq;
 580		break;
 581	case SCA3000_REG_MODE_MEAS_MODE_OP_1:
 582		*base_freq = info->option_mode_1_freq;
 583		break;
 584	case SCA3000_REG_MODE_MEAS_MODE_OP_2:
 585		*base_freq = info->option_mode_2_freq;
 586		break;
 587	default:
 588		ret = -EINVAL;
 589	}
 590	return ret;
 591}
 592
 593/**
 594 * sca3000_read_raw_samp_freq() - read_raw handler for IIO_CHAN_INFO_SAMP_FREQ
 595 * @st: Private driver specific device instance specific state.
 596 * @val: The frequency read back.
 597 *
 598 * lock must be held
 599 **/
 600static int sca3000_read_raw_samp_freq(struct sca3000_state *st, int *val)
 601{
 602	int ret;
 603
 604	ret = __sca3000_get_base_freq(st, st->info, val);
 605	if (ret)
 606		return ret;
 607
 608	ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
 609	if (ret < 0)
 610		return ret;
 611
 612	if (*val > 0) {
 613		ret &= SCA3000_REG_OUT_CTRL_BUF_DIV_MASK;
 614		switch (ret) {
 615		case SCA3000_REG_OUT_CTRL_BUF_DIV_2:
 616			*val /= 2;
 617			break;
 618		case SCA3000_REG_OUT_CTRL_BUF_DIV_4:
 619			*val /= 4;
 620			break;
 621		}
 622	}
 623
 624	return 0;
 625}
 626
 627/**
 628 * sca3000_write_raw_samp_freq() - write_raw handler for IIO_CHAN_INFO_SAMP_FREQ
 629 * @st: Private driver specific device instance specific state.
 630 * @val: The frequency desired.
 631 *
 632 * lock must be held
 633 */
 634static int sca3000_write_raw_samp_freq(struct sca3000_state *st, int val)
 635{
 636	int ret, base_freq, ctrlval;
 637
 638	ret = __sca3000_get_base_freq(st, st->info, &base_freq);
 639	if (ret)
 640		return ret;
 641
 642	ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
 643	if (ret < 0)
 644		return ret;
 645
 646	ctrlval = ret & ~SCA3000_REG_OUT_CTRL_BUF_DIV_MASK;
 647
 648	if (val == base_freq / 2)
 649		ctrlval |= SCA3000_REG_OUT_CTRL_BUF_DIV_2;
 650	if (val == base_freq / 4)
 651		ctrlval |= SCA3000_REG_OUT_CTRL_BUF_DIV_4;
 652	else if (val != base_freq)
 653		return -EINVAL;
 654
 655	return sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL,
 656				     ctrlval);
 657}
 658
 659static int sca3000_read_3db_freq(struct sca3000_state *st, int *val)
 660{
 661	int ret;
 662
 663	ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
 664	if (ret)
 665		return ret;
 666
 667	/* mask bottom 2 bits - only ones that are relevant */
 668	st->rx[0] &= SCA3000_REG_MODE_MODE_MASK;
 669	switch (st->rx[0]) {
 670	case SCA3000_REG_MODE_MEAS_MODE_NORMAL:
 671		*val = st->info->measurement_mode_3db_freq;
 672		return IIO_VAL_INT;
 673	case SCA3000_REG_MODE_MEAS_MODE_MOT_DET:
 674		return -EBUSY;
 675	case SCA3000_REG_MODE_MEAS_MODE_OP_1:
 676		*val = st->info->option_mode_1_3db_freq;
 677		return IIO_VAL_INT;
 678	case SCA3000_REG_MODE_MEAS_MODE_OP_2:
 679		*val = st->info->option_mode_2_3db_freq;
 680		return IIO_VAL_INT;
 681	default:
 682		return -EINVAL;
 683	}
 684}
 685
 686static int sca3000_write_3db_freq(struct sca3000_state *st, int val)
 687{
 688	int ret;
 689	int mode;
 690
 691	if (val == st->info->measurement_mode_3db_freq)
 692		mode = SCA3000_REG_MODE_MEAS_MODE_NORMAL;
 693	else if (st->info->option_mode_1 &&
 694		 (val == st->info->option_mode_1_3db_freq))
 695		mode = SCA3000_REG_MODE_MEAS_MODE_OP_1;
 696	else if (st->info->option_mode_2 &&
 697		 (val == st->info->option_mode_2_3db_freq))
 698		mode = SCA3000_REG_MODE_MEAS_MODE_OP_2;
 699	else
 700		return -EINVAL;
 701	ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
 702	if (ret)
 703		return ret;
 704
 705	st->rx[0] &= ~SCA3000_REG_MODE_MODE_MASK;
 706	st->rx[0] |= (mode & SCA3000_REG_MODE_MODE_MASK);
 707
 708	return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR, st->rx[0]);
 709}
 710
 711static int sca3000_read_raw(struct iio_dev *indio_dev,
 712			    struct iio_chan_spec const *chan,
 713			    int *val,
 714			    int *val2,
 715			    long mask)
 716{
 717	struct sca3000_state *st = iio_priv(indio_dev);
 718	int ret;
 719	u8 address;
 720
 721	switch (mask) {
 722	case IIO_CHAN_INFO_RAW:
 723		mutex_lock(&st->lock);
 724		if (chan->type == IIO_ACCEL) {
 725			if (st->mo_det_use_count) {
 726				mutex_unlock(&st->lock);
 727				return -EBUSY;
 728			}
 729			address = sca3000_addresses[chan->address][0];
 730			ret = sca3000_read_data_short(st, address, 2);
 731			if (ret < 0) {
 732				mutex_unlock(&st->lock);
 733				return ret;
 734			}
 735			*val = sign_extend32(be16_to_cpup((__be16 *)st->rx) >>
 736					     chan->scan_type.shift,
 737					     chan->scan_type.realbits - 1);
 738		} else {
 739			/* get the temperature when available */
 740			ret = sca3000_read_data_short(st,
 741						      SCA3000_REG_TEMP_MSB_ADDR,
 742						      2);
 743			if (ret < 0) {
 744				mutex_unlock(&st->lock);
 745				return ret;
 746			}
 747			*val = (be16_to_cpup((__be16 *)st->rx) >>
 748				chan->scan_type.shift) &
 749				GENMASK(chan->scan_type.realbits - 1, 0);
 750		}
 751		mutex_unlock(&st->lock);
 752		return IIO_VAL_INT;
 753	case IIO_CHAN_INFO_SCALE:
 754		*val = 0;
 755		if (chan->type == IIO_ACCEL)
 756			*val2 = st->info->scale;
 757		else /* temperature */
 758			*val2 = 555556;
 759		return IIO_VAL_INT_PLUS_MICRO;
 760	case IIO_CHAN_INFO_OFFSET:
 761		*val = -214;
 762		*val2 = 600000;
 763		return IIO_VAL_INT_PLUS_MICRO;
 764	case IIO_CHAN_INFO_SAMP_FREQ:
 765		mutex_lock(&st->lock);
 766		ret = sca3000_read_raw_samp_freq(st, val);
 767		mutex_unlock(&st->lock);
 768		return ret ? ret : IIO_VAL_INT;
 769	case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
 770		mutex_lock(&st->lock);
 771		ret = sca3000_read_3db_freq(st, val);
 772		mutex_unlock(&st->lock);
 773		return ret;
 774	default:
 775		return -EINVAL;
 776	}
 777}
 778
 779static int sca3000_write_raw(struct iio_dev *indio_dev,
 780			     struct iio_chan_spec const *chan,
 781			     int val, int val2, long mask)
 782{
 783	struct sca3000_state *st = iio_priv(indio_dev);
 784	int ret;
 785
 786	switch (mask) {
 787	case IIO_CHAN_INFO_SAMP_FREQ:
 788		if (val2)
 789			return -EINVAL;
 790		mutex_lock(&st->lock);
 791		ret = sca3000_write_raw_samp_freq(st, val);
 792		mutex_unlock(&st->lock);
 793		return ret;
 794	case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
 795		if (val2)
 796			return -EINVAL;
 797		mutex_lock(&st->lock);
 798		ret = sca3000_write_3db_freq(st, val);
 799		mutex_unlock(&st->lock);
 800		return ret;
 801	default:
 802		return -EINVAL;
 803	}
 804
 805	return ret;
 806}
 807
 808/**
 809 * sca3000_read_av_freq() - sysfs function to get available frequencies
 810 * @dev: Device structure for this device.
 811 * @attr: Description of the attribute.
 812 * @buf: Incoming string
 813 *
 814 * The later modes are only relevant to the ring buffer - and depend on current
 815 * mode. Note that data sheet gives rather wide tolerances for these so integer
 816 * division will give good enough answer and not all chips have them specified
 817 * at all.
 818 **/
 819static ssize_t sca3000_read_av_freq(struct device *dev,
 820				    struct device_attribute *attr,
 821				    char *buf)
 822{
 823	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 824	struct sca3000_state *st = iio_priv(indio_dev);
 825	int len = 0, ret, val;
 826
 827	mutex_lock(&st->lock);
 828	ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
 829	val = st->rx[0];
 830	mutex_unlock(&st->lock);
 831	if (ret)
 832		return ret;
 833
 834	switch (val & SCA3000_REG_MODE_MODE_MASK) {
 835	case SCA3000_REG_MODE_MEAS_MODE_NORMAL:
 836		len += sprintf(buf + len, "%d %d %d\n",
 837			       st->info->measurement_mode_freq,
 838			       st->info->measurement_mode_freq / 2,
 839			       st->info->measurement_mode_freq / 4);
 840		break;
 841	case SCA3000_REG_MODE_MEAS_MODE_OP_1:
 842		len += sprintf(buf + len, "%d %d %d\n",
 843			       st->info->option_mode_1_freq,
 844			       st->info->option_mode_1_freq / 2,
 845			       st->info->option_mode_1_freq / 4);
 846		break;
 847	case SCA3000_REG_MODE_MEAS_MODE_OP_2:
 848		len += sprintf(buf + len, "%d %d %d\n",
 849			       st->info->option_mode_2_freq,
 850			       st->info->option_mode_2_freq / 2,
 851			       st->info->option_mode_2_freq / 4);
 852		break;
 853	}
 854	return len;
 855}
 856
 857/*
 858 * Should only really be registered if ring buffer support is compiled in.
 859 * Does no harm however and doing it right would add a fair bit of complexity
 860 */
 861static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(sca3000_read_av_freq);
 862
 863/*
 864 * sca3000_read_event_value() - query of a threshold or period
 865 */
 866static int sca3000_read_event_value(struct iio_dev *indio_dev,
 867				    const struct iio_chan_spec *chan,
 868				    enum iio_event_type type,
 869				    enum iio_event_direction dir,
 870				    enum iio_event_info info,
 871				    int *val, int *val2)
 872{
 873	struct sca3000_state *st = iio_priv(indio_dev);
 874	long ret;
 875	int i;
 876
 877	switch (info) {
 878	case IIO_EV_INFO_VALUE:
 879		mutex_lock(&st->lock);
 880		ret = sca3000_read_ctrl_reg(st,
 881					    sca3000_addresses[chan->address][1]);
 882		mutex_unlock(&st->lock);
 883		if (ret < 0)
 884			return ret;
 885		*val = 0;
 886		if (chan->channel2 == IIO_MOD_Y)
 887			for_each_set_bit(i, &ret,
 888					 ARRAY_SIZE(st->info->mot_det_mult_y))
 889				*val += st->info->mot_det_mult_y[i];
 890		else
 891			for_each_set_bit(i, &ret,
 892					 ARRAY_SIZE(st->info->mot_det_mult_xz))
 893				*val += st->info->mot_det_mult_xz[i];
 894
 895		return IIO_VAL_INT;
 896	case IIO_EV_INFO_PERIOD:
 897		*val = 0;
 898		*val2 = 226000;
 899		return IIO_VAL_INT_PLUS_MICRO;
 900	default:
 901		return -EINVAL;
 902	}
 903}
 904
 905/**
 906 * sca3000_write_event_value() - control of threshold and period
 907 * @indio_dev: Device instance specific IIO information.
 908 * @chan: Description of the channel for which the event is being
 909 * configured.
 910 * @type: The type of event being configured, here magnitude rising
 911 * as everything else is read only.
 912 * @dir: Direction of the event (here rising)
 913 * @info: What information about the event are we configuring.
 914 * Here the threshold only.
 915 * @val: Integer part of the value being written..
 916 * @val2: Non integer part of the value being written. Here always 0.
 917 */
 918static int sca3000_write_event_value(struct iio_dev *indio_dev,
 919				     const struct iio_chan_spec *chan,
 920				     enum iio_event_type type,
 921				     enum iio_event_direction dir,
 922				     enum iio_event_info info,
 923				     int val, int val2)
 924{
 925	struct sca3000_state *st = iio_priv(indio_dev);
 926	int ret;
 927	int i;
 928	u8 nonlinear = 0;
 929
 930	if (chan->channel2 == IIO_MOD_Y) {
 931		i = ARRAY_SIZE(st->info->mot_det_mult_y);
 932		while (i > 0)
 933			if (val >= st->info->mot_det_mult_y[--i]) {
 934				nonlinear |= (1 << i);
 935				val -= st->info->mot_det_mult_y[i];
 936			}
 937	} else {
 938		i = ARRAY_SIZE(st->info->mot_det_mult_xz);
 939		while (i > 0)
 940			if (val >= st->info->mot_det_mult_xz[--i]) {
 941				nonlinear |= (1 << i);
 942				val -= st->info->mot_det_mult_xz[i];
 943			}
 944	}
 945
 946	mutex_lock(&st->lock);
 947	ret = sca3000_write_ctrl_reg(st,
 948				     sca3000_addresses[chan->address][1],
 949				     nonlinear);
 950	mutex_unlock(&st->lock);
 951
 952	return ret;
 953}
 954
 955static struct attribute *sca3000_attributes[] = {
 956	&iio_dev_attr_in_accel_filter_low_pass_3db_frequency_available.dev_attr.attr,
 957	&iio_dev_attr_sampling_frequency_available.dev_attr.attr,
 958	NULL,
 959};
 960
 961static const struct attribute_group sca3000_attribute_group = {
 962	.attrs = sca3000_attributes,
 963};
 964
 965static int sca3000_read_data(struct sca3000_state *st,
 966			     u8 reg_address_high,
 967			     u8 *rx,
 968			     int len)
 969{
 970	int ret;
 971	struct spi_transfer xfer[2] = {
 972		{
 973			.len = 1,
 974			.tx_buf = st->tx,
 975		}, {
 976			.len = len,
 977			.rx_buf = rx,
 978		}
 979	};
 980
 981	st->tx[0] = SCA3000_READ_REG(reg_address_high);
 982	ret = spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer));
 983	if (ret) {
 984		dev_err(&st->us->dev, "problem reading register\n");
 985		return ret;
 986	}
 987
 988	return 0;
 989}
 990
 991/**
 992 * sca3000_ring_int_process() - ring specific interrupt handling.
 993 * @val: Value of the interrupt status register.
 994 * @indio_dev: Device instance specific IIO device structure.
 995 */
 996static void sca3000_ring_int_process(u8 val, struct iio_dev *indio_dev)
 997{
 998	struct sca3000_state *st = iio_priv(indio_dev);
 999	int ret, i, num_available;
1000
1001	mutex_lock(&st->lock);
1002
1003	if (val & SCA3000_REG_INT_STATUS_HALF) {
1004		ret = sca3000_read_data_short(st, SCA3000_REG_BUF_COUNT_ADDR,
1005					      1);
1006		if (ret)
1007			goto error_ret;
1008		num_available = st->rx[0];
1009		/*
1010		 * num_available is the total number of samples available
1011		 * i.e. number of time points * number of channels.
1012		 */
1013		ret = sca3000_read_data(st, SCA3000_REG_RING_OUT_ADDR, st->rx,
1014					num_available * 2);
1015		if (ret)
1016			goto error_ret;
1017		for (i = 0; i < num_available / 3; i++) {
1018			/*
1019			 * Dirty hack to cover for 11 bit in fifo, 13 bit
1020			 * direct reading.
1021			 *
1022			 * In theory the bottom two bits are undefined.
1023			 * In reality they appear to always be 0.
1024			 */
1025			iio_push_to_buffers(indio_dev, st->rx + i * 3 * 2);
1026		}
1027	}
1028error_ret:
1029	mutex_unlock(&st->lock);
1030}
1031
1032/**
1033 * sca3000_event_handler() - handling ring and non ring events
1034 * @irq: The irq being handled.
1035 * @private: struct iio_device pointer for the device.
1036 *
1037 * Ring related interrupt handler. Depending on event, push to
1038 * the ring buffer event chrdev or the event one.
1039 *
1040 * This function is complicated by the fact that the devices can signify ring
1041 * and non ring events via the same interrupt line and they can only
1042 * be distinguished via a read of the relevant status register.
1043 */
1044static irqreturn_t sca3000_event_handler(int irq, void *private)
1045{
1046	struct iio_dev *indio_dev = private;
1047	struct sca3000_state *st = iio_priv(indio_dev);
1048	int ret, val;
1049	s64 last_timestamp = iio_get_time_ns(indio_dev);
1050
1051	/*
1052	 * Could lead if badly timed to an extra read of status reg,
1053	 * but ensures no interrupt is missed.
1054	 */
1055	mutex_lock(&st->lock);
1056	ret = sca3000_read_data_short(st, SCA3000_REG_INT_STATUS_ADDR, 1);
1057	val = st->rx[0];
1058	mutex_unlock(&st->lock);
1059	if (ret)
1060		goto done;
1061
1062	sca3000_ring_int_process(val, indio_dev);
1063
1064	if (val & SCA3000_INT_STATUS_FREE_FALL)
1065		iio_push_event(indio_dev,
1066			       IIO_MOD_EVENT_CODE(IIO_ACCEL,
1067						  0,
1068						  IIO_MOD_X_AND_Y_AND_Z,
1069						  IIO_EV_TYPE_MAG,
1070						  IIO_EV_DIR_FALLING),
1071			       last_timestamp);
1072
1073	if (val & SCA3000_INT_STATUS_Y_TRIGGER)
1074		iio_push_event(indio_dev,
1075			       IIO_MOD_EVENT_CODE(IIO_ACCEL,
1076						  0,
1077						  IIO_MOD_Y,
1078						  IIO_EV_TYPE_MAG,
1079						  IIO_EV_DIR_RISING),
1080			       last_timestamp);
1081
1082	if (val & SCA3000_INT_STATUS_X_TRIGGER)
1083		iio_push_event(indio_dev,
1084			       IIO_MOD_EVENT_CODE(IIO_ACCEL,
1085						  0,
1086						  IIO_MOD_X,
1087						  IIO_EV_TYPE_MAG,
1088						  IIO_EV_DIR_RISING),
1089			       last_timestamp);
1090
1091	if (val & SCA3000_INT_STATUS_Z_TRIGGER)
1092		iio_push_event(indio_dev,
1093			       IIO_MOD_EVENT_CODE(IIO_ACCEL,
1094						  0,
1095						  IIO_MOD_Z,
1096						  IIO_EV_TYPE_MAG,
1097						  IIO_EV_DIR_RISING),
1098			       last_timestamp);
1099
1100done:
1101	return IRQ_HANDLED;
1102}
1103
1104/*
1105 * sca3000_read_event_config() what events are enabled
1106 */
1107static int sca3000_read_event_config(struct iio_dev *indio_dev,
1108				     const struct iio_chan_spec *chan,
1109				     enum iio_event_type type,
1110				     enum iio_event_direction dir)
1111{
1112	struct sca3000_state *st = iio_priv(indio_dev);
1113	int ret;
1114	/* read current value of mode register */
1115	mutex_lock(&st->lock);
1116
1117	ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
1118	if (ret)
1119		goto error_ret;
1120
1121	switch (chan->channel2) {
1122	case IIO_MOD_X_AND_Y_AND_Z:
1123		ret = !!(st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT);
1124		break;
1125	case IIO_MOD_X:
1126	case IIO_MOD_Y:
1127	case IIO_MOD_Z:
1128		/*
1129		 * Motion detection mode cannot run at the same time as
1130		 * acceleration data being read.
1131		 */
1132		if ((st->rx[0] & SCA3000_REG_MODE_MODE_MASK)
1133		    != SCA3000_REG_MODE_MEAS_MODE_MOT_DET) {
1134			ret = 0;
1135		} else {
1136			ret = sca3000_read_ctrl_reg(st,
1137						SCA3000_REG_CTRL_SEL_MD_CTRL);
1138			if (ret < 0)
1139				goto error_ret;
1140			/* only supporting logical or's for now */
1141			ret = !!(ret & sca3000_addresses[chan->address][2]);
1142		}
1143		break;
1144	default:
1145		ret = -EINVAL;
1146	}
1147
1148error_ret:
1149	mutex_unlock(&st->lock);
1150
1151	return ret;
1152}
1153
1154static int sca3000_freefall_set_state(struct iio_dev *indio_dev, bool state)
1155{
1156	struct sca3000_state *st = iio_priv(indio_dev);
1157	int ret;
1158
1159	/* read current value of mode register */
1160	ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
1161	if (ret)
1162		return ret;
1163
1164	/* if off and should be on */
1165	if (state && !(st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT))
1166		return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
1167					 st->rx[0] | SCA3000_REG_MODE_FREE_FALL_DETECT);
1168	/* if on and should be off */
1169	else if (!state && (st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT))
1170		return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
1171					 st->rx[0] & ~SCA3000_REG_MODE_FREE_FALL_DETECT);
1172	else
1173		return 0;
1174}
1175
1176static int sca3000_motion_detect_set_state(struct iio_dev *indio_dev, int axis,
1177					   bool state)
1178{
1179	struct sca3000_state *st = iio_priv(indio_dev);
1180	int ret, ctrlval;
1181
1182	/*
1183	 * First read the motion detector config to find out if
1184	 * this axis is on
1185	 */
1186	ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL);
1187	if (ret < 0)
1188		return ret;
1189	ctrlval = ret;
1190	/* if off and should be on */
1191	if (state && !(ctrlval & sca3000_addresses[axis][2])) {
1192		ret = sca3000_write_ctrl_reg(st,
1193					     SCA3000_REG_CTRL_SEL_MD_CTRL,
1194					     ctrlval |
1195					     sca3000_addresses[axis][2]);
1196		if (ret)
1197			return ret;
1198		st->mo_det_use_count++;
1199	} else if (!state && (ctrlval & sca3000_addresses[axis][2])) {
1200		ret = sca3000_write_ctrl_reg(st,
1201					     SCA3000_REG_CTRL_SEL_MD_CTRL,
1202					     ctrlval &
1203					     ~(sca3000_addresses[axis][2]));
1204		if (ret)
1205			return ret;
1206		st->mo_det_use_count--;
1207	}
1208
1209	/* read current value of mode register */
1210	ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
1211	if (ret)
1212		return ret;
1213	/* if off and should be on */
1214	if ((st->mo_det_use_count) &&
1215	    ((st->rx[0] & SCA3000_REG_MODE_MODE_MASK)
1216	     != SCA3000_REG_MODE_MEAS_MODE_MOT_DET))
1217		return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
1218			(st->rx[0] & ~SCA3000_REG_MODE_MODE_MASK)
1219			| SCA3000_REG_MODE_MEAS_MODE_MOT_DET);
1220	/* if on and should be off */
1221	else if (!(st->mo_det_use_count) &&
1222		 ((st->rx[0] & SCA3000_REG_MODE_MODE_MASK)
1223		  == SCA3000_REG_MODE_MEAS_MODE_MOT_DET))
1224		return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
1225			st->rx[0] & SCA3000_REG_MODE_MODE_MASK);
1226	else
1227		return 0;
1228}
1229
1230/**
1231 * sca3000_write_event_config() - simple on off control for motion detector
1232 * @indio_dev: IIO device instance specific structure. Data specific to this
1233 * particular driver may be accessed via iio_priv(indio_dev).
1234 * @chan: Description of the channel whose event we are configuring.
1235 * @type: The type of event.
1236 * @dir: The direction of the event.
1237 * @state: Desired state of event being configured.
1238 *
1239 * This is a per axis control, but enabling any will result in the
1240 * motion detector unit being enabled.
1241 * N.B. enabling motion detector stops normal data acquisition.
1242 * There is a complexity in knowing which mode to return to when
1243 * this mode is disabled.  Currently normal mode is assumed.
1244 **/
1245static int sca3000_write_event_config(struct iio_dev *indio_dev,
1246				      const struct iio_chan_spec *chan,
1247				      enum iio_event_type type,
1248				      enum iio_event_direction dir,
1249				      bool state)
1250{
1251	struct sca3000_state *st = iio_priv(indio_dev);
1252	int ret;
1253
1254	mutex_lock(&st->lock);
1255	switch (chan->channel2) {
1256	case IIO_MOD_X_AND_Y_AND_Z:
1257		ret = sca3000_freefall_set_state(indio_dev, state);
1258		break;
1259
1260	case IIO_MOD_X:
1261	case IIO_MOD_Y:
1262	case IIO_MOD_Z:
1263		ret = sca3000_motion_detect_set_state(indio_dev,
1264						      chan->address,
1265						      state);
1266		break;
1267	default:
1268		ret = -EINVAL;
1269		break;
1270	}
1271	mutex_unlock(&st->lock);
1272
1273	return ret;
1274}
1275
1276static inline
1277int __sca3000_hw_ring_state_set(struct iio_dev *indio_dev, bool state)
1278{
1279	struct sca3000_state *st = iio_priv(indio_dev);
1280	int ret;
1281
1282	mutex_lock(&st->lock);
1283	ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
1284	if (ret)
1285		goto error_ret;
1286	if (state) {
1287		dev_info(&indio_dev->dev, "supposedly enabling ring buffer\n");
1288		ret = sca3000_write_reg(st,
1289			SCA3000_REG_MODE_ADDR,
1290			(st->rx[0] | SCA3000_REG_MODE_RING_BUF_ENABLE));
1291	} else
1292		ret = sca3000_write_reg(st,
1293			SCA3000_REG_MODE_ADDR,
1294			(st->rx[0] & ~SCA3000_REG_MODE_RING_BUF_ENABLE));
1295error_ret:
1296	mutex_unlock(&st->lock);
1297
1298	return ret;
1299}
1300
1301/**
1302 * sca3000_hw_ring_preenable() - hw ring buffer preenable function
1303 * @indio_dev: structure representing the IIO device. Device instance
1304 * specific state can be accessed via iio_priv(indio_dev).
1305 *
1306 * Very simple enable function as the chip will allows normal reads
1307 * during ring buffer operation so as long as it is indeed running
1308 * before we notify the core, the precise ordering does not matter.
1309 */
1310static int sca3000_hw_ring_preenable(struct iio_dev *indio_dev)
1311{
1312	int ret;
1313	struct sca3000_state *st = iio_priv(indio_dev);
1314
1315	mutex_lock(&st->lock);
1316
1317	/* Enable the 50% full interrupt */
1318	ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
1319	if (ret)
1320		goto error_unlock;
1321	ret = sca3000_write_reg(st,
1322				SCA3000_REG_INT_MASK_ADDR,
1323				st->rx[0] | SCA3000_REG_INT_MASK_RING_HALF);
1324	if (ret)
1325		goto error_unlock;
1326
1327	mutex_unlock(&st->lock);
1328
1329	return __sca3000_hw_ring_state_set(indio_dev, 1);
1330
1331error_unlock:
1332	mutex_unlock(&st->lock);
1333
1334	return ret;
1335}
1336
1337static int sca3000_hw_ring_postdisable(struct iio_dev *indio_dev)
1338{
1339	int ret;
1340	struct sca3000_state *st = iio_priv(indio_dev);
1341
1342	ret = __sca3000_hw_ring_state_set(indio_dev, 0);
1343	if (ret)
1344		return ret;
1345
1346	/* Disable the 50% full interrupt */
1347	mutex_lock(&st->lock);
1348
1349	ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
1350	if (ret)
1351		goto unlock;
1352	ret = sca3000_write_reg(st,
1353				SCA3000_REG_INT_MASK_ADDR,
1354				st->rx[0] & ~SCA3000_REG_INT_MASK_RING_HALF);
1355unlock:
1356	mutex_unlock(&st->lock);
1357	return ret;
1358}
1359
1360static const struct iio_buffer_setup_ops sca3000_ring_setup_ops = {
1361	.preenable = &sca3000_hw_ring_preenable,
1362	.postdisable = &sca3000_hw_ring_postdisable,
1363};
1364
1365/**
1366 * sca3000_clean_setup() - get the device into a predictable state
1367 * @st: Device instance specific private data structure
1368 *
1369 * Devices use flash memory to store many of the register values
1370 * and hence can come up in somewhat unpredictable states.
1371 * Hence reset everything on driver load.
1372 */
1373static int sca3000_clean_setup(struct sca3000_state *st)
1374{
1375	int ret;
1376
1377	mutex_lock(&st->lock);
1378	/* Ensure all interrupts have been acknowledged */
1379	ret = sca3000_read_data_short(st, SCA3000_REG_INT_STATUS_ADDR, 1);
1380	if (ret)
1381		goto error_ret;
1382
1383	/* Turn off all motion detection channels */
1384	ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL);
1385	if (ret < 0)
1386		goto error_ret;
1387	ret = sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL,
1388				     ret & SCA3000_MD_CTRL_PROT_MASK);
1389	if (ret)
1390		goto error_ret;
1391
1392	/* Disable ring buffer */
1393	ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
1394	if (ret < 0)
1395		goto error_ret;
1396	ret = sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL,
1397				     (ret & SCA3000_REG_OUT_CTRL_PROT_MASK)
1398				     | SCA3000_REG_OUT_CTRL_BUF_X_EN
1399				     | SCA3000_REG_OUT_CTRL_BUF_Y_EN
1400				     | SCA3000_REG_OUT_CTRL_BUF_Z_EN
1401				     | SCA3000_REG_OUT_CTRL_BUF_DIV_4);
1402	if (ret)
1403		goto error_ret;
1404	/* Enable interrupts, relevant to mode and set up as active low */
1405	ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
1406	if (ret)
1407		goto error_ret;
1408	ret = sca3000_write_reg(st,
1409				SCA3000_REG_INT_MASK_ADDR,
1410				(ret & SCA3000_REG_INT_MASK_PROT_MASK)
1411				| SCA3000_REG_INT_MASK_ACTIVE_LOW);
1412	if (ret)
1413		goto error_ret;
1414	/*
1415	 * Select normal measurement mode, free fall off, ring off
1416	 * Ring in 12 bit mode - it is fine to overwrite reserved bits 3,5
1417	 * as that occurs in one of the example on the datasheet
1418	 */
1419	ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
1420	if (ret)
1421		goto error_ret;
1422	ret = sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
1423				(st->rx[0] & SCA3000_MODE_PROT_MASK));
1424
1425error_ret:
1426	mutex_unlock(&st->lock);
1427	return ret;
1428}
1429
1430static const struct iio_info sca3000_info = {
1431	.attrs = &sca3000_attribute_group,
1432	.read_raw = &sca3000_read_raw,
1433	.write_raw = &sca3000_write_raw,
1434	.read_event_value = &sca3000_read_event_value,
1435	.write_event_value = &sca3000_write_event_value,
1436	.read_event_config = &sca3000_read_event_config,
1437	.write_event_config = &sca3000_write_event_config,
1438};
1439
1440static int sca3000_probe(struct spi_device *spi)
1441{
1442	int ret;
1443	struct sca3000_state *st;
1444	struct iio_dev *indio_dev;
1445
1446	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
1447	if (!indio_dev)
1448		return -ENOMEM;
1449
1450	st = iio_priv(indio_dev);
1451	spi_set_drvdata(spi, indio_dev);
1452	st->us = spi;
1453	mutex_init(&st->lock);
1454	st->info = &sca3000_spi_chip_info_tbl[spi_get_device_id(spi)
1455					      ->driver_data];
1456
1457	indio_dev->name = spi_get_device_id(spi)->name;
1458	indio_dev->info = &sca3000_info;
1459	if (st->info->temp_output) {
1460		indio_dev->channels = sca3000_channels_with_temp;
1461		indio_dev->num_channels =
1462			ARRAY_SIZE(sca3000_channels_with_temp);
1463	} else {
1464		indio_dev->channels = sca3000_channels;
1465		indio_dev->num_channels = ARRAY_SIZE(sca3000_channels);
1466	}
1467	indio_dev->modes = INDIO_DIRECT_MODE;
1468
1469	ret = devm_iio_kfifo_buffer_setup(&spi->dev, indio_dev,
1470					  &sca3000_ring_setup_ops);
1471	if (ret)
1472		return ret;
1473
1474	if (spi->irq) {
1475		ret = request_threaded_irq(spi->irq,
1476					   NULL,
1477					   &sca3000_event_handler,
1478					   IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1479					   "sca3000",
1480					   indio_dev);
1481		if (ret)
1482			return ret;
1483	}
1484	ret = sca3000_clean_setup(st);
1485	if (ret)
1486		goto error_free_irq;
1487
1488	ret = sca3000_print_rev(indio_dev);
1489	if (ret)
1490		goto error_free_irq;
1491
1492	ret = iio_device_register(indio_dev);
1493	if (ret)
1494		goto error_free_irq;
1495
1496	return 0;
1497
1498error_free_irq:
1499	if (spi->irq)
1500		free_irq(spi->irq, indio_dev);
1501
1502	return ret;
1503}
1504
1505static int sca3000_stop_all_interrupts(struct sca3000_state *st)
1506{
1507	int ret;
1508
1509	mutex_lock(&st->lock);
1510	ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
1511	if (ret)
1512		goto error_ret;
1513	ret = sca3000_write_reg(st, SCA3000_REG_INT_MASK_ADDR,
1514				(st->rx[0] &
1515				 ~(SCA3000_REG_INT_MASK_RING_THREE_QUARTER |
1516				   SCA3000_REG_INT_MASK_RING_HALF |
1517				   SCA3000_REG_INT_MASK_ALL_INTS)));
1518error_ret:
1519	mutex_unlock(&st->lock);
1520	return ret;
1521}
1522
1523static void sca3000_remove(struct spi_device *spi)
1524{
1525	struct iio_dev *indio_dev = spi_get_drvdata(spi);
1526	struct sca3000_state *st = iio_priv(indio_dev);
1527
1528	iio_device_unregister(indio_dev);
1529
1530	/* Must ensure no interrupts can be generated after this! */
1531	sca3000_stop_all_interrupts(st);
1532	if (spi->irq)
1533		free_irq(spi->irq, indio_dev);
1534}
1535
1536static const struct spi_device_id sca3000_id[] = {
1537	{"sca3000_d01", d01},
1538	{"sca3000_e02", e02},
1539	{"sca3000_e04", e04},
1540	{"sca3000_e05", e05},
1541	{ }
1542};
1543MODULE_DEVICE_TABLE(spi, sca3000_id);
1544
1545static struct spi_driver sca3000_driver = {
1546	.driver = {
1547		.name = "sca3000",
1548	},
1549	.probe = sca3000_probe,
1550	.remove = sca3000_remove,
1551	.id_table = sca3000_id,
1552};
1553module_spi_driver(sca3000_driver);
1554
1555MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
1556MODULE_DESCRIPTION("VTI SCA3000 Series Accelerometers SPI driver");
1557MODULE_LICENSE("GPL v2");