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msa311.c
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linux-6.19.14/drivers/iio/accel/msa311.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * MEMSensing digital 3-Axis accelerometer 4 * 5 * MSA311 is a tri-axial, low-g accelerometer with I2C digital output for 6 * sensitivity consumer applications. It has dynamic user-selectable full 7 * scales range of +-2g/+-4g/+-8g/+-16g and allows acceleration measurements 8 * with output data rates from 1Hz to 1000Hz. 9 * 10 * MSA311 is available in an ultra small (2mm x 2mm, height 0.95mm) LGA package 11 * and is guaranteed to operate over -40C to +85C. 12 * 13 * This driver supports following MSA311 features: 14 * - IIO interface 15 * - Different power modes: NORMAL, SUSPEND 16 * - ODR (Output Data Rate) selection 17 * - Scale selection 18 * - IIO triggered buffer 19 * - NEW_DATA interrupt + trigger 20 * 21 * Below features to be done: 22 * - Motion Events: ACTIVE, TAP, ORIENT, FREEFALL 23 * - Low Power mode 24 * 25 * Copyright (c) 2022, SberDevices. All Rights Reserved. 26 * 27 * Author: Dmitry Rokosov <ddrokosov@sberdevices.ru> 28 */ 29 30#include <linux/i2c.h> 31#include <linux/mod_devicetable.h> 32#include <linux/module.h> 33#include <linux/pm.h> 34#include <linux/pm_runtime.h> 35#include <linux/regmap.h> 36#include <linux/string_choices.h> 37#include <linux/types.h> 38#include <linux/units.h> 39 40#include <linux/iio/buffer.h> 41#include <linux/iio/iio.h> 42#include <linux/iio/sysfs.h> 43#include <linux/iio/trigger.h> 44#include <linux/iio/trigger_consumer.h> 45#include <linux/iio/triggered_buffer.h> 46 47#define MSA311_SOFT_RESET_REG 0x00 48#define MSA311_PARTID_REG 0x01 49#define MSA311_ACC_X_REG 0x02 50#define MSA311_ACC_Y_REG 0x04 51#define MSA311_ACC_Z_REG 0x06 52#define MSA311_MOTION_INT_REG 0x09 53#define MSA311_DATA_INT_REG 0x0A 54#define MSA311_TAP_ACTIVE_STS_REG 0x0B 55#define MSA311_ORIENT_STS_REG 0x0C 56#define MSA311_RANGE_REG 0x0F 57#define MSA311_ODR_REG 0x10 58#define MSA311_PWR_MODE_REG 0x11 59#define MSA311_SWAP_POLARITY_REG 0x12 60#define MSA311_INT_SET_0_REG 0x16 61#define MSA311_INT_SET_1_REG 0x17 62#define MSA311_INT_MAP_0_REG 0x19 63#define MSA311_INT_MAP_1_REG 0x1A 64#define MSA311_INT_CONFIG_REG 0x20 65#define MSA311_INT_LATCH_REG 0x21 66#define MSA311_FREEFALL_DUR_REG 0x22 67#define MSA311_FREEFALL_TH_REG 0x23 68#define MSA311_FREEFALL_HY_REG 0x24 69#define MSA311_ACTIVE_DUR_REG 0x27 70#define MSA311_ACTIVE_TH_REG 0x28 71#define MSA311_TAP_DUR_REG 0x2A 72#define MSA311_TAP_TH_REG 0x2B 73#define MSA311_ORIENT_HY_REG 0x2C 74#define MSA311_Z_BLOCK_REG 0x2D 75#define MSA311_OFFSET_X_REG 0x38 76#define MSA311_OFFSET_Y_REG 0x39 77#define MSA311_OFFSET_Z_REG 0x3A 78 79enum msa311_fields { 80 /* Soft_Reset */ 81 F_SOFT_RESET_I2C, F_SOFT_RESET_SPI, 82 /* Motion_Interrupt */ 83 F_ORIENT_INT, F_S_TAP_INT, F_D_TAP_INT, F_ACTIVE_INT, F_FREEFALL_INT, 84 /* Data_Interrupt */ 85 F_NEW_DATA_INT, 86 /* Tap_Active_Status */ 87 F_TAP_SIGN, F_TAP_FIRST_X, F_TAP_FIRST_Y, F_TAP_FIRST_Z, F_ACTV_SIGN, 88 F_ACTV_FIRST_X, F_ACTV_FIRST_Y, F_ACTV_FIRST_Z, 89 /* Orientation_Status */ 90 F_ORIENT_Z, F_ORIENT_X_Y, 91 /* Range */ 92 F_FS, 93 /* ODR */ 94 F_X_AXIS_DIS, F_Y_AXIS_DIS, F_Z_AXIS_DIS, F_ODR, 95 /* Power Mode/Bandwidth */ 96 F_PWR_MODE, F_LOW_POWER_BW, 97 /* Swap_Polarity */ 98 F_X_POLARITY, F_Y_POLARITY, F_Z_POLARITY, F_X_Y_SWAP, 99 /* Int_Set_0 */ 100 F_ORIENT_INT_EN, F_S_TAP_INT_EN, F_D_TAP_INT_EN, F_ACTIVE_INT_EN_Z, 101 F_ACTIVE_INT_EN_Y, F_ACTIVE_INT_EN_X, 102 /* Int_Set_1 */ 103 F_NEW_DATA_INT_EN, F_FREEFALL_INT_EN, 104 /* Int_Map_0 */ 105 F_INT1_ORIENT, F_INT1_S_TAP, F_INT1_D_TAP, F_INT1_ACTIVE, 106 F_INT1_FREEFALL, 107 /* Int_Map_1 */ 108 F_INT1_NEW_DATA, 109 /* Int_Config */ 110 F_INT1_OD, F_INT1_LVL, 111 /* Int_Latch */ 112 F_RESET_INT, F_LATCH_INT, 113 /* Freefall_Hy */ 114 F_FREEFALL_MODE, F_FREEFALL_HY, 115 /* Active_Dur */ 116 F_ACTIVE_DUR, 117 /* Tap_Dur */ 118 F_TAP_QUIET, F_TAP_SHOCK, F_TAP_DUR, 119 /* Tap_Th */ 120 F_TAP_TH, 121 /* Orient_Hy */ 122 F_ORIENT_HYST, F_ORIENT_BLOCKING, F_ORIENT_MODE, 123 /* Z_Block */ 124 F_Z_BLOCKING, 125 /* End of register map */ 126 F_MAX_FIELDS, 127}; 128 129static const struct reg_field msa311_reg_fields[] = { 130 /* Soft_Reset */ 131 [F_SOFT_RESET_I2C] = REG_FIELD(MSA311_SOFT_RESET_REG, 2, 2), 132 [F_SOFT_RESET_SPI] = REG_FIELD(MSA311_SOFT_RESET_REG, 5, 5), 133 /* Motion_Interrupt */ 134 [F_ORIENT_INT] = REG_FIELD(MSA311_MOTION_INT_REG, 6, 6), 135 [F_S_TAP_INT] = REG_FIELD(MSA311_MOTION_INT_REG, 5, 5), 136 [F_D_TAP_INT] = REG_FIELD(MSA311_MOTION_INT_REG, 4, 4), 137 [F_ACTIVE_INT] = REG_FIELD(MSA311_MOTION_INT_REG, 2, 2), 138 [F_FREEFALL_INT] = REG_FIELD(MSA311_MOTION_INT_REG, 0, 0), 139 /* Data_Interrupt */ 140 [F_NEW_DATA_INT] = REG_FIELD(MSA311_DATA_INT_REG, 0, 0), 141 /* Tap_Active_Status */ 142 [F_TAP_SIGN] = REG_FIELD(MSA311_TAP_ACTIVE_STS_REG, 7, 7), 143 [F_TAP_FIRST_X] = REG_FIELD(MSA311_TAP_ACTIVE_STS_REG, 6, 6), 144 [F_TAP_FIRST_Y] = REG_FIELD(MSA311_TAP_ACTIVE_STS_REG, 5, 5), 145 [F_TAP_FIRST_Z] = REG_FIELD(MSA311_TAP_ACTIVE_STS_REG, 4, 4), 146 [F_ACTV_SIGN] = REG_FIELD(MSA311_TAP_ACTIVE_STS_REG, 3, 3), 147 [F_ACTV_FIRST_X] = REG_FIELD(MSA311_TAP_ACTIVE_STS_REG, 2, 2), 148 [F_ACTV_FIRST_Y] = REG_FIELD(MSA311_TAP_ACTIVE_STS_REG, 1, 1), 149 [F_ACTV_FIRST_Z] = REG_FIELD(MSA311_TAP_ACTIVE_STS_REG, 0, 0), 150 /* Orientation_Status */ 151 [F_ORIENT_Z] = REG_FIELD(MSA311_ORIENT_STS_REG, 6, 6), 152 [F_ORIENT_X_Y] = REG_FIELD(MSA311_ORIENT_STS_REG, 4, 5), 153 /* Range */ 154 [F_FS] = REG_FIELD(MSA311_RANGE_REG, 0, 1), 155 /* ODR */ 156 [F_X_AXIS_DIS] = REG_FIELD(MSA311_ODR_REG, 7, 7), 157 [F_Y_AXIS_DIS] = REG_FIELD(MSA311_ODR_REG, 6, 6), 158 [F_Z_AXIS_DIS] = REG_FIELD(MSA311_ODR_REG, 5, 5), 159 [F_ODR] = REG_FIELD(MSA311_ODR_REG, 0, 3), 160 /* Power Mode/Bandwidth */ 161 [F_PWR_MODE] = REG_FIELD(MSA311_PWR_MODE_REG, 6, 7), 162 [F_LOW_POWER_BW] = REG_FIELD(MSA311_PWR_MODE_REG, 1, 4), 163 /* Swap_Polarity */ 164 [F_X_POLARITY] = REG_FIELD(MSA311_SWAP_POLARITY_REG, 3, 3), 165 [F_Y_POLARITY] = REG_FIELD(MSA311_SWAP_POLARITY_REG, 2, 2), 166 [F_Z_POLARITY] = REG_FIELD(MSA311_SWAP_POLARITY_REG, 1, 1), 167 [F_X_Y_SWAP] = REG_FIELD(MSA311_SWAP_POLARITY_REG, 0, 0), 168 /* Int_Set_0 */ 169 [F_ORIENT_INT_EN] = REG_FIELD(MSA311_INT_SET_0_REG, 6, 6), 170 [F_S_TAP_INT_EN] = REG_FIELD(MSA311_INT_SET_0_REG, 5, 5), 171 [F_D_TAP_INT_EN] = REG_FIELD(MSA311_INT_SET_0_REG, 4, 4), 172 [F_ACTIVE_INT_EN_Z] = REG_FIELD(MSA311_INT_SET_0_REG, 2, 2), 173 [F_ACTIVE_INT_EN_Y] = REG_FIELD(MSA311_INT_SET_0_REG, 1, 1), 174 [F_ACTIVE_INT_EN_X] = REG_FIELD(MSA311_INT_SET_0_REG, 0, 0), 175 /* Int_Set_1 */ 176 [F_NEW_DATA_INT_EN] = REG_FIELD(MSA311_INT_SET_1_REG, 4, 4), 177 [F_FREEFALL_INT_EN] = REG_FIELD(MSA311_INT_SET_1_REG, 3, 3), 178 /* Int_Map_0 */ 179 [F_INT1_ORIENT] = REG_FIELD(MSA311_INT_MAP_0_REG, 6, 6), 180 [F_INT1_S_TAP] = REG_FIELD(MSA311_INT_MAP_0_REG, 5, 5), 181 [F_INT1_D_TAP] = REG_FIELD(MSA311_INT_MAP_0_REG, 4, 4), 182 [F_INT1_ACTIVE] = REG_FIELD(MSA311_INT_MAP_0_REG, 2, 2), 183 [F_INT1_FREEFALL] = REG_FIELD(MSA311_INT_MAP_0_REG, 0, 0), 184 /* Int_Map_1 */ 185 [F_INT1_NEW_DATA] = REG_FIELD(MSA311_INT_MAP_1_REG, 0, 0), 186 /* Int_Config */ 187 [F_INT1_OD] = REG_FIELD(MSA311_INT_CONFIG_REG, 1, 1), 188 [F_INT1_LVL] = REG_FIELD(MSA311_INT_CONFIG_REG, 0, 0), 189 /* Int_Latch */ 190 [F_RESET_INT] = REG_FIELD(MSA311_INT_LATCH_REG, 7, 7), 191 [F_LATCH_INT] = REG_FIELD(MSA311_INT_LATCH_REG, 0, 3), 192 /* Freefall_Hy */ 193 [F_FREEFALL_MODE] = REG_FIELD(MSA311_FREEFALL_HY_REG, 2, 2), 194 [F_FREEFALL_HY] = REG_FIELD(MSA311_FREEFALL_HY_REG, 0, 1), 195 /* Active_Dur */ 196 [F_ACTIVE_DUR] = REG_FIELD(MSA311_ACTIVE_DUR_REG, 0, 1), 197 /* Tap_Dur */ 198 [F_TAP_QUIET] = REG_FIELD(MSA311_TAP_DUR_REG, 7, 7), 199 [F_TAP_SHOCK] = REG_FIELD(MSA311_TAP_DUR_REG, 6, 6), 200 [F_TAP_DUR] = REG_FIELD(MSA311_TAP_DUR_REG, 0, 2), 201 /* Tap_Th */ 202 [F_TAP_TH] = REG_FIELD(MSA311_TAP_TH_REG, 0, 4), 203 /* Orient_Hy */ 204 [F_ORIENT_HYST] = REG_FIELD(MSA311_ORIENT_HY_REG, 4, 6), 205 [F_ORIENT_BLOCKING] = REG_FIELD(MSA311_ORIENT_HY_REG, 2, 3), 206 [F_ORIENT_MODE] = REG_FIELD(MSA311_ORIENT_HY_REG, 0, 1), 207 /* Z_Block */ 208 [F_Z_BLOCKING] = REG_FIELD(MSA311_Z_BLOCK_REG, 0, 3), 209}; 210 211#define MSA311_WHO_AM_I 0x13 212 213/* 214 * Possible Full Scale ranges 215 * 216 * Axis data is 12-bit signed value, so 217 * 218 * fs0 = (2 + 2) * 9.81 / (2^11) = 0.009580 219 * fs1 = (4 + 4) * 9.81 / (2^11) = 0.019160 220 * fs2 = (8 + 8) * 9.81 / (2^11) = 0.038320 221 * fs3 = (16 + 16) * 9.81 / (2^11) = 0.076641 222 */ 223enum { 224 MSA311_FS_2G, 225 MSA311_FS_4G, 226 MSA311_FS_8G, 227 MSA311_FS_16G, 228}; 229 230struct iio_decimal_fract { 231 int integral; 232 int microfract; 233}; 234 235static const struct iio_decimal_fract msa311_fs_table[] = { 236 {0, 9580}, {0, 19160}, {0, 38320}, {0, 76641}, 237}; 238 239/* Possible Output Data Rate values */ 240enum { 241 MSA311_ODR_1_HZ, 242 MSA311_ODR_1_95_HZ, 243 MSA311_ODR_3_9_HZ, 244 MSA311_ODR_7_81_HZ, 245 MSA311_ODR_15_63_HZ, 246 MSA311_ODR_31_25_HZ, 247 MSA311_ODR_62_5_HZ, 248 MSA311_ODR_125_HZ, 249 MSA311_ODR_250_HZ, 250 MSA311_ODR_500_HZ, 251 MSA311_ODR_1000_HZ, 252}; 253 254static const struct iio_decimal_fract msa311_odr_table[] = { 255 {1, 0}, {1, 950000}, {3, 900000}, {7, 810000}, {15, 630000}, 256 {31, 250000}, {62, 500000}, {125, 0}, {250, 0}, {500, 0}, {1000, 0}, 257}; 258 259/* All supported power modes */ 260#define MSA311_PWR_MODE_NORMAL 0b00 261#define MSA311_PWR_MODE_LOW 0b01 262#define MSA311_PWR_MODE_UNKNOWN 0b10 263#define MSA311_PWR_MODE_SUSPEND 0b11 264static const char * const msa311_pwr_modes[] = { 265 [MSA311_PWR_MODE_NORMAL] = "normal", 266 [MSA311_PWR_MODE_LOW] = "low", 267 [MSA311_PWR_MODE_UNKNOWN] = "unknown", 268 [MSA311_PWR_MODE_SUSPEND] = "suspend", 269}; 270 271/* Autosuspend delay */ 272#define MSA311_PWR_SLEEP_DELAY_MS 2000 273 274/* Possible INT1 types and levels */ 275enum { 276 MSA311_INT1_OD_PUSH_PULL, 277 MSA311_INT1_OD_OPEN_DRAIN, 278}; 279 280enum { 281 MSA311_INT1_LVL_LOW, 282 MSA311_INT1_LVL_HIGH, 283}; 284 285/* Latch INT modes */ 286#define MSA311_LATCH_INT_NOT_LATCHED 0b0000 287#define MSA311_LATCH_INT_250MS 0b0001 288#define MSA311_LATCH_INT_500MS 0b0010 289#define MSA311_LATCH_INT_1S 0b0011 290#define MSA311_LATCH_INT_2S 0b0100 291#define MSA311_LATCH_INT_4S 0b0101 292#define MSA311_LATCH_INT_8S 0b0110 293#define MSA311_LATCH_INT_1MS 0b1010 294#define MSA311_LATCH_INT_2MS 0b1011 295#define MSA311_LATCH_INT_25MS 0b1100 296#define MSA311_LATCH_INT_50MS 0b1101 297#define MSA311_LATCH_INT_100MS 0b1110 298#define MSA311_LATCH_INT_LATCHED 0b0111 299 300static const struct regmap_range msa311_readonly_registers[] = { 301 regmap_reg_range(MSA311_PARTID_REG, MSA311_ORIENT_STS_REG), 302}; 303 304static const struct regmap_access_table msa311_writeable_table = { 305 .no_ranges = msa311_readonly_registers, 306 .n_no_ranges = ARRAY_SIZE(msa311_readonly_registers), 307}; 308 309static const struct regmap_range msa311_writeonly_registers[] = { 310 regmap_reg_range(MSA311_SOFT_RESET_REG, MSA311_SOFT_RESET_REG), 311}; 312 313static const struct regmap_access_table msa311_readable_table = { 314 .no_ranges = msa311_writeonly_registers, 315 .n_no_ranges = ARRAY_SIZE(msa311_writeonly_registers), 316}; 317 318static const struct regmap_range msa311_volatile_registers[] = { 319 regmap_reg_range(MSA311_ACC_X_REG, MSA311_ORIENT_STS_REG), 320}; 321 322static const struct regmap_access_table msa311_volatile_table = { 323 .yes_ranges = msa311_volatile_registers, 324 .n_yes_ranges = ARRAY_SIZE(msa311_volatile_registers), 325}; 326 327static const struct regmap_config msa311_regmap_config = { 328 .name = "msa311", 329 .reg_bits = 8, 330 .val_bits = 8, 331 .max_register = MSA311_OFFSET_Z_REG, 332 .wr_table = &msa311_writeable_table, 333 .rd_table = &msa311_readable_table, 334 .volatile_table = &msa311_volatile_table, 335 .cache_type = REGCACHE_MAPLE, 336}; 337 338#define MSA311_GENMASK(field) ({ \ 339 typeof(&(msa311_reg_fields)[0]) _field; \ 340 _field = &msa311_reg_fields[(field)]; \ 341 GENMASK(_field->msb, _field->lsb); \ 342}) 343 344/** 345 * struct msa311_priv - MSA311 internal private state 346 * @regs: Underlying I2C bus adapter used to abstract slave 347 * register accesses 348 * @fields: Abstract objects for each registers fields access 349 * @dev: Device handler associated with appropriate bus client 350 * @lock: Protects msa311 device state between setup and data access routines 351 * (power transitions, samp_freq/scale tune, retrieving axes data, etc) 352 * @chip_name: Chip name in the format "msa311-%02x" % partid 353 * @new_data_trig: Optional NEW_DATA interrupt driven trigger used 354 * to notify external consumers a new sample is ready 355 */ 356struct msa311_priv { 357 struct regmap *regs; 358 struct regmap_field *fields[F_MAX_FIELDS]; 359 360 struct device *dev; 361 struct mutex lock; 362 char *chip_name; 363 364 struct iio_trigger *new_data_trig; 365}; 366 367enum msa311_si { 368 MSA311_SI_X, 369 MSA311_SI_Y, 370 MSA311_SI_Z, 371 MSA311_SI_TIMESTAMP, 372}; 373 374#define MSA311_ACCEL_CHANNEL(axis) { \ 375 .type = IIO_ACCEL, \ 376 .modified = 1, \ 377 .channel2 = IIO_MOD_##axis, \ 378 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 379 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 380 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 381 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE) | \ 382 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 383 .scan_index = MSA311_SI_##axis, \ 384 .scan_type = { \ 385 .sign = 's', \ 386 .realbits = 12, \ 387 .storagebits = 16, \ 388 .shift = 4, \ 389 .endianness = IIO_LE, \ 390 }, \ 391 .datasheet_name = "ACC_"#axis, \ 392} 393 394static const struct iio_chan_spec msa311_channels[] = { 395 MSA311_ACCEL_CHANNEL(X), 396 MSA311_ACCEL_CHANNEL(Y), 397 MSA311_ACCEL_CHANNEL(Z), 398 IIO_CHAN_SOFT_TIMESTAMP(MSA311_SI_TIMESTAMP), 399}; 400 401/** 402 * msa311_get_odr() - Read Output Data Rate (ODR) value from MSA311 accel 403 * @msa311: MSA311 internal private state 404 * @odr: output ODR value 405 * 406 * This function should be called under msa311->lock. 407 * 408 * Return: 0 on success, -ERRNO in other failures 409 */ 410static int msa311_get_odr(struct msa311_priv *msa311, unsigned int *odr) 411{ 412 int err; 413 414 err = regmap_field_read(msa311->fields[F_ODR], odr); 415 if (err) 416 return err; 417 418 /* 419 * Filter the same 1000Hz ODR register values based on datasheet info. 420 * ODR can be equal to 1010-1111 for 1000Hz, but function returns 1010 421 * all the time. 422 */ 423 if (*odr > MSA311_ODR_1000_HZ) 424 *odr = MSA311_ODR_1000_HZ; 425 426 return 0; 427} 428 429/** 430 * msa311_set_odr() - Setup Output Data Rate (ODR) value for MSA311 accel 431 * @msa311: MSA311 internal private state 432 * @odr: requested ODR value 433 * 434 * This function should be called under msa311->lock. Possible ODR values: 435 * - 1Hz (not available in normal mode) 436 * - 1.95Hz (not available in normal mode) 437 * - 3.9Hz 438 * - 7.81Hz 439 * - 15.63Hz 440 * - 31.25Hz 441 * - 62.5Hz 442 * - 125Hz 443 * - 250Hz 444 * - 500Hz 445 * - 1000Hz 446 * 447 * Return: 0 on success, -EINVAL for bad ODR value in the certain power mode, 448 * -ERRNO in other failures 449 */ 450static int msa311_set_odr(struct msa311_priv *msa311, unsigned int odr) 451{ 452 struct device *dev = msa311->dev; 453 unsigned int pwr_mode; 454 bool good_odr; 455 int err; 456 457 err = regmap_field_read(msa311->fields[F_PWR_MODE], &pwr_mode); 458 if (err) 459 return err; 460 461 /* Filter bad ODR values */ 462 if (pwr_mode == MSA311_PWR_MODE_NORMAL) 463 good_odr = (odr > MSA311_ODR_1_95_HZ); 464 else 465 good_odr = false; 466 467 if (!good_odr) { 468 dev_err(dev, 469 "can't set odr %u.%06uHz, not available in %s mode\n", 470 msa311_odr_table[odr].integral, 471 msa311_odr_table[odr].microfract, 472 msa311_pwr_modes[pwr_mode]); 473 return -EINVAL; 474 } 475 476 return regmap_field_write(msa311->fields[F_ODR], odr); 477} 478 479/** 480 * msa311_wait_for_next_data() - Wait next accel data available after resume 481 * @msa311: MSA311 internal private state 482 * 483 * Return: 0 on success, -EINTR if msleep() was interrupted, 484 * -ERRNO in other failures 485 */ 486static int msa311_wait_for_next_data(struct msa311_priv *msa311) 487{ 488 static const unsigned int unintr_thresh_ms = 20; 489 struct device *dev = msa311->dev; 490 unsigned long freq_uhz; 491 unsigned long wait_ms; 492 unsigned int odr; 493 int err; 494 495 err = msa311_get_odr(msa311, &odr); 496 if (err) { 497 dev_err(dev, "can't get actual frequency (%pe)\n", 498 ERR_PTR(err)); 499 return err; 500 } 501 502 /* 503 * After msa311 resuming is done, we need to wait for data 504 * to be refreshed by accel logic. 505 * A certain timeout is calculated based on the current ODR value. 506 * If requested timeout isn't so long (let's assume 20ms), 507 * we can wait for next data in uninterruptible sleep. 508 */ 509 freq_uhz = msa311_odr_table[odr].integral * MICROHZ_PER_HZ + 510 msa311_odr_table[odr].microfract; 511 wait_ms = (MICROHZ_PER_HZ / freq_uhz) * MSEC_PER_SEC; 512 513 if (wait_ms < unintr_thresh_ms) 514 usleep_range(wait_ms * USEC_PER_MSEC, 515 unintr_thresh_ms * USEC_PER_MSEC); 516 else if (msleep_interruptible(wait_ms)) 517 return -EINTR; 518 519 return 0; 520} 521 522/** 523 * msa311_set_pwr_mode() - Install certain MSA311 power mode 524 * @msa311: MSA311 internal private state 525 * @mode: Power mode can be equal to NORMAL or SUSPEND 526 * 527 * This function should be called under msa311->lock. 528 * 529 * Return: 0 on success, -ERRNO on failure 530 */ 531static int msa311_set_pwr_mode(struct msa311_priv *msa311, unsigned int mode) 532{ 533 struct device *dev = msa311->dev; 534 unsigned int prev_mode; 535 int err; 536 537 if (mode >= ARRAY_SIZE(msa311_pwr_modes)) 538 return -EINVAL; 539 540 dev_dbg(dev, "transition to %s mode\n", msa311_pwr_modes[mode]); 541 542 err = regmap_field_read(msa311->fields[F_PWR_MODE], &prev_mode); 543 if (err) 544 return err; 545 546 err = regmap_field_write(msa311->fields[F_PWR_MODE], mode); 547 if (err) 548 return err; 549 550 /* Wait actual data if we wake up */ 551 if (prev_mode == MSA311_PWR_MODE_SUSPEND && 552 mode == MSA311_PWR_MODE_NORMAL) 553 return msa311_wait_for_next_data(msa311); 554 555 return 0; 556} 557 558/** 559 * msa311_get_axis() - Read MSA311 accel data for certain IIO channel axis spec 560 * @msa311: MSA311 internal private state 561 * @chan: IIO channel specification 562 * @axis: Output accel axis data for requested IIO channel spec 563 * 564 * This function should be called under msa311->lock. 565 * 566 * Return: 0 on success, -EINVAL for unknown IIO channel specification, 567 * -ERRNO in other failures 568 */ 569static int msa311_get_axis(struct msa311_priv *msa311, 570 const struct iio_chan_spec * const chan, 571 __le16 *axis) 572{ 573 struct device *dev = msa311->dev; 574 unsigned int axis_reg; 575 576 if (chan->scan_index < MSA311_SI_X || chan->scan_index > MSA311_SI_Z) { 577 dev_err(dev, "invalid scan_index value [%d]\n", 578 chan->scan_index); 579 return -EINVAL; 580 } 581 582 /* Axes data layout has 2 byte gap for each axis starting from X axis */ 583 axis_reg = MSA311_ACC_X_REG + (chan->scan_index << 1); 584 585 return regmap_bulk_read(msa311->regs, axis_reg, axis, sizeof(*axis)); 586} 587 588static int msa311_read_raw_data(struct iio_dev *indio_dev, 589 struct iio_chan_spec const *chan, 590 int *val, int *val2) 591{ 592 struct msa311_priv *msa311 = iio_priv(indio_dev); 593 struct device *dev = msa311->dev; 594 __le16 axis; 595 int err; 596 597 if (!iio_device_claim_direct(indio_dev)) 598 return -EBUSY; 599 600 err = pm_runtime_resume_and_get(dev); 601 if (err) { 602 iio_device_release_direct(indio_dev); 603 return err; 604 } 605 606 mutex_lock(&msa311->lock); 607 err = msa311_get_axis(msa311, chan, &axis); 608 mutex_unlock(&msa311->lock); 609 610 pm_runtime_put_autosuspend(dev); 611 612 iio_device_release_direct(indio_dev); 613 614 if (err) { 615 dev_err(dev, "can't get axis %s (%pe)\n", 616 chan->datasheet_name, ERR_PTR(err)); 617 return err; 618 } 619 620 /* 621 * Axis data format is: 622 * ACC_X = (ACC_X_MSB[7:0] << 4) | ACC_X_LSB[7:4] 623 */ 624 *val = sign_extend32(le16_to_cpu(axis) >> chan->scan_type.shift, 625 chan->scan_type.realbits - 1); 626 627 return IIO_VAL_INT; 628} 629 630static int msa311_read_scale(struct iio_dev *indio_dev, int *val, int *val2) 631{ 632 struct msa311_priv *msa311 = iio_priv(indio_dev); 633 struct device *dev = msa311->dev; 634 unsigned int fs; 635 int err; 636 637 mutex_lock(&msa311->lock); 638 err = regmap_field_read(msa311->fields[F_FS], &fs); 639 mutex_unlock(&msa311->lock); 640 if (err) { 641 dev_err(dev, "can't get actual scale (%pe)\n", ERR_PTR(err)); 642 return err; 643 } 644 645 *val = msa311_fs_table[fs].integral; 646 *val2 = msa311_fs_table[fs].microfract; 647 648 return IIO_VAL_INT_PLUS_MICRO; 649} 650 651static int msa311_read_samp_freq(struct iio_dev *indio_dev, 652 int *val, int *val2) 653{ 654 struct msa311_priv *msa311 = iio_priv(indio_dev); 655 struct device *dev = msa311->dev; 656 unsigned int odr; 657 int err; 658 659 mutex_lock(&msa311->lock); 660 err = msa311_get_odr(msa311, &odr); 661 mutex_unlock(&msa311->lock); 662 if (err) { 663 dev_err(dev, "can't get actual frequency (%pe)\n", 664 ERR_PTR(err)); 665 return err; 666 } 667 668 *val = msa311_odr_table[odr].integral; 669 *val2 = msa311_odr_table[odr].microfract; 670 671 return IIO_VAL_INT_PLUS_MICRO; 672} 673 674static int msa311_read_raw(struct iio_dev *indio_dev, 675 struct iio_chan_spec const *chan, 676 int *val, int *val2, long mask) 677{ 678 switch (mask) { 679 case IIO_CHAN_INFO_RAW: 680 return msa311_read_raw_data(indio_dev, chan, val, val2); 681 682 case IIO_CHAN_INFO_SCALE: 683 return msa311_read_scale(indio_dev, val, val2); 684 685 case IIO_CHAN_INFO_SAMP_FREQ: 686 return msa311_read_samp_freq(indio_dev, val, val2); 687 688 default: 689 return -EINVAL; 690 } 691} 692 693static int msa311_read_avail(struct iio_dev *indio_dev, 694 struct iio_chan_spec const *chan, 695 const int **vals, int *type, 696 int *length, long mask) 697{ 698 switch (mask) { 699 case IIO_CHAN_INFO_SAMP_FREQ: 700 *vals = (int *)msa311_odr_table; 701 *type = IIO_VAL_INT_PLUS_MICRO; 702 /* ODR value has 2 ints (integer and fractional parts) */ 703 *length = ARRAY_SIZE(msa311_odr_table) * 2; 704 return IIO_AVAIL_LIST; 705 706 case IIO_CHAN_INFO_SCALE: 707 *vals = (int *)msa311_fs_table; 708 *type = IIO_VAL_INT_PLUS_MICRO; 709 /* FS value has 2 ints (integer and fractional parts) */ 710 *length = ARRAY_SIZE(msa311_fs_table) * 2; 711 return IIO_AVAIL_LIST; 712 713 default: 714 return -EINVAL; 715 } 716} 717 718static int msa311_write_scale(struct iio_dev *indio_dev, int val, int val2) 719{ 720 struct msa311_priv *msa311 = iio_priv(indio_dev); 721 struct device *dev = msa311->dev; 722 unsigned int fs; 723 int err; 724 725 /* We do not have fs >= 1, so skip such values */ 726 if (val) 727 return 0; 728 729 err = pm_runtime_resume_and_get(dev); 730 if (err) 731 return err; 732 733 err = -EINVAL; 734 for (fs = 0; fs < ARRAY_SIZE(msa311_fs_table); fs++) 735 /* Do not check msa311_fs_table[fs].integral, it's always 0 */ 736 if (val2 == msa311_fs_table[fs].microfract) { 737 mutex_lock(&msa311->lock); 738 err = regmap_field_write(msa311->fields[F_FS], fs); 739 mutex_unlock(&msa311->lock); 740 break; 741 } 742 743 pm_runtime_put_autosuspend(dev); 744 745 if (err) 746 dev_err(dev, "can't update scale (%pe)\n", ERR_PTR(err)); 747 748 return err; 749} 750 751static int msa311_write_samp_freq(struct iio_dev *indio_dev, int val, int val2) 752{ 753 struct msa311_priv *msa311 = iio_priv(indio_dev); 754 struct device *dev = msa311->dev; 755 unsigned int odr; 756 int err; 757 758 /* 759 * Sampling frequency changing is prohibited when buffer mode is 760 * enabled, because sometimes MSA311 chip returns outliers during 761 * frequency values growing up in the read operation moment. 762 */ 763 if (!iio_device_claim_direct(indio_dev)) 764 return -EBUSY; 765 766 err = pm_runtime_resume_and_get(dev); 767 if (err) { 768 iio_device_release_direct(indio_dev); 769 return err; 770 } 771 772 err = -EINVAL; 773 for (odr = 0; odr < ARRAY_SIZE(msa311_odr_table); odr++) 774 if (val == msa311_odr_table[odr].integral && 775 val2 == msa311_odr_table[odr].microfract) { 776 mutex_lock(&msa311->lock); 777 err = msa311_set_odr(msa311, odr); 778 mutex_unlock(&msa311->lock); 779 break; 780 } 781 782 pm_runtime_put_autosuspend(dev); 783 784 iio_device_release_direct(indio_dev); 785 786 if (err) 787 dev_err(dev, "can't update frequency (%pe)\n", ERR_PTR(err)); 788 789 return err; 790} 791 792static int msa311_write_raw(struct iio_dev *indio_dev, 793 struct iio_chan_spec const *chan, 794 int val, int val2, long mask) 795{ 796 switch (mask) { 797 case IIO_CHAN_INFO_SCALE: 798 return msa311_write_scale(indio_dev, val, val2); 799 800 case IIO_CHAN_INFO_SAMP_FREQ: 801 return msa311_write_samp_freq(indio_dev, val, val2); 802 803 default: 804 return -EINVAL; 805 } 806} 807 808static int msa311_debugfs_reg_access(struct iio_dev *indio_dev, 809 unsigned int reg, unsigned int writeval, 810 unsigned int *readval) 811{ 812 struct msa311_priv *msa311 = iio_priv(indio_dev); 813 struct device *dev = msa311->dev; 814 int err; 815 816 if (reg > regmap_get_max_register(msa311->regs)) 817 return -EINVAL; 818 819 err = pm_runtime_resume_and_get(dev); 820 if (err) 821 return err; 822 823 mutex_lock(&msa311->lock); 824 825 if (readval) 826 err = regmap_read(msa311->regs, reg, readval); 827 else 828 err = regmap_write(msa311->regs, reg, writeval); 829 830 mutex_unlock(&msa311->lock); 831 832 pm_runtime_put_autosuspend(dev); 833 834 if (err) 835 dev_err(dev, "can't %s register %u from debugfs (%pe)\n", 836 str_read_write(readval), reg, ERR_PTR(err)); 837 838 return err; 839} 840 841static int msa311_buffer_preenable(struct iio_dev *indio_dev) 842{ 843 struct msa311_priv *msa311 = iio_priv(indio_dev); 844 struct device *dev = msa311->dev; 845 846 return pm_runtime_resume_and_get(dev); 847} 848 849static int msa311_buffer_postdisable(struct iio_dev *indio_dev) 850{ 851 struct msa311_priv *msa311 = iio_priv(indio_dev); 852 struct device *dev = msa311->dev; 853 854 pm_runtime_put_autosuspend(dev); 855 856 return 0; 857} 858 859static int msa311_set_new_data_trig_state(struct iio_trigger *trig, bool state) 860{ 861 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 862 struct msa311_priv *msa311 = iio_priv(indio_dev); 863 struct device *dev = msa311->dev; 864 int err; 865 866 mutex_lock(&msa311->lock); 867 err = regmap_field_write(msa311->fields[F_NEW_DATA_INT_EN], state); 868 mutex_unlock(&msa311->lock); 869 if (err) 870 dev_err(dev, 871 "can't %s buffer due to new_data_int failure (%pe)\n", 872 str_enable_disable(state), ERR_PTR(err)); 873 874 return err; 875} 876 877static int msa311_validate_device(struct iio_trigger *trig, 878 struct iio_dev *indio_dev) 879{ 880 return iio_trigger_get_drvdata(trig) == indio_dev ? 0 : -EINVAL; 881} 882 883static irqreturn_t msa311_buffer_thread(int irq, void *p) 884{ 885 struct iio_poll_func *pf = p; 886 struct msa311_priv *msa311 = iio_priv(pf->indio_dev); 887 struct iio_dev *indio_dev = pf->indio_dev; 888 const struct iio_chan_spec *chan; 889 struct device *dev = msa311->dev; 890 int bit, err, i = 0; 891 __le16 axis; 892 struct { 893 __le16 channels[MSA311_SI_Z + 1]; 894 aligned_s64 ts; 895 } buf = { }; 896 897 mutex_lock(&msa311->lock); 898 899 iio_for_each_active_channel(indio_dev, bit) { 900 chan = &msa311_channels[bit]; 901 902 err = msa311_get_axis(msa311, chan, &axis); 903 if (err) { 904 mutex_unlock(&msa311->lock); 905 dev_err(dev, "can't get axis %s (%pe)\n", 906 chan->datasheet_name, ERR_PTR(err)); 907 goto notify_done; 908 } 909 910 buf.channels[i++] = axis; 911 } 912 913 mutex_unlock(&msa311->lock); 914 915 iio_push_to_buffers_with_ts(indio_dev, &buf, sizeof(buf), 916 iio_get_time_ns(indio_dev)); 917 918notify_done: 919 iio_trigger_notify_done(indio_dev->trig); 920 921 return IRQ_HANDLED; 922} 923 924static irqreturn_t msa311_irq_thread(int irq, void *p) 925{ 926 struct msa311_priv *msa311 = iio_priv(p); 927 unsigned int new_data_int_enabled; 928 struct device *dev = msa311->dev; 929 int err; 930 931 mutex_lock(&msa311->lock); 932 933 /* 934 * We do not check NEW_DATA int status, because based on the 935 * specification it's cleared automatically after a fixed time. 936 * So just check that is enabled by driver logic. 937 */ 938 err = regmap_field_read(msa311->fields[F_NEW_DATA_INT_EN], 939 &new_data_int_enabled); 940 941 mutex_unlock(&msa311->lock); 942 if (err) { 943 dev_err(dev, "can't read new_data interrupt state (%pe)\n", 944 ERR_PTR(err)); 945 return IRQ_NONE; 946 } 947 948 if (new_data_int_enabled) 949 iio_trigger_poll_nested(msa311->new_data_trig); 950 951 return IRQ_HANDLED; 952} 953 954static const struct iio_info msa311_info = { 955 .read_raw = msa311_read_raw, 956 .read_avail = msa311_read_avail, 957 .write_raw = msa311_write_raw, 958 .debugfs_reg_access = msa311_debugfs_reg_access, 959}; 960 961static const struct iio_buffer_setup_ops msa311_buffer_setup_ops = { 962 .preenable = msa311_buffer_preenable, 963 .postdisable = msa311_buffer_postdisable, 964}; 965 966static const struct iio_trigger_ops msa311_new_data_trig_ops = { 967 .set_trigger_state = msa311_set_new_data_trig_state, 968 .validate_device = msa311_validate_device, 969}; 970 971static int msa311_check_partid(struct msa311_priv *msa311) 972{ 973 struct device *dev = msa311->dev; 974 unsigned int partid; 975 int err; 976 977 err = regmap_read(msa311->regs, MSA311_PARTID_REG, &partid); 978 if (err) 979 return dev_err_probe(dev, err, "failed to read partid\n"); 980 981 if (partid != MSA311_WHO_AM_I) 982 dev_warn(dev, "invalid partid (%#x), expected (%#x)\n", 983 partid, MSA311_WHO_AM_I); 984 985 msa311->chip_name = devm_kasprintf(dev, GFP_KERNEL, 986 "msa311-%02x", partid); 987 if (!msa311->chip_name) 988 return -ENOMEM; 989 990 return 0; 991} 992 993static int msa311_soft_reset(struct msa311_priv *msa311) 994{ 995 struct device *dev = msa311->dev; 996 int err; 997 998 err = regmap_write(msa311->regs, MSA311_SOFT_RESET_REG, 999 MSA311_GENMASK(F_SOFT_RESET_I2C) | 1000 MSA311_GENMASK(F_SOFT_RESET_SPI)); 1001 if (err) 1002 return dev_err_probe(dev, err, "can't soft reset all logic\n"); 1003 1004 return 0; 1005} 1006 1007static int msa311_chip_init(struct msa311_priv *msa311) 1008{ 1009 struct device *dev = msa311->dev; 1010 const char zero_bulk[2] = { }; 1011 int err; 1012 1013 err = regmap_write(msa311->regs, MSA311_RANGE_REG, MSA311_FS_16G); 1014 if (err) 1015 return dev_err_probe(dev, err, "failed to setup accel range\n"); 1016 1017 /* Disable all interrupts by default */ 1018 err = regmap_bulk_write(msa311->regs, MSA311_INT_SET_0_REG, 1019 zero_bulk, sizeof(zero_bulk)); 1020 if (err) 1021 return dev_err_probe(dev, err, 1022 "can't disable set0/set1 interrupts\n"); 1023 1024 /* Unmap all INT1 interrupts by default */ 1025 err = regmap_bulk_write(msa311->regs, MSA311_INT_MAP_0_REG, 1026 zero_bulk, sizeof(zero_bulk)); 1027 if (err) 1028 return dev_err_probe(dev, err, 1029 "failed to unmap map0/map1 interrupts\n"); 1030 1031 /* Disable all axes by default */ 1032 err = regmap_clear_bits(msa311->regs, MSA311_ODR_REG, 1033 MSA311_GENMASK(F_X_AXIS_DIS) | 1034 MSA311_GENMASK(F_Y_AXIS_DIS) | 1035 MSA311_GENMASK(F_Z_AXIS_DIS)); 1036 if (err) 1037 return dev_err_probe(dev, err, "can't enable all axes\n"); 1038 1039 err = msa311_set_odr(msa311, MSA311_ODR_125_HZ); 1040 if (err) 1041 return dev_err_probe(dev, err, 1042 "failed to set accel frequency\n"); 1043 1044 return 0; 1045} 1046 1047static int msa311_setup_interrupts(struct msa311_priv *msa311) 1048{ 1049 struct device *dev = msa311->dev; 1050 struct i2c_client *i2c = to_i2c_client(dev); 1051 struct iio_dev *indio_dev = i2c_get_clientdata(i2c); 1052 struct iio_trigger *trig; 1053 int err; 1054 1055 /* Keep going without interrupts if no initialized I2C IRQ */ 1056 if (i2c->irq <= 0) 1057 return 0; 1058 1059 err = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, 1060 msa311_irq_thread, IRQF_ONESHOT, 1061 msa311->chip_name, indio_dev); 1062 if (err) 1063 return dev_err_probe(dev, err, "failed to request IRQ\n"); 1064 1065 trig = devm_iio_trigger_alloc(dev, "%s-new-data", msa311->chip_name); 1066 if (!trig) 1067 return -ENOMEM; 1068 1069 msa311->new_data_trig = trig; 1070 msa311->new_data_trig->ops = &msa311_new_data_trig_ops; 1071 iio_trigger_set_drvdata(msa311->new_data_trig, indio_dev); 1072 1073 err = devm_iio_trigger_register(dev, msa311->new_data_trig); 1074 if (err) 1075 return dev_err_probe(dev, err, 1076 "can't register newdata trigger\n"); 1077 1078 err = regmap_field_write(msa311->fields[F_INT1_OD], 1079 MSA311_INT1_OD_PUSH_PULL); 1080 if (err) 1081 return dev_err_probe(dev, err, 1082 "can't enable push-pull interrupt\n"); 1083 1084 err = regmap_field_write(msa311->fields[F_INT1_LVL], 1085 MSA311_INT1_LVL_HIGH); 1086 if (err) 1087 return dev_err_probe(dev, err, 1088 "can't set active interrupt level\n"); 1089 1090 err = regmap_field_write(msa311->fields[F_LATCH_INT], 1091 MSA311_LATCH_INT_LATCHED); 1092 if (err) 1093 return dev_err_probe(dev, err, 1094 "can't latch interrupt\n"); 1095 1096 err = regmap_field_write(msa311->fields[F_RESET_INT], 1); 1097 if (err) 1098 return dev_err_probe(dev, err, 1099 "can't reset interrupt\n"); 1100 1101 err = regmap_field_write(msa311->fields[F_INT1_NEW_DATA], 1); 1102 if (err) 1103 return dev_err_probe(dev, err, 1104 "can't map new data interrupt\n"); 1105 1106 return 0; 1107} 1108 1109static int msa311_regmap_init(struct msa311_priv *msa311) 1110{ 1111 struct regmap_field **fields = msa311->fields; 1112 struct device *dev = msa311->dev; 1113 struct i2c_client *i2c = to_i2c_client(dev); 1114 struct regmap *regmap; 1115 int i; 1116 1117 regmap = devm_regmap_init_i2c(i2c, &msa311_regmap_config); 1118 if (IS_ERR(regmap)) 1119 return dev_err_probe(dev, PTR_ERR(regmap), 1120 "failed to register i2c regmap\n"); 1121 1122 msa311->regs = regmap; 1123 1124 for (i = 0; i < F_MAX_FIELDS; i++) { 1125 fields[i] = devm_regmap_field_alloc(dev, 1126 msa311->regs, 1127 msa311_reg_fields[i]); 1128 if (IS_ERR(msa311->fields[i])) 1129 return dev_err_probe(dev, PTR_ERR(msa311->fields[i]), 1130 "can't alloc field[%d]\n", i); 1131 } 1132 1133 return 0; 1134} 1135 1136static void msa311_powerdown(void *msa311) 1137{ 1138 msa311_set_pwr_mode(msa311, MSA311_PWR_MODE_SUSPEND); 1139} 1140 1141static int msa311_probe(struct i2c_client *i2c) 1142{ 1143 struct device *dev = &i2c->dev; 1144 struct msa311_priv *msa311; 1145 struct iio_dev *indio_dev; 1146 int err; 1147 1148 indio_dev = devm_iio_device_alloc(dev, sizeof(*msa311)); 1149 if (!indio_dev) 1150 return -ENOMEM; 1151 1152 msa311 = iio_priv(indio_dev); 1153 msa311->dev = dev; 1154 i2c_set_clientdata(i2c, indio_dev); 1155 1156 err = msa311_regmap_init(msa311); 1157 if (err) 1158 return err; 1159 1160 mutex_init(&msa311->lock); 1161 1162 err = devm_regulator_get_enable(dev, "vdd"); 1163 if (err) 1164 return dev_err_probe(dev, err, "can't get vdd supply\n"); 1165 1166 err = msa311_check_partid(msa311); 1167 if (err) 1168 return err; 1169 1170 err = msa311_soft_reset(msa311); 1171 if (err) 1172 return err; 1173 1174 err = msa311_set_pwr_mode(msa311, MSA311_PWR_MODE_NORMAL); 1175 if (err) 1176 return dev_err_probe(dev, err, "failed to power on device\n"); 1177 1178 /* 1179 * Register powerdown deferred callback which suspends the chip 1180 * after module unloaded. 1181 * 1182 * MSA311 should be in SUSPEND mode in the two cases: 1183 * 1) When driver is loaded, but we do not have any data or 1184 * configuration requests to it (we are solving it using 1185 * autosuspend feature). 1186 * 2) When driver is unloaded and device is not used (devm action is 1187 * used in this case). 1188 */ 1189 err = devm_add_action_or_reset(dev, msa311_powerdown, msa311); 1190 if (err) 1191 return err; 1192 1193 err = pm_runtime_set_active(dev); 1194 if (err) 1195 return err; 1196 1197 err = devm_pm_runtime_enable(dev); 1198 if (err) 1199 return err; 1200 1201 pm_runtime_get_noresume(dev); 1202 pm_runtime_set_autosuspend_delay(dev, MSA311_PWR_SLEEP_DELAY_MS); 1203 pm_runtime_use_autosuspend(dev); 1204 1205 err = msa311_chip_init(msa311); 1206 if (err) 1207 return err; 1208 1209 indio_dev->modes = INDIO_DIRECT_MODE; 1210 indio_dev->channels = msa311_channels; 1211 indio_dev->num_channels = ARRAY_SIZE(msa311_channels); 1212 indio_dev->name = msa311->chip_name; 1213 indio_dev->info = &msa311_info; 1214 1215 err = devm_iio_triggered_buffer_setup(dev, indio_dev, 1216 iio_pollfunc_store_time, 1217 msa311_buffer_thread, 1218 &msa311_buffer_setup_ops); 1219 if (err) 1220 return dev_err_probe(dev, err, 1221 "can't setup IIO trigger buffer\n"); 1222 1223 err = msa311_setup_interrupts(msa311); 1224 if (err) 1225 return err; 1226 1227 pm_runtime_put_autosuspend(dev); 1228 1229 err = devm_iio_device_register(dev, indio_dev); 1230 if (err) 1231 return dev_err_probe(dev, err, "IIO device register failed\n"); 1232 1233 return 0; 1234} 1235 1236static int msa311_runtime_suspend(struct device *dev) 1237{ 1238 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1239 struct msa311_priv *msa311 = iio_priv(indio_dev); 1240 int err; 1241 1242 mutex_lock(&msa311->lock); 1243 err = msa311_set_pwr_mode(msa311, MSA311_PWR_MODE_SUSPEND); 1244 mutex_unlock(&msa311->lock); 1245 if (err) 1246 dev_err(dev, "failed to power off device (%pe)\n", 1247 ERR_PTR(err)); 1248 1249 return err; 1250} 1251 1252static int msa311_runtime_resume(struct device *dev) 1253{ 1254 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1255 struct msa311_priv *msa311 = iio_priv(indio_dev); 1256 int err; 1257 1258 mutex_lock(&msa311->lock); 1259 err = msa311_set_pwr_mode(msa311, MSA311_PWR_MODE_NORMAL); 1260 mutex_unlock(&msa311->lock); 1261 if (err) 1262 dev_err(dev, "failed to power on device (%pe)\n", 1263 ERR_PTR(err)); 1264 1265 return err; 1266} 1267 1268static DEFINE_RUNTIME_DEV_PM_OPS(msa311_pm_ops, msa311_runtime_suspend, 1269 msa311_runtime_resume, NULL); 1270 1271static const struct i2c_device_id msa311_i2c_id[] = { 1272 { .name = "msa311" }, 1273 { } 1274}; 1275MODULE_DEVICE_TABLE(i2c, msa311_i2c_id); 1276 1277static const struct of_device_id msa311_of_match[] = { 1278 { .compatible = "memsensing,msa311" }, 1279 { } 1280}; 1281MODULE_DEVICE_TABLE(of, msa311_of_match); 1282 1283static struct i2c_driver msa311_driver = { 1284 .driver = { 1285 .name = "msa311", 1286 .of_match_table = msa311_of_match, 1287 .pm = pm_ptr(&msa311_pm_ops), 1288 }, 1289 .probe = msa311_probe, 1290 .id_table = msa311_i2c_id, 1291}; 1292module_i2c_driver(msa311_driver); 1293 1294MODULE_AUTHOR("Dmitry Rokosov <ddrokosov@sberdevices.ru>"); 1295MODULE_DESCRIPTION("MEMSensing MSA311 3-axis accelerometer driver"); 1296MODULE_LICENSE("GPL");
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