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mma8452.c
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linux-6.19.14/drivers/iio/accel/mma8452.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers: 4 * 5 * device name digital output 7-bit I2C slave address (pin selectable) 6 * --------------------------------------------------------------------- 7 * MMA8451Q 14 bit 0x1c / 0x1d 8 * MMA8452Q 12 bit 0x1c / 0x1d 9 * MMA8453Q 10 bit 0x1c / 0x1d 10 * MMA8652FC 12 bit 0x1d 11 * MMA8653FC 10 bit 0x1d 12 * FXLS8471Q 14 bit 0x1e / 0x1d / 0x1c / 0x1f 13 * 14 * Copyright 2015 Martin Kepplinger <martink@posteo.de> 15 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net> 16 * 17 * 18 * TODO: orientation events 19 */ 20 21#include <linux/module.h> 22#include <linux/mod_devicetable.h> 23#include <linux/property.h> 24#include <linux/i2c.h> 25#include <linux/iio/iio.h> 26#include <linux/iio/sysfs.h> 27#include <linux/iio/buffer.h> 28#include <linux/iio/trigger.h> 29#include <linux/iio/trigger_consumer.h> 30#include <linux/iio/triggered_buffer.h> 31#include <linux/iio/events.h> 32#include <linux/delay.h> 33#include <linux/pm_runtime.h> 34#include <linux/regulator/consumer.h> 35#include <linux/types.h> 36 37#define MMA8452_STATUS 0x00 38#define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0)) 39#define MMA8452_OUT_X 0x01 /* MSB first */ 40#define MMA8452_OUT_Y 0x03 41#define MMA8452_OUT_Z 0x05 42#define MMA8452_INT_SRC 0x0c 43#define MMA8452_WHO_AM_I 0x0d 44#define MMA8452_DATA_CFG 0x0e 45#define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0) 46#define MMA8452_DATA_CFG_FS_2G 0 47#define MMA8452_DATA_CFG_FS_4G 1 48#define MMA8452_DATA_CFG_FS_8G 2 49#define MMA8452_DATA_CFG_HPF_MASK BIT(4) 50#define MMA8452_HP_FILTER_CUTOFF 0x0f 51#define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0) 52#define MMA8452_FF_MT_CFG 0x15 53#define MMA8452_FF_MT_CFG_OAE BIT(6) 54#define MMA8452_FF_MT_CFG_ELE BIT(7) 55#define MMA8452_FF_MT_SRC 0x16 56#define MMA8452_FF_MT_SRC_XHE BIT(1) 57#define MMA8452_FF_MT_SRC_YHE BIT(3) 58#define MMA8452_FF_MT_SRC_ZHE BIT(5) 59#define MMA8452_FF_MT_THS 0x17 60#define MMA8452_FF_MT_THS_MASK 0x7f 61#define MMA8452_FF_MT_COUNT 0x18 62#define MMA8452_FF_MT_CHAN_SHIFT 3 63#define MMA8452_TRANSIENT_CFG 0x1d 64#define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1) 65#define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0) 66#define MMA8452_TRANSIENT_CFG_ELE BIT(4) 67#define MMA8452_TRANSIENT_SRC 0x1e 68#define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1) 69#define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3) 70#define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5) 71#define MMA8452_TRANSIENT_THS 0x1f 72#define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0) 73#define MMA8452_TRANSIENT_COUNT 0x20 74#define MMA8452_TRANSIENT_CHAN_SHIFT 1 75#define MMA8452_CTRL_REG1 0x2a 76#define MMA8452_CTRL_ACTIVE BIT(0) 77#define MMA8452_CTRL_DR_MASK GENMASK(5, 3) 78#define MMA8452_CTRL_DR_SHIFT 3 79#define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */ 80#define MMA8452_CTRL_REG2 0x2b 81#define MMA8452_CTRL_REG2_RST BIT(6) 82#define MMA8452_CTRL_REG2_MODS_SHIFT 3 83#define MMA8452_CTRL_REG2_MODS_MASK 0x1b 84#define MMA8452_CTRL_REG4 0x2d 85#define MMA8452_CTRL_REG5 0x2e 86#define MMA8452_OFF_X 0x2f 87#define MMA8452_OFF_Y 0x30 88#define MMA8452_OFF_Z 0x31 89 90#define MMA8452_MAX_REG 0x31 91 92#define MMA8452_INT_DRDY BIT(0) 93#define MMA8452_INT_FF_MT BIT(2) 94#define MMA8452_INT_TRANS BIT(5) 95 96#define MMA8451_DEVICE_ID 0x1a 97#define MMA8452_DEVICE_ID 0x2a 98#define MMA8453_DEVICE_ID 0x3a 99#define MMA8652_DEVICE_ID 0x4a 100#define MMA8653_DEVICE_ID 0x5a 101#define FXLS8471_DEVICE_ID 0x6a 102 103#define MMA8452_AUTO_SUSPEND_DELAY_MS 2000 104 105struct mma8452_data { 106 struct i2c_client *client; 107 struct mutex lock; 108 struct iio_mount_matrix orientation; 109 u8 ctrl_reg1; 110 u8 data_cfg; 111 const struct mma_chip_info *chip_info; 112 int sleep_val; 113 struct regulator *vdd_reg; 114 struct regulator *vddio_reg; 115 116 /* Ensure correct alignment of time stamp when present */ 117 struct { 118 __be16 channels[3]; 119 aligned_s64 ts; 120 } buffer; 121}; 122 123 /** 124 * struct mma8452_event_regs - chip specific data related to events 125 * @ev_cfg: event config register address 126 * @ev_cfg_ele: latch bit in event config register 127 * @ev_cfg_chan_shift: number of the bit to enable events in X 128 * direction; in event config register 129 * @ev_src: event source register address 130 * @ev_ths: event threshold register address 131 * @ev_ths_mask: mask for the threshold value 132 * @ev_count: event count (period) register address 133 * 134 * Since not all chips supported by the driver support comparing high pass 135 * filtered data for events (interrupts), different interrupt sources are 136 * used for different chips and the relevant registers are included here. 137 */ 138struct mma8452_event_regs { 139 u8 ev_cfg; 140 u8 ev_cfg_ele; 141 u8 ev_cfg_chan_shift; 142 u8 ev_src; 143 u8 ev_ths; 144 u8 ev_ths_mask; 145 u8 ev_count; 146}; 147 148static const struct mma8452_event_regs ff_mt_ev_regs = { 149 .ev_cfg = MMA8452_FF_MT_CFG, 150 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE, 151 .ev_cfg_chan_shift = MMA8452_FF_MT_CHAN_SHIFT, 152 .ev_src = MMA8452_FF_MT_SRC, 153 .ev_ths = MMA8452_FF_MT_THS, 154 .ev_ths_mask = MMA8452_FF_MT_THS_MASK, 155 .ev_count = MMA8452_FF_MT_COUNT 156}; 157 158static const struct mma8452_event_regs trans_ev_regs = { 159 .ev_cfg = MMA8452_TRANSIENT_CFG, 160 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE, 161 .ev_cfg_chan_shift = MMA8452_TRANSIENT_CHAN_SHIFT, 162 .ev_src = MMA8452_TRANSIENT_SRC, 163 .ev_ths = MMA8452_TRANSIENT_THS, 164 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK, 165 .ev_count = MMA8452_TRANSIENT_COUNT, 166}; 167 168/** 169 * struct mma_chip_info - chip specific data 170 * @name: part number of device reported via 'name' attr 171 * @chip_id: WHO_AM_I register's value 172 * @channels: struct iio_chan_spec matching the device's 173 * capabilities 174 * @num_channels: number of channels 175 * @mma_scales: scale factors for converting register values 176 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers 177 * per mode: m/s^2 and micro m/s^2 178 * @all_events: all events supported by this chip 179 * @enabled_events: event flags enabled and handled by this driver 180 */ 181struct mma_chip_info { 182 const char *name; 183 u8 chip_id; 184 const struct iio_chan_spec *channels; 185 int num_channels; 186 const int mma_scales[3][2]; 187 int all_events; 188 int enabled_events; 189}; 190 191enum { 192 idx_x, 193 idx_y, 194 idx_z, 195 idx_ts, 196}; 197 198static int mma8452_drdy(struct mma8452_data *data) 199{ 200 int tries = 150; 201 202 while (tries-- > 0) { 203 int ret = i2c_smbus_read_byte_data(data->client, 204 MMA8452_STATUS); 205 if (ret < 0) 206 return ret; 207 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY) 208 return 0; 209 210 if (data->sleep_val <= 20) 211 usleep_range(data->sleep_val * 250, 212 data->sleep_val * 500); 213 else 214 msleep(20); 215 } 216 217 dev_err(&data->client->dev, "data not ready\n"); 218 219 return -EIO; 220} 221 222static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on) 223{ 224#ifdef CONFIG_PM 225 int ret; 226 227 if (on) 228 ret = pm_runtime_resume_and_get(&client->dev); 229 else 230 ret = pm_runtime_put_autosuspend(&client->dev); 231 if (ret < 0) { 232 dev_err(&client->dev, 233 "failed to change power state to %d\n", on); 234 235 return ret; 236 } 237#endif 238 239 return 0; 240} 241 242static int mma8452_read(struct mma8452_data *data, __be16 buf[3]) 243{ 244 int ret = mma8452_drdy(data); 245 246 if (ret < 0) 247 return ret; 248 249 ret = mma8452_set_runtime_pm_state(data->client, true); 250 if (ret) 251 return ret; 252 253 ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X, 254 3 * sizeof(__be16), (u8 *)buf); 255 256 ret = mma8452_set_runtime_pm_state(data->client, false); 257 258 return ret; 259} 260 261static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2], 262 int n) 263{ 264 size_t len = 0; 265 266 while (n-- > 0) 267 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ", 268 vals[n][0], vals[n][1]); 269 270 /* replace trailing space by newline */ 271 buf[len - 1] = '\n'; 272 273 return len; 274} 275 276static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n, 277 int val, int val2) 278{ 279 while (n-- > 0) 280 if (val == vals[n][0] && val2 == vals[n][1]) 281 return n; 282 283 return -EINVAL; 284} 285 286static unsigned int mma8452_get_odr_index(struct mma8452_data *data) 287{ 288 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >> 289 MMA8452_CTRL_DR_SHIFT; 290} 291 292static const int mma8452_samp_freq[8][2] = { 293 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000}, 294 {6, 250000}, {1, 560000} 295}; 296 297/* Datasheet table: step time "Relationship with the ODR" (sample frequency) */ 298static const unsigned int mma8452_time_step_us[4][8] = { 299 { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 }, /* normal */ 300 { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 }, /* l p l n */ 301 { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 }, /* high res*/ 302 { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */ 303}; 304 305/* Datasheet table "High-Pass Filter Cutoff Options" */ 306static const int mma8452_hp_filter_cutoff[4][8][4][2] = { 307 { /* normal */ 308 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */ 309 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */ 310 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */ 311 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */ 312 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */ 313 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */ 314 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */ 315 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */ 316 }, 317 { /* low noise low power */ 318 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 319 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 320 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, 321 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, 322 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, 323 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }, 324 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }, 325 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} } 326 }, 327 { /* high resolution */ 328 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 329 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 330 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 331 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 332 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 333 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 334 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 335 { {16, 0}, {8, 0}, {4, 0}, {2, 0} } 336 }, 337 { /* low power */ 338 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 339 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, 340 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, 341 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, 342 { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} }, 343 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }, 344 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }, 345 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} } 346 } 347}; 348 349/* Datasheet table "MODS Oversampling modes averaging values at each ODR" */ 350static const u16 mma8452_os_ratio[4][8] = { 351 /* 800 Hz, 400 Hz, ... , 1.56 Hz */ 352 { 2, 4, 4, 4, 4, 16, 32, 128 }, /* normal */ 353 { 2, 4, 4, 4, 4, 4, 8, 32 }, /* low power low noise */ 354 { 2, 4, 8, 16, 32, 128, 256, 1024 }, /* high resolution */ 355 { 2, 2, 2, 2, 2, 2, 4, 16 } /* low power */ 356}; 357 358static int mma8452_get_power_mode(struct mma8452_data *data) 359{ 360 int reg; 361 362 reg = i2c_smbus_read_byte_data(data->client, 363 MMA8452_CTRL_REG2); 364 if (reg < 0) 365 return reg; 366 367 return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >> 368 MMA8452_CTRL_REG2_MODS_SHIFT); 369} 370 371static ssize_t mma8452_show_samp_freq_avail(struct device *dev, 372 struct device_attribute *attr, 373 char *buf) 374{ 375 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq, 376 ARRAY_SIZE(mma8452_samp_freq)); 377} 378 379static ssize_t mma8452_show_scale_avail(struct device *dev, 380 struct device_attribute *attr, 381 char *buf) 382{ 383 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 384 struct mma8452_data *data = iio_priv(indio_dev); 385 386 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales, 387 ARRAY_SIZE(data->chip_info->mma_scales)); 388} 389 390static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev, 391 struct device_attribute *attr, 392 char *buf) 393{ 394 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 395 struct mma8452_data *data = iio_priv(indio_dev); 396 int i, j; 397 398 i = mma8452_get_odr_index(data); 399 j = mma8452_get_power_mode(data); 400 if (j < 0) 401 return j; 402 403 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i], 404 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0])); 405} 406 407static ssize_t mma8452_show_os_ratio_avail(struct device *dev, 408 struct device_attribute *attr, 409 char *buf) 410{ 411 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 412 struct mma8452_data *data = iio_priv(indio_dev); 413 int i = mma8452_get_odr_index(data); 414 int j; 415 u16 val = 0; 416 size_t len = 0; 417 418 for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) { 419 if (val == mma8452_os_ratio[j][i]) 420 continue; 421 422 val = mma8452_os_ratio[j][i]; 423 424 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val); 425 } 426 buf[len - 1] = '\n'; 427 428 return len; 429} 430 431static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail); 432static IIO_DEVICE_ATTR(in_accel_scale_available, 0444, 433 mma8452_show_scale_avail, NULL, 0); 434static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available, 435 0444, mma8452_show_hp_cutoff_avail, NULL, 0); 436static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, 0444, 437 mma8452_show_os_ratio_avail, NULL, 0); 438 439static int mma8452_get_samp_freq_index(struct mma8452_data *data, 440 int val, int val2) 441{ 442 return mma8452_get_int_plus_micros_index(mma8452_samp_freq, 443 ARRAY_SIZE(mma8452_samp_freq), 444 val, val2); 445} 446 447static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2) 448{ 449 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales, 450 ARRAY_SIZE(data->chip_info->mma_scales), val, val2); 451} 452 453static int mma8452_get_hp_filter_index(struct mma8452_data *data, 454 int val, int val2) 455{ 456 int i, j; 457 458 i = mma8452_get_odr_index(data); 459 j = mma8452_get_power_mode(data); 460 if (j < 0) 461 return j; 462 463 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i], 464 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2); 465} 466 467static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz) 468{ 469 int j, i, ret; 470 471 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF); 472 if (ret < 0) 473 return ret; 474 475 i = mma8452_get_odr_index(data); 476 j = mma8452_get_power_mode(data); 477 if (j < 0) 478 return j; 479 480 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK; 481 *hz = mma8452_hp_filter_cutoff[j][i][ret][0]; 482 *uHz = mma8452_hp_filter_cutoff[j][i][ret][1]; 483 484 return 0; 485} 486 487static int mma8452_read_raw(struct iio_dev *indio_dev, 488 struct iio_chan_spec const *chan, 489 int *val, int *val2, long mask) 490{ 491 struct mma8452_data *data = iio_priv(indio_dev); 492 __be16 buffer[3]; 493 int i, ret; 494 495 switch (mask) { 496 case IIO_CHAN_INFO_RAW: 497 if (!iio_device_claim_direct(indio_dev)) 498 return -EBUSY; 499 500 mutex_lock(&data->lock); 501 ret = mma8452_read(data, buffer); 502 mutex_unlock(&data->lock); 503 iio_device_release_direct(indio_dev); 504 if (ret < 0) 505 return ret; 506 507 *val = sign_extend32(be16_to_cpu( 508 buffer[chan->scan_index]) >> chan->scan_type.shift, 509 chan->scan_type.realbits - 1); 510 511 return IIO_VAL_INT; 512 case IIO_CHAN_INFO_SCALE: 513 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK; 514 *val = data->chip_info->mma_scales[i][0]; 515 *val2 = data->chip_info->mma_scales[i][1]; 516 517 return IIO_VAL_INT_PLUS_MICRO; 518 case IIO_CHAN_INFO_SAMP_FREQ: 519 i = mma8452_get_odr_index(data); 520 *val = mma8452_samp_freq[i][0]; 521 *val2 = mma8452_samp_freq[i][1]; 522 523 return IIO_VAL_INT_PLUS_MICRO; 524 case IIO_CHAN_INFO_CALIBBIAS: 525 ret = i2c_smbus_read_byte_data(data->client, 526 MMA8452_OFF_X + 527 chan->scan_index); 528 if (ret < 0) 529 return ret; 530 531 *val = sign_extend32(ret, 7); 532 533 return IIO_VAL_INT; 534 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 535 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) { 536 ret = mma8452_read_hp_filter(data, val, val2); 537 if (ret < 0) 538 return ret; 539 } else { 540 *val = 0; 541 *val2 = 0; 542 } 543 544 return IIO_VAL_INT_PLUS_MICRO; 545 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 546 ret = mma8452_get_power_mode(data); 547 if (ret < 0) 548 return ret; 549 550 i = mma8452_get_odr_index(data); 551 552 *val = mma8452_os_ratio[ret][i]; 553 return IIO_VAL_INT; 554 } 555 556 return -EINVAL; 557} 558 559static int mma8452_calculate_sleep(struct mma8452_data *data) 560{ 561 int ret, i = mma8452_get_odr_index(data); 562 563 if (mma8452_samp_freq[i][0] > 0) 564 ret = 1000 / mma8452_samp_freq[i][0]; 565 else 566 ret = 1000; 567 568 return ret == 0 ? 1 : ret; 569} 570 571static int mma8452_standby(struct mma8452_data *data) 572{ 573 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1, 574 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE); 575} 576 577static int mma8452_active(struct mma8452_data *data) 578{ 579 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1, 580 data->ctrl_reg1); 581} 582 583/* returns >0 if active, 0 if in standby and <0 on error */ 584static int mma8452_is_active(struct mma8452_data *data) 585{ 586 int reg; 587 588 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1); 589 if (reg < 0) 590 return reg; 591 592 return reg & MMA8452_CTRL_ACTIVE; 593} 594 595static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val) 596{ 597 int ret; 598 int is_active; 599 600 mutex_lock(&data->lock); 601 602 is_active = mma8452_is_active(data); 603 if (is_active < 0) { 604 ret = is_active; 605 goto fail; 606 } 607 608 /* config can only be changed when in standby */ 609 if (is_active > 0) { 610 ret = mma8452_standby(data); 611 if (ret < 0) 612 goto fail; 613 } 614 615 ret = i2c_smbus_write_byte_data(data->client, reg, val); 616 if (ret < 0) 617 goto fail; 618 619 if (is_active > 0) { 620 ret = mma8452_active(data); 621 if (ret < 0) 622 goto fail; 623 } 624 625 ret = 0; 626fail: 627 mutex_unlock(&data->lock); 628 629 return ret; 630} 631 632static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode) 633{ 634 int reg; 635 636 reg = i2c_smbus_read_byte_data(data->client, 637 MMA8452_CTRL_REG2); 638 if (reg < 0) 639 return reg; 640 641 reg &= ~MMA8452_CTRL_REG2_MODS_MASK; 642 reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT; 643 644 return mma8452_change_config(data, MMA8452_CTRL_REG2, reg); 645} 646 647/* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */ 648static int mma8452_freefall_mode_enabled(struct mma8452_data *data) 649{ 650 int val; 651 652 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG); 653 if (val < 0) 654 return val; 655 656 return !(val & MMA8452_FF_MT_CFG_OAE); 657} 658 659static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state) 660{ 661 int val; 662 663 if ((state && mma8452_freefall_mode_enabled(data)) || 664 (!state && !(mma8452_freefall_mode_enabled(data)))) 665 return 0; 666 667 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG); 668 if (val < 0) 669 return val; 670 671 if (state) { 672 val |= BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT); 673 val |= BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT); 674 val |= BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT); 675 val &= ~MMA8452_FF_MT_CFG_OAE; 676 } else { 677 val &= ~BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT); 678 val &= ~BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT); 679 val &= ~BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT); 680 val |= MMA8452_FF_MT_CFG_OAE; 681 } 682 683 return mma8452_change_config(data, MMA8452_FF_MT_CFG, val); 684} 685 686static int mma8452_set_hp_filter_frequency(struct mma8452_data *data, 687 int val, int val2) 688{ 689 int i, reg; 690 691 i = mma8452_get_hp_filter_index(data, val, val2); 692 if (i < 0) 693 return i; 694 695 reg = i2c_smbus_read_byte_data(data->client, 696 MMA8452_HP_FILTER_CUTOFF); 697 if (reg < 0) 698 return reg; 699 700 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK; 701 reg |= i; 702 703 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg); 704} 705 706static int __mma8452_write_raw(struct iio_dev *indio_dev, 707 struct iio_chan_spec const *chan, 708 int val, int val2, long mask) 709{ 710 struct mma8452_data *data = iio_priv(indio_dev); 711 int i, j, ret; 712 713 switch (mask) { 714 case IIO_CHAN_INFO_SAMP_FREQ: 715 i = mma8452_get_samp_freq_index(data, val, val2); 716 if (i < 0) 717 return i; 718 719 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK; 720 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT; 721 722 data->sleep_val = mma8452_calculate_sleep(data); 723 724 return mma8452_change_config(data, MMA8452_CTRL_REG1, 725 data->ctrl_reg1); 726 727 case IIO_CHAN_INFO_SCALE: 728 i = mma8452_get_scale_index(data, val, val2); 729 if (i < 0) 730 return i; 731 732 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK; 733 data->data_cfg |= i; 734 735 return mma8452_change_config(data, MMA8452_DATA_CFG, 736 data->data_cfg); 737 738 case IIO_CHAN_INFO_CALIBBIAS: 739 if (val < -128 || val > 127) 740 return -EINVAL; 741 742 return mma8452_change_config(data, 743 MMA8452_OFF_X + chan->scan_index, 744 val); 745 746 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 747 if (val == 0 && val2 == 0) { 748 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK; 749 } else { 750 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK; 751 ret = mma8452_set_hp_filter_frequency(data, val, val2); 752 if (ret < 0) 753 return ret; 754 } 755 756 return mma8452_change_config(data, MMA8452_DATA_CFG, 757 data->data_cfg); 758 759 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 760 j = mma8452_get_odr_index(data); 761 762 for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) { 763 if (mma8452_os_ratio[i][j] == val) 764 return mma8452_set_power_mode(data, i); 765 } 766 767 return -EINVAL; 768 769 default: 770 return -EINVAL; 771 } 772} 773 774static int mma8452_write_raw(struct iio_dev *indio_dev, 775 struct iio_chan_spec const *chan, 776 int val, int val2, long mask) 777{ 778 int ret; 779 780 if (!iio_device_claim_direct(indio_dev)) 781 return -EBUSY; 782 783 ret = __mma8452_write_raw(indio_dev, chan, val, val2, mask); 784 iio_device_release_direct(indio_dev); 785 return ret; 786} 787 788static int mma8452_get_event_regs(struct mma8452_data *data, 789 const struct iio_chan_spec *chan, enum iio_event_direction dir, 790 const struct mma8452_event_regs **ev_reg) 791{ 792 if (!chan) 793 return -EINVAL; 794 795 switch (chan->type) { 796 case IIO_ACCEL: 797 switch (dir) { 798 case IIO_EV_DIR_RISING: 799 if ((data->chip_info->all_events 800 & MMA8452_INT_TRANS) && 801 (data->chip_info->enabled_events 802 & MMA8452_INT_TRANS)) 803 *ev_reg = &trans_ev_regs; 804 else 805 *ev_reg = &ff_mt_ev_regs; 806 return 0; 807 case IIO_EV_DIR_FALLING: 808 *ev_reg = &ff_mt_ev_regs; 809 return 0; 810 default: 811 return -EINVAL; 812 } 813 default: 814 return -EINVAL; 815 } 816} 817 818static int mma8452_read_event_value(struct iio_dev *indio_dev, 819 const struct iio_chan_spec *chan, 820 enum iio_event_type type, 821 enum iio_event_direction dir, 822 enum iio_event_info info, 823 int *val, int *val2) 824{ 825 struct mma8452_data *data = iio_priv(indio_dev); 826 int ret, us, power_mode; 827 const struct mma8452_event_regs *ev_regs; 828 829 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 830 if (ret) 831 return ret; 832 833 switch (info) { 834 case IIO_EV_INFO_VALUE: 835 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_ths); 836 if (ret < 0) 837 return ret; 838 839 *val = ret & ev_regs->ev_ths_mask; 840 841 return IIO_VAL_INT; 842 843 case IIO_EV_INFO_PERIOD: 844 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_count); 845 if (ret < 0) 846 return ret; 847 848 power_mode = mma8452_get_power_mode(data); 849 if (power_mode < 0) 850 return power_mode; 851 852 us = ret * mma8452_time_step_us[power_mode][ 853 mma8452_get_odr_index(data)]; 854 *val = us / USEC_PER_SEC; 855 *val2 = us % USEC_PER_SEC; 856 857 return IIO_VAL_INT_PLUS_MICRO; 858 859 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB: 860 ret = i2c_smbus_read_byte_data(data->client, 861 MMA8452_TRANSIENT_CFG); 862 if (ret < 0) 863 return ret; 864 865 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) { 866 *val = 0; 867 *val2 = 0; 868 } else { 869 ret = mma8452_read_hp_filter(data, val, val2); 870 if (ret < 0) 871 return ret; 872 } 873 874 return IIO_VAL_INT_PLUS_MICRO; 875 876 default: 877 return -EINVAL; 878 } 879} 880 881static int mma8452_write_event_value(struct iio_dev *indio_dev, 882 const struct iio_chan_spec *chan, 883 enum iio_event_type type, 884 enum iio_event_direction dir, 885 enum iio_event_info info, 886 int val, int val2) 887{ 888 struct mma8452_data *data = iio_priv(indio_dev); 889 int ret, reg, steps; 890 const struct mma8452_event_regs *ev_regs; 891 892 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 893 if (ret) 894 return ret; 895 896 switch (info) { 897 case IIO_EV_INFO_VALUE: 898 if (val < 0 || val > ev_regs->ev_ths_mask) 899 return -EINVAL; 900 901 return mma8452_change_config(data, ev_regs->ev_ths, val); 902 903 case IIO_EV_INFO_PERIOD: 904 ret = mma8452_get_power_mode(data); 905 if (ret < 0) 906 return ret; 907 908 steps = (val * USEC_PER_SEC + val2) / 909 mma8452_time_step_us[ret][ 910 mma8452_get_odr_index(data)]; 911 912 if (steps < 0 || steps > 0xff) 913 return -EINVAL; 914 915 return mma8452_change_config(data, ev_regs->ev_count, steps); 916 917 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB: 918 reg = i2c_smbus_read_byte_data(data->client, 919 MMA8452_TRANSIENT_CFG); 920 if (reg < 0) 921 return reg; 922 923 if (val == 0 && val2 == 0) { 924 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP; 925 } else { 926 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP; 927 ret = mma8452_set_hp_filter_frequency(data, val, val2); 928 if (ret < 0) 929 return ret; 930 } 931 932 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg); 933 934 default: 935 return -EINVAL; 936 } 937} 938 939static int mma8452_read_event_config(struct iio_dev *indio_dev, 940 const struct iio_chan_spec *chan, 941 enum iio_event_type type, 942 enum iio_event_direction dir) 943{ 944 struct mma8452_data *data = iio_priv(indio_dev); 945 int ret; 946 const struct mma8452_event_regs *ev_regs; 947 948 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 949 if (ret) 950 return ret; 951 952 switch (dir) { 953 case IIO_EV_DIR_FALLING: 954 return mma8452_freefall_mode_enabled(data); 955 case IIO_EV_DIR_RISING: 956 ret = i2c_smbus_read_byte_data(data->client, 957 ev_regs->ev_cfg); 958 if (ret < 0) 959 return ret; 960 961 return !!(ret & BIT(chan->scan_index + 962 ev_regs->ev_cfg_chan_shift)); 963 default: 964 return -EINVAL; 965 } 966} 967 968static int mma8452_write_event_config(struct iio_dev *indio_dev, 969 const struct iio_chan_spec *chan, 970 enum iio_event_type type, 971 enum iio_event_direction dir, 972 bool state) 973{ 974 struct mma8452_data *data = iio_priv(indio_dev); 975 int val, ret; 976 const struct mma8452_event_regs *ev_regs; 977 978 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 979 if (ret) 980 return ret; 981 982 ret = mma8452_set_runtime_pm_state(data->client, state); 983 if (ret) 984 return ret; 985 986 switch (dir) { 987 case IIO_EV_DIR_FALLING: 988 return mma8452_set_freefall_mode(data, state); 989 case IIO_EV_DIR_RISING: 990 val = i2c_smbus_read_byte_data(data->client, ev_regs->ev_cfg); 991 if (val < 0) 992 return val; 993 994 if (state) { 995 if (mma8452_freefall_mode_enabled(data)) { 996 val &= ~BIT(idx_x + ev_regs->ev_cfg_chan_shift); 997 val &= ~BIT(idx_y + ev_regs->ev_cfg_chan_shift); 998 val &= ~BIT(idx_z + ev_regs->ev_cfg_chan_shift); 999 val |= MMA8452_FF_MT_CFG_OAE; 1000 } 1001 val |= BIT(chan->scan_index + 1002 ev_regs->ev_cfg_chan_shift); 1003 } else { 1004 if (mma8452_freefall_mode_enabled(data)) 1005 return 0; 1006 1007 val &= ~BIT(chan->scan_index + 1008 ev_regs->ev_cfg_chan_shift); 1009 } 1010 1011 val |= ev_regs->ev_cfg_ele; 1012 1013 return mma8452_change_config(data, ev_regs->ev_cfg, val); 1014 default: 1015 return -EINVAL; 1016 } 1017} 1018 1019static void mma8452_transient_interrupt(struct iio_dev *indio_dev) 1020{ 1021 struct mma8452_data *data = iio_priv(indio_dev); 1022 s64 ts = iio_get_time_ns(indio_dev); 1023 int src; 1024 1025 src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC); 1026 if (src < 0) 1027 return; 1028 1029 if (src & MMA8452_TRANSIENT_SRC_XTRANSE) 1030 iio_push_event(indio_dev, 1031 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1032 IIO_EV_TYPE_MAG, 1033 IIO_EV_DIR_RISING), 1034 ts); 1035 1036 if (src & MMA8452_TRANSIENT_SRC_YTRANSE) 1037 iio_push_event(indio_dev, 1038 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y, 1039 IIO_EV_TYPE_MAG, 1040 IIO_EV_DIR_RISING), 1041 ts); 1042 1043 if (src & MMA8452_TRANSIENT_SRC_ZTRANSE) 1044 iio_push_event(indio_dev, 1045 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z, 1046 IIO_EV_TYPE_MAG, 1047 IIO_EV_DIR_RISING), 1048 ts); 1049} 1050 1051static irqreturn_t mma8452_interrupt(int irq, void *p) 1052{ 1053 struct iio_dev *indio_dev = p; 1054 struct mma8452_data *data = iio_priv(indio_dev); 1055 irqreturn_t ret = IRQ_NONE; 1056 int src; 1057 1058 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC); 1059 if (src < 0) 1060 return IRQ_NONE; 1061 1062 if (!(src & (data->chip_info->enabled_events | MMA8452_INT_DRDY))) 1063 return IRQ_NONE; 1064 1065 if (src & MMA8452_INT_DRDY) { 1066 iio_trigger_poll_nested(indio_dev->trig); 1067 ret = IRQ_HANDLED; 1068 } 1069 1070 if (src & MMA8452_INT_FF_MT) { 1071 if (mma8452_freefall_mode_enabled(data)) { 1072 s64 ts = iio_get_time_ns(indio_dev); 1073 1074 iio_push_event(indio_dev, 1075 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, 1076 IIO_MOD_X_AND_Y_AND_Z, 1077 IIO_EV_TYPE_MAG, 1078 IIO_EV_DIR_FALLING), 1079 ts); 1080 } 1081 ret = IRQ_HANDLED; 1082 } 1083 1084 if (src & MMA8452_INT_TRANS) { 1085 mma8452_transient_interrupt(indio_dev); 1086 ret = IRQ_HANDLED; 1087 } 1088 1089 return ret; 1090} 1091 1092static irqreturn_t mma8452_trigger_handler(int irq, void *p) 1093{ 1094 struct iio_poll_func *pf = p; 1095 struct iio_dev *indio_dev = pf->indio_dev; 1096 struct mma8452_data *data = iio_priv(indio_dev); 1097 int ret; 1098 1099 ret = mma8452_read(data, data->buffer.channels); 1100 if (ret < 0) 1101 goto done; 1102 1103 iio_push_to_buffers_with_ts(indio_dev, &data->buffer, 1104 sizeof(data->buffer), 1105 iio_get_time_ns(indio_dev)); 1106 1107done: 1108 iio_trigger_notify_done(indio_dev->trig); 1109 1110 return IRQ_HANDLED; 1111} 1112 1113static int mma8452_reg_access_dbg(struct iio_dev *indio_dev, 1114 unsigned int reg, unsigned int writeval, 1115 unsigned int *readval) 1116{ 1117 int ret; 1118 struct mma8452_data *data = iio_priv(indio_dev); 1119 1120 if (reg > MMA8452_MAX_REG) 1121 return -EINVAL; 1122 1123 if (!readval) 1124 return mma8452_change_config(data, reg, writeval); 1125 1126 ret = i2c_smbus_read_byte_data(data->client, reg); 1127 if (ret < 0) 1128 return ret; 1129 1130 *readval = ret; 1131 1132 return 0; 1133} 1134 1135static const struct iio_event_spec mma8452_freefall_event[] = { 1136 { 1137 .type = IIO_EV_TYPE_MAG, 1138 .dir = IIO_EV_DIR_FALLING, 1139 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1140 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1141 BIT(IIO_EV_INFO_PERIOD) | 1142 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB) 1143 }, 1144}; 1145 1146static const struct iio_event_spec mma8652_freefall_event[] = { 1147 { 1148 .type = IIO_EV_TYPE_MAG, 1149 .dir = IIO_EV_DIR_FALLING, 1150 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1151 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1152 BIT(IIO_EV_INFO_PERIOD) 1153 }, 1154}; 1155 1156static const struct iio_event_spec mma8452_transient_event[] = { 1157 { 1158 .type = IIO_EV_TYPE_MAG, 1159 .dir = IIO_EV_DIR_RISING, 1160 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1161 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1162 BIT(IIO_EV_INFO_PERIOD) | 1163 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB) 1164 }, 1165}; 1166 1167static const struct iio_event_spec mma8452_motion_event[] = { 1168 { 1169 .type = IIO_EV_TYPE_MAG, 1170 .dir = IIO_EV_DIR_RISING, 1171 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1172 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1173 BIT(IIO_EV_INFO_PERIOD) 1174 }, 1175}; 1176 1177/* 1178 * Threshold is configured in fixed 8G/127 steps regardless of 1179 * currently selected scale for measurement. 1180 */ 1181static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742"); 1182 1183static struct attribute *mma8452_event_attributes[] = { 1184 &iio_const_attr_accel_transient_scale.dev_attr.attr, 1185 NULL, 1186}; 1187 1188static const struct attribute_group mma8452_event_attribute_group = { 1189 .attrs = mma8452_event_attributes, 1190}; 1191 1192static const struct iio_mount_matrix * 1193mma8452_get_mount_matrix(const struct iio_dev *indio_dev, 1194 const struct iio_chan_spec *chan) 1195{ 1196 struct mma8452_data *data = iio_priv(indio_dev); 1197 1198 return &data->orientation; 1199} 1200 1201static const struct iio_chan_spec_ext_info mma8452_ext_info[] = { 1202 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, mma8452_get_mount_matrix), 1203 { } 1204}; 1205 1206#define MMA8452_FREEFALL_CHANNEL(modifier) { \ 1207 .type = IIO_ACCEL, \ 1208 .modified = 1, \ 1209 .channel2 = modifier, \ 1210 .scan_index = -1, \ 1211 .event_spec = mma8452_freefall_event, \ 1212 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \ 1213} 1214 1215#define MMA8652_FREEFALL_CHANNEL(modifier) { \ 1216 .type = IIO_ACCEL, \ 1217 .modified = 1, \ 1218 .channel2 = modifier, \ 1219 .scan_index = -1, \ 1220 .event_spec = mma8652_freefall_event, \ 1221 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \ 1222} 1223 1224#define MMA8452_CHANNEL(axis, idx, bits) { \ 1225 .type = IIO_ACCEL, \ 1226 .modified = 1, \ 1227 .channel2 = IIO_MOD_##axis, \ 1228 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1229 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 1230 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 1231 BIT(IIO_CHAN_INFO_SCALE) | \ 1232 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \ 1233 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 1234 .scan_index = idx, \ 1235 .scan_type = { \ 1236 .sign = 's', \ 1237 .realbits = (bits), \ 1238 .storagebits = 16, \ 1239 .shift = 16 - (bits), \ 1240 .endianness = IIO_BE, \ 1241 }, \ 1242 .event_spec = mma8452_transient_event, \ 1243 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \ 1244 .ext_info = mma8452_ext_info, \ 1245} 1246 1247#define MMA8652_CHANNEL(axis, idx, bits) { \ 1248 .type = IIO_ACCEL, \ 1249 .modified = 1, \ 1250 .channel2 = IIO_MOD_##axis, \ 1251 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1252 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 1253 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 1254 BIT(IIO_CHAN_INFO_SCALE) | \ 1255 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 1256 .scan_index = idx, \ 1257 .scan_type = { \ 1258 .sign = 's', \ 1259 .realbits = (bits), \ 1260 .storagebits = 16, \ 1261 .shift = 16 - (bits), \ 1262 .endianness = IIO_BE, \ 1263 }, \ 1264 .event_spec = mma8452_motion_event, \ 1265 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \ 1266 .ext_info = mma8452_ext_info, \ 1267} 1268 1269static const struct iio_chan_spec mma8451_channels[] = { 1270 MMA8452_CHANNEL(X, idx_x, 14), 1271 MMA8452_CHANNEL(Y, idx_y, 14), 1272 MMA8452_CHANNEL(Z, idx_z, 14), 1273 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1274 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1275}; 1276 1277static const struct iio_chan_spec mma8452_channels[] = { 1278 MMA8452_CHANNEL(X, idx_x, 12), 1279 MMA8452_CHANNEL(Y, idx_y, 12), 1280 MMA8452_CHANNEL(Z, idx_z, 12), 1281 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1282 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1283}; 1284 1285static const struct iio_chan_spec mma8453_channels[] = { 1286 MMA8452_CHANNEL(X, idx_x, 10), 1287 MMA8452_CHANNEL(Y, idx_y, 10), 1288 MMA8452_CHANNEL(Z, idx_z, 10), 1289 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1290 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1291}; 1292 1293static const struct iio_chan_spec mma8652_channels[] = { 1294 MMA8652_CHANNEL(X, idx_x, 12), 1295 MMA8652_CHANNEL(Y, idx_y, 12), 1296 MMA8652_CHANNEL(Z, idx_z, 12), 1297 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1298 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1299}; 1300 1301static const struct iio_chan_spec mma8653_channels[] = { 1302 MMA8652_CHANNEL(X, idx_x, 10), 1303 MMA8652_CHANNEL(Y, idx_y, 10), 1304 MMA8652_CHANNEL(Z, idx_z, 10), 1305 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1306 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1307}; 1308 1309enum { 1310 mma8451, 1311 mma8452, 1312 mma8453, 1313 mma8652, 1314 mma8653, 1315 fxls8471, 1316}; 1317 1318static const struct mma_chip_info mma_chip_info_table[] = { 1319 [mma8451] = { 1320 .name = "mma8451", 1321 .chip_id = MMA8451_DEVICE_ID, 1322 .channels = mma8451_channels, 1323 .num_channels = ARRAY_SIZE(mma8451_channels), 1324 /* 1325 * Hardware has fullscale of -2G, -4G, -8G corresponding to 1326 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10 1327 * bit. 1328 * The userspace interface uses m/s^2 and we declare micro units 1329 * So scale factor for 12 bit here is given by: 1330 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665 1331 */ 1332 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} }, 1333 /* 1334 * Although we enable the interrupt sources once and for 1335 * all here the event detection itself is not enabled until 1336 * userspace asks for it by mma8452_write_event_config() 1337 */ 1338 .all_events = MMA8452_INT_DRDY | 1339 MMA8452_INT_TRANS | 1340 MMA8452_INT_FF_MT, 1341 .enabled_events = MMA8452_INT_TRANS | 1342 MMA8452_INT_FF_MT, 1343 }, 1344 [mma8452] = { 1345 .name = "mma8452", 1346 .chip_id = MMA8452_DEVICE_ID, 1347 .channels = mma8452_channels, 1348 .num_channels = ARRAY_SIZE(mma8452_channels), 1349 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} }, 1350 /* 1351 * Although we enable the interrupt sources once and for 1352 * all here the event detection itself is not enabled until 1353 * userspace asks for it by mma8452_write_event_config() 1354 */ 1355 .all_events = MMA8452_INT_DRDY | 1356 MMA8452_INT_TRANS | 1357 MMA8452_INT_FF_MT, 1358 .enabled_events = MMA8452_INT_TRANS | 1359 MMA8452_INT_FF_MT, 1360 }, 1361 [mma8453] = { 1362 .name = "mma8453", 1363 .chip_id = MMA8453_DEVICE_ID, 1364 .channels = mma8453_channels, 1365 .num_channels = ARRAY_SIZE(mma8453_channels), 1366 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} }, 1367 /* 1368 * Although we enable the interrupt sources once and for 1369 * all here the event detection itself is not enabled until 1370 * userspace asks for it by mma8452_write_event_config() 1371 */ 1372 .all_events = MMA8452_INT_DRDY | 1373 MMA8452_INT_TRANS | 1374 MMA8452_INT_FF_MT, 1375 .enabled_events = MMA8452_INT_TRANS | 1376 MMA8452_INT_FF_MT, 1377 }, 1378 [mma8652] = { 1379 .name = "mma8652", 1380 .chip_id = MMA8652_DEVICE_ID, 1381 .channels = mma8652_channels, 1382 .num_channels = ARRAY_SIZE(mma8652_channels), 1383 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} }, 1384 .all_events = MMA8452_INT_DRDY | 1385 MMA8452_INT_FF_MT, 1386 .enabled_events = MMA8452_INT_FF_MT, 1387 }, 1388 [mma8653] = { 1389 .name = "mma8653", 1390 .chip_id = MMA8653_DEVICE_ID, 1391 .channels = mma8653_channels, 1392 .num_channels = ARRAY_SIZE(mma8653_channels), 1393 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} }, 1394 /* 1395 * Although we enable the interrupt sources once and for 1396 * all here the event detection itself is not enabled until 1397 * userspace asks for it by mma8452_write_event_config() 1398 */ 1399 .all_events = MMA8452_INT_DRDY | 1400 MMA8452_INT_FF_MT, 1401 .enabled_events = MMA8452_INT_FF_MT, 1402 }, 1403 [fxls8471] = { 1404 .name = "fxls8471", 1405 .chip_id = FXLS8471_DEVICE_ID, 1406 .channels = mma8451_channels, 1407 .num_channels = ARRAY_SIZE(mma8451_channels), 1408 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} }, 1409 /* 1410 * Although we enable the interrupt sources once and for 1411 * all here the event detection itself is not enabled until 1412 * userspace asks for it by mma8452_write_event_config() 1413 */ 1414 .all_events = MMA8452_INT_DRDY | 1415 MMA8452_INT_TRANS | 1416 MMA8452_INT_FF_MT, 1417 .enabled_events = MMA8452_INT_TRANS | 1418 MMA8452_INT_FF_MT, 1419 }, 1420}; 1421 1422static struct attribute *mma8452_attributes[] = { 1423 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 1424 &iio_dev_attr_in_accel_scale_available.dev_attr.attr, 1425 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr, 1426 &iio_dev_attr_in_accel_oversampling_ratio_available.dev_attr.attr, 1427 NULL 1428}; 1429 1430static const struct attribute_group mma8452_group = { 1431 .attrs = mma8452_attributes, 1432}; 1433 1434static const struct iio_info mma8452_info = { 1435 .attrs = &mma8452_group, 1436 .read_raw = &mma8452_read_raw, 1437 .write_raw = &mma8452_write_raw, 1438 .event_attrs = &mma8452_event_attribute_group, 1439 .read_event_value = &mma8452_read_event_value, 1440 .write_event_value = &mma8452_write_event_value, 1441 .read_event_config = &mma8452_read_event_config, 1442 .write_event_config = &mma8452_write_event_config, 1443 .debugfs_reg_access = &mma8452_reg_access_dbg, 1444}; 1445 1446static const unsigned long mma8452_scan_masks[] = {0x7, 0}; 1447 1448static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig, 1449 bool state) 1450{ 1451 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 1452 struct mma8452_data *data = iio_priv(indio_dev); 1453 int reg, ret; 1454 1455 ret = mma8452_set_runtime_pm_state(data->client, state); 1456 if (ret) 1457 return ret; 1458 1459 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4); 1460 if (reg < 0) 1461 return reg; 1462 1463 if (state) 1464 reg |= MMA8452_INT_DRDY; 1465 else 1466 reg &= ~MMA8452_INT_DRDY; 1467 1468 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg); 1469} 1470 1471static const struct iio_trigger_ops mma8452_trigger_ops = { 1472 .set_trigger_state = mma8452_data_rdy_trigger_set_state, 1473 .validate_device = iio_trigger_validate_own_device, 1474}; 1475 1476static int mma8452_trigger_setup(struct iio_dev *indio_dev) 1477{ 1478 struct mma8452_data *data = iio_priv(indio_dev); 1479 struct iio_trigger *trig; 1480 int ret; 1481 1482 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d", 1483 indio_dev->name, 1484 iio_device_id(indio_dev)); 1485 if (!trig) 1486 return -ENOMEM; 1487 1488 trig->ops = &mma8452_trigger_ops; 1489 iio_trigger_set_drvdata(trig, indio_dev); 1490 1491 ret = iio_trigger_register(trig); 1492 if (ret) 1493 return ret; 1494 1495 indio_dev->trig = iio_trigger_get(trig); 1496 1497 return 0; 1498} 1499 1500static void mma8452_trigger_cleanup(struct iio_dev *indio_dev) 1501{ 1502 if (indio_dev->trig) 1503 iio_trigger_unregister(indio_dev->trig); 1504} 1505 1506static int mma8452_reset(struct i2c_client *client) 1507{ 1508 int i; 1509 int ret; 1510 1511 /* 1512 * Find on fxls8471, after config reset bit, it reset immediately, 1513 * and will not give ACK, so here do not check the return value. 1514 * The following code will read the reset register, and check whether 1515 * this reset works. 1516 */ 1517 i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2, 1518 MMA8452_CTRL_REG2_RST); 1519 1520 for (i = 0; i < 10; i++) { 1521 usleep_range(100, 200); 1522 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2); 1523 if (ret == -EIO) 1524 continue; /* I2C comm reset */ 1525 if (ret < 0) 1526 return ret; 1527 if (!(ret & MMA8452_CTRL_REG2_RST)) 1528 return 0; 1529 } 1530 1531 return -ETIMEDOUT; 1532} 1533 1534static const struct of_device_id mma8452_dt_ids[] = { 1535 { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] }, 1536 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] }, 1537 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] }, 1538 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] }, 1539 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] }, 1540 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] }, 1541 { } 1542}; 1543MODULE_DEVICE_TABLE(of, mma8452_dt_ids); 1544 1545static int mma8452_probe(struct i2c_client *client) 1546{ 1547 struct mma8452_data *data; 1548 struct iio_dev *indio_dev; 1549 int ret; 1550 1551 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 1552 if (!indio_dev) 1553 return -ENOMEM; 1554 1555 data = iio_priv(indio_dev); 1556 data->client = client; 1557 mutex_init(&data->lock); 1558 1559 data->chip_info = i2c_get_match_data(client); 1560 if (!data->chip_info) 1561 return dev_err_probe(&client->dev, -ENODEV, 1562 "unknown device model\n"); 1563 1564 ret = iio_read_mount_matrix(&client->dev, &data->orientation); 1565 if (ret) 1566 return ret; 1567 1568 data->vdd_reg = devm_regulator_get(&client->dev, "vdd"); 1569 if (IS_ERR(data->vdd_reg)) 1570 return dev_err_probe(&client->dev, PTR_ERR(data->vdd_reg), 1571 "failed to get VDD regulator!\n"); 1572 1573 data->vddio_reg = devm_regulator_get(&client->dev, "vddio"); 1574 if (IS_ERR(data->vddio_reg)) 1575 return dev_err_probe(&client->dev, PTR_ERR(data->vddio_reg), 1576 "failed to get VDDIO regulator!\n"); 1577 1578 ret = regulator_enable(data->vdd_reg); 1579 if (ret) { 1580 dev_err(&client->dev, "failed to enable VDD regulator!\n"); 1581 return ret; 1582 } 1583 1584 ret = regulator_enable(data->vddio_reg); 1585 if (ret) { 1586 dev_err(&client->dev, "failed to enable VDDIO regulator!\n"); 1587 goto disable_regulator_vdd; 1588 } 1589 1590 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I); 1591 if (ret < 0) 1592 goto disable_regulators; 1593 1594 switch (ret) { 1595 case MMA8451_DEVICE_ID: 1596 case MMA8452_DEVICE_ID: 1597 case MMA8453_DEVICE_ID: 1598 case MMA8652_DEVICE_ID: 1599 case MMA8653_DEVICE_ID: 1600 case FXLS8471_DEVICE_ID: 1601 if (ret == data->chip_info->chip_id) 1602 break; 1603 fallthrough; 1604 default: 1605 ret = -ENODEV; 1606 goto disable_regulators; 1607 } 1608 1609 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n", 1610 data->chip_info->name, data->chip_info->chip_id); 1611 1612 i2c_set_clientdata(client, indio_dev); 1613 indio_dev->info = &mma8452_info; 1614 indio_dev->name = data->chip_info->name; 1615 indio_dev->modes = INDIO_DIRECT_MODE; 1616 indio_dev->channels = data->chip_info->channels; 1617 indio_dev->num_channels = data->chip_info->num_channels; 1618 indio_dev->available_scan_masks = mma8452_scan_masks; 1619 1620 ret = mma8452_reset(client); 1621 if (ret < 0) 1622 goto disable_regulators; 1623 1624 data->data_cfg = MMA8452_DATA_CFG_FS_2G; 1625 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG, 1626 data->data_cfg); 1627 if (ret < 0) 1628 goto disable_regulators; 1629 1630 /* 1631 * By default set transient threshold to max to avoid events if 1632 * enabling without configuring threshold. 1633 */ 1634 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS, 1635 MMA8452_TRANSIENT_THS_MASK); 1636 if (ret < 0) 1637 goto disable_regulators; 1638 1639 if (client->irq) { 1640 int irq2; 1641 1642 irq2 = fwnode_irq_get_byname(dev_fwnode(&client->dev), "INT2"); 1643 1644 if (irq2 == client->irq) { 1645 dev_dbg(&client->dev, "using interrupt line INT2\n"); 1646 } else { 1647 ret = i2c_smbus_write_byte_data(client, 1648 MMA8452_CTRL_REG5, 1649 data->chip_info->all_events); 1650 if (ret < 0) 1651 goto disable_regulators; 1652 1653 dev_dbg(&client->dev, "using interrupt line INT1\n"); 1654 } 1655 1656 ret = i2c_smbus_write_byte_data(client, 1657 MMA8452_CTRL_REG4, 1658 data->chip_info->enabled_events); 1659 if (ret < 0) 1660 goto disable_regulators; 1661 1662 ret = mma8452_trigger_setup(indio_dev); 1663 if (ret < 0) 1664 goto disable_regulators; 1665 } 1666 1667 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE | 1668 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT); 1669 1670 data->sleep_val = mma8452_calculate_sleep(data); 1671 1672 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1, 1673 data->ctrl_reg1); 1674 if (ret < 0) 1675 goto trigger_cleanup; 1676 1677 ret = iio_triggered_buffer_setup(indio_dev, NULL, 1678 mma8452_trigger_handler, NULL); 1679 if (ret < 0) 1680 goto trigger_cleanup; 1681 1682 if (client->irq) { 1683 ret = devm_request_threaded_irq(&client->dev, 1684 client->irq, 1685 NULL, mma8452_interrupt, 1686 IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1687 client->name, indio_dev); 1688 if (ret) 1689 goto buffer_cleanup; 1690 } 1691 1692 ret = pm_runtime_set_active(&client->dev); 1693 if (ret < 0) 1694 goto buffer_cleanup; 1695 1696 pm_runtime_enable(&client->dev); 1697 pm_runtime_set_autosuspend_delay(&client->dev, 1698 MMA8452_AUTO_SUSPEND_DELAY_MS); 1699 pm_runtime_use_autosuspend(&client->dev); 1700 1701 ret = iio_device_register(indio_dev); 1702 if (ret < 0) 1703 goto buffer_cleanup; 1704 1705 ret = mma8452_set_freefall_mode(data, false); 1706 if (ret < 0) 1707 goto unregister_device; 1708 1709 return 0; 1710 1711unregister_device: 1712 iio_device_unregister(indio_dev); 1713 1714buffer_cleanup: 1715 iio_triggered_buffer_cleanup(indio_dev); 1716 1717trigger_cleanup: 1718 mma8452_trigger_cleanup(indio_dev); 1719 1720disable_regulators: 1721 regulator_disable(data->vddio_reg); 1722 1723disable_regulator_vdd: 1724 regulator_disable(data->vdd_reg); 1725 1726 return ret; 1727} 1728 1729static void mma8452_remove(struct i2c_client *client) 1730{ 1731 struct iio_dev *indio_dev = i2c_get_clientdata(client); 1732 struct mma8452_data *data = iio_priv(indio_dev); 1733 1734 iio_device_unregister(indio_dev); 1735 1736 pm_runtime_disable(&client->dev); 1737 pm_runtime_set_suspended(&client->dev); 1738 1739 iio_triggered_buffer_cleanup(indio_dev); 1740 mma8452_trigger_cleanup(indio_dev); 1741 mma8452_standby(iio_priv(indio_dev)); 1742 1743 regulator_disable(data->vddio_reg); 1744 regulator_disable(data->vdd_reg); 1745} 1746 1747#ifdef CONFIG_PM 1748static int mma8452_runtime_suspend(struct device *dev) 1749{ 1750 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1751 struct mma8452_data *data = iio_priv(indio_dev); 1752 int ret; 1753 1754 mutex_lock(&data->lock); 1755 ret = mma8452_standby(data); 1756 mutex_unlock(&data->lock); 1757 if (ret < 0) { 1758 dev_err(&data->client->dev, "powering off device failed\n"); 1759 return -EAGAIN; 1760 } 1761 1762 ret = regulator_disable(data->vddio_reg); 1763 if (ret) { 1764 dev_err(dev, "failed to disable VDDIO regulator\n"); 1765 return ret; 1766 } 1767 1768 ret = regulator_disable(data->vdd_reg); 1769 if (ret) { 1770 dev_err(dev, "failed to disable VDD regulator\n"); 1771 return ret; 1772 } 1773 1774 return 0; 1775} 1776 1777static int mma8452_runtime_resume(struct device *dev) 1778{ 1779 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1780 struct mma8452_data *data = iio_priv(indio_dev); 1781 int ret, sleep_val; 1782 1783 ret = regulator_enable(data->vdd_reg); 1784 if (ret) { 1785 dev_err(dev, "failed to enable VDD regulator\n"); 1786 return ret; 1787 } 1788 1789 ret = regulator_enable(data->vddio_reg); 1790 if (ret) { 1791 dev_err(dev, "failed to enable VDDIO regulator\n"); 1792 regulator_disable(data->vdd_reg); 1793 return ret; 1794 } 1795 1796 ret = mma8452_active(data); 1797 if (ret < 0) 1798 goto runtime_resume_failed; 1799 1800 ret = mma8452_get_odr_index(data); 1801 sleep_val = 1000 / mma8452_samp_freq[ret][0]; 1802 if (sleep_val < 20) 1803 usleep_range(sleep_val * 1000, 20000); 1804 else 1805 msleep_interruptible(sleep_val); 1806 1807 return 0; 1808 1809runtime_resume_failed: 1810 regulator_disable(data->vddio_reg); 1811 regulator_disable(data->vdd_reg); 1812 1813 return ret; 1814} 1815#endif 1816 1817static const struct dev_pm_ops mma8452_pm_ops = { 1818 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 1819 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend, 1820 mma8452_runtime_resume, NULL) 1821}; 1822 1823static const struct i2c_device_id mma8452_id[] = { 1824 { "fxls8471", (kernel_ulong_t)&mma_chip_info_table[fxls8471] }, 1825 { "mma8451", (kernel_ulong_t)&mma_chip_info_table[mma8451] }, 1826 { "mma8452", (kernel_ulong_t)&mma_chip_info_table[mma8452] }, 1827 { "mma8453", (kernel_ulong_t)&mma_chip_info_table[mma8453] }, 1828 { "mma8652", (kernel_ulong_t)&mma_chip_info_table[mma8652] }, 1829 { "mma8653", (kernel_ulong_t)&mma_chip_info_table[mma8653] }, 1830 { } 1831}; 1832MODULE_DEVICE_TABLE(i2c, mma8452_id); 1833 1834static struct i2c_driver mma8452_driver = { 1835 .driver = { 1836 .name = "mma8452", 1837 .of_match_table = mma8452_dt_ids, 1838 .pm = &mma8452_pm_ops, 1839 }, 1840 .probe = mma8452_probe, 1841 .remove = mma8452_remove, 1842 .id_table = mma8452_id, 1843}; 1844module_i2c_driver(mma8452_driver); 1845 1846MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>"); 1847MODULE_DESCRIPTION("Freescale / NXP MMA8452 accelerometer driver"); 1848MODULE_LICENSE("GPL");
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