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kionix-kx022a.c
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linux-6.19.14/drivers/iio/accel/kionix-kx022a.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2022 ROHM Semiconductors 4 * 5 * ROHM/KIONIX accelerometer driver 6 */ 7 8#include <linux/array_size.h> 9#include <linux/bitmap.h> 10#include <linux/cleanup.h> 11#include <linux/delay.h> 12#include <linux/device.h> 13#include <linux/errno.h> 14#include <linux/export.h> 15#include <linux/interrupt.h> 16#include <linux/math64.h> 17#include <linux/minmax.h> 18#include <linux/module.h> 19#include <linux/mutex.h> 20#include <linux/property.h> 21#include <linux/regmap.h> 22#include <linux/regulator/consumer.h> 23#include <linux/slab.h> 24#include <linux/string_choices.h> 25#include <linux/sysfs.h> 26#include <linux/time64.h> 27#include <linux/types.h> 28#include <linux/units.h> 29 30#include <linux/iio/iio.h> 31#include <linux/iio/buffer.h> 32#include <linux/iio/sysfs.h> 33#include <linux/iio/trigger.h> 34#include <linux/iio/trigger_consumer.h> 35#include <linux/iio/triggered_buffer.h> 36 37#include <asm/byteorder.h> 38 39#include "kionix-kx022a.h" 40 41/* 42 * The KX022A has FIFO which can store 43 samples of HiRes data from 2 43 * channels. This equals to 43 (samples) * 3 (channels) * 2 (bytes/sample) to 44 * 258 bytes of sample data. The quirk to know is that the amount of bytes in 45 * the FIFO is advertised via 8 bit register (max value 255). The thing to note 46 * is that full 258 bytes of data is indicated using the max value 255. 47 */ 48#define KX022A_FIFO_LENGTH 43 49#define KX022A_FIFO_FULL_VALUE 255 50#define KX022A_SOFT_RESET_WAIT_TIME_US (5 * USEC_PER_MSEC) 51#define KX022A_SOFT_RESET_TOTAL_WAIT_TIME_US (500 * USEC_PER_MSEC) 52 53/* 3 axis, 2 bytes of data for each of the axis */ 54#define KX022A_FIFO_SAMPLES_SIZE_BYTES 6 55#define KX022A_FIFO_MAX_BYTES \ 56 (KX022A_FIFO_LENGTH * KX022A_FIFO_SAMPLES_SIZE_BYTES) 57 58enum { 59 KX022A_STATE_SAMPLE, 60 KX022A_STATE_FIFO, 61}; 62 63/* kx022a Regmap configs */ 64static const struct regmap_range kx022a_volatile_ranges[] = { 65 { 66 .range_min = KX022A_REG_XHP_L, 67 .range_max = KX022A_REG_COTR, 68 }, { 69 .range_min = KX022A_REG_TSCP, 70 .range_max = KX022A_REG_INT_REL, 71 }, { 72 /* The reset bit will be cleared by sensor */ 73 .range_min = KX022A_REG_CNTL2, 74 .range_max = KX022A_REG_CNTL2, 75 }, { 76 .range_min = KX022A_REG_BUF_STATUS_1, 77 .range_max = KX022A_REG_BUF_READ, 78 }, 79}; 80 81static const struct regmap_access_table kx022a_volatile_regs = { 82 .yes_ranges = &kx022a_volatile_ranges[0], 83 .n_yes_ranges = ARRAY_SIZE(kx022a_volatile_ranges), 84}; 85 86static const struct regmap_range kx022a_precious_ranges[] = { 87 { 88 .range_min = KX022A_REG_INT_REL, 89 .range_max = KX022A_REG_INT_REL, 90 }, 91}; 92 93static const struct regmap_access_table kx022a_precious_regs = { 94 .yes_ranges = &kx022a_precious_ranges[0], 95 .n_yes_ranges = ARRAY_SIZE(kx022a_precious_ranges), 96}; 97 98/* 99 * The HW does not set WHO_AM_I reg as read-only but we don't want to write it 100 * so we still include it in the read-only ranges. 101 */ 102static const struct regmap_range kx022a_read_only_ranges[] = { 103 { 104 .range_min = KX022A_REG_XHP_L, 105 .range_max = KX022A_REG_INT_REL, 106 }, { 107 .range_min = KX022A_REG_BUF_STATUS_1, 108 .range_max = KX022A_REG_BUF_STATUS_2, 109 }, { 110 .range_min = KX022A_REG_BUF_READ, 111 .range_max = KX022A_REG_BUF_READ, 112 }, 113}; 114 115static const struct regmap_access_table kx022a_ro_regs = { 116 .no_ranges = &kx022a_read_only_ranges[0], 117 .n_no_ranges = ARRAY_SIZE(kx022a_read_only_ranges), 118}; 119 120static const struct regmap_range kx022a_write_only_ranges[] = { 121 { 122 .range_min = KX022A_REG_BTS_WUF_TH, 123 .range_max = KX022A_REG_BTS_WUF_TH, 124 }, { 125 .range_min = KX022A_REG_MAN_WAKE, 126 .range_max = KX022A_REG_MAN_WAKE, 127 }, { 128 .range_min = KX022A_REG_SELF_TEST, 129 .range_max = KX022A_REG_SELF_TEST, 130 }, { 131 .range_min = KX022A_REG_BUF_CLEAR, 132 .range_max = KX022A_REG_BUF_CLEAR, 133 }, 134}; 135 136static const struct regmap_access_table kx022a_wo_regs = { 137 .no_ranges = &kx022a_write_only_ranges[0], 138 .n_no_ranges = ARRAY_SIZE(kx022a_write_only_ranges), 139}; 140 141static const struct regmap_range kx022a_noinc_read_ranges[] = { 142 { 143 .range_min = KX022A_REG_BUF_READ, 144 .range_max = KX022A_REG_BUF_READ, 145 }, 146}; 147 148static const struct regmap_access_table kx022a_nir_regs = { 149 .yes_ranges = &kx022a_noinc_read_ranges[0], 150 .n_yes_ranges = ARRAY_SIZE(kx022a_noinc_read_ranges), 151}; 152 153static const struct regmap_config kx022a_regmap_config = { 154 .reg_bits = 8, 155 .val_bits = 8, 156 .volatile_table = &kx022a_volatile_regs, 157 .rd_table = &kx022a_wo_regs, 158 .wr_table = &kx022a_ro_regs, 159 .rd_noinc_table = &kx022a_nir_regs, 160 .precious_table = &kx022a_precious_regs, 161 .max_register = KX022A_MAX_REGISTER, 162 .cache_type = REGCACHE_MAPLE, 163}; 164 165/* Regmap configs kx132 */ 166static const struct regmap_range kx132_volatile_ranges[] = { 167 { 168 .range_min = KX132_REG_XADP_L, 169 .range_max = KX132_REG_COTR, 170 }, { 171 .range_min = KX132_REG_TSCP, 172 .range_max = KX132_REG_INT_REL, 173 }, { 174 /* The reset bit will be cleared by sensor */ 175 .range_min = KX132_REG_CNTL2, 176 .range_max = KX132_REG_CNTL2, 177 }, { 178 .range_min = KX132_REG_CNTL5, 179 .range_max = KX132_REG_CNTL5, 180 }, { 181 .range_min = KX132_REG_BUF_STATUS_1, 182 .range_max = KX132_REG_BUF_READ, 183 }, 184}; 185 186static const struct regmap_access_table kx132_volatile_regs = { 187 .yes_ranges = &kx132_volatile_ranges[0], 188 .n_yes_ranges = ARRAY_SIZE(kx132_volatile_ranges), 189}; 190 191static const struct regmap_range kx132_precious_ranges[] = { 192 { 193 .range_min = KX132_REG_INT_REL, 194 .range_max = KX132_REG_INT_REL, 195 }, 196}; 197 198static const struct regmap_access_table kx132_precious_regs = { 199 .yes_ranges = &kx132_precious_ranges[0], 200 .n_yes_ranges = ARRAY_SIZE(kx132_precious_ranges), 201}; 202 203static const struct regmap_range kx132_read_only_ranges[] = { 204 { 205 .range_min = KX132_REG_XADP_L, 206 .range_max = KX132_REG_INT_REL, 207 }, { 208 .range_min = KX132_REG_BUF_STATUS_1, 209 .range_max = KX132_REG_BUF_STATUS_2, 210 }, { 211 .range_min = KX132_REG_BUF_READ, 212 .range_max = KX132_REG_BUF_READ, 213 }, { 214 /* Kionix reserved registers: should not be written */ 215 .range_min = 0x28, 216 .range_max = 0x28, 217 }, { 218 .range_min = 0x35, 219 .range_max = 0x36, 220 }, { 221 .range_min = 0x3c, 222 .range_max = 0x48, 223 }, { 224 .range_min = 0x4e, 225 .range_max = 0x5c, 226 }, { 227 .range_min = 0x77, 228 .range_max = 0x7f, 229 }, 230}; 231 232static const struct regmap_access_table kx132_ro_regs = { 233 .no_ranges = &kx132_read_only_ranges[0], 234 .n_no_ranges = ARRAY_SIZE(kx132_read_only_ranges), 235}; 236 237static const struct regmap_range kx132_write_only_ranges[] = { 238 { 239 .range_min = KX132_REG_SELF_TEST, 240 .range_max = KX132_REG_SELF_TEST, 241 }, { 242 .range_min = KX132_REG_BUF_CLEAR, 243 .range_max = KX132_REG_BUF_CLEAR, 244 }, 245}; 246 247static const struct regmap_access_table kx132_wo_regs = { 248 .no_ranges = &kx132_write_only_ranges[0], 249 .n_no_ranges = ARRAY_SIZE(kx132_write_only_ranges), 250}; 251 252static const struct regmap_range kx132_noinc_read_ranges[] = { 253 { 254 .range_min = KX132_REG_BUF_READ, 255 .range_max = KX132_REG_BUF_READ, 256 }, 257}; 258 259static const struct regmap_access_table kx132_nir_regs = { 260 .yes_ranges = &kx132_noinc_read_ranges[0], 261 .n_yes_ranges = ARRAY_SIZE(kx132_noinc_read_ranges), 262}; 263 264static const struct regmap_config kx132_regmap_config = { 265 .reg_bits = 8, 266 .val_bits = 8, 267 .volatile_table = &kx132_volatile_regs, 268 .rd_table = &kx132_wo_regs, 269 .wr_table = &kx132_ro_regs, 270 .rd_noinc_table = &kx132_nir_regs, 271 .precious_table = &kx132_precious_regs, 272 .max_register = KX132_MAX_REGISTER, 273 .cache_type = REGCACHE_MAPLE, 274}; 275 276struct kx022a_data { 277 struct regmap *regmap; 278 const struct kx022a_chip_info *chip_info; 279 struct iio_trigger *trig; 280 struct device *dev; 281 struct iio_mount_matrix orientation; 282 int64_t timestamp, old_timestamp; 283 284 int irq; 285 int inc_reg; 286 int ien_reg; 287 288 unsigned int state; 289 unsigned int odr_ns; 290 291 bool trigger_enabled; 292 /* 293 * Prevent toggling the sensor stby/active state (PC1 bit) in the 294 * middle of a configuration, or when the fifo is enabled. Also, 295 * protect the data stored/retrieved from this structure from 296 * concurrent accesses. 297 */ 298 struct mutex mutex; 299 u8 watermark; 300 301 __le16 *fifo_buffer; 302 303 /* 3 x 16bit accel data + timestamp */ 304 __le16 buffer[8] __aligned(IIO_DMA_MINALIGN); 305 struct { 306 __le16 channels[3]; 307 aligned_s64 ts; 308 } scan; 309}; 310 311static const struct iio_mount_matrix * 312kx022a_get_mount_matrix(const struct iio_dev *idev, 313 const struct iio_chan_spec *chan) 314{ 315 struct kx022a_data *data = iio_priv(idev); 316 317 return &data->orientation; 318} 319 320enum { 321 AXIS_X, 322 AXIS_Y, 323 AXIS_Z, 324 AXIS_MAX 325}; 326 327static const unsigned long kx022a_scan_masks[] = { 328 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), 0 329}; 330 331static const struct iio_chan_spec_ext_info kx022a_ext_info[] = { 332 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, kx022a_get_mount_matrix), 333 { } 334}; 335 336#define KX022A_ACCEL_CHAN(axis, reg, index) \ 337{ \ 338 .type = IIO_ACCEL, \ 339 .modified = 1, \ 340 .channel2 = IIO_MOD_##axis, \ 341 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 342 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 343 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 344 .info_mask_shared_by_type_available = \ 345 BIT(IIO_CHAN_INFO_SCALE) | \ 346 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 347 .ext_info = kx022a_ext_info, \ 348 .address = reg, \ 349 .scan_index = index, \ 350 .scan_type = { \ 351 .sign = 's', \ 352 .realbits = 16, \ 353 .storagebits = 16, \ 354 .endianness = IIO_LE, \ 355 }, \ 356} 357 358static const struct iio_chan_spec kx022a_channels[] = { 359 KX022A_ACCEL_CHAN(X, KX022A_REG_XOUT_L, 0), 360 KX022A_ACCEL_CHAN(Y, KX022A_REG_YOUT_L, 1), 361 KX022A_ACCEL_CHAN(Z, KX022A_REG_ZOUT_L, 2), 362 IIO_CHAN_SOFT_TIMESTAMP(3), 363}; 364 365static const struct iio_chan_spec kx132_channels[] = { 366 KX022A_ACCEL_CHAN(X, KX132_REG_XOUT_L, 0), 367 KX022A_ACCEL_CHAN(Y, KX132_REG_YOUT_L, 1), 368 KX022A_ACCEL_CHAN(Z, KX132_REG_ZOUT_L, 2), 369 IIO_CHAN_SOFT_TIMESTAMP(3), 370}; 371 372/* 373 * The sensor HW can support ODR up to 1600 Hz, which is beyond what most of the 374 * Linux CPUs can handle without dropping samples. Also, the low power mode is 375 * not available for higher sample rates. Thus, the driver only supports 200 Hz 376 * and slower ODRs. The slowest is 0.78 Hz. 377 */ 378static const int kx022a_accel_samp_freq_table[][2] = { 379 { 0, 780000 }, 380 { 1, 563000 }, 381 { 3, 125000 }, 382 { 6, 250000 }, 383 { 12, 500000 }, 384 { 25, 0 }, 385 { 50, 0 }, 386 { 100, 0 }, 387 { 200, 0 }, 388}; 389 390static const unsigned int kx022a_odrs[] = { 391 1282051282, 392 639795266, 393 320 * MEGA, 394 160 * MEGA, 395 80 * MEGA, 396 40 * MEGA, 397 20 * MEGA, 398 10 * MEGA, 399 5 * MEGA, 400}; 401 402/* 403 * range is typically +-2G/4G/8G/16G, distributed over the amount of bits. 404 * The scale table can be calculated using 405 * (range / 2^bits) * g = (range / 2^bits) * 9.80665 m/s^2 406 * => KX022A uses 16 bit (HiRes mode - assume the low 8 bits are zeroed 407 * in low-power mode(?) ) 408 * => +/-2G => 4 / 2^16 * 9,80665 409 * => +/-2G - 0.000598550415 410 * +/-4G - 0.00119710083 411 * +/-8G - 0.00239420166 412 * +/-16G - 0.00478840332 413 */ 414static const int kx022a_scale_table[][2] = { 415 { 0, 598550 }, 416 { 0, 1197101 }, 417 { 0, 2394202 }, 418 { 0, 4788403 }, 419}; 420 421/* KX134ACR-LBZ ranges are (+/-) 8, 16, 32, 64 G */ 422static const int kx134acr_lbz_scale_table[][2] = { 423 { 0, 2394202 }, 424 { 0, 4788403 }, 425 { 0, 9576807 }, 426 { 0, 19153613 }, 427}; 428 429static int kx022a_read_avail(struct iio_dev *indio_dev, 430 struct iio_chan_spec const *chan, 431 const int **vals, int *type, int *length, 432 long mask) 433{ 434 struct kx022a_data *data = iio_priv(indio_dev); 435 436 switch (mask) { 437 case IIO_CHAN_INFO_SAMP_FREQ: 438 *vals = (const int *)kx022a_accel_samp_freq_table; 439 *length = ARRAY_SIZE(kx022a_accel_samp_freq_table) * 440 ARRAY_SIZE(kx022a_accel_samp_freq_table[0]); 441 *type = IIO_VAL_INT_PLUS_MICRO; 442 return IIO_AVAIL_LIST; 443 case IIO_CHAN_INFO_SCALE: 444 *vals = (const int *)data->chip_info->scale_table; 445 *length = data->chip_info->scale_table_size; 446 *type = IIO_VAL_INT_PLUS_NANO; 447 return IIO_AVAIL_LIST; 448 default: 449 return -EINVAL; 450 } 451} 452 453#define KX022A_DEFAULT_PERIOD_NS (20 * NSEC_PER_MSEC) 454 455static void kx022a_reg2freq(unsigned int val, int *val1, int *val2) 456{ 457 *val1 = kx022a_accel_samp_freq_table[val & KX022A_MASK_ODR][0]; 458 *val2 = kx022a_accel_samp_freq_table[val & KX022A_MASK_ODR][1]; 459} 460 461static void kx022a_reg2scale(struct kx022a_data *data, unsigned int val, 462 unsigned int *val1, unsigned int *val2) 463{ 464 val &= KX022A_MASK_GSEL; 465 val >>= KX022A_GSEL_SHIFT; 466 467 *val1 = data->chip_info->scale_table[val][0]; 468 *val2 = data->chip_info->scale_table[val][1]; 469} 470 471static int __kx022a_turn_on_off(struct kx022a_data *data, bool on) 472{ 473 int ret; 474 475 if (on) 476 ret = regmap_set_bits(data->regmap, data->chip_info->cntl, 477 KX022A_MASK_PC1); 478 else 479 ret = regmap_clear_bits(data->regmap, data->chip_info->cntl, 480 KX022A_MASK_PC1); 481 if (ret) 482 dev_err(data->dev, "Turn %s fail %d\n", str_on_off(on), ret); 483 484 return ret; 485} 486 487static int kx022a_turn_off_lock(struct kx022a_data *data) 488{ 489 int ret; 490 491 mutex_lock(&data->mutex); 492 ret = __kx022a_turn_on_off(data, false); 493 if (ret) 494 mutex_unlock(&data->mutex); 495 496 return ret; 497} 498 499static int kx022a_turn_on_unlock(struct kx022a_data *data) 500{ 501 int ret; 502 503 ret = __kx022a_turn_on_off(data, true); 504 mutex_unlock(&data->mutex); 505 506 return ret; 507} 508 509static int kx022a_write_raw_get_fmt(struct iio_dev *idev, 510 struct iio_chan_spec const *chan, 511 long mask) 512{ 513 switch (mask) { 514 case IIO_CHAN_INFO_SCALE: 515 return IIO_VAL_INT_PLUS_NANO; 516 case IIO_CHAN_INFO_SAMP_FREQ: 517 return IIO_VAL_INT_PLUS_MICRO; 518 default: 519 return -EINVAL; 520 } 521} 522 523static int __kx022a_write_raw(struct iio_dev *idev, 524 struct iio_chan_spec const *chan, 525 int val, int val2, long mask) 526{ 527 struct kx022a_data *data = iio_priv(idev); 528 int ret, n; 529 530 switch (mask) { 531 case IIO_CHAN_INFO_SAMP_FREQ: 532 n = ARRAY_SIZE(kx022a_accel_samp_freq_table); 533 534 while (n--) 535 if (val == kx022a_accel_samp_freq_table[n][0] && 536 val2 == kx022a_accel_samp_freq_table[n][1]) 537 break; 538 if (n < 0) 539 return -EINVAL; 540 541 ret = kx022a_turn_off_lock(data); 542 if (ret) 543 return ret; 544 545 ret = regmap_update_bits(data->regmap, 546 data->chip_info->odcntl, 547 KX022A_MASK_ODR, n); 548 data->odr_ns = kx022a_odrs[n]; 549 kx022a_turn_on_unlock(data); 550 return ret; 551 case IIO_CHAN_INFO_SCALE: 552 n = data->chip_info->scale_table_size / 2; 553 554 while (n-- > 0) 555 if (val == data->chip_info->scale_table[n][0] && 556 val2 == data->chip_info->scale_table[n][1]) 557 break; 558 if (n < 0) 559 return -EINVAL; 560 561 ret = kx022a_turn_off_lock(data); 562 if (ret) 563 return ret; 564 565 ret = regmap_update_bits(data->regmap, data->chip_info->cntl, 566 KX022A_MASK_GSEL, 567 n << KX022A_GSEL_SHIFT); 568 kx022a_turn_on_unlock(data); 569 return ret; 570 default: 571 return -EINVAL; 572 } 573} 574 575static int kx022a_write_raw(struct iio_dev *idev, 576 struct iio_chan_spec const *chan, 577 int val, int val2, long mask) 578{ 579 int ret; 580 581 /* 582 * We should not allow changing scale or frequency when FIFO is running 583 * as it will mess the timestamp/scale for samples existing in the 584 * buffer. If this turns out to be an issue we can later change logic 585 * to internally flush the fifo before reconfiguring so the samples in 586 * fifo keep matching the freq/scale settings. (Such setup could cause 587 * issues if users trust the watermark to be reached within known 588 * time-limit). 589 */ 590 if (!iio_device_claim_direct(idev)) 591 return -EBUSY; 592 593 ret = __kx022a_write_raw(idev, chan, val, val2, mask); 594 595 iio_device_release_direct(idev); 596 597 return ret; 598} 599 600static int kx022a_fifo_set_wmi(struct kx022a_data *data) 601{ 602 u8 threshold; 603 604 threshold = data->watermark; 605 606 return regmap_update_bits(data->regmap, data->chip_info->buf_cntl1, 607 KX022A_MASK_WM_TH, threshold); 608} 609 610static int kx022a_get_axis(struct kx022a_data *data, 611 struct iio_chan_spec const *chan, 612 int *val) 613{ 614 int ret; 615 616 ret = regmap_bulk_read(data->regmap, chan->address, &data->buffer[0], 617 sizeof(__le16)); 618 if (ret) 619 return ret; 620 621 *val = (s16)le16_to_cpu(data->buffer[0]); 622 623 return IIO_VAL_INT; 624} 625 626static int kx022a_read_raw(struct iio_dev *idev, 627 struct iio_chan_spec const *chan, 628 int *val, int *val2, long mask) 629{ 630 struct kx022a_data *data = iio_priv(idev); 631 unsigned int regval; 632 int ret; 633 634 switch (mask) { 635 case IIO_CHAN_INFO_RAW: 636 if (!iio_device_claim_direct(idev)) 637 return -EBUSY; 638 639 mutex_lock(&data->mutex); 640 ret = kx022a_get_axis(data, chan, val); 641 mutex_unlock(&data->mutex); 642 643 iio_device_release_direct(idev); 644 645 return ret; 646 647 case IIO_CHAN_INFO_SAMP_FREQ: 648 ret = regmap_read(data->regmap, data->chip_info->odcntl, ®val); 649 if (ret) 650 return ret; 651 652 if ((regval & KX022A_MASK_ODR) > 653 ARRAY_SIZE(kx022a_accel_samp_freq_table)) { 654 dev_err(data->dev, "Invalid ODR\n"); 655 return -EINVAL; 656 } 657 658 kx022a_reg2freq(regval, val, val2); 659 660 return IIO_VAL_INT_PLUS_MICRO; 661 662 case IIO_CHAN_INFO_SCALE: 663 ret = regmap_read(data->regmap, data->chip_info->cntl, ®val); 664 if (ret < 0) 665 return ret; 666 667 kx022a_reg2scale(data, regval, val, val2); 668 669 return IIO_VAL_INT_PLUS_NANO; 670 } 671 672 return -EINVAL; 673}; 674 675static int kx022a_set_watermark(struct iio_dev *idev, unsigned int val) 676{ 677 struct kx022a_data *data = iio_priv(idev); 678 679 val = min(data->chip_info->fifo_length, val); 680 681 mutex_lock(&data->mutex); 682 data->watermark = val; 683 mutex_unlock(&data->mutex); 684 685 return 0; 686} 687 688static ssize_t hwfifo_enabled_show(struct device *dev, 689 struct device_attribute *attr, 690 char *buf) 691{ 692 struct iio_dev *idev = dev_to_iio_dev(dev); 693 struct kx022a_data *data = iio_priv(idev); 694 bool state; 695 696 mutex_lock(&data->mutex); 697 state = data->state; 698 mutex_unlock(&data->mutex); 699 700 return sysfs_emit(buf, "%d\n", state); 701} 702 703static ssize_t hwfifo_watermark_show(struct device *dev, 704 struct device_attribute *attr, 705 char *buf) 706{ 707 struct iio_dev *idev = dev_to_iio_dev(dev); 708 struct kx022a_data *data = iio_priv(idev); 709 int wm; 710 711 mutex_lock(&data->mutex); 712 wm = data->watermark; 713 mutex_unlock(&data->mutex); 714 715 return sysfs_emit(buf, "%d\n", wm); 716} 717 718static IIO_DEVICE_ATTR_RO(hwfifo_enabled, 0); 719static IIO_DEVICE_ATTR_RO(hwfifo_watermark, 0); 720 721static const struct iio_dev_attr *kx022a_fifo_attributes[] = { 722 &iio_dev_attr_hwfifo_watermark, 723 &iio_dev_attr_hwfifo_enabled, 724 NULL 725}; 726 727static int kx022a_drop_fifo_contents(struct kx022a_data *data) 728{ 729 /* 730 * We must clear the old time-stamp to avoid computing the timestamps 731 * based on samples acquired when buffer was last enabled. 732 * 733 * We don't need to protect the timestamp as long as we are only 734 * called from fifo-disable where we can guarantee the sensor is not 735 * triggering interrupts and where the mutex is locked to prevent the 736 * user-space access. 737 */ 738 data->timestamp = 0; 739 740 return regmap_write(data->regmap, data->chip_info->buf_clear, 0x0); 741} 742 743static int kx022a_get_fifo_bytes_available(struct kx022a_data *data) 744{ 745 int ret, fifo_bytes; 746 747 ret = regmap_read(data->regmap, KX022A_REG_BUF_STATUS_1, &fifo_bytes); 748 if (ret) { 749 dev_err(data->dev, "Error reading buffer status\n"); 750 return ret; 751 } 752 753 if (fifo_bytes == KX022A_FIFO_FULL_VALUE) 754 return KX022A_FIFO_MAX_BYTES; 755 756 return fifo_bytes; 757} 758 759static int kx132_get_fifo_bytes_available(struct kx022a_data *data) 760{ 761 __le16 buf_status; 762 int ret, fifo_bytes; 763 764 ret = regmap_bulk_read(data->regmap, data->chip_info->buf_status1, 765 &buf_status, sizeof(buf_status)); 766 if (ret) { 767 dev_err(data->dev, "Error reading buffer status\n"); 768 return ret; 769 } 770 771 fifo_bytes = le16_to_cpu(buf_status); 772 fifo_bytes &= data->chip_info->buf_smp_lvl_mask; 773 fifo_bytes = min((unsigned int)fifo_bytes, data->chip_info->fifo_length * 774 KX022A_FIFO_SAMPLES_SIZE_BYTES); 775 776 return fifo_bytes; 777} 778 779static int __kx022a_fifo_flush(struct iio_dev *idev, unsigned int samples, 780 bool irq) 781{ 782 struct kx022a_data *data = iio_priv(idev); 783 uint64_t sample_period; 784 int count, fifo_bytes; 785 bool renable = false; 786 int64_t tstamp; 787 int ret, i; 788 789 fifo_bytes = data->chip_info->get_fifo_bytes_available(data); 790 791 if (fifo_bytes % KX022A_FIFO_SAMPLES_SIZE_BYTES) 792 dev_warn(data->dev, "Bad FIFO alignment. Data may be corrupt\n"); 793 794 count = fifo_bytes / KX022A_FIFO_SAMPLES_SIZE_BYTES; 795 if (!count) 796 return 0; 797 798 /* 799 * If we are being called from IRQ handler we know the stored timestamp 800 * is fairly accurate for the last stored sample. Otherwise, if we are 801 * called as a result of a read operation from userspace and hence 802 * before the watermark interrupt was triggered, take a timestamp 803 * now. We can fall anywhere in between two samples so the error in this 804 * case is at most one sample period. 805 */ 806 if (!irq) { 807 /* 808 * We need to have the IRQ disabled or we risk of messing-up 809 * the timestamps. If we are ran from IRQ, then the 810 * IRQF_ONESHOT has us covered - but if we are ran by the 811 * user-space read we need to disable the IRQ to be on a safe 812 * side. We do this usng synchronous disable so that if the 813 * IRQ thread is being ran on other CPU we wait for it to be 814 * finished. 815 */ 816 disable_irq(data->irq); 817 renable = true; 818 819 data->old_timestamp = data->timestamp; 820 data->timestamp = iio_get_time_ns(idev); 821 } 822 823 /* 824 * Approximate timestamps for each of the sample based on the sampling 825 * frequency, timestamp for last sample and number of samples. 826 * 827 * We'd better not use the current bandwidth settings to compute the 828 * sample period. The real sample rate varies with the device and 829 * small variation adds when we store a large number of samples. 830 * 831 * To avoid this issue we compute the actual sample period ourselves 832 * based on the timestamp delta between the last two flush operations. 833 */ 834 if (data->old_timestamp) { 835 sample_period = data->timestamp - data->old_timestamp; 836 do_div(sample_period, count); 837 } else { 838 sample_period = data->odr_ns; 839 } 840 tstamp = data->timestamp - (count - 1) * sample_period; 841 842 if (samples && count > samples) { 843 /* 844 * Here we leave some old samples to the buffer. We need to 845 * adjust the timestamp to match the first sample in the buffer 846 * or we will miscalculate the sample_period at next round. 847 */ 848 data->timestamp -= (count - samples) * sample_period; 849 count = samples; 850 } 851 852 fifo_bytes = count * KX022A_FIFO_SAMPLES_SIZE_BYTES; 853 ret = regmap_noinc_read(data->regmap, data->chip_info->buf_read, 854 data->fifo_buffer, fifo_bytes); 855 if (ret) 856 goto renable_out; 857 858 for (i = 0; i < count; i++) { 859 __le16 *sam = &data->fifo_buffer[i * 3]; 860 __le16 *chs; 861 int bit; 862 863 chs = &data->scan.channels[0]; 864 for_each_set_bit(bit, idev->active_scan_mask, AXIS_MAX) 865 chs[bit] = sam[bit]; 866 867 iio_push_to_buffers_with_timestamp(idev, &data->scan, tstamp); 868 869 tstamp += sample_period; 870 } 871 872 ret = count; 873 874renable_out: 875 if (renable) 876 enable_irq(data->irq); 877 878 return ret; 879} 880 881static int kx022a_fifo_flush(struct iio_dev *idev, unsigned int samples) 882{ 883 struct kx022a_data *data = iio_priv(idev); 884 int ret; 885 886 mutex_lock(&data->mutex); 887 ret = __kx022a_fifo_flush(idev, samples, false); 888 mutex_unlock(&data->mutex); 889 890 return ret; 891} 892 893static const struct iio_info kx022a_info = { 894 .read_raw = &kx022a_read_raw, 895 .write_raw = &kx022a_write_raw, 896 .write_raw_get_fmt = &kx022a_write_raw_get_fmt, 897 .read_avail = &kx022a_read_avail, 898 899 .validate_trigger = iio_validate_own_trigger, 900 .hwfifo_set_watermark = kx022a_set_watermark, 901 .hwfifo_flush_to_buffer = kx022a_fifo_flush, 902}; 903 904static int kx022a_set_drdy_irq(struct kx022a_data *data, bool en) 905{ 906 if (en) 907 return regmap_set_bits(data->regmap, data->chip_info->cntl, 908 KX022A_MASK_DRDY); 909 910 return regmap_clear_bits(data->regmap, data->chip_info->cntl, 911 KX022A_MASK_DRDY); 912} 913 914static int kx022a_prepare_irq_pin(struct kx022a_data *data) 915{ 916 /* Enable IRQ1 pin. Set polarity to active low */ 917 int mask = KX022A_MASK_IEN | KX022A_MASK_IPOL | 918 KX022A_MASK_ITYP; 919 int val = KX022A_MASK_IEN | KX022A_IPOL_LOW | 920 KX022A_ITYP_LEVEL; 921 int ret; 922 923 ret = regmap_update_bits(data->regmap, data->inc_reg, mask, val); 924 if (ret) 925 return ret; 926 927 /* We enable WMI to IRQ pin only at buffer_enable */ 928 mask = KX022A_MASK_INS2_DRDY; 929 930 return regmap_set_bits(data->regmap, data->ien_reg, mask); 931} 932 933static int kx022a_fifo_disable(struct kx022a_data *data) 934{ 935 int ret = 0; 936 937 guard(mutex)(&data->mutex); 938 ret = __kx022a_turn_on_off(data, false); 939 if (ret) 940 return ret; 941 942 ret = regmap_clear_bits(data->regmap, data->ien_reg, KX022A_MASK_WMI); 943 if (ret) 944 return ret; 945 946 ret = regmap_clear_bits(data->regmap, data->chip_info->buf_cntl2, 947 KX022A_MASK_BUF_EN); 948 if (ret) 949 return ret; 950 951 data->state &= ~KX022A_STATE_FIFO; 952 953 kx022a_drop_fifo_contents(data); 954 955 kfree(data->fifo_buffer); 956 957 return __kx022a_turn_on_off(data, true); 958} 959 960static int kx022a_buffer_predisable(struct iio_dev *idev) 961{ 962 struct kx022a_data *data = iio_priv(idev); 963 964 if (iio_device_get_current_mode(idev) == INDIO_BUFFER_TRIGGERED) 965 return 0; 966 967 return kx022a_fifo_disable(data); 968} 969 970static int kx022a_fifo_enable(struct kx022a_data *data) 971{ 972 int ret; 973 974 data->fifo_buffer = kmalloc_array(data->chip_info->fifo_length, 975 KX022A_FIFO_SAMPLES_SIZE_BYTES, 976 GFP_KERNEL); 977 if (!data->fifo_buffer) 978 return -ENOMEM; 979 980 guard(mutex)(&data->mutex); 981 ret = __kx022a_turn_on_off(data, false); 982 if (ret) 983 return ret; 984 985 /* Update watermark to HW */ 986 ret = kx022a_fifo_set_wmi(data); 987 if (ret) 988 return ret; 989 990 /* Enable buffer */ 991 ret = regmap_set_bits(data->regmap, data->chip_info->buf_cntl2, 992 KX022A_MASK_BUF_EN); 993 if (ret) 994 return ret; 995 996 data->state |= KX022A_STATE_FIFO; 997 ret = regmap_set_bits(data->regmap, data->ien_reg, 998 KX022A_MASK_WMI); 999 if (ret) 1000 return ret; 1001 1002 return __kx022a_turn_on_off(data, true); 1003} 1004 1005static int kx022a_buffer_postenable(struct iio_dev *idev) 1006{ 1007 struct kx022a_data *data = iio_priv(idev); 1008 1009 /* 1010 * If we use data-ready trigger, then the IRQ masks should be handled by 1011 * trigger enable and the hardware buffer is not used but we just update 1012 * results to the IIO fifo when data-ready triggers. 1013 */ 1014 if (iio_device_get_current_mode(idev) == INDIO_BUFFER_TRIGGERED) 1015 return 0; 1016 1017 return kx022a_fifo_enable(data); 1018} 1019 1020static const struct iio_buffer_setup_ops kx022a_buffer_ops = { 1021 .postenable = kx022a_buffer_postenable, 1022 .predisable = kx022a_buffer_predisable, 1023}; 1024 1025static irqreturn_t kx022a_trigger_handler(int irq, void *p) 1026{ 1027 struct iio_poll_func *pf = p; 1028 struct iio_dev *idev = pf->indio_dev; 1029 struct kx022a_data *data = iio_priv(idev); 1030 int ret; 1031 1032 ret = regmap_bulk_read(data->regmap, data->chip_info->xout_l, data->buffer, 1033 KX022A_FIFO_SAMPLES_SIZE_BYTES); 1034 if (ret < 0) 1035 goto err_read; 1036 1037 iio_push_to_buffers_with_timestamp(idev, data->buffer, data->timestamp); 1038err_read: 1039 iio_trigger_notify_done(idev->trig); 1040 1041 return IRQ_HANDLED; 1042} 1043 1044/* Get timestamps and wake the thread if we need to read data */ 1045static irqreturn_t kx022a_irq_handler(int irq, void *private) 1046{ 1047 struct iio_dev *idev = private; 1048 struct kx022a_data *data = iio_priv(idev); 1049 1050 data->old_timestamp = data->timestamp; 1051 data->timestamp = iio_get_time_ns(idev); 1052 1053 if (data->state & KX022A_STATE_FIFO || data->trigger_enabled) 1054 return IRQ_WAKE_THREAD; 1055 1056 return IRQ_NONE; 1057} 1058 1059/* 1060 * WMI and data-ready IRQs are acked when results are read. If we add 1061 * TILT/WAKE or other IRQs - then we may need to implement the acking 1062 * (which is racy). 1063 */ 1064static irqreturn_t kx022a_irq_thread_handler(int irq, void *private) 1065{ 1066 struct iio_dev *idev = private; 1067 struct kx022a_data *data = iio_priv(idev); 1068 irqreturn_t ret = IRQ_NONE; 1069 1070 guard(mutex)(&data->mutex); 1071 1072 if (data->trigger_enabled) { 1073 iio_trigger_poll_nested(data->trig); 1074 ret = IRQ_HANDLED; 1075 } 1076 1077 if (data->state & KX022A_STATE_FIFO) { 1078 int ok; 1079 1080 ok = __kx022a_fifo_flush(idev, data->chip_info->fifo_length, true); 1081 if (ok > 0) 1082 ret = IRQ_HANDLED; 1083 } 1084 1085 return ret; 1086} 1087 1088static int kx022a_trigger_set_state(struct iio_trigger *trig, 1089 bool state) 1090{ 1091 struct kx022a_data *data = iio_trigger_get_drvdata(trig); 1092 int ret = 0; 1093 1094 guard(mutex)(&data->mutex); 1095 1096 if (data->trigger_enabled == state) 1097 return 0; 1098 1099 if (data->state & KX022A_STATE_FIFO) { 1100 dev_warn(data->dev, "Can't set trigger when FIFO enabled\n"); 1101 return -EBUSY; 1102 } 1103 1104 ret = __kx022a_turn_on_off(data, false); 1105 if (ret) 1106 return ret; 1107 1108 data->trigger_enabled = state; 1109 ret = kx022a_set_drdy_irq(data, state); 1110 if (ret) 1111 return ret; 1112 1113 return __kx022a_turn_on_off(data, true); 1114} 1115 1116static const struct iio_trigger_ops kx022a_trigger_ops = { 1117 .set_trigger_state = kx022a_trigger_set_state, 1118}; 1119 1120static int kx022a_chip_init(struct kx022a_data *data) 1121{ 1122 int ret, val; 1123 1124 /* Reset the senor */ 1125 ret = regmap_write(data->regmap, data->chip_info->cntl2, KX022A_MASK_SRST); 1126 if (ret) 1127 return ret; 1128 1129 /* 1130 * According to the power-on procedure documents, there is (at least) 1131 * 2ms delay required after the software reset. This should be same for 1132 * all, KX022ACR-Z, KX132-1211, KX132ACR-LBZ and KX134ACR-LBZ. 1133 * 1134 * https://fscdn.rohm.com/kionix/en/document/AN010_KX022ACR-Z_Power-on_Procedure_E.pdf 1135 * https://fscdn.rohm.com/kionix/en/document/TN027-Power-On-Procedure.pdf 1136 * https://fscdn.rohm.com/kionix/en/document/AN011_KX134ACR-LBZ_Power-on_Procedure_E.pdf 1137 */ 1138 msleep(2); 1139 1140 ret = regmap_read_poll_timeout(data->regmap, data->chip_info->cntl2, val, 1141 !(val & KX022A_MASK_SRST), 1142 KX022A_SOFT_RESET_WAIT_TIME_US, 1143 KX022A_SOFT_RESET_TOTAL_WAIT_TIME_US); 1144 if (ret) { 1145 dev_err(data->dev, "Sensor reset %s\n", 1146 val & KX022A_MASK_SRST ? "timeout" : "fail#"); 1147 return ret; 1148 } 1149 1150 ret = regmap_reinit_cache(data->regmap, data->chip_info->regmap_config); 1151 if (ret) { 1152 dev_err(data->dev, "Failed to reinit reg cache\n"); 1153 return ret; 1154 } 1155 1156 /* set data res 16bit */ 1157 ret = regmap_set_bits(data->regmap, data->chip_info->buf_cntl2, 1158 KX022A_MASK_BRES16); 1159 if (ret) { 1160 dev_err(data->dev, "Failed to set data resolution\n"); 1161 return ret; 1162 } 1163 1164 return kx022a_prepare_irq_pin(data); 1165} 1166 1167const struct kx022a_chip_info kx022a_chip_info = { 1168 .name = "kx022-accel", 1169 .regmap_config = &kx022a_regmap_config, 1170 .channels = kx022a_channels, 1171 .num_channels = ARRAY_SIZE(kx022a_channels), 1172 .scale_table = kx022a_scale_table, 1173 .scale_table_size = ARRAY_SIZE(kx022a_scale_table) * 1174 ARRAY_SIZE(kx022a_scale_table[0]), 1175 .fifo_length = KX022A_FIFO_LENGTH, 1176 .who = KX022A_REG_WHO, 1177 .id = KX022A_ID, 1178 .cntl = KX022A_REG_CNTL, 1179 .cntl2 = KX022A_REG_CNTL2, 1180 .odcntl = KX022A_REG_ODCNTL, 1181 .buf_cntl1 = KX022A_REG_BUF_CNTL1, 1182 .buf_cntl2 = KX022A_REG_BUF_CNTL2, 1183 .buf_clear = KX022A_REG_BUF_CLEAR, 1184 .buf_status1 = KX022A_REG_BUF_STATUS_1, 1185 .buf_read = KX022A_REG_BUF_READ, 1186 .inc1 = KX022A_REG_INC1, 1187 .inc4 = KX022A_REG_INC4, 1188 .inc5 = KX022A_REG_INC5, 1189 .inc6 = KX022A_REG_INC6, 1190 .xout_l = KX022A_REG_XOUT_L, 1191 .get_fifo_bytes_available = kx022a_get_fifo_bytes_available, 1192}; 1193EXPORT_SYMBOL_NS_GPL(kx022a_chip_info, "IIO_KX022A"); 1194 1195const struct kx022a_chip_info kx132_chip_info = { 1196 .name = "kx132-1211", 1197 .regmap_config = &kx132_regmap_config, 1198 .channels = kx132_channels, 1199 .num_channels = ARRAY_SIZE(kx132_channels), 1200 .scale_table = kx022a_scale_table, 1201 .scale_table_size = ARRAY_SIZE(kx022a_scale_table) * 1202 ARRAY_SIZE(kx022a_scale_table[0]), 1203 .fifo_length = KX132_FIFO_LENGTH, 1204 .who = KX132_REG_WHO, 1205 .id = KX132_ID, 1206 .cntl = KX132_REG_CNTL, 1207 .cntl2 = KX132_REG_CNTL2, 1208 .odcntl = KX132_REG_ODCNTL, 1209 .buf_cntl1 = KX132_REG_BUF_CNTL1, 1210 .buf_cntl2 = KX132_REG_BUF_CNTL2, 1211 .buf_clear = KX132_REG_BUF_CLEAR, 1212 .buf_status1 = KX132_REG_BUF_STATUS_1, 1213 .buf_smp_lvl_mask = KX132_MASK_BUF_SMP_LVL, 1214 .buf_read = KX132_REG_BUF_READ, 1215 .inc1 = KX132_REG_INC1, 1216 .inc4 = KX132_REG_INC4, 1217 .inc5 = KX132_REG_INC5, 1218 .inc6 = KX132_REG_INC6, 1219 .xout_l = KX132_REG_XOUT_L, 1220 .get_fifo_bytes_available = kx132_get_fifo_bytes_available, 1221}; 1222EXPORT_SYMBOL_NS_GPL(kx132_chip_info, "IIO_KX022A"); 1223 1224const struct kx022a_chip_info kx134_chip_info = { 1225 .name = "kx134-1211", 1226 .regmap_config = &kx132_regmap_config, 1227 .channels = kx132_channels, 1228 .num_channels = ARRAY_SIZE(kx132_channels), 1229 .scale_table = kx134acr_lbz_scale_table, 1230 .scale_table_size = ARRAY_SIZE(kx134acr_lbz_scale_table) * 1231 ARRAY_SIZE(kx134acr_lbz_scale_table[0]), 1232 .fifo_length = KX132_FIFO_LENGTH, 1233 .who = KX132_REG_WHO, 1234 .id = KX134_1211_ID, 1235 .cntl = KX132_REG_CNTL, 1236 .cntl2 = KX132_REG_CNTL2, 1237 .odcntl = KX132_REG_ODCNTL, 1238 .buf_cntl1 = KX132_REG_BUF_CNTL1, 1239 .buf_cntl2 = KX132_REG_BUF_CNTL2, 1240 .buf_clear = KX132_REG_BUF_CLEAR, 1241 .buf_status1 = KX132_REG_BUF_STATUS_1, 1242 .buf_smp_lvl_mask = KX132_MASK_BUF_SMP_LVL, 1243 .buf_read = KX132_REG_BUF_READ, 1244 .inc1 = KX132_REG_INC1, 1245 .inc4 = KX132_REG_INC4, 1246 .inc5 = KX132_REG_INC5, 1247 .inc6 = KX132_REG_INC6, 1248 .xout_l = KX132_REG_XOUT_L, 1249 .get_fifo_bytes_available = kx132_get_fifo_bytes_available, 1250}; 1251EXPORT_SYMBOL_NS_GPL(kx134_chip_info, "IIO_KX022A"); 1252 1253/* 1254 * Despite the naming, KX132ACR-LBZ is not similar to KX132-1211 but it is 1255 * exact subset of KX022A. KX132ACR-LBZ is meant to be used for industrial 1256 * applications and the tap/double tap, free fall and tilt engines were 1257 * removed. Rest of the registers and functionalities (excluding the ID 1258 * register) are exact match to what is found in KX022. 1259 */ 1260const struct kx022a_chip_info kx132acr_chip_info = { 1261 .name = "kx132acr-lbz", 1262 .regmap_config = &kx022a_regmap_config, 1263 .channels = kx022a_channels, 1264 .num_channels = ARRAY_SIZE(kx022a_channels), 1265 .scale_table = kx022a_scale_table, 1266 .scale_table_size = ARRAY_SIZE(kx022a_scale_table) * 1267 ARRAY_SIZE(kx022a_scale_table[0]), 1268 .fifo_length = KX022A_FIFO_LENGTH, 1269 .who = KX022A_REG_WHO, 1270 .id = KX132ACR_LBZ_ID, 1271 .cntl = KX022A_REG_CNTL, 1272 .cntl2 = KX022A_REG_CNTL2, 1273 .odcntl = KX022A_REG_ODCNTL, 1274 .buf_cntl1 = KX022A_REG_BUF_CNTL1, 1275 .buf_cntl2 = KX022A_REG_BUF_CNTL2, 1276 .buf_clear = KX022A_REG_BUF_CLEAR, 1277 .buf_status1 = KX022A_REG_BUF_STATUS_1, 1278 .buf_read = KX022A_REG_BUF_READ, 1279 .inc1 = KX022A_REG_INC1, 1280 .inc4 = KX022A_REG_INC4, 1281 .inc5 = KX022A_REG_INC5, 1282 .inc6 = KX022A_REG_INC6, 1283 .xout_l = KX022A_REG_XOUT_L, 1284 .get_fifo_bytes_available = kx022a_get_fifo_bytes_available, 1285}; 1286EXPORT_SYMBOL_NS_GPL(kx132acr_chip_info, "IIO_KX022A"); 1287 1288const struct kx022a_chip_info kx134acr_chip_info = { 1289 .name = "kx134acr-lbz", 1290 .regmap_config = &kx022a_regmap_config, 1291 .channels = kx022a_channels, 1292 .num_channels = ARRAY_SIZE(kx022a_channels), 1293 .scale_table = kx134acr_lbz_scale_table, 1294 .scale_table_size = ARRAY_SIZE(kx134acr_lbz_scale_table) * 1295 ARRAY_SIZE(kx134acr_lbz_scale_table[0]), 1296 .fifo_length = KX022A_FIFO_LENGTH, 1297 .who = KX022A_REG_WHO, 1298 .id = KX134ACR_LBZ_ID, 1299 .cntl = KX022A_REG_CNTL, 1300 .cntl2 = KX022A_REG_CNTL2, 1301 .odcntl = KX022A_REG_ODCNTL, 1302 .buf_cntl1 = KX022A_REG_BUF_CNTL1, 1303 .buf_cntl2 = KX022A_REG_BUF_CNTL2, 1304 .buf_clear = KX022A_REG_BUF_CLEAR, 1305 .buf_status1 = KX022A_REG_BUF_STATUS_1, 1306 .buf_read = KX022A_REG_BUF_READ, 1307 .inc1 = KX022A_REG_INC1, 1308 .inc4 = KX022A_REG_INC4, 1309 .inc5 = KX022A_REG_INC5, 1310 .inc6 = KX022A_REG_INC6, 1311 .xout_l = KX022A_REG_XOUT_L, 1312 .get_fifo_bytes_available = kx022a_get_fifo_bytes_available, 1313}; 1314EXPORT_SYMBOL_NS_GPL(kx134acr_chip_info, "IIO_KX022A"); 1315 1316int kx022a_probe_internal(struct device *dev, const struct kx022a_chip_info *chip_info) 1317{ 1318 static const char * const regulator_names[] = {"io-vdd", "vdd"}; 1319 struct iio_trigger *indio_trig; 1320 struct fwnode_handle *fwnode; 1321 struct kx022a_data *data; 1322 struct regmap *regmap; 1323 unsigned int chip_id; 1324 struct iio_dev *idev; 1325 int ret, irq; 1326 char *name; 1327 1328 regmap = dev_get_regmap(dev, NULL); 1329 if (!regmap) { 1330 dev_err(dev, "no regmap\n"); 1331 return -EINVAL; 1332 } 1333 1334 fwnode = dev_fwnode(dev); 1335 if (!fwnode) 1336 return -ENODEV; 1337 1338 idev = devm_iio_device_alloc(dev, sizeof(*data)); 1339 if (!idev) 1340 return -ENOMEM; 1341 1342 data = iio_priv(idev); 1343 data->chip_info = chip_info; 1344 1345 /* 1346 * VDD is the analog and digital domain voltage supply and 1347 * IO_VDD is the digital I/O voltage supply. 1348 */ 1349 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulator_names), 1350 regulator_names); 1351 if (ret && ret != -ENODEV) 1352 return dev_err_probe(dev, ret, "failed to enable regulator\n"); 1353 1354 ret = regmap_read(regmap, chip_info->who, &chip_id); 1355 if (ret) 1356 return dev_err_probe(dev, ret, "Failed to access sensor\n"); 1357 1358 if (chip_id != chip_info->id) 1359 dev_warn(dev, "unknown device 0x%x\n", chip_id); 1360 1361 irq = fwnode_irq_get_byname(fwnode, "INT1"); 1362 if (irq > 0) { 1363 data->inc_reg = chip_info->inc1; 1364 data->ien_reg = chip_info->inc4; 1365 } else { 1366 irq = fwnode_irq_get_byname(fwnode, "INT2"); 1367 if (irq < 0) 1368 return dev_err_probe(dev, irq, "No suitable IRQ\n"); 1369 1370 data->inc_reg = chip_info->inc5; 1371 data->ien_reg = chip_info->inc6; 1372 } 1373 1374 data->regmap = regmap; 1375 data->dev = dev; 1376 data->irq = irq; 1377 data->odr_ns = KX022A_DEFAULT_PERIOD_NS; 1378 mutex_init(&data->mutex); 1379 1380 idev->channels = chip_info->channels; 1381 idev->num_channels = chip_info->num_channels; 1382 idev->name = chip_info->name; 1383 idev->info = &kx022a_info; 1384 idev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; 1385 idev->available_scan_masks = kx022a_scan_masks; 1386 1387 /* Read the mounting matrix, if present */ 1388 ret = iio_read_mount_matrix(dev, &data->orientation); 1389 if (ret) 1390 return ret; 1391 1392 /* The sensor must be turned off for configuration */ 1393 ret = kx022a_turn_off_lock(data); 1394 if (ret) 1395 return ret; 1396 1397 ret = kx022a_chip_init(data); 1398 if (ret) { 1399 mutex_unlock(&data->mutex); 1400 return ret; 1401 } 1402 1403 ret = kx022a_turn_on_unlock(data); 1404 if (ret) 1405 return ret; 1406 1407 ret = devm_iio_triggered_buffer_setup_ext(dev, idev, 1408 &iio_pollfunc_store_time, 1409 kx022a_trigger_handler, 1410 IIO_BUFFER_DIRECTION_IN, 1411 &kx022a_buffer_ops, 1412 kx022a_fifo_attributes); 1413 1414 if (ret) 1415 return dev_err_probe(data->dev, ret, 1416 "iio_triggered_buffer_setup_ext FAIL\n"); 1417 indio_trig = devm_iio_trigger_alloc(dev, "%sdata-rdy-dev%d", idev->name, 1418 iio_device_id(idev)); 1419 if (!indio_trig) 1420 return -ENOMEM; 1421 1422 data->trig = indio_trig; 1423 1424 indio_trig->ops = &kx022a_trigger_ops; 1425 iio_trigger_set_drvdata(indio_trig, data); 1426 1427 /* 1428 * No need to check for NULL. request_threaded_irq() defaults to 1429 * dev_name() should the alloc fail. 1430 */ 1431 name = devm_kasprintf(data->dev, GFP_KERNEL, "%s-kx022a", 1432 dev_name(data->dev)); 1433 1434 ret = devm_request_threaded_irq(data->dev, irq, kx022a_irq_handler, 1435 &kx022a_irq_thread_handler, 1436 IRQF_ONESHOT, name, idev); 1437 if (ret) 1438 return dev_err_probe(data->dev, ret, "Could not request IRQ\n"); 1439 1440 ret = devm_iio_trigger_register(dev, indio_trig); 1441 if (ret) 1442 return dev_err_probe(data->dev, ret, 1443 "Trigger registration failed\n"); 1444 1445 ret = devm_iio_device_register(data->dev, idev); 1446 if (ret < 0) 1447 return dev_err_probe(dev, ret, 1448 "Unable to register iio device\n"); 1449 1450 return ret; 1451} 1452EXPORT_SYMBOL_NS_GPL(kx022a_probe_internal, "IIO_KX022A"); 1453 1454MODULE_DESCRIPTION("ROHM/Kionix KX022A accelerometer driver"); 1455MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>"); 1456MODULE_LICENSE("GPL");
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