adxl313.h

  1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * ADXL313 3-Axis Digital Accelerometer
  4 *
  5 * Copyright (c) 2021 Lucas Stankus <lucas.p.stankus@gmail.com>
  6 */
  7
  8#ifndef _ADXL313_H_
  9#define _ADXL313_H_
 10
 11#include <linux/iio/iio.h>
 12
 13/* ADXL313 register definitions */
 14#define ADXL313_REG_DEVID0		0x00
 15#define ADXL313_REG_DEVID1		0x01
 16#define ADXL313_REG_PARTID		0x02
 17#define ADXL313_REG_XID			0x04
 18#define ADXL313_REG_SOFT_RESET		0x18
 19#define ADXL313_REG_OFS_AXIS(index)	(0x1E + (index))
 20#define ADXL313_REG_THRESH_ACT		0x24
 21#define ADXL313_REG_THRESH_INACT	0x25
 22#define ADXL313_REG_TIME_INACT		0x26
 23#define ADXL313_REG_ACT_INACT_CTL	0x27
 24#define ADXL313_REG_BW_RATE		0x2C
 25#define ADXL313_REG_POWER_CTL		0x2D
 26#define ADXL313_REG_INT_ENABLE		0x2E
 27#define ADXL313_REG_INT_MAP		0x2F
 28#define ADXL313_REG_INT_SOURCE		0x30
 29#define ADXL313_REG_DATA_FORMAT		0x31
 30#define ADXL313_REG_DATA_AXIS(index)	(0x32 + ((index) * 2))
 31#define ADXL313_REG_FIFO_CTL		0x38
 32#define ADXL313_REG_FIFO_STATUS		0x39
 33
 34#define ADXL313_DEVID0			0xAD
 35#define ADXL313_DEVID0_ADXL312_314	0xE5
 36#define ADXL313_DEVID1			0x1D
 37#define ADXL313_PARTID			0xCB
 38#define ADXL313_SOFT_RESET		0x52
 39
 40#define ADXL313_RATE_MSK		GENMASK(3, 0)
 41#define ADXL313_RATE_BASE		6
 42
 43#define ADXL313_POWER_CTL_MSK		BIT(3)
 44#define ADXL313_POWER_CTL_INACT_MSK	GENMASK(5, 4)
 45#define ADXL313_POWER_CTL_LINK		BIT(5)
 46#define ADXL313_POWER_CTL_AUTO_SLEEP	BIT(4)
 47
 48#define ADXL313_RANGE_MSK		GENMASK(1, 0)
 49#define ADXL313_RANGE_MAX		3
 50
 51#define ADXL313_FULL_RES		BIT(3)
 52#define ADXL313_SPI_3WIRE		BIT(6)
 53#define ADXL313_I2C_DISABLE		BIT(6)
 54
 55#define ADXL313_INT_OVERRUN		BIT(0)
 56#define ADXL313_INT_WATERMARK		BIT(1)
 57#define ADXL313_INT_INACTIVITY		BIT(3)
 58#define ADXL313_INT_ACTIVITY		BIT(4)
 59#define ADXL313_INT_DREADY		BIT(7)
 60
 61/* FIFO entries: how many values are stored in the FIFO */
 62#define ADXL313_REG_FIFO_STATUS_ENTRIES_MSK	GENMASK(5, 0)
 63/* FIFO samples: number of samples needed for watermark (FIFO mode) */
 64#define ADXL313_REG_FIFO_CTL_SAMPLES_MSK	GENMASK(4, 0)
 65#define ADXL313_REG_FIFO_CTL_MODE_MSK		GENMASK(7, 6)
 66
 67#define ADXL313_FIFO_BYPASS			0
 68#define ADXL313_FIFO_STREAM			2
 69
 70#define ADXL313_FIFO_SIZE			32
 71
 72#define ADXL313_NUM_AXIS			3
 73
 74extern const struct regmap_access_table adxl312_readable_regs_table;
 75extern const struct regmap_access_table adxl313_readable_regs_table;
 76extern const struct regmap_access_table adxl314_readable_regs_table;
 77
 78extern const struct regmap_access_table adxl312_writable_regs_table;
 79extern const struct regmap_access_table adxl313_writable_regs_table;
 80extern const struct regmap_access_table adxl314_writable_regs_table;
 81
 82bool adxl313_is_volatile_reg(struct device *dev, unsigned int reg);
 83
 84enum adxl313_device_type {
 85	ADXL312,
 86	ADXL313,
 87	ADXL314,
 88};
 89
 90struct adxl313_data {
 91	struct regmap	*regmap;
 92	const struct adxl313_chip_info *chip_info;
 93	struct mutex	lock; /* lock to protect transf_buf */
 94	u8 watermark;
 95	__le16		transf_buf __aligned(IIO_DMA_MINALIGN);
 96	__le16		fifo_buf[ADXL313_NUM_AXIS * ADXL313_FIFO_SIZE + 1];
 97};
 98
 99struct adxl313_chip_info {
100	const char			*name;
101	enum adxl313_device_type	type;
102	int				scale_factor;
103	bool				variable_range;
104	bool				soft_reset;
105	int (*check_id)(struct device *dev, struct adxl313_data *data);
106};
107
108extern const struct adxl313_chip_info adxl31x_chip_info[];
109
110int adxl313_core_probe(struct device *dev,
111		       struct regmap *regmap,
112		       const struct adxl313_chip_info *chip_info,
113		       int (*setup)(struct device *, struct regmap *));
114#endif /* _ADXL313_H_ */