renesas-i3c.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Renesas I3C Controller driver
   4 * Copyright (C) 2023-25 Renesas Electronics Corp.
   5 *
   6 * TODO: IBI support, HotJoin support, Target support
   7 */
   8
   9#include <linux/bitfield.h>
  10#include <linux/bitops.h>
  11#include <linux/clk.h>
  12#include <linux/completion.h>
  13#include <linux/err.h>
  14#include <linux/errno.h>
  15#include <linux/i2c.h>
  16#include <linux/i3c/master.h>
  17#include <linux/interrupt.h>
  18#include <linux/ioport.h>
  19#include <linux/iopoll.h>
  20#include <linux/list.h>
  21#include <linux/module.h>
  22#include <linux/of.h>
  23#include <linux/platform_device.h>
  24#include <linux/reset.h>
  25#include <linux/slab.h>
  26#include "../internals.h"
  27
  28#define PRTS			0x00
  29#define  PRTS_PRTMD		BIT(0)
  30
  31#define BCTL			0x14
  32#define  BCTL_INCBA		BIT(0)
  33#define  BCTL_HJACKCTL		BIT(8)
  34#define  BCTL_ABT		BIT(29)
  35#define  BCTL_BUSE		BIT(31)
  36
  37#define MSDVAD			0x18
  38#define  MSDVAD_MDYAD(x)	FIELD_PREP(GENMASK(21, 16), x)
  39#define  MSDVAD_MDYADV		BIT(31)
  40
  41#define RSTCTL			0x20
  42#define  RSTCTL_RI3CRST		BIT(0)
  43#define  RSTCTL_INTLRST		BIT(16)
  44
  45#define INST			0x30
  46
  47#define IBINCTL			0x58
  48#define  IBINCTL_NRHJCTL	BIT(0)
  49#define  IBINCTL_NRMRCTL	BIT(1)
  50#define  IBINCTL_NRSIRCTL	BIT(3)
  51
  52#define SVCTL			0x64
  53
  54#define REFCKCTL		0x70
  55#define  REFCKCTL_IREFCKS(x)	FIELD_PREP(GENMASK(2, 0), x)
  56
  57#define STDBR			0x74
  58#define  STDBR_SBRLO(cond, x)	FIELD_PREP(GENMASK(7, 0), (x) >> (cond))
  59#define  STDBR_SBRHO(cond, x)	FIELD_PREP(GENMASK(15, 8), (x) >> (cond))
  60#define  STDBR_SBRLP(x)		FIELD_PREP(GENMASK(21, 16), x)
  61#define  STDBR_SBRHP(x)		FIELD_PREP(GENMASK(29, 24), x)
  62#define  STDBR_DSBRPO		BIT(31)
  63
  64#define EXTBR			0x78
  65#define  EXTBR_EBRLO(x)		FIELD_PREP(GENMASK(7, 0), x)
  66#define  EXTBR_EBRHO(x)		FIELD_PREP(GENMASK(15, 8), x)
  67#define  EXTBR_EBRLP(x)		FIELD_PREP(GENMASK(21, 16), x)
  68#define  EXTBR_EBRHP(x)		FIELD_PREP(GENMASK(29, 24), x)
  69
  70#define BFRECDT			0x7c
  71#define  BFRECDT_FRECYC(x)	FIELD_PREP(GENMASK(8, 0), x)
  72
  73#define BAVLCDT			0x80
  74#define  BAVLCDT_AVLCYC(x)	FIELD_PREP(GENMASK(8, 0), x)
  75
  76#define BIDLCDT			0x84
  77#define  BIDLCDT_IDLCYC(x)	FIELD_PREP(GENMASK(17, 0), x)
  78
  79#define ACKCTL			0xa0
  80#define  ACKCTL_ACKT		BIT(1)
  81#define  ACKCTL_ACKTWP		BIT(2)
  82
  83#define SCSTRCTL		0xa4
  84#define  SCSTRCTL_ACKTWE	BIT(0)
  85#define  SCSTRCTL_RWE		BIT(1)
  86
  87#define SCSTLCTL		0xb0
  88
  89#define CNDCTL			0x140
  90#define  CNDCTL_STCND		BIT(0)
  91#define  CNDCTL_SRCND		BIT(1)
  92#define  CNDCTL_SPCND		BIT(2)
  93
  94#define NCMDQP			0x150 /* Normal Command Queue */
  95#define  NCMDQP_CMD_ATTR(x)	FIELD_PREP(GENMASK(2, 0), x)
  96#define  NCMDQP_IMMED_XFER	0x01
  97#define  NCMDQP_ADDR_ASSGN	0x02
  98#define  NCMDQP_TID(x)		FIELD_PREP(GENMASK(6, 3), x)
  99#define  NCMDQP_CMD(x)		FIELD_PREP(GENMASK(14, 7), x)
 100#define  NCMDQP_CP		BIT(15)
 101#define  NCMDQP_DEV_INDEX(x)	FIELD_PREP(GENMASK(20, 16), x)
 102#define  NCMDQP_BYTE_CNT(x)	FIELD_PREP(GENMASK(25, 23), x)
 103#define  NCMDQP_DEV_COUNT(x)	FIELD_PREP(GENMASK(29, 26), x)
 104#define  NCMDQP_MODE(x)		FIELD_PREP(GENMASK(28, 26), x)
 105#define  NCMDQP_RNW(x)		FIELD_PREP(GENMASK(29, 29), x)
 106#define  NCMDQP_ROC		BIT(30)
 107#define  NCMDQP_TOC		BIT(31)
 108#define  NCMDQP_DATA_LENGTH(x)	FIELD_PREP(GENMASK(31, 16), x)
 109
 110#define NRSPQP			0x154 /* Normal Respone Queue */
 111#define  NRSPQP_NO_ERROR			0
 112#define  NRSPQP_ERROR_CRC		1
 113#define  NRSPQP_ERROR_PARITY		2
 114#define  NRSPQP_ERROR_FRAME		3
 115#define  NRSPQP_ERROR_IBA_NACK		4
 116#define  NRSPQP_ERROR_ADDRESS_NACK	5
 117#define  NRSPQP_ERROR_OVER_UNDER_FLOW	6
 118#define  NRSPQP_ERROR_TRANSF_ABORT	8
 119#define  NRSPQP_ERROR_I2C_W_NACK_ERR	9
 120#define  NRSPQP_ERROR_UNSUPPORTED	10
 121#define  NRSPQP_DATA_LEN(x)	FIELD_GET(GENMASK(15, 0), x)
 122#define  NRSPQP_ERR_STATUS(x)	FIELD_GET(GENMASK(31, 28), x)
 123
 124#define NTDTBP0			0x158 /* Normal Transfer Data Buffer */
 125#define  NTDTBP0_DEPTH		16
 126
 127#define NQTHCTL			0x190
 128#define  NQTHCTL_CMDQTH(x)	FIELD_PREP(GENMASK(1, 0), x)
 129#define  NQTHCTL_IBIDSSZ(x)	FIELD_PREP(GENMASK(23, 16), x)
 130
 131#define NTBTHCTL0		0x194
 132
 133#define NRQTHCTL		0x1c0
 134
 135#define BST			0x1d0
 136#define  BST_STCNDDF		BIT(0)
 137#define  BST_SPCNDDF		BIT(1)
 138#define  BST_NACKDF		BIT(4)
 139#define  BST_TENDF		BIT(8)
 140
 141#define BSTE			0x1d4
 142#define  BSTE_STCNDDE		BIT(0)
 143#define  BSTE_SPCNDDE		BIT(1)
 144#define  BSTE_NACKDE		BIT(4)
 145#define  BSTE_TENDE		BIT(8)
 146#define  BSTE_ALE		BIT(16)
 147#define  BSTE_TODE		BIT(20)
 148#define  BSTE_WUCNDDE		BIT(24)
 149#define  BSTE_ALL_FLAG		(BSTE_STCNDDE | BSTE_SPCNDDE |\
 150				BSTE_NACKDE | BSTE_TENDE |\
 151				BSTE_ALE | BSTE_TODE | BSTE_WUCNDDE)
 152
 153#define BIE			0x1d8
 154#define  BIE_STCNDDIE		BIT(0)
 155#define  BIE_SPCNDDIE		BIT(1)
 156#define  BIE_NACKDIE		BIT(4)
 157#define  BIE_TENDIE		BIT(8)
 158
 159#define NTST			0x1e0
 160#define  NTST_TDBEF0		BIT(0)
 161#define  NTST_RDBFF0		BIT(1)
 162#define  NTST_CMDQEF		BIT(3)
 163#define  NTST_RSPQFF		BIT(4)
 164#define  NTST_TABTF		BIT(5)
 165#define  NTST_TEF		BIT(9)
 166
 167#define NTSTE			0x1e4
 168#define  NTSTE_TDBEE0		BIT(0)
 169#define  NTSTE_RDBFE0		BIT(1)
 170#define  NTSTE_IBIQEFE		BIT(2)
 171#define  NTSTE_CMDQEE		BIT(3)
 172#define  NTSTE_RSPQFE		BIT(4)
 173#define  NTSTE_TABTE		BIT(5)
 174#define  NTSTE_TEE		BIT(9)
 175#define  NTSTE_RSQFE		BIT(20)
 176#define  NTSTE_ALL_FLAG		(NTSTE_TDBEE0 | NTSTE_RDBFE0 |\
 177				NTSTE_IBIQEFE | NTSTE_CMDQEE |\
 178				NTSTE_RSPQFE | NTSTE_TABTE |\
 179				NTSTE_TEE | NTSTE_RSQFE)
 180
 181#define NTIE			0x1e8
 182#define  NTIE_TDBEIE0		BIT(0)
 183#define  NTIE_RDBFIE0		BIT(1)
 184#define  NTIE_IBIQEFIE		BIT(2)
 185#define  NTIE_RSPQFIE		BIT(4)
 186#define  NTIE_RSQFIE		BIT(20)
 187
 188#define BCST			0x210
 189#define  BCST_BFREF		BIT(0)
 190
 191#define DATBAS(x)		(0x224 + 0x8 * (x))
 192#define  DATBAS_DVSTAD(x)	FIELD_PREP(GENMASK(6, 0), x)
 193#define  DATBAS_DVDYAD(x)	FIELD_PREP(GENMASK(23, 16), x)
 194
 195#define NDBSTLV0		0x398
 196#define  NDBSTLV0_RDBLV(x)	FIELD_GET(GENMASK(15, 8), x)
 197
 198#define RENESAS_I3C_MAX_DEVS	8
 199#define I2C_INIT_MSG		-1
 200
 201enum i3c_internal_state {
 202	I3C_INTERNAL_STATE_DISABLED,
 203	I3C_INTERNAL_STATE_CONTROLLER_IDLE,
 204	I3C_INTERNAL_STATE_CONTROLLER_ENTDAA,
 205	I3C_INTERNAL_STATE_CONTROLLER_SETDASA,
 206	I3C_INTERNAL_STATE_CONTROLLER_WRITE,
 207	I3C_INTERNAL_STATE_CONTROLLER_READ,
 208	I3C_INTERNAL_STATE_CONTROLLER_COMMAND_WRITE,
 209	I3C_INTERNAL_STATE_CONTROLLER_COMMAND_READ,
 210};
 211
 212enum renesas_i3c_event {
 213	I3C_COMMAND_ADDRESS_ASSIGNMENT,
 214	I3C_WRITE,
 215	I3C_READ,
 216	I3C_COMMAND_WRITE,
 217	I3C_COMMAND_READ,
 218};
 219
 220struct renesas_i3c_cmd {
 221	u32 cmd0;
 222	u32 len;
 223	const void *tx_buf;
 224	u32 tx_count;
 225	void *rx_buf;
 226	u32 rx_count;
 227	u32 err;
 228	u8 rnw;
 229	/* i2c xfer */
 230	int i2c_bytes_left;
 231	int i2c_is_last;
 232	u8 *i2c_buf;
 233	const struct i2c_msg *msg;
 234};
 235
 236struct renesas_i3c_xfer {
 237	struct list_head node;
 238	struct completion comp;
 239	int ret;
 240	bool is_i2c_xfer;
 241	unsigned int ncmds;
 242	struct renesas_i3c_cmd cmds[] __counted_by(ncmds);
 243};
 244
 245struct renesas_i3c_xferqueue {
 246	struct list_head list;
 247	struct renesas_i3c_xfer *cur;
 248	/* Lock for accessing the xfer queue */
 249	spinlock_t lock;
 250};
 251
 252struct renesas_i3c {
 253	struct i3c_master_controller base;
 254	enum i3c_internal_state internal_state;
 255	u16 maxdevs;
 256	u32 free_pos;
 257	u32 i2c_STDBR;
 258	u32 i3c_STDBR;
 259	u8 addrs[RENESAS_I3C_MAX_DEVS];
 260	struct renesas_i3c_xferqueue xferqueue;
 261	void __iomem *regs;
 262	struct clk *tclk;
 263};
 264
 265struct renesas_i3c_i2c_dev_data {
 266	u8 index;
 267};
 268
 269struct renesas_i3c_irq_desc {
 270	const char *name;
 271	irq_handler_t isr;
 272	const char *desc;
 273};
 274
 275struct renesas_i3c_config {
 276	unsigned int has_pclkrw:1;
 277};
 278
 279static inline void renesas_i3c_reg_update(void __iomem *reg, u32 mask, u32 val)
 280{
 281	u32 data = readl(reg);
 282
 283	data &= ~mask;
 284	data |= (val & mask);
 285	writel(data, reg);
 286}
 287
 288static inline u32 renesas_readl(void __iomem *base, u32 reg)
 289{
 290	return readl(base + reg);
 291}
 292
 293static inline void renesas_writel(void __iomem *base, u32 reg, u32 val)
 294{
 295	writel(val, base + reg);
 296}
 297
 298static void renesas_set_bit(void __iomem *base, u32 reg, u32 val)
 299{
 300	renesas_i3c_reg_update(base + reg, val, val);
 301}
 302
 303static void renesas_clear_bit(void __iomem *base, u32 reg, u32 val)
 304{
 305	renesas_i3c_reg_update(base + reg, val, 0);
 306}
 307
 308static inline struct renesas_i3c *to_renesas_i3c(struct i3c_master_controller *m)
 309{
 310	return container_of(m, struct renesas_i3c, base);
 311}
 312
 313static inline u32 datbas_dvdyad_with_parity(u8 addr)
 314{
 315	return DATBAS_DVDYAD(addr | (parity8(addr) ? 0 : BIT(7)));
 316}
 317
 318static int renesas_i3c_get_free_pos(struct renesas_i3c *i3c)
 319{
 320	if (!(i3c->free_pos & GENMASK(i3c->maxdevs - 1, 0)))
 321		return -ENOSPC;
 322
 323	return ffs(i3c->free_pos) - 1;
 324}
 325
 326static int renesas_i3c_get_addr_pos(struct renesas_i3c *i3c, u8 addr)
 327{
 328	int pos;
 329
 330	for (pos = 0; pos < i3c->maxdevs; pos++) {
 331		if (addr == i3c->addrs[pos])
 332			return pos;
 333	}
 334
 335	return -EINVAL;
 336}
 337
 338static struct renesas_i3c_xfer *renesas_i3c_alloc_xfer(struct renesas_i3c *i3c,
 339						       unsigned int ncmds)
 340{
 341	struct renesas_i3c_xfer *xfer;
 342
 343	xfer = kzalloc(struct_size(xfer, cmds, ncmds), GFP_KERNEL);
 344	if (!xfer)
 345		return NULL;
 346
 347	INIT_LIST_HEAD(&xfer->node);
 348	xfer->ncmds = ncmds;
 349	xfer->ret = -ETIMEDOUT;
 350
 351	return xfer;
 352}
 353
 354static void renesas_i3c_start_xfer_locked(struct renesas_i3c *i3c)
 355{
 356	struct renesas_i3c_xfer *xfer = i3c->xferqueue.cur;
 357	struct renesas_i3c_cmd *cmd;
 358	u32 cmd1;
 359
 360	if (!xfer)
 361		return;
 362
 363	cmd = xfer->cmds;
 364
 365	switch (i3c->internal_state) {
 366	case I3C_INTERNAL_STATE_CONTROLLER_ENTDAA:
 367	case I3C_INTERNAL_STATE_CONTROLLER_SETDASA:
 368		renesas_set_bit(i3c->regs, NTIE, NTIE_RSPQFIE);
 369		renesas_writel(i3c->regs, NCMDQP, cmd->cmd0);
 370		renesas_writel(i3c->regs, NCMDQP, 0);
 371		break;
 372	case I3C_INTERNAL_STATE_CONTROLLER_WRITE:
 373	case I3C_INTERNAL_STATE_CONTROLLER_COMMAND_WRITE:
 374		renesas_set_bit(i3c->regs, NTIE, NTIE_RSPQFIE);
 375		if (cmd->len <= 4) {
 376			cmd->cmd0 |= NCMDQP_CMD_ATTR(NCMDQP_IMMED_XFER);
 377			cmd->cmd0 |= NCMDQP_BYTE_CNT(cmd->len);
 378			cmd->tx_count = cmd->len;
 379			cmd1 = cmd->len == 0 ? 0 : *(u32 *)cmd->tx_buf;
 380		} else {
 381			cmd1 = NCMDQP_DATA_LENGTH(cmd->len);
 382		}
 383		renesas_writel(i3c->regs, NCMDQP, cmd->cmd0);
 384		renesas_writel(i3c->regs, NCMDQP, cmd1);
 385		break;
 386	case I3C_INTERNAL_STATE_CONTROLLER_READ:
 387	case I3C_INTERNAL_STATE_CONTROLLER_COMMAND_READ:
 388		renesas_set_bit(i3c->regs, NTIE, NTIE_RDBFIE0);
 389		cmd1 = NCMDQP_DATA_LENGTH(cmd->len);
 390		renesas_writel(i3c->regs, NCMDQP, cmd->cmd0);
 391		renesas_writel(i3c->regs, NCMDQP, cmd1);
 392		break;
 393	default:
 394		break;
 395	}
 396
 397	/* Clear the command queue empty flag */
 398	renesas_clear_bit(i3c->regs, NTST, NTST_CMDQEF);
 399}
 400
 401static void renesas_i3c_dequeue_xfer_locked(struct renesas_i3c *i3c,
 402					    struct renesas_i3c_xfer *xfer)
 403{
 404	if (i3c->xferqueue.cur == xfer)
 405		i3c->xferqueue.cur = NULL;
 406	else
 407		list_del_init(&xfer->node);
 408}
 409
 410static void renesas_i3c_dequeue_xfer(struct renesas_i3c *i3c, struct renesas_i3c_xfer *xfer)
 411{
 412	scoped_guard(spinlock_irqsave, &i3c->xferqueue.lock)
 413		renesas_i3c_dequeue_xfer_locked(i3c, xfer);
 414}
 415
 416static void renesas_i3c_enqueue_xfer(struct renesas_i3c *i3c, struct renesas_i3c_xfer *xfer)
 417{
 418	reinit_completion(&xfer->comp);
 419	scoped_guard(spinlock_irqsave, &i3c->xferqueue.lock) {
 420		if (i3c->xferqueue.cur) {
 421			list_add_tail(&xfer->node, &i3c->xferqueue.list);
 422		} else {
 423			i3c->xferqueue.cur = xfer;
 424			if (!xfer->is_i2c_xfer)
 425				renesas_i3c_start_xfer_locked(i3c);
 426		}
 427	}
 428}
 429
 430static void renesas_i3c_wait_xfer(struct renesas_i3c *i3c, struct renesas_i3c_xfer *xfer)
 431{
 432	unsigned long time_left;
 433
 434	renesas_i3c_enqueue_xfer(i3c, xfer);
 435
 436	time_left = wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000));
 437	if (!time_left)
 438		renesas_i3c_dequeue_xfer(i3c, xfer);
 439}
 440
 441static void renesas_i3c_set_prts(struct renesas_i3c *i3c, u32 val)
 442{
 443	/* Required sequence according to tnrza0140ae */
 444	renesas_set_bit(i3c->regs, RSTCTL, RSTCTL_INTLRST);
 445	renesas_writel(i3c->regs, PRTS, val);
 446	renesas_clear_bit(i3c->regs, RSTCTL, RSTCTL_INTLRST);
 447}
 448
 449static void renesas_i3c_bus_enable(struct i3c_master_controller *m, bool i3c_mode)
 450{
 451	struct renesas_i3c *i3c = to_renesas_i3c(m);
 452
 453	/* Setup either I3C or I2C protocol */
 454	if (i3c_mode) {
 455		renesas_i3c_set_prts(i3c, 0);
 456		/* Revisit: INCBA handling, especially after I2C transfers */
 457		renesas_set_bit(i3c->regs, BCTL, BCTL_HJACKCTL | BCTL_INCBA);
 458		renesas_set_bit(i3c->regs, MSDVAD, MSDVAD_MDYADV);
 459		renesas_writel(i3c->regs, STDBR, i3c->i3c_STDBR);
 460	} else {
 461		renesas_i3c_set_prts(i3c, PRTS_PRTMD);
 462		renesas_writel(i3c->regs, STDBR, i3c->i2c_STDBR);
 463	}
 464
 465	/* Enable I3C bus */
 466	renesas_set_bit(i3c->regs, BCTL, BCTL_BUSE);
 467}
 468
 469static int renesas_i3c_reset(struct renesas_i3c *i3c)
 470{
 471	u32 val;
 472
 473	renesas_writel(i3c->regs, BCTL, 0);
 474	renesas_set_bit(i3c->regs, RSTCTL, RSTCTL_RI3CRST);
 475
 476	return read_poll_timeout(renesas_readl, val, !(val & RSTCTL_RI3CRST),
 477				 0, 1000, false, i3c->regs, RSTCTL);
 478}
 479
 480static int renesas_i3c_bus_init(struct i3c_master_controller *m)
 481{
 482	struct renesas_i3c *i3c = to_renesas_i3c(m);
 483	struct i3c_bus *bus = i3c_master_get_bus(m);
 484	struct i3c_device_info info = {};
 485	struct i2c_timings t;
 486	unsigned long rate;
 487	u32 double_SBR, val;
 488	int cks, pp_high_ticks, pp_low_ticks, i3c_total_ticks;
 489	int od_high_ticks, od_low_ticks, i2c_total_ticks;
 490	int ret;
 491
 492	rate = clk_get_rate(i3c->tclk);
 493	if (!rate)
 494		return -EINVAL;
 495
 496	ret = renesas_i3c_reset(i3c);
 497	if (ret)
 498		return ret;
 499
 500	i2c_total_ticks = DIV_ROUND_UP(rate, bus->scl_rate.i2c);
 501	i3c_total_ticks = DIV_ROUND_UP(rate, bus->scl_rate.i3c);
 502
 503	i2c_parse_fw_timings(&m->dev, &t, true);
 504
 505	for (cks = 0; cks < 7; cks++) {
 506		/* SCL low-period calculation in Open-drain mode */
 507		od_low_ticks = ((i2c_total_ticks * 6) / 10);
 508
 509		/* SCL clock calculation in Push-Pull mode */
 510		if (bus->mode == I3C_BUS_MODE_PURE)
 511			pp_high_ticks = ((i3c_total_ticks * 5) / 10);
 512		else
 513			pp_high_ticks = DIV_ROUND_UP(I3C_BUS_THIGH_MIXED_MAX_NS,
 514						     NSEC_PER_SEC / rate);
 515		pp_low_ticks = i3c_total_ticks - pp_high_ticks;
 516
 517		if ((od_low_ticks / 2) <= 0xFF && pp_low_ticks < 0x3F)
 518			break;
 519
 520		i2c_total_ticks /= 2;
 521		i3c_total_ticks /= 2;
 522		rate /= 2;
 523	}
 524
 525	/* SCL clock period calculation in Open-drain mode */
 526	if ((od_low_ticks / 2) > 0xFF || pp_low_ticks > 0x3F) {
 527		dev_err(&m->dev, "invalid speed (i2c-scl = %lu Hz, i3c-scl = %lu Hz). Too slow.\n",
 528			(unsigned long)bus->scl_rate.i2c, (unsigned long)bus->scl_rate.i3c);
 529		return -EINVAL;
 530	}
 531
 532	/* SCL high-period calculation in Open-drain mode */
 533	od_high_ticks = i2c_total_ticks - od_low_ticks;
 534
 535	/* Standard Bit Rate setting */
 536	double_SBR = od_low_ticks > 0xFF ? 1 : 0;
 537	i3c->i3c_STDBR = (double_SBR ? STDBR_DSBRPO : 0) |
 538			STDBR_SBRLO(double_SBR, od_low_ticks) |
 539			STDBR_SBRHO(double_SBR, od_high_ticks) |
 540			STDBR_SBRLP(pp_low_ticks) |
 541			STDBR_SBRHP(pp_high_ticks);
 542
 543	od_low_ticks -= t.scl_fall_ns / (NSEC_PER_SEC / rate) + 1;
 544	od_high_ticks -= t.scl_rise_ns / (NSEC_PER_SEC / rate) + 1;
 545	i3c->i2c_STDBR = (double_SBR ? STDBR_DSBRPO : 0) |
 546			STDBR_SBRLO(double_SBR, od_low_ticks) |
 547			STDBR_SBRHO(double_SBR, od_high_ticks) |
 548			STDBR_SBRLP(pp_low_ticks) |
 549			STDBR_SBRHP(pp_high_ticks);
 550	renesas_writel(i3c->regs, STDBR, i3c->i3c_STDBR);
 551
 552	/* Extended Bit Rate setting */
 553	renesas_writel(i3c->regs, EXTBR, EXTBR_EBRLO(od_low_ticks) |
 554					   EXTBR_EBRHO(od_high_ticks) |
 555					   EXTBR_EBRLP(pp_low_ticks) |
 556					   EXTBR_EBRHP(pp_high_ticks));
 557
 558	renesas_writel(i3c->regs, REFCKCTL, REFCKCTL_IREFCKS(cks));
 559
 560	/* Disable Slave Mode */
 561	renesas_writel(i3c->regs, SVCTL, 0);
 562
 563	/* Initialize Queue/Buffer threshold */
 564	renesas_writel(i3c->regs, NQTHCTL, NQTHCTL_IBIDSSZ(6) |
 565					     NQTHCTL_CMDQTH(1));
 566
 567	/* The only supported configuration is two entries*/
 568	renesas_writel(i3c->regs, NTBTHCTL0, 0);
 569	/* Interrupt when there is one entry in the queue */
 570	renesas_writel(i3c->regs, NRQTHCTL, 0);
 571
 572	/* Enable all Bus/Transfer Status Flags */
 573	renesas_writel(i3c->regs, BSTE, BSTE_ALL_FLAG);
 574	renesas_writel(i3c->regs, NTSTE, NTSTE_ALL_FLAG);
 575
 576	/* Interrupt enable settings */
 577	renesas_writel(i3c->regs, BIE, BIE_NACKDIE | BIE_TENDIE);
 578	renesas_writel(i3c->regs, NTIE, 0);
 579
 580	/* Clear Status register */
 581	renesas_writel(i3c->regs, NTST, 0);
 582	renesas_writel(i3c->regs, INST, 0);
 583	renesas_writel(i3c->regs, BST, 0);
 584
 585	/* Hot-Join Acknowlege setting. */
 586	renesas_set_bit(i3c->regs, BCTL, BCTL_HJACKCTL);
 587
 588	renesas_writel(i3c->regs, IBINCTL, IBINCTL_NRHJCTL | IBINCTL_NRMRCTL |
 589					     IBINCTL_NRSIRCTL);
 590
 591	renesas_writel(i3c->regs, SCSTLCTL, 0);
 592	renesas_set_bit(i3c->regs, SCSTRCTL, SCSTRCTL_ACKTWE);
 593
 594	/* Bus condition timing */
 595	val = DIV_ROUND_UP(I3C_BUS_TBUF_MIXED_FM_MIN_NS, NSEC_PER_SEC / rate);
 596	renesas_writel(i3c->regs, BFRECDT, BFRECDT_FRECYC(val));
 597
 598	val = DIV_ROUND_UP(I3C_BUS_TAVAL_MIN_NS, NSEC_PER_SEC / rate);
 599	renesas_writel(i3c->regs, BAVLCDT, BAVLCDT_AVLCYC(val));
 600
 601	val = DIV_ROUND_UP(I3C_BUS_TIDLE_MIN_NS, NSEC_PER_SEC / rate);
 602	renesas_writel(i3c->regs, BIDLCDT, BIDLCDT_IDLCYC(val));
 603
 604	ret = i3c_master_get_free_addr(m, 0);
 605	if (ret < 0)
 606		return ret;
 607
 608	renesas_writel(i3c->regs, MSDVAD, MSDVAD_MDYAD(ret) | MSDVAD_MDYADV);
 609
 610	memset(&info, 0, sizeof(info));
 611	info.dyn_addr = ret;
 612	return i3c_master_set_info(&i3c->base, &info);
 613}
 614
 615static void renesas_i3c_bus_cleanup(struct i3c_master_controller *m)
 616{
 617	struct renesas_i3c *i3c = to_renesas_i3c(m);
 618
 619	renesas_i3c_reset(i3c);
 620}
 621
 622static int renesas_i3c_daa(struct i3c_master_controller *m)
 623{
 624	struct renesas_i3c *i3c = to_renesas_i3c(m);
 625	struct renesas_i3c_cmd *cmd;
 626	u32 olddevs, newdevs;
 627	u8 last_addr = 0, pos;
 628	int ret;
 629
 630	struct renesas_i3c_xfer *xfer __free(kfree) = renesas_i3c_alloc_xfer(i3c, 1);
 631	if (!xfer)
 632		return -ENOMEM;
 633
 634	/* Enable I3C bus. */
 635	renesas_i3c_bus_enable(m, true);
 636
 637	olddevs = ~(i3c->free_pos);
 638	i3c->internal_state = I3C_INTERNAL_STATE_CONTROLLER_ENTDAA;
 639
 640	/* Setting DATBASn registers for target devices. */
 641	for (pos = 0; pos < i3c->maxdevs; pos++) {
 642		if (olddevs & BIT(pos))
 643			continue;
 644
 645		ret = i3c_master_get_free_addr(m, last_addr + 1);
 646		if (ret < 0)
 647			return -ENOSPC;
 648
 649		i3c->addrs[pos] = ret;
 650		last_addr = ret;
 651
 652		renesas_writel(i3c->regs, DATBAS(pos), datbas_dvdyad_with_parity(ret));
 653	}
 654
 655	init_completion(&xfer->comp);
 656	cmd = xfer->cmds;
 657	cmd->rx_count = 0;
 658
 659	ret = renesas_i3c_get_free_pos(i3c);
 660	if (ret < 0)
 661		return ret;
 662
 663	/*
 664	 * Setup the command descriptor to start the ENTDAA command
 665	 * and starting at the selected device index.
 666	 */
 667	cmd->cmd0 = NCMDQP_CMD_ATTR(NCMDQP_ADDR_ASSGN) | NCMDQP_ROC |
 668		    NCMDQP_TID(I3C_COMMAND_ADDRESS_ASSIGNMENT) |
 669		    NCMDQP_CMD(I3C_CCC_ENTDAA) | NCMDQP_DEV_INDEX(ret) |
 670		    NCMDQP_DEV_COUNT(i3c->maxdevs - ret) | NCMDQP_TOC;
 671
 672	renesas_i3c_wait_xfer(i3c, xfer);
 673
 674	newdevs = GENMASK(i3c->maxdevs - cmd->rx_count - 1, 0);
 675	newdevs &= ~olddevs;
 676
 677	for (pos = 0; pos < i3c->maxdevs; pos++) {
 678		if (newdevs & BIT(pos))
 679			i3c_master_add_i3c_dev_locked(m, i3c->addrs[pos]);
 680	}
 681
 682	return 0;
 683}
 684
 685static bool renesas_i3c_supports_ccc_cmd(struct i3c_master_controller *m,
 686						const struct i3c_ccc_cmd *cmd)
 687{
 688	if (cmd->ndests > 1)
 689		return false;
 690
 691	switch (cmd->id) {
 692	case I3C_CCC_ENEC(true):
 693	case I3C_CCC_ENEC(false):
 694	case I3C_CCC_DISEC(true):
 695	case I3C_CCC_DISEC(false):
 696	case I3C_CCC_ENTAS(0, true):
 697	case I3C_CCC_ENTAS(1, true):
 698	case I3C_CCC_ENTAS(2, true):
 699	case I3C_CCC_ENTAS(3, true):
 700	case I3C_CCC_ENTAS(0, false):
 701	case I3C_CCC_ENTAS(1, false):
 702	case I3C_CCC_ENTAS(2, false):
 703	case I3C_CCC_ENTAS(3, false):
 704	case I3C_CCC_RSTDAA(true):
 705	case I3C_CCC_RSTDAA(false):
 706	case I3C_CCC_ENTDAA:
 707	case I3C_CCC_DEFSLVS:
 708	case I3C_CCC_SETMWL(true):
 709	case I3C_CCC_SETMWL(false):
 710	case I3C_CCC_SETMRL(true):
 711	case I3C_CCC_SETMRL(false):
 712	case I3C_CCC_ENTTM:
 713	case I3C_CCC_SETDASA:
 714	case I3C_CCC_SETNEWDA:
 715	case I3C_CCC_GETMWL:
 716	case I3C_CCC_GETMRL:
 717	case I3C_CCC_GETPID:
 718	case I3C_CCC_GETBCR:
 719	case I3C_CCC_GETDCR:
 720	case I3C_CCC_GETSTATUS:
 721	case I3C_CCC_GETACCMST:
 722	case I3C_CCC_GETMXDS:
 723		return true;
 724	default:
 725		return false;
 726	}
 727}
 728
 729static int renesas_i3c_send_ccc_cmd(struct i3c_master_controller *m,
 730					   struct i3c_ccc_cmd *ccc)
 731{
 732	struct renesas_i3c *i3c = to_renesas_i3c(m);
 733	struct renesas_i3c_xfer *xfer;
 734	struct renesas_i3c_cmd *cmd;
 735	int ret, pos = 0;
 736
 737	if (ccc->id & I3C_CCC_DIRECT) {
 738		pos = renesas_i3c_get_addr_pos(i3c, ccc->dests[0].addr);
 739		if (pos < 0)
 740			return pos;
 741	}
 742
 743	xfer = renesas_i3c_alloc_xfer(i3c, 1);
 744	if (!xfer)
 745		return -ENOMEM;
 746
 747	renesas_i3c_bus_enable(m, true);
 748
 749	init_completion(&xfer->comp);
 750	cmd = xfer->cmds;
 751	cmd->rnw = ccc->rnw;
 752	cmd->cmd0 = 0;
 753
 754	/* Calculate the command descriptor. */
 755	switch (ccc->id) {
 756	case I3C_CCC_SETDASA:
 757		renesas_writel(i3c->regs, DATBAS(pos),
 758			DATBAS_DVSTAD(ccc->dests[0].addr) |
 759			DATBAS_DVDYAD(*(u8 *)ccc->dests[0].payload.data >> 1));
 760		cmd->cmd0 = NCMDQP_CMD_ATTR(NCMDQP_ADDR_ASSGN) | NCMDQP_ROC |
 761			NCMDQP_TID(I3C_COMMAND_ADDRESS_ASSIGNMENT) |
 762			NCMDQP_CMD(I3C_CCC_SETDASA) | NCMDQP_DEV_INDEX(pos) |
 763			NCMDQP_DEV_COUNT(0) | NCMDQP_TOC;
 764		i3c->internal_state = I3C_INTERNAL_STATE_CONTROLLER_SETDASA;
 765		break;
 766	default:
 767		/* Calculate the command descriptor. */
 768		cmd->cmd0 = NCMDQP_TID(I3C_COMMAND_WRITE) | NCMDQP_MODE(0) |
 769				NCMDQP_RNW(ccc->rnw) | NCMDQP_CMD(ccc->id) |
 770				NCMDQP_ROC | NCMDQP_TOC | NCMDQP_CP |
 771				NCMDQP_DEV_INDEX(pos);
 772
 773		if (ccc->rnw) {
 774			cmd->rx_buf = ccc->dests[0].payload.data;
 775			cmd->len = ccc->dests[0].payload.len;
 776			cmd->rx_count = 0;
 777			i3c->internal_state = I3C_INTERNAL_STATE_CONTROLLER_COMMAND_READ;
 778		} else {
 779			cmd->tx_buf = ccc->dests[0].payload.data;
 780			cmd->len = ccc->dests[0].payload.len;
 781			cmd->tx_count = 0;
 782			i3c->internal_state = I3C_INTERNAL_STATE_CONTROLLER_COMMAND_WRITE;
 783		}
 784	}
 785
 786	renesas_i3c_wait_xfer(i3c, xfer);
 787
 788	ret = xfer->ret;
 789	if (ret)
 790		ccc->err = I3C_ERROR_M2;
 791
 792	kfree(xfer);
 793
 794	return ret;
 795}
 796
 797static int renesas_i3c_i3c_xfers(struct i3c_dev_desc *dev, struct i3c_xfer *i3c_xfers,
 798				 int i3c_nxfers, enum i3c_xfer_mode mode)
 799{
 800	struct i3c_master_controller *m = i3c_dev_get_master(dev);
 801	struct renesas_i3c *i3c = to_renesas_i3c(m);
 802	struct renesas_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
 803	struct renesas_i3c_xfer *xfer;
 804	int i;
 805
 806	/* Enable I3C bus. */
 807	renesas_i3c_bus_enable(m, true);
 808
 809	xfer = renesas_i3c_alloc_xfer(i3c, 1);
 810	if (!xfer)
 811		return -ENOMEM;
 812
 813	init_completion(&xfer->comp);
 814
 815	for (i = 0; i < i3c_nxfers; i++) {
 816		struct renesas_i3c_cmd *cmd = xfer->cmds;
 817
 818		/* Calculate the Transfer Command Descriptor */
 819		cmd->rnw = i3c_xfers[i].rnw;
 820		cmd->cmd0 = NCMDQP_DEV_INDEX(data->index) | NCMDQP_MODE(0) |
 821			    NCMDQP_RNW(cmd->rnw) | NCMDQP_ROC | NCMDQP_TOC;
 822
 823		if (i3c_xfers[i].rnw) {
 824			cmd->rx_count = 0;
 825			cmd->cmd0 |= NCMDQP_TID(I3C_READ);
 826			cmd->rx_buf = i3c_xfers[i].data.in;
 827			cmd->len = i3c_xfers[i].len;
 828			i3c->internal_state = I3C_INTERNAL_STATE_CONTROLLER_READ;
 829		} else {
 830			cmd->tx_count = 0;
 831			cmd->cmd0 |= NCMDQP_TID(I3C_WRITE);
 832			cmd->tx_buf = i3c_xfers[i].data.out;
 833			cmd->len = i3c_xfers[i].len;
 834			i3c->internal_state = I3C_INTERNAL_STATE_CONTROLLER_WRITE;
 835		}
 836
 837		if (!i3c_xfers[i].rnw && i3c_xfers[i].len > 4) {
 838			i3c_writel_fifo(i3c->regs + NTDTBP0, cmd->tx_buf, cmd->len);
 839			if (cmd->len > NTDTBP0_DEPTH * sizeof(u32))
 840				renesas_set_bit(i3c->regs, NTIE, NTIE_TDBEIE0);
 841		}
 842
 843		renesas_i3c_wait_xfer(i3c, xfer);
 844	}
 845
 846	return 0;
 847}
 848
 849static int renesas_i3c_attach_i3c_dev(struct i3c_dev_desc *dev)
 850{
 851	struct i3c_master_controller *m = i3c_dev_get_master(dev);
 852	struct renesas_i3c *i3c = to_renesas_i3c(m);
 853	struct renesas_i3c_i2c_dev_data *data;
 854	int pos;
 855
 856	pos = renesas_i3c_get_free_pos(i3c);
 857	if (pos < 0)
 858		return pos;
 859
 860	data = kzalloc(sizeof(*data), GFP_KERNEL);
 861	if (!data)
 862		return -ENOMEM;
 863
 864	data->index = pos;
 865	i3c->addrs[pos] = dev->info.dyn_addr ? : dev->info.static_addr;
 866	i3c->free_pos &= ~BIT(pos);
 867
 868	renesas_writel(i3c->regs, DATBAS(pos), DATBAS_DVSTAD(dev->info.static_addr) |
 869				    datbas_dvdyad_with_parity(i3c->addrs[pos]));
 870	i3c_dev_set_master_data(dev, data);
 871
 872	return 0;
 873}
 874
 875static int renesas_i3c_reattach_i3c_dev(struct i3c_dev_desc *dev,
 876					       u8 old_dyn_addr)
 877{
 878	struct i3c_master_controller *m = i3c_dev_get_master(dev);
 879	struct renesas_i3c *i3c = to_renesas_i3c(m);
 880	struct renesas_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
 881
 882	i3c->addrs[data->index] = dev->info.dyn_addr ? dev->info.dyn_addr :
 883							dev->info.static_addr;
 884
 885	return 0;
 886}
 887
 888static void renesas_i3c_detach_i3c_dev(struct i3c_dev_desc *dev)
 889{
 890	struct renesas_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev);
 891	struct i3c_master_controller *m = i3c_dev_get_master(dev);
 892	struct renesas_i3c *i3c = to_renesas_i3c(m);
 893
 894	i3c_dev_set_master_data(dev, NULL);
 895	i3c->addrs[data->index] = 0;
 896	i3c->free_pos |= BIT(data->index);
 897	kfree(data);
 898}
 899
 900static int renesas_i3c_i2c_xfers(struct i2c_dev_desc *dev,
 901					struct i2c_msg *i2c_xfers,
 902					int i2c_nxfers)
 903{
 904	struct i3c_master_controller *m = i2c_dev_get_master(dev);
 905	struct renesas_i3c *i3c = to_renesas_i3c(m);
 906	struct renesas_i3c_cmd *cmd;
 907	u8 start_bit = CNDCTL_STCND;
 908	int i;
 909
 910	struct renesas_i3c_xfer *xfer __free(kfree) = renesas_i3c_alloc_xfer(i3c, 1);
 911	if (!xfer)
 912		return -ENOMEM;
 913
 914	if (!i2c_nxfers)
 915		return 0;
 916
 917	renesas_i3c_bus_enable(m, false);
 918
 919	init_completion(&xfer->comp);
 920	xfer->is_i2c_xfer = true;
 921	cmd = xfer->cmds;
 922
 923	if (!(renesas_readl(i3c->regs, BCST) & BCST_BFREF)) {
 924		cmd->err = -EBUSY;
 925		return cmd->err;
 926	}
 927
 928	renesas_writel(i3c->regs, BST, 0);
 929
 930	renesas_i3c_enqueue_xfer(i3c, xfer);
 931
 932	for (i = 0; i < i2c_nxfers; i++) {
 933		cmd->i2c_bytes_left = I2C_INIT_MSG;
 934		cmd->i2c_buf = i2c_xfers[i].buf;
 935		cmd->msg = &i2c_xfers[i];
 936		cmd->i2c_is_last = (i == i2c_nxfers - 1);
 937
 938		renesas_set_bit(i3c->regs, BIE, BIE_NACKDIE);
 939		renesas_set_bit(i3c->regs, NTIE, NTIE_TDBEIE0);
 940		renesas_set_bit(i3c->regs, BIE, BIE_STCNDDIE);
 941
 942		/* Issue Start condition */
 943		renesas_set_bit(i3c->regs, CNDCTL, start_bit);
 944
 945		renesas_set_bit(i3c->regs, NTSTE, NTSTE_TDBEE0);
 946
 947		wait_for_completion_timeout(&xfer->comp, m->i2c.timeout);
 948
 949		if (cmd->err)
 950			break;
 951
 952		start_bit = CNDCTL_SRCND;
 953	}
 954
 955	renesas_i3c_dequeue_xfer(i3c, xfer);
 956	return cmd->err;
 957}
 958
 959static int renesas_i3c_attach_i2c_dev(struct i2c_dev_desc *dev)
 960{
 961	struct i3c_master_controller *m = i2c_dev_get_master(dev);
 962	struct renesas_i3c *i3c = to_renesas_i3c(m);
 963	struct renesas_i3c_i2c_dev_data *data;
 964	int pos;
 965
 966	pos = renesas_i3c_get_free_pos(i3c);
 967	if (pos < 0)
 968		return pos;
 969
 970	data = kzalloc(sizeof(*data), GFP_KERNEL);
 971	if (!data)
 972		return -ENOMEM;
 973
 974	data->index = pos;
 975	i3c->addrs[pos] = dev->addr;
 976	i3c->free_pos &= ~BIT(pos);
 977	i2c_dev_set_master_data(dev, data);
 978
 979	return 0;
 980}
 981
 982static void renesas_i3c_detach_i2c_dev(struct i2c_dev_desc *dev)
 983{
 984	struct renesas_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev);
 985	struct i3c_master_controller *m = i2c_dev_get_master(dev);
 986	struct renesas_i3c *i3c = to_renesas_i3c(m);
 987
 988	i2c_dev_set_master_data(dev, NULL);
 989	i3c->addrs[data->index] = 0;
 990	i3c->free_pos |= BIT(data->index);
 991	kfree(data);
 992}
 993
 994static irqreturn_t renesas_i3c_tx_isr(int irq, void *data)
 995{
 996	struct renesas_i3c *i3c = data;
 997	struct renesas_i3c_xfer *xfer;
 998	struct renesas_i3c_cmd *cmd;
 999	u8 val;
1000
1001	scoped_guard(spinlock, &i3c->xferqueue.lock) {
1002		xfer = i3c->xferqueue.cur;
1003		cmd = xfer->cmds;
1004
1005		if (xfer->is_i2c_xfer) {
1006			if (!cmd->i2c_bytes_left)
1007				return IRQ_NONE;
1008
1009			if (cmd->i2c_bytes_left != I2C_INIT_MSG) {
1010				val = *cmd->i2c_buf;
1011				cmd->i2c_buf++;
1012				cmd->i2c_bytes_left--;
1013				renesas_writel(i3c->regs, NTDTBP0, val);
1014			}
1015
1016			if (cmd->i2c_bytes_left == 0) {
1017				renesas_clear_bit(i3c->regs, NTIE, NTIE_TDBEIE0);
1018				renesas_set_bit(i3c->regs, BIE, BIE_TENDIE);
1019			}
1020
1021			/* Clear the Transmit Buffer Empty status flag. */
1022			renesas_clear_bit(i3c->regs, NTST, NTST_TDBEF0);
1023		} else {
1024			i3c_writel_fifo(i3c->regs + NTDTBP0, cmd->tx_buf, cmd->len);
1025		}
1026	}
1027
1028	return IRQ_HANDLED;
1029}
1030
1031static irqreturn_t renesas_i3c_resp_isr(int irq, void *data)
1032{
1033	struct renesas_i3c *i3c = data;
1034	struct renesas_i3c_xfer *xfer;
1035	struct renesas_i3c_cmd *cmd;
1036	u32 resp_descriptor = renesas_readl(i3c->regs, NRSPQP);
1037	u32 bytes_remaining = 0;
1038	u32 ntst, data_len;
1039	int ret = 0;
1040
1041	scoped_guard(spinlock, &i3c->xferqueue.lock) {
1042		xfer = i3c->xferqueue.cur;
1043		cmd = xfer->cmds;
1044
1045		/* Clear the Respone Queue Full status flag*/
1046		renesas_clear_bit(i3c->regs, NTST, NTST_RSPQFF);
1047
1048		data_len = NRSPQP_DATA_LEN(resp_descriptor);
1049
1050		switch (i3c->internal_state) {
1051		case I3C_INTERNAL_STATE_CONTROLLER_ENTDAA:
1052			cmd->rx_count = data_len;
1053			break;
1054		case I3C_INTERNAL_STATE_CONTROLLER_WRITE:
1055		case I3C_INTERNAL_STATE_CONTROLLER_COMMAND_WRITE:
1056			/* Disable the transmit IRQ if it hasn't been disabled already. */
1057			renesas_clear_bit(i3c->regs, NTIE, NTIE_TDBEIE0);
1058			break;
1059		case I3C_INTERNAL_STATE_CONTROLLER_READ:
1060		case I3C_INTERNAL_STATE_CONTROLLER_COMMAND_READ:
1061			if (NDBSTLV0_RDBLV(renesas_readl(i3c->regs, NDBSTLV0)) && !cmd->err)
1062				bytes_remaining = data_len - cmd->rx_count;
1063
1064			i3c_readl_fifo(i3c->regs + NTDTBP0, cmd->rx_buf, bytes_remaining);
1065			renesas_clear_bit(i3c->regs, NTIE, NTIE_RDBFIE0);
1066			break;
1067		default:
1068			break;
1069		}
1070
1071		switch (NRSPQP_ERR_STATUS(resp_descriptor)) {
1072		case NRSPQP_NO_ERROR:
1073			break;
1074		case NRSPQP_ERROR_PARITY:
1075		case NRSPQP_ERROR_IBA_NACK:
1076		case NRSPQP_ERROR_TRANSF_ABORT:
1077		case NRSPQP_ERROR_CRC:
1078		case NRSPQP_ERROR_FRAME:
1079			ret = -EIO;
1080			break;
1081		case NRSPQP_ERROR_OVER_UNDER_FLOW:
1082			ret = -ENOSPC;
1083			break;
1084		case NRSPQP_ERROR_UNSUPPORTED:
1085			ret = -EOPNOTSUPP;
1086			break;
1087		case NRSPQP_ERROR_I2C_W_NACK_ERR:
1088		case NRSPQP_ERROR_ADDRESS_NACK:
1089		default:
1090			ret = -EINVAL;
1091			break;
1092		}
1093
1094		/*
1095		 * If the transfer was aborted, then the abort flag must be cleared
1096		 * before notifying the application that a transfer has completed.
1097		 */
1098		ntst = renesas_readl(i3c->regs, NTST);
1099		if (ntst & NTST_TABTF)
1100			renesas_clear_bit(i3c->regs, BCTL, BCTL_ABT);
1101
1102		/* Clear error status flags. */
1103		renesas_clear_bit(i3c->regs, NTST, NTST_TEF | NTST_TABTF);
1104
1105		xfer->ret = ret;
1106		complete(&xfer->comp);
1107
1108		xfer = list_first_entry_or_null(&i3c->xferqueue.list,
1109						struct renesas_i3c_xfer, node);
1110		if (xfer)
1111			list_del_init(&xfer->node);
1112
1113		i3c->xferqueue.cur = xfer;
1114	}
1115
1116	return IRQ_HANDLED;
1117}
1118
1119static irqreturn_t renesas_i3c_tend_isr(int irq, void *data)
1120{
1121	struct renesas_i3c *i3c = data;
1122	struct renesas_i3c_xfer *xfer;
1123	struct renesas_i3c_cmd *cmd;
1124
1125	scoped_guard(spinlock, &i3c->xferqueue.lock) {
1126		xfer = i3c->xferqueue.cur;
1127		cmd = xfer->cmds;
1128
1129		if (xfer->is_i2c_xfer) {
1130			if (renesas_readl(i3c->regs, BST) & BST_NACKDF) {
1131				/* We got a NACKIE */
1132				renesas_readl(i3c->regs, NTDTBP0); /* dummy read */
1133				renesas_clear_bit(i3c->regs, BST, BST_NACKDF);
1134				cmd->err = -ENXIO;
1135			} else if (cmd->i2c_bytes_left) {
1136				renesas_set_bit(i3c->regs, NTIE, NTIE_TDBEIE0);
1137				return IRQ_NONE;
1138			}
1139
1140			if (cmd->i2c_is_last || cmd->err) {
1141				renesas_clear_bit(i3c->regs, BIE, BIE_TENDIE);
1142				renesas_set_bit(i3c->regs, BIE, BIE_SPCNDDIE);
1143				renesas_set_bit(i3c->regs, CNDCTL, CNDCTL_SPCND);
1144			} else {
1145				/* Transfer is complete, but do not send STOP */
1146				renesas_clear_bit(i3c->regs, NTSTE, NTSTE_TDBEE0);
1147				renesas_clear_bit(i3c->regs, BIE, BIE_TENDIE);
1148				xfer->ret = 0;
1149				complete(&xfer->comp);
1150			}
1151		}
1152
1153		/* Clear the Transmit Buffer Empty status flag. */
1154		renesas_clear_bit(i3c->regs, BST, BST_TENDF);
1155	}
1156
1157	return IRQ_HANDLED;
1158}
1159
1160static irqreturn_t renesas_i3c_rx_isr(int irq, void *data)
1161{
1162	struct renesas_i3c *i3c = data;
1163	struct renesas_i3c_xfer *xfer;
1164	struct renesas_i3c_cmd *cmd;
1165	int read_bytes;
1166
1167	/* If resp_isr already read the data and updated 'xfer', we can just leave */
1168	if (!(renesas_readl(i3c->regs, NTIE) & NTIE_RDBFIE0))
1169		return IRQ_NONE;
1170
1171	scoped_guard(spinlock, &i3c->xferqueue.lock) {
1172		xfer = i3c->xferqueue.cur;
1173		cmd = xfer->cmds;
1174
1175		if (xfer->is_i2c_xfer) {
1176			if (!cmd->i2c_bytes_left)
1177				return IRQ_NONE;
1178
1179			if (cmd->i2c_bytes_left == I2C_INIT_MSG) {
1180				cmd->i2c_bytes_left = cmd->msg->len;
1181				renesas_set_bit(i3c->regs, SCSTRCTL, SCSTRCTL_RWE);
1182				renesas_readl(i3c->regs, NTDTBP0); /* dummy read */
1183				if (cmd->i2c_bytes_left == 1)
1184					renesas_writel(i3c->regs, ACKCTL, ACKCTL_ACKT | ACKCTL_ACKTWP);
1185				return IRQ_HANDLED;
1186			}
1187
1188			if (cmd->i2c_bytes_left == 1) {
1189				/* STOP must come before we set ACKCTL! */
1190				if (cmd->i2c_is_last) {
1191					renesas_set_bit(i3c->regs, BIE, BIE_SPCNDDIE);
1192					renesas_clear_bit(i3c->regs, BST, BST_SPCNDDF);
1193					renesas_set_bit(i3c->regs, CNDCTL, CNDCTL_SPCND);
1194				}
1195				renesas_writel(i3c->regs, ACKCTL, ACKCTL_ACKT | ACKCTL_ACKTWP);
1196			} else {
1197				renesas_writel(i3c->regs, ACKCTL, ACKCTL_ACKTWP);
1198			}
1199
1200			/* Reading acks the RIE interrupt */
1201			*cmd->i2c_buf = renesas_readl(i3c->regs, NTDTBP0);
1202			cmd->i2c_buf++;
1203			cmd->i2c_bytes_left--;
1204		} else {
1205			read_bytes = NDBSTLV0_RDBLV(renesas_readl(i3c->regs, NDBSTLV0)) * sizeof(u32);
1206			i3c_readl_fifo(i3c->regs + NTDTBP0, cmd->rx_buf, read_bytes);
1207			cmd->rx_count = read_bytes;
1208		}
1209
1210		/* Clear the Read Buffer Full status flag. */
1211		renesas_clear_bit(i3c->regs, NTST, NTST_RDBFF0);
1212	}
1213
1214	return IRQ_HANDLED;
1215}
1216
1217static irqreturn_t renesas_i3c_stop_isr(int irq, void *data)
1218{
1219	struct renesas_i3c *i3c = data;
1220	struct renesas_i3c_xfer *xfer;
1221
1222	scoped_guard(spinlock, &i3c->xferqueue.lock) {
1223		xfer = i3c->xferqueue.cur;
1224
1225		/* read back registers to confirm writes have fully propagated */
1226		renesas_writel(i3c->regs, BST, 0);
1227		renesas_readl(i3c->regs, BST);
1228		renesas_writel(i3c->regs, BIE, 0);
1229		renesas_clear_bit(i3c->regs, NTST, NTST_TDBEF0 | NTST_RDBFF0);
1230		renesas_clear_bit(i3c->regs, SCSTRCTL, SCSTRCTL_RWE);
1231
1232		xfer->ret = 0;
1233		complete(&xfer->comp);
1234	}
1235
1236	return IRQ_HANDLED;
1237}
1238
1239static irqreturn_t renesas_i3c_start_isr(int irq, void *data)
1240{
1241	struct renesas_i3c *i3c = data;
1242	struct renesas_i3c_xfer *xfer;
1243	struct renesas_i3c_cmd *cmd;
1244	u8 val;
1245
1246	scoped_guard(spinlock, &i3c->xferqueue.lock) {
1247		xfer = i3c->xferqueue.cur;
1248		cmd = xfer->cmds;
1249
1250		if (xfer->is_i2c_xfer) {
1251			if (!cmd->i2c_bytes_left)
1252				return IRQ_NONE;
1253
1254			if (cmd->i2c_bytes_left == I2C_INIT_MSG) {
1255				if (cmd->msg->flags & I2C_M_RD) {
1256					/* On read, switch over to receive interrupt */
1257					renesas_clear_bit(i3c->regs, NTIE, NTIE_TDBEIE0);
1258					renesas_set_bit(i3c->regs, NTIE, NTIE_RDBFIE0);
1259				} else {
1260					/* On write, initialize length */
1261					cmd->i2c_bytes_left = cmd->msg->len;
1262				}
1263
1264				val = i2c_8bit_addr_from_msg(cmd->msg);
1265				renesas_writel(i3c->regs, NTDTBP0, val);
1266			}
1267		}
1268
1269		renesas_clear_bit(i3c->regs, BIE, BIE_STCNDDIE);
1270		renesas_clear_bit(i3c->regs, BST, BST_STCNDDF);
1271	}
1272
1273	return IRQ_HANDLED;
1274}
1275
1276static const struct i3c_master_controller_ops renesas_i3c_ops = {
1277	.bus_init = renesas_i3c_bus_init,
1278	.bus_cleanup = renesas_i3c_bus_cleanup,
1279	.attach_i3c_dev = renesas_i3c_attach_i3c_dev,
1280	.reattach_i3c_dev = renesas_i3c_reattach_i3c_dev,
1281	.detach_i3c_dev = renesas_i3c_detach_i3c_dev,
1282	.do_daa = renesas_i3c_daa,
1283	.supports_ccc_cmd = renesas_i3c_supports_ccc_cmd,
1284	.send_ccc_cmd = renesas_i3c_send_ccc_cmd,
1285	.i3c_xfers = renesas_i3c_i3c_xfers,
1286	.attach_i2c_dev = renesas_i3c_attach_i2c_dev,
1287	.detach_i2c_dev = renesas_i3c_detach_i2c_dev,
1288	.i2c_xfers = renesas_i3c_i2c_xfers,
1289};
1290
1291static const struct renesas_i3c_irq_desc renesas_i3c_irqs[] = {
1292	{ .name = "resp", .isr = renesas_i3c_resp_isr, .desc = "i3c-resp" },
1293	{ .name = "rx", .isr = renesas_i3c_rx_isr, .desc = "i3c-rx" },
1294	{ .name = "tx", .isr = renesas_i3c_tx_isr, .desc = "i3c-tx" },
1295	{ .name = "st", .isr = renesas_i3c_start_isr, .desc = "i3c-start" },
1296	{ .name = "sp", .isr = renesas_i3c_stop_isr, .desc = "i3c-stop" },
1297	{ .name = "tend", .isr = renesas_i3c_tend_isr, .desc = "i3c-tend" },
1298	{ .name = "nack", .isr = renesas_i3c_tend_isr, .desc = "i3c-nack" },
1299};
1300
1301static int renesas_i3c_probe(struct platform_device *pdev)
1302{
1303	struct renesas_i3c *i3c;
1304	struct reset_control *reset;
1305	struct clk *clk;
1306	const struct renesas_i3c_config *config = of_device_get_match_data(&pdev->dev);
1307	int ret, i;
1308
1309	if (!config)
1310		return -ENODATA;
1311
1312	i3c = devm_kzalloc(&pdev->dev, sizeof(*i3c), GFP_KERNEL);
1313	if (!i3c)
1314		return -ENOMEM;
1315
1316	i3c->regs = devm_platform_ioremap_resource(pdev, 0);
1317	if (IS_ERR(i3c->regs))
1318		return PTR_ERR(i3c->regs);
1319
1320	clk = devm_clk_get_enabled(&pdev->dev, "pclk");
1321	if (IS_ERR(clk))
1322		return PTR_ERR(clk);
1323
1324	if (config->has_pclkrw) {
1325		clk = devm_clk_get_enabled(&pdev->dev, "pclkrw");
1326		if (IS_ERR(clk))
1327			return PTR_ERR(clk);
1328	}
1329
1330	i3c->tclk = devm_clk_get_enabled(&pdev->dev, "tclk");
1331	if (IS_ERR(i3c->tclk))
1332		return PTR_ERR(i3c->tclk);
1333
1334	reset = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, "tresetn");
1335	if (IS_ERR(reset))
1336		return dev_err_probe(&pdev->dev, PTR_ERR(reset),
1337				     "Error: missing tresetn ctrl\n");
1338
1339	reset = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, "presetn");
1340	if (IS_ERR(reset))
1341		return dev_err_probe(&pdev->dev, PTR_ERR(reset),
1342				     "Error: missing presetn ctrl\n");
1343
1344	spin_lock_init(&i3c->xferqueue.lock);
1345	INIT_LIST_HEAD(&i3c->xferqueue.list);
1346
1347	ret = renesas_i3c_reset(i3c);
1348	if (ret)
1349		return ret;
1350
1351	for (i = 0; i < ARRAY_SIZE(renesas_i3c_irqs); i++) {
1352		ret = platform_get_irq_byname(pdev, renesas_i3c_irqs[i].name);
1353		if (ret < 0)
1354			return ret;
1355
1356		ret = devm_request_irq(&pdev->dev, ret, renesas_i3c_irqs[i].isr,
1357				       0, renesas_i3c_irqs[i].desc, i3c);
1358		if (ret)
1359			return ret;
1360	}
1361
1362	platform_set_drvdata(pdev, i3c);
1363
1364	i3c->maxdevs = RENESAS_I3C_MAX_DEVS;
1365	i3c->free_pos = GENMASK(i3c->maxdevs - 1, 0);
1366
1367	return i3c_master_register(&i3c->base, &pdev->dev, &renesas_i3c_ops, false);
1368}
1369
1370static void renesas_i3c_remove(struct platform_device *pdev)
1371{
1372	struct renesas_i3c *i3c = platform_get_drvdata(pdev);
1373
1374	i3c_master_unregister(&i3c->base);
1375}
1376
1377static const struct renesas_i3c_config empty_i3c_config = {
1378};
1379
1380static const struct renesas_i3c_config r9a09g047_i3c_config = {
1381	.has_pclkrw = 1,
1382};
1383
1384static const struct of_device_id renesas_i3c_of_ids[] = {
1385	{ .compatible = "renesas,r9a08g045-i3c", .data = &empty_i3c_config },
1386	{ .compatible = "renesas,r9a09g047-i3c", .data = &r9a09g047_i3c_config },
1387	{ /* sentinel */ },
1388};
1389MODULE_DEVICE_TABLE(of, renesas_i3c_of_ids);
1390
1391static struct platform_driver renesas_i3c = {
1392	.probe = renesas_i3c_probe,
1393	.remove = renesas_i3c_remove,
1394	.driver = {
1395		.name = "renesas-i3c",
1396		.of_match_table = renesas_i3c_of_ids,
1397	},
1398};
1399module_platform_driver(renesas_i3c);
1400
1401MODULE_AUTHOR("Wolfram Sang <wsa+renesas@sang-engineering.com>");
1402MODULE_AUTHOR("Renesas BSP teams");
1403MODULE_DESCRIPTION("Renesas I3C controller driver");
1404MODULE_LICENSE("GPL");