hci.h

  1/* SPDX-License-Identifier: BSD-3-Clause */
  2/*
  3 * Copyright (c) 2020, MIPI Alliance, Inc.
  4 *
  5 * Author: Nicolas Pitre <npitre@baylibre.com>
  6 *
  7 * Common HCI stuff
  8 */
  9
 10#ifndef HCI_H
 11#define HCI_H
 12
 13#include <linux/io.h>
 14
 15/* 32-bit word aware bit and mask macros */
 16#define W0_MASK(h, l)  GENMASK((h) - 0,  (l) - 0)
 17#define W1_MASK(h, l)  GENMASK((h) - 32, (l) - 32)
 18#define W2_MASK(h, l)  GENMASK((h) - 64, (l) - 64)
 19#define W3_MASK(h, l)  GENMASK((h) - 96, (l) - 96)
 20
 21/* Same for single bit macros (trailing _ to align with W*_MASK width) */
 22#define W0_BIT_(x)  BIT((x) - 0)
 23#define W1_BIT_(x)  BIT((x) - 32)
 24#define W2_BIT_(x)  BIT((x) - 64)
 25#define W3_BIT_(x)  BIT((x) - 96)
 26
 27#define reg_read(r)		readl(hci->base_regs + (r))
 28#define reg_write(r, v)		writel(v, hci->base_regs + (r))
 29#define reg_set(r, v)		reg_write(r, reg_read(r) | (v))
 30#define reg_clear(r, v)		reg_write(r, reg_read(r) & ~(v))
 31
 32struct hci_cmd_ops;
 33
 34/* Our main structure */
 35struct i3c_hci {
 36	struct i3c_master_controller master;
 37	void __iomem *base_regs;
 38	void __iomem *DAT_regs;
 39	void __iomem *DCT_regs;
 40	void __iomem *RHS_regs;
 41	void __iomem *PIO_regs;
 42	void __iomem *EXTCAPS_regs;
 43	void __iomem *AUTOCMD_regs;
 44	void __iomem *DEBUG_regs;
 45	const struct hci_io_ops *io;
 46	void *io_data;
 47	const struct hci_cmd_ops *cmd;
 48	spinlock_t lock;
 49	struct mutex control_mutex;
 50	atomic_t next_cmd_tid;
 51	u32 caps;
 52	unsigned int quirks;
 53	unsigned int DAT_entries;
 54	unsigned int DAT_entry_size;
 55	void *DAT_data;
 56	unsigned int DCT_entries;
 57	unsigned int DCT_entry_size;
 58	u8 version_major;
 59	u8 version_minor;
 60	u8 revision;
 61	u32 vendor_mipi_id;
 62	u32 vendor_version_id;
 63	u32 vendor_product_id;
 64	void *vendor_data;
 65};
 66
 67
 68/*
 69 * Structure to represent a master initiated transfer.
 70 * The rnw, data and data_len fields must be initialized before calling any
 71 * hci->cmd->*() method. The cmd method will initialize cmd_desc[] and
 72 * possibly modify (clear) the data field. Then xfer->cmd_desc[0] can
 73 * be augmented with CMD_0_ROC and/or CMD_0_TOC.
 74 * The completion field needs to be initialized before queueing with
 75 * hci->io->queue_xfer(), and requires CMD_0_ROC to be set.
 76 */
 77struct hci_xfer {
 78	u32 cmd_desc[4];
 79	u32 response;
 80	bool rnw;
 81	void *data;
 82	unsigned int data_len;
 83	unsigned int cmd_tid;
 84	struct completion *completion;
 85	union {
 86		struct {
 87			/* PIO specific */
 88			struct hci_xfer *next_xfer;
 89			struct hci_xfer *next_data;
 90			struct hci_xfer *next_resp;
 91			unsigned int data_left;
 92			u32 data_word_before_partial;
 93		};
 94		struct {
 95			/* DMA specific */
 96			struct i3c_dma *dma;
 97			int ring_number;
 98			int ring_entry;
 99		};
100	};
101};
102
103static inline struct hci_xfer *hci_alloc_xfer(unsigned int n)
104{
105	return kcalloc(n, sizeof(struct hci_xfer), GFP_KERNEL);
106}
107
108static inline void hci_free_xfer(struct hci_xfer *xfer, unsigned int n)
109{
110	kfree(xfer);
111}
112
113
114/* This abstracts PIO vs DMA operations */
115struct hci_io_ops {
116	bool (*irq_handler)(struct i3c_hci *hci);
117	int (*queue_xfer)(struct i3c_hci *hci, struct hci_xfer *xfer, int n);
118	bool (*dequeue_xfer)(struct i3c_hci *hci, struct hci_xfer *xfer, int n);
119	int (*request_ibi)(struct i3c_hci *hci, struct i3c_dev_desc *dev,
120			   const struct i3c_ibi_setup *req);
121	void (*free_ibi)(struct i3c_hci *hci, struct i3c_dev_desc *dev);
122	void (*recycle_ibi_slot)(struct i3c_hci *hci, struct i3c_dev_desc *dev,
123				struct i3c_ibi_slot *slot);
124	int (*init)(struct i3c_hci *hci);
125	void (*cleanup)(struct i3c_hci *hci);
126};
127
128extern const struct hci_io_ops mipi_i3c_hci_pio;
129extern const struct hci_io_ops mipi_i3c_hci_dma;
130
131
132/* Our per device master private data */
133struct i3c_hci_dev_data {
134	int dat_idx;
135	void *ibi_data;
136};
137
138
139/* list of quirks */
140#define HCI_QUIRK_RAW_CCC	BIT(1)	/* CCC framing must be explicit */
141#define HCI_QUIRK_PIO_MODE	BIT(2)  /* Set PIO mode for AMD platforms */
142#define HCI_QUIRK_OD_PP_TIMING		BIT(3)  /* Set OD and PP timings for AMD platforms */
143#define HCI_QUIRK_RESP_BUF_THLD		BIT(4)  /* Set resp buf thld to 0 for AMD platforms */
144
145
146/* global functions */
147void mipi_i3c_hci_resume(struct i3c_hci *hci);
148void mipi_i3c_hci_pio_reset(struct i3c_hci *hci);
149void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci);
150void amd_set_od_pp_timing(struct i3c_hci *hci);
151void amd_set_resp_buf_thld(struct i3c_hci *hci);
152
153#endif