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adi-i3c-master.c
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linux-6.19.14/drivers/i3c/master/adi-i3c-master.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * I3C Controller driver 4 * Copyright 2025 Analog Devices Inc. 5 * Author: Jorge Marques <jorge.marques@analog.com> 6 */ 7 8#include <linux/bitops.h> 9#include <linux/bitfield.h> 10#include <linux/clk.h> 11#include <linux/err.h> 12#include <linux/errno.h> 13#include <linux/adi-axi-common.h> 14#include <linux/i3c/master.h> 15#include <linux/interrupt.h> 16#include <linux/io.h> 17#include <linux/module.h> 18#include <linux/of.h> 19#include <linux/platform_device.h> 20 21#include "../internals.h" 22 23#define ADI_MAX_DEVS 16 24#define ADI_HAS_MDB_FROM_BCR(x) (FIELD_GET(BIT(2), (x))) 25 26#define REG_ENABLE 0x040 27 28#define REG_PID_L 0x054 29#define REG_PID_H 0x058 30#define REG_DCR_BCR_DA 0x05c 31#define REG_DCR_BCR_DA_GET_DA(x) FIELD_GET(GENMASK(22, 16), (x)) 32#define REG_DCR_BCR_DA_GET_BCR(x) FIELD_GET(GENMASK(15, 8), (x)) 33#define REG_DCR_BCR_DA_GET_DCR(x) FIELD_GET(GENMASK(7, 0), (x)) 34 35#define REG_IRQ_MASK 0x080 36#define REG_IRQ_PENDING 0x084 37#define REG_IRQ_PENDING_DAA BIT(7) 38#define REG_IRQ_PENDING_IBI BIT(6) 39#define REG_IRQ_PENDING_CMDR BIT(5) 40 41#define REG_CMD_FIFO 0x0d4 42#define REG_CMD_FIFO_0_IS_CCC BIT(22) 43#define REG_CMD_FIFO_0_BCAST BIT(21) 44#define REG_CMD_FIFO_0_SR BIT(20) 45#define REG_CMD_FIFO_0_LEN(l) FIELD_PREP(GENMASK(19, 8), (l)) 46#define REG_CMD_FIFO_0_DEV_ADDR(a) FIELD_PREP(GENMASK(7, 1), (a)) 47#define REG_CMD_FIFO_0_RNW BIT(0) 48#define REG_CMD_FIFO_1_CCC(id) FIELD_PREP(GENMASK(7, 0), (id)) 49 50#define REG_CMD_FIFO_ROOM 0x0c0 51#define REG_CMDR_FIFO 0x0d8 52#define REG_CMDR_FIFO_UDA_ERROR 8 53#define REG_CMDR_FIFO_NACK_RESP 6 54#define REG_CMDR_FIFO_CE2_ERROR 4 55#define REG_CMDR_FIFO_CE0_ERROR 1 56#define REG_CMDR_FIFO_NO_ERROR 0 57#define REG_CMDR_FIFO_ERROR(x) FIELD_GET(GENMASK(23, 20), (x)) 58#define REG_CMDR_FIFO_XFER_BYTES(x) FIELD_GET(GENMASK(19, 8), (x)) 59 60#define REG_SDO_FIFO 0x0dc 61#define REG_SDO_FIFO_ROOM 0x0c8 62#define REG_SDI_FIFO 0x0e0 63#define REG_IBI_FIFO 0x0e4 64#define REG_FIFO_STATUS 0x0e8 65#define REG_FIFO_STATUS_CMDR_EMPTY BIT(0) 66#define REG_FIFO_STATUS_IBI_EMPTY BIT(1) 67 68#define REG_OPS 0x100 69#define REG_OPS_PP_SG_MASK GENMASK(6, 5) 70#define REG_OPS_SET_SG(x) FIELD_PREP(REG_OPS_PP_SG_MASK, (x)) 71 72#define REG_IBI_CONFIG 0x140 73#define REG_IBI_CONFIG_ENABLE BIT(0) 74#define REG_IBI_CONFIG_LISTEN BIT(1) 75 76#define REG_DEV_CHAR 0x180 77#define REG_DEV_CHAR_IS_I2C BIT(0) 78#define REG_DEV_CHAR_IS_ATTACHED BIT(1) 79#define REG_DEV_CHAR_BCR_IBI(x) FIELD_PREP(GENMASK(3, 2), (x)) 80#define REG_DEV_CHAR_WEN BIT(8) 81#define REG_DEV_CHAR_ADDR(x) FIELD_PREP(GENMASK(15, 9), (x)) 82 83enum speed_grade {PP_SG_UNSET, PP_SG_1MHZ, PP_SG_3MHZ, PP_SG_6MHZ, PP_SG_12MHZ}; 84 85struct adi_i3c_cmd { 86 u32 cmd0; 87 u32 cmd1; 88 u32 tx_len; 89 const void *tx_buf; 90 u32 rx_len; 91 void *rx_buf; 92 u32 error; 93}; 94 95struct adi_i3c_xfer { 96 struct list_head node; 97 struct completion comp; 98 int ret; 99 unsigned int ncmds; 100 unsigned int ncmds_comp; 101 struct adi_i3c_cmd cmds[] __counted_by(ncmds); 102}; 103 104struct adi_i3c_master { 105 struct i3c_master_controller base; 106 u32 free_rr_slots; 107 struct { 108 unsigned int num_slots; 109 struct i3c_dev_desc **slots; 110 spinlock_t lock; /* Protect IBI slot access */ 111 } ibi; 112 struct { 113 struct list_head list; 114 struct adi_i3c_xfer *cur; 115 spinlock_t lock; /* Protect transfer */ 116 } xferqueue; 117 void __iomem *regs; 118 struct clk *clk; 119 unsigned long i3c_scl_lim; 120 struct { 121 u8 addrs[ADI_MAX_DEVS]; 122 u8 index; 123 } daa; 124}; 125 126static inline struct adi_i3c_master *to_adi_i3c_master(struct i3c_master_controller *master) 127{ 128 return container_of(master, struct adi_i3c_master, base); 129} 130 131static void adi_i3c_master_wr_to_tx_fifo(struct adi_i3c_master *master, 132 const u8 *buf, unsigned int nbytes) 133{ 134 unsigned int n, m; 135 136 n = readl(master->regs + REG_SDO_FIFO_ROOM); 137 m = min(n, nbytes); 138 i3c_writel_fifo(master->regs + REG_SDO_FIFO, buf, m); 139} 140 141static void adi_i3c_master_rd_from_rx_fifo(struct adi_i3c_master *master, 142 u8 *buf, unsigned int nbytes) 143{ 144 i3c_readl_fifo(master->regs + REG_SDI_FIFO, buf, nbytes); 145} 146 147static bool adi_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m, 148 const struct i3c_ccc_cmd *cmd) 149{ 150 if (cmd->ndests > 1) 151 return false; 152 153 switch (cmd->id) { 154 case I3C_CCC_ENEC(true): 155 case I3C_CCC_ENEC(false): 156 case I3C_CCC_DISEC(true): 157 case I3C_CCC_DISEC(false): 158 case I3C_CCC_RSTDAA(true): 159 case I3C_CCC_RSTDAA(false): 160 case I3C_CCC_ENTDAA: 161 case I3C_CCC_SETDASA: 162 case I3C_CCC_SETNEWDA: 163 case I3C_CCC_GETMWL: 164 case I3C_CCC_GETMRL: 165 case I3C_CCC_GETPID: 166 case I3C_CCC_GETBCR: 167 case I3C_CCC_GETDCR: 168 case I3C_CCC_GETSTATUS: 169 case I3C_CCC_GETHDRCAP: 170 return true; 171 default: 172 break; 173 } 174 175 return false; 176} 177 178static int adi_i3c_master_disable(struct adi_i3c_master *master) 179{ 180 writel(0, master->regs + REG_IBI_CONFIG); 181 182 return 0; 183} 184 185static struct adi_i3c_xfer *adi_i3c_master_alloc_xfer(struct adi_i3c_master *master, 186 unsigned int ncmds) 187{ 188 struct adi_i3c_xfer *xfer; 189 190 xfer = kzalloc(struct_size(xfer, cmds, ncmds), GFP_KERNEL); 191 if (!xfer) 192 return NULL; 193 194 INIT_LIST_HEAD(&xfer->node); 195 xfer->ncmds = ncmds; 196 xfer->ret = -ETIMEDOUT; 197 198 return xfer; 199} 200 201static void adi_i3c_master_start_xfer_locked(struct adi_i3c_master *master) 202{ 203 struct adi_i3c_xfer *xfer = master->xferqueue.cur; 204 unsigned int i, n, m; 205 206 if (!xfer) 207 return; 208 209 for (i = 0; i < xfer->ncmds; i++) { 210 struct adi_i3c_cmd *cmd = &xfer->cmds[i]; 211 212 if (!(cmd->cmd0 & REG_CMD_FIFO_0_RNW)) 213 adi_i3c_master_wr_to_tx_fifo(master, cmd->tx_buf, cmd->tx_len); 214 } 215 216 n = readl(master->regs + REG_CMD_FIFO_ROOM); 217 for (i = 0; i < xfer->ncmds; i++) { 218 struct adi_i3c_cmd *cmd = &xfer->cmds[i]; 219 220 m = cmd->cmd0 & REG_CMD_FIFO_0_IS_CCC ? 2 : 1; 221 if (m > n) 222 break; 223 writel(cmd->cmd0, master->regs + REG_CMD_FIFO); 224 if (cmd->cmd0 & REG_CMD_FIFO_0_IS_CCC) 225 writel(cmd->cmd1, master->regs + REG_CMD_FIFO); 226 n -= m; 227 } 228} 229 230static void adi_i3c_master_end_xfer_locked(struct adi_i3c_master *master, 231 u32 pending) 232{ 233 struct adi_i3c_xfer *xfer = master->xferqueue.cur; 234 int i, ret = 0; 235 236 if (!xfer) 237 return; 238 239 while (!(readl(master->regs + REG_FIFO_STATUS) & REG_FIFO_STATUS_CMDR_EMPTY)) { 240 struct adi_i3c_cmd *cmd; 241 u32 cmdr, rx_len; 242 243 cmdr = readl(master->regs + REG_CMDR_FIFO); 244 245 cmd = &xfer->cmds[xfer->ncmds_comp++]; 246 if (cmd->cmd0 & REG_CMD_FIFO_0_RNW) { 247 rx_len = min_t(u32, REG_CMDR_FIFO_XFER_BYTES(cmdr), cmd->rx_len); 248 adi_i3c_master_rd_from_rx_fifo(master, cmd->rx_buf, rx_len); 249 } 250 cmd->error = REG_CMDR_FIFO_ERROR(cmdr); 251 } 252 253 for (i = 0; i < xfer->ncmds_comp; i++) { 254 switch (xfer->cmds[i].error) { 255 case REG_CMDR_FIFO_NO_ERROR: 256 break; 257 258 case REG_CMDR_FIFO_CE0_ERROR: 259 case REG_CMDR_FIFO_CE2_ERROR: 260 case REG_CMDR_FIFO_NACK_RESP: 261 case REG_CMDR_FIFO_UDA_ERROR: 262 ret = -EIO; 263 break; 264 265 default: 266 ret = -EINVAL; 267 break; 268 } 269 } 270 271 xfer->ret = ret; 272 273 if (xfer->ncmds_comp != xfer->ncmds) 274 return; 275 276 complete(&xfer->comp); 277 278 xfer = list_first_entry_or_null(&master->xferqueue.list, 279 struct adi_i3c_xfer, node); 280 if (xfer) 281 list_del_init(&xfer->node); 282 283 master->xferqueue.cur = xfer; 284 adi_i3c_master_start_xfer_locked(master); 285} 286 287static void adi_i3c_master_queue_xfer(struct adi_i3c_master *master, 288 struct adi_i3c_xfer *xfer) 289{ 290 init_completion(&xfer->comp); 291 guard(spinlock_irqsave)(&master->xferqueue.lock); 292 if (master->xferqueue.cur) { 293 list_add_tail(&xfer->node, &master->xferqueue.list); 294 } else { 295 master->xferqueue.cur = xfer; 296 adi_i3c_master_start_xfer_locked(master); 297 } 298} 299 300static void adi_i3c_master_unqueue_xfer(struct adi_i3c_master *master, 301 struct adi_i3c_xfer *xfer) 302{ 303 guard(spinlock_irqsave)(&master->xferqueue.lock); 304 if (master->xferqueue.cur == xfer) 305 master->xferqueue.cur = NULL; 306 else 307 list_del_init(&xfer->node); 308 309 writel(0x01, master->regs + REG_ENABLE); 310 writel(0x00, master->regs + REG_ENABLE); 311 writel(REG_IRQ_PENDING_CMDR, master->regs + REG_IRQ_MASK); 312} 313 314static enum i3c_error_code adi_i3c_cmd_get_err(struct adi_i3c_cmd *cmd) 315{ 316 switch (cmd->error) { 317 case REG_CMDR_FIFO_CE0_ERROR: 318 return I3C_ERROR_M0; 319 320 case REG_CMDR_FIFO_CE2_ERROR: 321 case REG_CMDR_FIFO_NACK_RESP: 322 return I3C_ERROR_M2; 323 324 default: 325 break; 326 } 327 328 return I3C_ERROR_UNKNOWN; 329} 330 331static int adi_i3c_master_send_ccc_cmd(struct i3c_master_controller *m, 332 struct i3c_ccc_cmd *cmd) 333{ 334 struct adi_i3c_master *master = to_adi_i3c_master(m); 335 struct adi_i3c_cmd *ccmd; 336 337 struct adi_i3c_xfer *xfer __free(kfree) = adi_i3c_master_alloc_xfer(master, 1); 338 if (!xfer) 339 return -ENOMEM; 340 341 ccmd = xfer->cmds; 342 ccmd->cmd1 = REG_CMD_FIFO_1_CCC(cmd->id); 343 ccmd->cmd0 = REG_CMD_FIFO_0_IS_CCC | 344 REG_CMD_FIFO_0_LEN(cmd->dests[0].payload.len); 345 346 if (cmd->id & I3C_CCC_DIRECT) 347 ccmd->cmd0 |= REG_CMD_FIFO_0_DEV_ADDR(cmd->dests[0].addr); 348 349 if (cmd->rnw) { 350 ccmd->cmd0 |= REG_CMD_FIFO_0_RNW; 351 ccmd->rx_buf = cmd->dests[0].payload.data; 352 ccmd->rx_len = cmd->dests[0].payload.len; 353 } else { 354 ccmd->tx_buf = cmd->dests[0].payload.data; 355 ccmd->tx_len = cmd->dests[0].payload.len; 356 } 357 358 adi_i3c_master_queue_xfer(master, xfer); 359 if (!wait_for_completion_timeout(&xfer->comp, msecs_to_jiffies(1000))) 360 adi_i3c_master_unqueue_xfer(master, xfer); 361 362 cmd->err = adi_i3c_cmd_get_err(&xfer->cmds[0]); 363 364 return 0; 365} 366 367static int adi_i3c_master_i3c_xfers(struct i3c_dev_desc *dev, 368 struct i3c_xfer *xfers, 369 int nxfers, enum i3c_xfer_mode mode) 370{ 371 struct i3c_master_controller *m = i3c_dev_get_master(dev); 372 struct adi_i3c_master *master = to_adi_i3c_master(m); 373 int i, ret; 374 375 if (!nxfers) 376 return 0; 377 378 struct adi_i3c_xfer *xfer __free(kfree) = adi_i3c_master_alloc_xfer(master, nxfers); 379 if (!xfer) 380 return -ENOMEM; 381 382 for (i = 0; i < nxfers; i++) { 383 struct adi_i3c_cmd *ccmd = &xfer->cmds[i]; 384 385 ccmd->cmd0 = REG_CMD_FIFO_0_DEV_ADDR(dev->info.dyn_addr); 386 387 if (xfers[i].rnw) { 388 ccmd->cmd0 |= REG_CMD_FIFO_0_RNW; 389 ccmd->rx_buf = xfers[i].data.in; 390 ccmd->rx_len = xfers[i].len; 391 } else { 392 ccmd->tx_buf = xfers[i].data.out; 393 ccmd->tx_len = xfers[i].len; 394 } 395 396 ccmd->cmd0 |= REG_CMD_FIFO_0_LEN(xfers[i].len); 397 398 if (i < nxfers - 1) 399 ccmd->cmd0 |= REG_CMD_FIFO_0_SR; 400 401 if (!i) 402 ccmd->cmd0 |= REG_CMD_FIFO_0_BCAST; 403 } 404 405 adi_i3c_master_queue_xfer(master, xfer); 406 if (!wait_for_completion_timeout(&xfer->comp, 407 msecs_to_jiffies(1000))) 408 adi_i3c_master_unqueue_xfer(master, xfer); 409 410 ret = xfer->ret; 411 412 for (i = 0; i < nxfers; i++) 413 xfers[i].err = adi_i3c_cmd_get_err(&xfer->cmds[i]); 414 415 return ret; 416} 417 418struct adi_i3c_i2c_dev_data { 419 struct i3c_generic_ibi_pool *ibi_pool; 420 u16 id; 421 s16 ibi; 422}; 423 424static int adi_i3c_master_get_rr_slot(struct adi_i3c_master *master, 425 u8 dyn_addr) 426{ 427 if (!master->free_rr_slots) 428 return -ENOSPC; 429 430 return ffs(master->free_rr_slots) - 1; 431} 432 433static int adi_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev, u8 dyn_addr) 434{ 435 struct i3c_master_controller *m = i3c_dev_get_master(dev); 436 struct adi_i3c_master *master = to_adi_i3c_master(m); 437 u8 addr; 438 439 addr = dev->info.dyn_addr ? dev->info.dyn_addr : dev->info.static_addr; 440 441 writel(REG_DEV_CHAR_ADDR(dyn_addr), master->regs + REG_DEV_CHAR); 442 writel((readl(master->regs + REG_DEV_CHAR) & 443 ~REG_DEV_CHAR_IS_ATTACHED) | REG_DEV_CHAR_WEN, 444 master->regs + REG_DEV_CHAR); 445 446 writel(REG_DEV_CHAR_ADDR(addr), master->regs + REG_DEV_CHAR); 447 writel(readl(master->regs + REG_DEV_CHAR) | 448 REG_DEV_CHAR_IS_ATTACHED | REG_DEV_CHAR_WEN, 449 master->regs + REG_DEV_CHAR); 450 451 return 0; 452} 453 454static int adi_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev) 455{ 456 struct i3c_master_controller *m = i3c_dev_get_master(dev); 457 struct adi_i3c_master *master = to_adi_i3c_master(m); 458 struct adi_i3c_i2c_dev_data *data; 459 int slot; 460 u8 addr; 461 462 data = kzalloc(sizeof(*data), GFP_KERNEL); 463 if (!data) 464 return -ENOMEM; 465 466 slot = adi_i3c_master_get_rr_slot(master, dev->info.dyn_addr); 467 if (slot < 0) { 468 kfree(data); 469 return slot; 470 } 471 472 data->id = slot; 473 i3c_dev_set_master_data(dev, data); 474 master->free_rr_slots &= ~BIT(slot); 475 476 addr = dev->info.dyn_addr ? dev->info.dyn_addr : dev->info.static_addr; 477 478 writel(REG_DEV_CHAR_ADDR(addr), master->regs + REG_DEV_CHAR); 479 writel(readl(master->regs + REG_DEV_CHAR) | 480 REG_DEV_CHAR_IS_ATTACHED | REG_DEV_CHAR_WEN, 481 master->regs + REG_DEV_CHAR); 482 483 return 0; 484} 485 486static void adi_i3c_master_sync_dev_char(struct i3c_master_controller *m) 487{ 488 struct adi_i3c_master *master = to_adi_i3c_master(m); 489 struct i3c_dev_desc *i3cdev; 490 u32 bcr_ibi; 491 u8 addr; 492 493 i3c_bus_for_each_i3cdev(&m->bus, i3cdev) { 494 addr = i3cdev->info.dyn_addr ? 495 i3cdev->info.dyn_addr : i3cdev->info.static_addr; 496 writel(REG_DEV_CHAR_ADDR(addr), master->regs + REG_DEV_CHAR); 497 bcr_ibi = FIELD_GET(I3C_BCR_IBI_PAYLOAD | I3C_BCR_IBI_REQ_CAP, (i3cdev->info.bcr)); 498 writel(readl(master->regs + REG_DEV_CHAR) | 499 REG_DEV_CHAR_BCR_IBI(bcr_ibi) | REG_DEV_CHAR_WEN, 500 master->regs + REG_DEV_CHAR); 501 } 502} 503 504static void adi_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev) 505{ 506 struct i3c_master_controller *m = i3c_dev_get_master(dev); 507 struct adi_i3c_master *master = to_adi_i3c_master(m); 508 struct adi_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 509 u8 addr; 510 511 addr = dev->info.dyn_addr ? dev->info.dyn_addr : dev->info.static_addr; 512 513 writel(REG_DEV_CHAR_ADDR(addr), master->regs + REG_DEV_CHAR); 514 writel((readl(master->regs + REG_DEV_CHAR) & 515 ~REG_DEV_CHAR_IS_ATTACHED) | REG_DEV_CHAR_WEN, 516 master->regs + REG_DEV_CHAR); 517 518 i3c_dev_set_master_data(dev, NULL); 519 master->free_rr_slots |= BIT(data->id); 520 kfree(data); 521} 522 523static int adi_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev) 524{ 525 struct i3c_master_controller *m = i2c_dev_get_master(dev); 526 struct adi_i3c_master *master = to_adi_i3c_master(m); 527 struct adi_i3c_i2c_dev_data *data; 528 int slot; 529 530 slot = adi_i3c_master_get_rr_slot(master, 0); 531 if (slot < 0) 532 return slot; 533 534 data = kzalloc(sizeof(*data), GFP_KERNEL); 535 if (!data) 536 return -ENOMEM; 537 538 data->id = slot; 539 master->free_rr_slots &= ~BIT(slot); 540 i2c_dev_set_master_data(dev, data); 541 542 writel(REG_DEV_CHAR_ADDR(dev->addr) | 543 REG_DEV_CHAR_IS_I2C | REG_DEV_CHAR_IS_ATTACHED | REG_DEV_CHAR_WEN, 544 master->regs + REG_DEV_CHAR); 545 546 return 0; 547} 548 549static void adi_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev) 550{ 551 struct i3c_master_controller *m = i2c_dev_get_master(dev); 552 struct adi_i3c_master *master = to_adi_i3c_master(m); 553 struct adi_i3c_i2c_dev_data *data = i2c_dev_get_master_data(dev); 554 555 writel(REG_DEV_CHAR_ADDR(dev->addr) | 556 REG_DEV_CHAR_IS_I2C | REG_DEV_CHAR_WEN, 557 master->regs + REG_DEV_CHAR); 558 559 i2c_dev_set_master_data(dev, NULL); 560 master->free_rr_slots |= BIT(data->id); 561 kfree(data); 562} 563 564static void adi_i3c_master_bus_cleanup(struct i3c_master_controller *m) 565{ 566 struct adi_i3c_master *master = to_adi_i3c_master(m); 567 568 adi_i3c_master_disable(master); 569} 570 571static void adi_i3c_master_upd_i3c_scl_lim(struct adi_i3c_master *master) 572{ 573 struct i3c_master_controller *m = &master->base; 574 struct i3c_bus *bus = i3c_master_get_bus(m); 575 u8 i3c_scl_lim = 0; 576 struct i3c_dev_desc *dev; 577 u8 pp_sg; 578 579 i3c_bus_for_each_i3cdev(bus, dev) { 580 u8 max_fscl; 581 582 max_fscl = max(I3C_CCC_MAX_SDR_FSCL(dev->info.max_read_ds), 583 I3C_CCC_MAX_SDR_FSCL(dev->info.max_write_ds)); 584 585 switch (max_fscl) { 586 case I3C_SDR1_FSCL_8MHZ: 587 max_fscl = PP_SG_6MHZ; 588 break; 589 case I3C_SDR2_FSCL_6MHZ: 590 max_fscl = PP_SG_3MHZ; 591 break; 592 case I3C_SDR3_FSCL_4MHZ: 593 max_fscl = PP_SG_3MHZ; 594 break; 595 case I3C_SDR4_FSCL_2MHZ: 596 max_fscl = PP_SG_1MHZ; 597 break; 598 case I3C_SDR0_FSCL_MAX: 599 default: 600 max_fscl = PP_SG_12MHZ; 601 break; 602 } 603 604 if (max_fscl && 605 (i3c_scl_lim > max_fscl || !i3c_scl_lim)) 606 i3c_scl_lim = max_fscl; 607 } 608 609 if (!i3c_scl_lim) 610 return; 611 612 master->i3c_scl_lim = i3c_scl_lim - 1; 613 614 pp_sg = readl(master->regs + REG_OPS) & ~REG_OPS_PP_SG_MASK; 615 pp_sg |= REG_OPS_SET_SG(master->i3c_scl_lim); 616 617 writel(pp_sg, master->regs + REG_OPS); 618} 619 620static void adi_i3c_master_get_features(struct adi_i3c_master *master, 621 unsigned int slot, 622 struct i3c_device_info *info) 623{ 624 u32 buf; 625 626 /* Dynamic address and PID are for identification only */ 627 memset(info, 0, sizeof(*info)); 628 buf = readl(master->regs + REG_DCR_BCR_DA); 629 info->dyn_addr = REG_DCR_BCR_DA_GET_DA(buf); 630 info->dcr = REG_DCR_BCR_DA_GET_DCR(buf); 631 info->bcr = REG_DCR_BCR_DA_GET_BCR(buf); 632 info->pid = readl(master->regs + REG_PID_L); 633 info->pid |= (u64)readl(master->regs + REG_PID_H) << 32; 634} 635 636static int adi_i3c_master_do_daa(struct i3c_master_controller *m) 637{ 638 struct adi_i3c_master *master = to_adi_i3c_master(m); 639 int ret, addr = 0; 640 u32 irq_mask; 641 642 for (u8 i = 0; i < ADI_MAX_DEVS; i++) { 643 addr = i3c_master_get_free_addr(m, addr); 644 if (addr < 0) 645 return addr; 646 master->daa.addrs[i] = addr; 647 } 648 649 irq_mask = readl(master->regs + REG_IRQ_MASK); 650 writel(irq_mask | REG_IRQ_PENDING_DAA, 651 master->regs + REG_IRQ_MASK); 652 653 master->daa.index = 0; 654 ret = i3c_master_entdaa_locked(&master->base); 655 656 writel(irq_mask, master->regs + REG_IRQ_MASK); 657 658 /* DAA always finishes with CE2_ERROR or NACK_RESP */ 659 if (ret && ret != I3C_ERROR_M2) 660 return ret; 661 662 /* Add I3C devices discovered */ 663 for (u8 i = 0; i < master->daa.index; i++) 664 i3c_master_add_i3c_dev_locked(m, master->daa.addrs[i]); 665 /* Sync retrieved devs info with the IP */ 666 adi_i3c_master_sync_dev_char(m); 667 668 i3c_master_defslvs_locked(&master->base); 669 670 adi_i3c_master_upd_i3c_scl_lim(master); 671 672 return 0; 673} 674 675static int adi_i3c_master_bus_init(struct i3c_master_controller *m) 676{ 677 struct adi_i3c_master *master = to_adi_i3c_master(m); 678 struct i3c_device_info info = { }; 679 int ret; 680 681 ret = i3c_master_get_free_addr(m, 0); 682 if (ret < 0) 683 return ret; 684 685 adi_i3c_master_get_features(master, 0, &info); 686 ret = i3c_master_set_info(&master->base, &info); 687 if (ret) 688 return ret; 689 690 writel(REG_IBI_CONFIG_LISTEN, 691 master->regs + REG_IBI_CONFIG); 692 693 return 0; 694} 695 696static void adi_i3c_master_handle_ibi(struct adi_i3c_master *master, 697 u32 raw) 698{ 699 struct adi_i3c_i2c_dev_data *data; 700 struct i3c_ibi_slot *slot; 701 struct i3c_dev_desc *dev; 702 u8 da, id, mdb, len; 703 u8 *buf; 704 705 da = FIELD_GET(GENMASK(23, 17), raw); 706 mdb = FIELD_GET(GENMASK(15, 8), raw); 707 for (id = 0; id < master->ibi.num_slots; id++) { 708 if (master->ibi.slots[id] && 709 master->ibi.slots[id]->info.dyn_addr == da) 710 break; 711 } 712 713 if (id == master->ibi.num_slots) 714 return; 715 716 dev = master->ibi.slots[id]; 717 len = ADI_HAS_MDB_FROM_BCR(dev->info.bcr); 718 data = i3c_dev_get_master_data(dev); 719 720 guard(spinlock)(&master->ibi.lock); 721 slot = i3c_generic_ibi_get_free_slot(data->ibi_pool); 722 if (!slot) 723 return; 724 725 slot->len = len; 726 buf = slot->data; 727 buf[0] = mdb; 728 i3c_master_queue_ibi(dev, slot); 729} 730 731static void adi_i3c_master_demux_ibis(struct adi_i3c_master *master) 732{ 733 while (!(readl(master->regs + REG_FIFO_STATUS) & REG_FIFO_STATUS_IBI_EMPTY)) { 734 u32 raw = readl(master->regs + REG_IBI_FIFO); 735 736 adi_i3c_master_handle_ibi(master, raw); 737 } 738} 739 740static void adi_i3c_master_handle_da_req(struct adi_i3c_master *master) 741{ 742 u8 payload0[8]; 743 u32 addr; 744 745 adi_i3c_master_rd_from_rx_fifo(master, payload0, 6); 746 addr = master->daa.addrs[master->daa.index++]; 747 addr = (addr << 1) | (parity8(addr) ? 0 : 1); 748 749 writel(addr, master->regs + REG_SDO_FIFO); 750} 751 752static irqreturn_t adi_i3c_master_irq(int irq, void *data) 753{ 754 struct adi_i3c_master *master = data; 755 u32 pending; 756 757 pending = readl(master->regs + REG_IRQ_PENDING); 758 writel(pending, master->regs + REG_IRQ_PENDING); 759 if (pending & REG_IRQ_PENDING_CMDR) { 760 scoped_guard(spinlock_irqsave, &master->xferqueue.lock) { 761 adi_i3c_master_end_xfer_locked(master, pending); 762 } 763 } 764 if (pending & REG_IRQ_PENDING_IBI) 765 adi_i3c_master_demux_ibis(master); 766 if (pending & REG_IRQ_PENDING_DAA) 767 adi_i3c_master_handle_da_req(master); 768 769 return IRQ_HANDLED; 770} 771 772static int adi_i3c_master_i2c_xfers(struct i2c_dev_desc *dev, 773 struct i2c_msg *xfers, 774 int nxfers) 775{ 776 struct i3c_master_controller *m = i2c_dev_get_master(dev); 777 struct adi_i3c_master *master = to_adi_i3c_master(m); 778 int i; 779 780 if (!nxfers) 781 return 0; 782 for (i = 0; i < nxfers; i++) { 783 if (xfers[i].flags & I2C_M_TEN) 784 return -EOPNOTSUPP; 785 } 786 787 struct adi_i3c_xfer *xfer __free(kfree) = adi_i3c_master_alloc_xfer(master, nxfers); 788 if (!xfer) 789 return -ENOMEM; 790 791 for (i = 0; i < nxfers; i++) { 792 struct adi_i3c_cmd *ccmd = &xfer->cmds[i]; 793 794 ccmd->cmd0 = REG_CMD_FIFO_0_DEV_ADDR(xfers[i].addr); 795 796 if (xfers[i].flags & I2C_M_RD) { 797 ccmd->cmd0 |= REG_CMD_FIFO_0_RNW; 798 ccmd->rx_buf = xfers[i].buf; 799 ccmd->rx_len = xfers[i].len; 800 } else { 801 ccmd->tx_buf = xfers[i].buf; 802 ccmd->tx_len = xfers[i].len; 803 } 804 805 ccmd->cmd0 |= REG_CMD_FIFO_0_LEN(xfers[i].len); 806 } 807 808 adi_i3c_master_queue_xfer(master, xfer); 809 if (!wait_for_completion_timeout(&xfer->comp, 810 m->i2c.timeout)) 811 adi_i3c_master_unqueue_xfer(master, xfer); 812 813 return xfer->ret; 814} 815 816static int adi_i3c_master_disable_ibi(struct i3c_dev_desc *dev) 817{ 818 struct i3c_master_controller *m = i3c_dev_get_master(dev); 819 struct adi_i3c_master *master = to_adi_i3c_master(m); 820 struct i3c_dev_desc *i3cdev; 821 u32 enabled = 0; 822 int ret; 823 824 ret = i3c_master_disec_locked(m, dev->info.dyn_addr, 825 I3C_CCC_EVENT_SIR); 826 827 i3c_bus_for_each_i3cdev(&m->bus, i3cdev) { 828 if (dev != i3cdev && i3cdev->ibi) 829 enabled |= i3cdev->ibi->enabled; 830 } 831 if (!enabled) { 832 writel(REG_IBI_CONFIG_LISTEN, 833 master->regs + REG_IBI_CONFIG); 834 writel(readl(master->regs + REG_IRQ_MASK) & ~REG_IRQ_PENDING_IBI, 835 master->regs + REG_IRQ_MASK); 836 } 837 838 return ret; 839} 840 841static int adi_i3c_master_enable_ibi(struct i3c_dev_desc *dev) 842{ 843 struct i3c_master_controller *m = i3c_dev_get_master(dev); 844 struct adi_i3c_master *master = to_adi_i3c_master(m); 845 846 writel(REG_IBI_CONFIG_LISTEN | REG_IBI_CONFIG_ENABLE, 847 master->regs + REG_IBI_CONFIG); 848 849 writel(readl(master->regs + REG_IRQ_MASK) | REG_IRQ_PENDING_IBI, 850 master->regs + REG_IRQ_MASK); 851 852 return i3c_master_enec_locked(m, dev->info.dyn_addr, 853 I3C_CCC_EVENT_SIR); 854} 855 856static int adi_i3c_master_request_ibi(struct i3c_dev_desc *dev, 857 const struct i3c_ibi_setup *req) 858{ 859 struct i3c_master_controller *m = i3c_dev_get_master(dev); 860 struct adi_i3c_master *master = to_adi_i3c_master(m); 861 struct adi_i3c_i2c_dev_data *data; 862 unsigned int i; 863 864 data = i3c_dev_get_master_data(dev); 865 data->ibi_pool = i3c_generic_ibi_alloc_pool(dev, req); 866 if (IS_ERR(data->ibi_pool)) 867 return PTR_ERR(data->ibi_pool); 868 869 scoped_guard(spinlock_irqsave, &master->ibi.lock) { 870 for (i = 0; i < master->ibi.num_slots; i++) { 871 if (!master->ibi.slots[i]) { 872 data->ibi = i; 873 master->ibi.slots[i] = dev; 874 break; 875 } 876 } 877 } 878 879 if (i < master->ibi.num_slots) 880 return 0; 881 882 i3c_generic_ibi_free_pool(data->ibi_pool); 883 data->ibi_pool = NULL; 884 885 return -ENOSPC; 886} 887 888static void adi_i3c_master_free_ibi(struct i3c_dev_desc *dev) 889{ 890 struct i3c_master_controller *m = i3c_dev_get_master(dev); 891 struct adi_i3c_master *master = to_adi_i3c_master(m); 892 struct adi_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 893 894 scoped_guard(spinlock_irqsave, &master->ibi.lock) { 895 master->ibi.slots[data->ibi] = NULL; 896 } 897 898 i3c_generic_ibi_free_pool(data->ibi_pool); 899} 900 901static void adi_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev, 902 struct i3c_ibi_slot *slot) 903{ 904 struct adi_i3c_i2c_dev_data *data = i3c_dev_get_master_data(dev); 905 906 i3c_generic_ibi_recycle_slot(data->ibi_pool, slot); 907} 908 909static const struct i3c_master_controller_ops adi_i3c_master_ops = { 910 .bus_init = adi_i3c_master_bus_init, 911 .bus_cleanup = adi_i3c_master_bus_cleanup, 912 .attach_i3c_dev = adi_i3c_master_attach_i3c_dev, 913 .reattach_i3c_dev = adi_i3c_master_reattach_i3c_dev, 914 .detach_i3c_dev = adi_i3c_master_detach_i3c_dev, 915 .attach_i2c_dev = adi_i3c_master_attach_i2c_dev, 916 .detach_i2c_dev = adi_i3c_master_detach_i2c_dev, 917 .do_daa = adi_i3c_master_do_daa, 918 .supports_ccc_cmd = adi_i3c_master_supports_ccc_cmd, 919 .send_ccc_cmd = adi_i3c_master_send_ccc_cmd, 920 .i3c_xfers = adi_i3c_master_i3c_xfers, 921 .i2c_xfers = adi_i3c_master_i2c_xfers, 922 .request_ibi = adi_i3c_master_request_ibi, 923 .enable_ibi = adi_i3c_master_enable_ibi, 924 .disable_ibi = adi_i3c_master_disable_ibi, 925 .free_ibi = adi_i3c_master_free_ibi, 926 .recycle_ibi_slot = adi_i3c_master_recycle_ibi_slot, 927}; 928 929static const struct of_device_id adi_i3c_master_of_match[] = { 930 { .compatible = "adi,i3c-master-v1" }, 931 {} 932}; 933 934static int adi_i3c_master_probe(struct platform_device *pdev) 935{ 936 struct adi_i3c_master *master; 937 struct clk_bulk_data *clk; 938 unsigned int version; 939 int ret, irq; 940 941 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL); 942 if (!master) 943 return -ENOMEM; 944 945 master->regs = devm_platform_ioremap_resource(pdev, 0); 946 if (IS_ERR(master->regs)) 947 return PTR_ERR(master->regs); 948 949 ret = devm_clk_bulk_get_all_enabled(&pdev->dev, &clk); 950 if (ret < 0) 951 return dev_err_probe(&pdev->dev, ret, 952 "Failed to get clocks\n"); 953 954 irq = platform_get_irq(pdev, 0); 955 if (irq < 0) 956 return irq; 957 958 version = readl(master->regs + ADI_AXI_REG_VERSION); 959 if (ADI_AXI_PCORE_VER_MAJOR(version) != 1) 960 dev_err_probe(&pdev->dev, -ENODEV, "Unsupported peripheral version %u.%u.%u\n", 961 ADI_AXI_PCORE_VER_MAJOR(version), 962 ADI_AXI_PCORE_VER_MINOR(version), 963 ADI_AXI_PCORE_VER_PATCH(version)); 964 965 writel(0x00, master->regs + REG_ENABLE); 966 writel(0x00, master->regs + REG_IRQ_MASK); 967 968 ret = devm_request_irq(&pdev->dev, irq, adi_i3c_master_irq, 0, 969 dev_name(&pdev->dev), master); 970 if (ret) 971 return ret; 972 973 platform_set_drvdata(pdev, master); 974 975 master->free_rr_slots = GENMASK(ADI_MAX_DEVS, 1); 976 977 writel(REG_IRQ_PENDING_CMDR, master->regs + REG_IRQ_MASK); 978 979 spin_lock_init(&master->ibi.lock); 980 master->ibi.num_slots = 15; 981 master->ibi.slots = devm_kcalloc(&pdev->dev, master->ibi.num_slots, 982 sizeof(*master->ibi.slots), 983 GFP_KERNEL); 984 if (!master->ibi.slots) 985 return -ENOMEM; 986 987 spin_lock_init(&master->xferqueue.lock); 988 INIT_LIST_HEAD(&master->xferqueue.list); 989 990 return i3c_master_register(&master->base, &pdev->dev, 991 &adi_i3c_master_ops, false); 992} 993 994static void adi_i3c_master_remove(struct platform_device *pdev) 995{ 996 struct adi_i3c_master *master = platform_get_drvdata(pdev); 997 998 writel(0xff, master->regs + REG_IRQ_PENDING); 999 writel(0x00, master->regs + REG_IRQ_MASK); 1000 writel(0x01, master->regs + REG_ENABLE); 1001 1002 i3c_master_unregister(&master->base); 1003} 1004 1005static struct platform_driver adi_i3c_master = { 1006 .probe = adi_i3c_master_probe, 1007 .remove = adi_i3c_master_remove, 1008 .driver = { 1009 .name = "adi-i3c-master", 1010 .of_match_table = adi_i3c_master_of_match, 1011 }, 1012}; 1013module_platform_driver(adi_i3c_master); 1014 1015MODULE_AUTHOR("Jorge Marques <jorge.marques@analog.com>"); 1016MODULE_DESCRIPTION("Analog Devices I3C master driver"); 1017MODULE_LICENSE("GPL");
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