i2c-tegra.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * drivers/i2c/busses/i2c-tegra.c
   4 *
   5 * Copyright (C) 2010 Google, Inc.
   6 * Author: Colin Cross <ccross@android.com>
   7 */
   8
   9#include <linux/acpi.h>
  10#include <linux/bitfield.h>
  11#include <linux/clk.h>
  12#include <linux/delay.h>
  13#include <linux/dmaengine.h>
  14#include <linux/dma-mapping.h>
  15#include <linux/err.h>
  16#include <linux/i2c.h>
  17#include <linux/init.h>
  18#include <linux/interrupt.h>
  19#include <linux/io.h>
  20#include <linux/iopoll.h>
  21#include <linux/irq.h>
  22#include <linux/kernel.h>
  23#include <linux/ktime.h>
  24#include <linux/module.h>
  25#include <linux/of.h>
  26#include <linux/pinctrl/consumer.h>
  27#include <linux/platform_device.h>
  28#include <linux/pm_runtime.h>
  29#include <linux/reset.h>
  30
  31#define BYTES_PER_FIFO_WORD 4
  32
  33#define I2C_CNFG				0x000
  34#define I2C_CNFG_DEBOUNCE_CNT			GENMASK(14, 12)
  35#define I2C_CNFG_PACKET_MODE_EN			BIT(10)
  36#define I2C_CNFG_NEW_MASTER_FSM			BIT(11)
  37#define I2C_CNFG_MULTI_MASTER_MODE		BIT(17)
  38#define I2C_STATUS				0x01c
  39#define I2C_SL_CNFG				0x020
  40#define I2C_SL_CNFG_NACK			BIT(1)
  41#define I2C_SL_CNFG_NEWSL			BIT(2)
  42#define I2C_SL_ADDR1				0x02c
  43#define I2C_SL_ADDR2				0x030
  44#define I2C_TLOW_SEXT				0x034
  45#define I2C_TX_FIFO				0x050
  46#define I2C_RX_FIFO				0x054
  47#define I2C_PACKET_TRANSFER_STATUS		0x058
  48#define I2C_FIFO_CONTROL			0x05c
  49#define I2C_FIFO_CONTROL_TX_FLUSH		BIT(1)
  50#define I2C_FIFO_CONTROL_RX_FLUSH		BIT(0)
  51#define I2C_FIFO_CONTROL_TX_TRIG(x)		(((x) - 1) << 5)
  52#define I2C_FIFO_CONTROL_RX_TRIG(x)		(((x) - 1) << 2)
  53#define I2C_FIFO_STATUS				0x060
  54#define I2C_FIFO_STATUS_TX			GENMASK(7, 4)
  55#define I2C_FIFO_STATUS_RX			GENMASK(3, 0)
  56#define I2C_INT_MASK				0x064
  57#define I2C_INT_STATUS				0x068
  58#define I2C_INT_BUS_CLR_DONE			BIT(11)
  59#define I2C_INT_PACKET_XFER_COMPLETE		BIT(7)
  60#define I2C_INT_NO_ACK				BIT(3)
  61#define I2C_INT_ARBITRATION_LOST		BIT(2)
  62#define I2C_INT_TX_FIFO_DATA_REQ		BIT(1)
  63#define I2C_INT_RX_FIFO_DATA_REQ		BIT(0)
  64#define I2C_CLK_DIVISOR				0x06c
  65#define I2C_CLK_DIVISOR_STD_FAST_MODE		GENMASK(31, 16)
  66#define I2C_CLK_DIVISOR_HSMODE			GENMASK(15, 0)
  67
  68#define DVC_CTRL_REG1				0x000
  69#define DVC_CTRL_REG1_INTR_EN			BIT(10)
  70#define DVC_CTRL_REG3				0x008
  71#define DVC_CTRL_REG3_SW_PROG			BIT(26)
  72#define DVC_CTRL_REG3_I2C_DONE_INTR_EN		BIT(30)
  73#define DVC_STATUS				0x00c
  74#define DVC_STATUS_I2C_DONE_INTR		BIT(30)
  75
  76#define I2C_ERR_NONE				0x00
  77#define I2C_ERR_NO_ACK				BIT(0)
  78#define I2C_ERR_ARBITRATION_LOST		BIT(1)
  79#define I2C_ERR_UNKNOWN_INTERRUPT		BIT(2)
  80#define I2C_ERR_RX_BUFFER_OVERFLOW		BIT(3)
  81
  82#define PACKET_HEADER0_HEADER_SIZE		GENMASK(29, 28)
  83#define PACKET_HEADER0_PACKET_ID		GENMASK(23, 16)
  84#define PACKET_HEADER0_CONT_ID			GENMASK(15, 12)
  85#define PACKET_HEADER0_PROTOCOL			GENMASK(7, 4)
  86#define PACKET_HEADER0_PROTOCOL_I2C		1
  87
  88#define I2C_HEADER_CONT_ON_NAK			BIT(21)
  89#define I2C_HEADER_READ				BIT(19)
  90#define I2C_HEADER_10BIT_ADDR			BIT(18)
  91#define I2C_HEADER_IE_ENABLE			BIT(17)
  92#define I2C_HEADER_REPEAT_START			BIT(16)
  93#define I2C_HEADER_CONTINUE_XFER		BIT(15)
  94#define I2C_HEADER_SLAVE_ADDR_SHIFT		1
  95
  96#define I2C_BUS_CLEAR_CNFG			0x084
  97#define I2C_BC_SCLK_THRESHOLD			GENMASK(23, 16)
  98#define I2C_BC_STOP_COND			BIT(2)
  99#define I2C_BC_TERMINATE			BIT(1)
 100#define I2C_BC_ENABLE				BIT(0)
 101#define I2C_BUS_CLEAR_STATUS			0x088
 102#define I2C_BC_STATUS				BIT(0)
 103
 104#define I2C_CONFIG_LOAD				0x08c
 105#define I2C_MSTR_CONFIG_LOAD			BIT(0)
 106
 107#define I2C_CLKEN_OVERRIDE			0x090
 108#define I2C_MST_CORE_CLKEN_OVR			BIT(0)
 109
 110#define I2C_INTERFACE_TIMING_0			0x094
 111#define  I2C_INTERFACE_TIMING_THIGH		GENMASK(13, 8)
 112#define  I2C_INTERFACE_TIMING_TLOW		GENMASK(5, 0)
 113#define I2C_INTERFACE_TIMING_1			0x098
 114#define  I2C_INTERFACE_TIMING_TBUF		GENMASK(29, 24)
 115#define  I2C_INTERFACE_TIMING_TSU_STO		GENMASK(21, 16)
 116#define  I2C_INTERFACE_TIMING_THD_STA		GENMASK(13, 8)
 117#define  I2C_INTERFACE_TIMING_TSU_STA		GENMASK(5, 0)
 118
 119#define I2C_HS_INTERFACE_TIMING_0		0x09c
 120#define  I2C_HS_INTERFACE_TIMING_THIGH		GENMASK(13, 8)
 121#define  I2C_HS_INTERFACE_TIMING_TLOW		GENMASK(5, 0)
 122#define I2C_HS_INTERFACE_TIMING_1		0x0a0
 123#define  I2C_HS_INTERFACE_TIMING_TSU_STO	GENMASK(21, 16)
 124#define  I2C_HS_INTERFACE_TIMING_THD_STA	GENMASK(13, 8)
 125#define  I2C_HS_INTERFACE_TIMING_TSU_STA	GENMASK(5, 0)
 126
 127#define I2C_MST_FIFO_CONTROL			0x0b4
 128#define I2C_MST_FIFO_CONTROL_RX_FLUSH		BIT(0)
 129#define I2C_MST_FIFO_CONTROL_TX_FLUSH		BIT(1)
 130#define I2C_MST_FIFO_CONTROL_RX_TRIG(x)		(((x) - 1) <<  4)
 131#define I2C_MST_FIFO_CONTROL_TX_TRIG(x)		(((x) - 1) << 16)
 132
 133#define I2C_MST_FIFO_STATUS			0x0b8
 134#define I2C_MST_FIFO_STATUS_TX			GENMASK(23, 16)
 135#define I2C_MST_FIFO_STATUS_RX			GENMASK(7, 0)
 136
 137#define I2C_MASTER_RESET_CNTRL			0x0a8
 138
 139/* configuration load timeout in microseconds */
 140#define I2C_CONFIG_LOAD_TIMEOUT			1000000
 141
 142/* packet header size in bytes */
 143#define I2C_PACKET_HEADER_SIZE			12
 144
 145/*
 146 * I2C Controller will use PIO mode for transfers up to 32 bytes in order to
 147 * avoid DMA overhead, otherwise external APB DMA controller will be used.
 148 * Note that the actual MAX PIO length is 20 bytes because 32 bytes include
 149 * I2C_PACKET_HEADER_SIZE.
 150 */
 151#define I2C_PIO_MODE_PREFERRED_LEN		32
 152
 153/*
 154 * msg_end_type: The bus control which needs to be sent at end of transfer.
 155 * @MSG_END_STOP: Send stop pulse.
 156 * @MSG_END_REPEAT_START: Send repeat-start.
 157 * @MSG_END_CONTINUE: Don't send stop or repeat-start.
 158 */
 159enum msg_end_type {
 160	MSG_END_STOP,
 161	MSG_END_REPEAT_START,
 162	MSG_END_CONTINUE,
 163};
 164
 165/**
 166 * struct tegra_i2c_hw_feature : per hardware generation features
 167 * @has_continue_xfer_support: continue-transfer supported
 168 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
 169 *		completion interrupt on per packet basis.
 170 * @has_config_load_reg: Has the config load register to load the new
 171 *		configuration.
 172 * @clk_divisor_hs_mode: Clock divisor in HS mode.
 173 * @clk_divisor_std_mode: Clock divisor in standard mode. It is
 174 *		applicable if there is no fast clock source i.e. single clock
 175 *		source.
 176 * @clk_divisor_fast_mode: Clock divisor in fast mode. It is
 177 *		applicable if there is no fast clock source i.e. single clock
 178 *		source.
 179 * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is
 180 *		applicable if there is no fast clock source (i.e. single
 181 *		clock source).
 182 * @has_multi_master_mode: The I2C controller supports running in single-master
 183 *		or multi-master mode.
 184 * @has_slcg_override_reg: The I2C controller supports a register that
 185 *		overrides the second level clock gating.
 186 * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that
 187 *		provides additional features and allows for longer messages to
 188 *		be transferred in one go.
 189 * @has_mst_reset: The I2C controller contains MASTER_RESET_CTRL register which
 190 *		provides an alternative to controller reset when configured as
 191 *		I2C master
 192 * @quirks: I2C adapter quirks for limiting write/read transfer size and not
 193 *		allowing 0 length transfers.
 194 * @supports_bus_clear: Bus Clear support to recover from bus hang during
 195 *		SDA stuck low from device for some unknown reasons.
 196 * @has_apb_dma: Support of APBDMA on corresponding Tegra chip.
 197 * @tlow_std_mode: Low period of the clock in standard mode.
 198 * @thigh_std_mode: High period of the clock in standard mode.
 199 * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes.
 200 * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes.
 201 * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions
 202 *		in standard mode.
 203 * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and stop
 204 *		conditions in fast/fast-plus modes.
 205 * @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions
 206 *		in HS mode.
 207 * @has_interface_timing_reg: Has interface timing register to program the tuned
 208 *		timing settings.
 209 */
 210struct tegra_i2c_hw_feature {
 211	bool has_continue_xfer_support;
 212	bool has_per_pkt_xfer_complete_irq;
 213	bool has_config_load_reg;
 214	u32 clk_divisor_hs_mode;
 215	u32 clk_divisor_std_mode;
 216	u32 clk_divisor_fast_mode;
 217	u32 clk_divisor_fast_plus_mode;
 218	bool has_multi_master_mode;
 219	bool has_slcg_override_reg;
 220	bool has_mst_fifo;
 221	bool has_mst_reset;
 222	const struct i2c_adapter_quirks *quirks;
 223	bool supports_bus_clear;
 224	bool has_apb_dma;
 225	u32 tlow_std_mode;
 226	u32 thigh_std_mode;
 227	u32 tlow_fast_fastplus_mode;
 228	u32 thigh_fast_fastplus_mode;
 229	u32 setup_hold_time_std_mode;
 230	u32 setup_hold_time_fast_fast_plus_mode;
 231	u32 setup_hold_time_hs_mode;
 232	bool has_interface_timing_reg;
 233};
 234
 235/**
 236 * struct tegra_i2c_dev - per device I2C context
 237 * @dev: device reference for power management
 238 * @hw: Tegra I2C HW feature
 239 * @adapter: core I2C layer adapter information
 240 * @div_clk: clock reference for div clock of I2C controller
 241 * @clocks: array of I2C controller clocks
 242 * @nclocks: number of clocks in the array
 243 * @rst: reset control for the I2C controller
 244 * @base: ioremapped registers cookie
 245 * @base_phys: physical base address of the I2C controller
 246 * @cont_id: I2C controller ID, used for packet header
 247 * @irq: IRQ number of transfer complete interrupt
 248 * @is_dvc: identifies the DVC I2C controller, has a different register layout
 249 * @is_vi: identifies the VI I2C controller, has a different register layout
 250 * @msg_complete: transfer completion notifier
 251 * @msg_buf_remaining: size of unsent data in the message buffer
 252 * @msg_len: length of message in current transfer
 253 * @msg_err: error code for completed message
 254 * @msg_buf: pointer to current message data
 255 * @msg_read: indicates that the transfer is a read access
 256 * @timings: i2c timings information like bus frequency
 257 * @multimaster_mode: indicates that I2C controller is in multi-master mode
 258 * @dma_chan: DMA channel
 259 * @dma_phys: handle to DMA resources
 260 * @dma_buf: pointer to allocated DMA buffer
 261 * @dma_buf_size: DMA buffer size
 262 * @dma_dev: DMA device used for transfers
 263 * @dma_mode: indicates active DMA transfer
 264 * @dma_complete: DMA completion notifier
 265 * @atomic_mode: indicates active atomic transfer
 266 */
 267struct tegra_i2c_dev {
 268	struct device *dev;
 269	struct i2c_adapter adapter;
 270
 271	const struct tegra_i2c_hw_feature *hw;
 272	struct reset_control *rst;
 273	unsigned int cont_id;
 274	unsigned int irq;
 275
 276	phys_addr_t base_phys;
 277	void __iomem *base;
 278
 279	struct clk_bulk_data clocks[2];
 280	unsigned int nclocks;
 281
 282	struct clk *div_clk;
 283	struct i2c_timings timings;
 284
 285	struct completion msg_complete;
 286	size_t msg_buf_remaining;
 287	unsigned int msg_len;
 288	int msg_err;
 289	u8 *msg_buf;
 290
 291	struct completion dma_complete;
 292	struct dma_chan *dma_chan;
 293	unsigned int dma_buf_size;
 294	struct device *dma_dev;
 295	dma_addr_t dma_phys;
 296	void *dma_buf;
 297
 298	bool multimaster_mode;
 299	bool atomic_mode;
 300	bool dma_mode;
 301	bool msg_read;
 302	bool is_dvc;
 303	bool is_vi;
 304};
 305
 306#define IS_DVC(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && (dev)->is_dvc)
 307#define IS_VI(dev)  (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && (dev)->is_vi)
 308
 309static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 310		       unsigned int reg)
 311{
 312	writel_relaxed(val, i2c_dev->base + reg);
 313}
 314
 315static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
 316{
 317	return readl_relaxed(i2c_dev->base + reg);
 318}
 319
 320/*
 321 * If necessary, i2c_writel() and i2c_readl() will offset the register
 322 * in order to talk to the I2C block inside the DVC block.
 323 */
 324static u32 tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
 325{
 326	if (IS_DVC(i2c_dev))
 327		reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
 328	else if (IS_VI(i2c_dev))
 329		reg = 0xc00 + (reg << 2);
 330
 331	return reg;
 332}
 333
 334static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned int reg)
 335{
 336	writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 337
 338	/* read back register to make sure that register writes completed */
 339	if (reg != I2C_TX_FIFO)
 340		readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 341	else if (IS_VI(i2c_dev))
 342		readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, I2C_INT_STATUS));
 343}
 344
 345static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
 346{
 347	return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 348}
 349
 350static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
 351			unsigned int reg, unsigned int len)
 352{
 353	writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 354}
 355
 356static void i2c_writesl_vi(struct tegra_i2c_dev *i2c_dev, void *data,
 357			   unsigned int reg, unsigned int len)
 358{
 359	u32 *data32 = data;
 360
 361	/*
 362	 * VI I2C controller has known hardware bug where writes get stuck
 363	 * when immediate multiple writes happen to TX_FIFO register.
 364	 * Recommended software work around is to read I2C register after
 365	 * each write to TX_FIFO register to flush out the data.
 366	 */
 367	while (len--)
 368		i2c_writel(i2c_dev, *data32++, reg);
 369}
 370
 371static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
 372		       unsigned int reg, unsigned int len)
 373{
 374	readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 375}
 376
 377static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 378{
 379	u32 int_mask;
 380
 381	int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask;
 382	i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 383}
 384
 385static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 386{
 387	u32 int_mask;
 388
 389	int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask;
 390	i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 391}
 392
 393static void tegra_i2c_dma_complete(void *args)
 394{
 395	struct tegra_i2c_dev *i2c_dev = args;
 396
 397	complete(&i2c_dev->dma_complete);
 398}
 399
 400static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len)
 401{
 402	struct dma_async_tx_descriptor *dma_desc;
 403	enum dma_transfer_direction dir;
 404
 405	dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len);
 406
 407	reinit_completion(&i2c_dev->dma_complete);
 408
 409	dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
 410
 411	dma_desc = dmaengine_prep_slave_single(i2c_dev->dma_chan, i2c_dev->dma_phys,
 412					       len, dir, DMA_PREP_INTERRUPT |
 413					       DMA_CTRL_ACK);
 414	if (!dma_desc) {
 415		dev_err(i2c_dev->dev, "failed to get %s DMA descriptor\n",
 416			i2c_dev->msg_read ? "RX" : "TX");
 417		return -EINVAL;
 418	}
 419
 420	dma_desc->callback = tegra_i2c_dma_complete;
 421	dma_desc->callback_param = i2c_dev;
 422
 423	dmaengine_submit(dma_desc);
 424	dma_async_issue_pending(i2c_dev->dma_chan);
 425
 426	return 0;
 427}
 428
 429static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev)
 430{
 431	if (i2c_dev->dma_buf) {
 432		dma_free_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size,
 433				  i2c_dev->dma_buf, i2c_dev->dma_phys);
 434		i2c_dev->dma_buf = NULL;
 435	}
 436
 437	if (i2c_dev->dma_chan) {
 438		dma_release_channel(i2c_dev->dma_chan);
 439		i2c_dev->dma_chan = NULL;
 440	}
 441}
 442
 443static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev)
 444{
 445	dma_addr_t dma_phys;
 446	u32 *dma_buf;
 447	int err;
 448
 449	if (IS_VI(i2c_dev))
 450		return 0;
 451
 452	if (i2c_dev->hw->has_apb_dma) {
 453		if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) {
 454			dev_dbg(i2c_dev->dev, "APB DMA support not enabled\n");
 455			return 0;
 456		}
 457	} else if (!IS_ENABLED(CONFIG_TEGRA186_GPC_DMA)) {
 458		dev_dbg(i2c_dev->dev, "GPC DMA support not enabled\n");
 459		return 0;
 460	}
 461
 462	/*
 463	 * The same channel will be used for both RX and TX.
 464	 * Keeping the name as "tx" for backward compatibility
 465	 * with existing devicetrees.
 466	 */
 467	i2c_dev->dma_chan = dma_request_chan(i2c_dev->dev, "tx");
 468	if (IS_ERR(i2c_dev->dma_chan)) {
 469		err = PTR_ERR(i2c_dev->dma_chan);
 470		i2c_dev->dma_chan = NULL;
 471		goto err_out;
 472	}
 473
 474	i2c_dev->dma_dev = i2c_dev->dma_chan->device->dev;
 475	i2c_dev->dma_buf_size = i2c_dev->hw->quirks->max_write_len +
 476				I2C_PACKET_HEADER_SIZE;
 477
 478	dma_buf = dma_alloc_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size,
 479				     &dma_phys, GFP_KERNEL | __GFP_NOWARN);
 480	if (!dma_buf) {
 481		dev_err(i2c_dev->dev, "failed to allocate DMA buffer\n");
 482		err = -ENOMEM;
 483		goto err_out;
 484	}
 485
 486	i2c_dev->dma_buf = dma_buf;
 487	i2c_dev->dma_phys = dma_phys;
 488
 489	return 0;
 490
 491err_out:
 492	tegra_i2c_release_dma(i2c_dev);
 493	if (err != -EPROBE_DEFER) {
 494		dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err);
 495		dev_err(i2c_dev->dev, "falling back to PIO\n");
 496		return 0;
 497	}
 498
 499	return err;
 500}
 501
 502/*
 503 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
 504 * block.  This block is identical to the rest of the I2C blocks, except that
 505 * it only supports master mode, it has registers moved around, and it needs
 506 * some extra init to get it into I2C mode.  The register moves are handled
 507 * by i2c_readl() and i2c_writel().
 508 */
 509static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
 510{
 511	u32 val;
 512
 513	val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
 514	val |= DVC_CTRL_REG3_SW_PROG;
 515	val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
 516	dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
 517
 518	val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
 519	val |= DVC_CTRL_REG1_INTR_EN;
 520	dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
 521}
 522
 523static void tegra_i2c_vi_init(struct tegra_i2c_dev *i2c_dev)
 524{
 525	u32 value;
 526
 527	value = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, 2) |
 528		FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, 4);
 529	i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_0);
 530
 531	value = FIELD_PREP(I2C_INTERFACE_TIMING_TBUF, 4) |
 532		FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STO, 7) |
 533		FIELD_PREP(I2C_INTERFACE_TIMING_THD_STA, 4) |
 534		FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STA, 4);
 535	i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_1);
 536
 537	value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, 3) |
 538		FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, 8);
 539	i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_0);
 540
 541	value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STO, 11) |
 542		FIELD_PREP(I2C_HS_INTERFACE_TIMING_THD_STA, 11) |
 543		FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STA, 11);
 544	i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_1);
 545
 546	value = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND;
 547	i2c_writel(i2c_dev, value, I2C_BUS_CLEAR_CNFG);
 548
 549	i2c_writel(i2c_dev, 0x0, I2C_TLOW_SEXT);
 550}
 551
 552static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev,
 553				   u32 reg, u32 mask, u32 delay_us,
 554				   u32 timeout_us)
 555{
 556	void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg);
 557	u32 val;
 558
 559	if (!i2c_dev->atomic_mode)
 560		return readl_relaxed_poll_timeout(addr, val, !(val & mask),
 561						  delay_us, timeout_us);
 562
 563	return readl_relaxed_poll_timeout_atomic(addr, val, !(val & mask),
 564						 delay_us, timeout_us);
 565}
 566
 567static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
 568{
 569	u32 mask, val, offset;
 570	int err;
 571
 572	if (i2c_dev->hw->has_mst_fifo) {
 573		mask = I2C_MST_FIFO_CONTROL_TX_FLUSH |
 574		       I2C_MST_FIFO_CONTROL_RX_FLUSH;
 575		offset = I2C_MST_FIFO_CONTROL;
 576	} else {
 577		mask = I2C_FIFO_CONTROL_TX_FLUSH |
 578		       I2C_FIFO_CONTROL_RX_FLUSH;
 579		offset = I2C_FIFO_CONTROL;
 580	}
 581
 582	val = i2c_readl(i2c_dev, offset);
 583	val |= mask;
 584	i2c_writel(i2c_dev, val, offset);
 585
 586	err = tegra_i2c_poll_register(i2c_dev, offset, mask, 1000, 1000000);
 587	if (err) {
 588		dev_err(i2c_dev->dev, "failed to flush FIFO\n");
 589		return err;
 590	}
 591
 592	return 0;
 593}
 594
 595static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
 596{
 597	int err;
 598
 599	if (!i2c_dev->hw->has_config_load_reg)
 600		return 0;
 601
 602	i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
 603
 604	err = tegra_i2c_poll_register(i2c_dev, I2C_CONFIG_LOAD, 0xffffffff,
 605				      1000, I2C_CONFIG_LOAD_TIMEOUT);
 606	if (err) {
 607		dev_err(i2c_dev->dev, "failed to load config\n");
 608		return err;
 609	}
 610
 611	return 0;
 612}
 613
 614static int tegra_i2c_master_reset(struct tegra_i2c_dev *i2c_dev)
 615{
 616	if (!i2c_dev->hw->has_mst_reset)
 617		return -EOPNOTSUPP;
 618
 619	/*
 620	 * Writing 1 to I2C_MASTER_RESET_CNTRL will reset all internal state of
 621	 * Master logic including FIFOs. Clear this bit to 0 for normal operation.
 622	 * SW needs to wait for 2us after assertion and de-assertion of this soft
 623	 * reset.
 624	 */
 625	i2c_writel(i2c_dev, 0x1, I2C_MASTER_RESET_CNTRL);
 626	fsleep(2);
 627
 628	i2c_writel(i2c_dev, 0x0, I2C_MASTER_RESET_CNTRL);
 629	fsleep(2);
 630
 631	return 0;
 632}
 633
 634static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
 635{
 636	u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode;
 637	struct i2c_timings *t = &i2c_dev->timings;
 638	int err;
 639
 640	/*
 641	 * Reset the controller before initializing it.
 642	 * In case if device_reset() returns -ENOENT, i.e. when the reset is
 643	 * not available, the internal software reset will be used if it is
 644	 * supported by the controller.
 645	 */
 646	err = device_reset(i2c_dev->dev);
 647	if (err == -ENOENT)
 648		err = tegra_i2c_master_reset(i2c_dev);
 649
 650	/*
 651	 * The reset shouldn't ever fail in practice. The failure will be a
 652	 * sign of a severe problem that needs to be resolved. Still we don't
 653	 * want to fail the initialization completely because this may break
 654	 * kernel boot up since voltage regulators use I2C. Hence, we will
 655	 * emit a noisy warning on error, which won't stay unnoticed and
 656	 * won't hose machine entirely.
 657	 */
 658	WARN_ON_ONCE(err);
 659
 660	if (IS_DVC(i2c_dev))
 661		tegra_dvc_init(i2c_dev);
 662
 663	val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
 664	      FIELD_PREP(I2C_CNFG_DEBOUNCE_CNT, 2);
 665
 666	if (i2c_dev->hw->has_multi_master_mode)
 667		val |= I2C_CNFG_MULTI_MASTER_MODE;
 668
 669	i2c_writel(i2c_dev, val, I2C_CNFG);
 670	i2c_writel(i2c_dev, 0, I2C_INT_MASK);
 671
 672	if (IS_VI(i2c_dev))
 673		tegra_i2c_vi_init(i2c_dev);
 674
 675	switch (t->bus_freq_hz) {
 676	case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ:
 677	default:
 678		tlow = i2c_dev->hw->tlow_fast_fastplus_mode;
 679		thigh = i2c_dev->hw->thigh_fast_fastplus_mode;
 680		tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode;
 681
 682		if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ)
 683			non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode;
 684		else
 685			non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
 686		break;
 687
 688	case 0 ... I2C_MAX_STANDARD_MODE_FREQ:
 689		tlow = i2c_dev->hw->tlow_std_mode;
 690		thigh = i2c_dev->hw->thigh_std_mode;
 691		tsu_thd = i2c_dev->hw->setup_hold_time_std_mode;
 692		non_hs_mode = i2c_dev->hw->clk_divisor_std_mode;
 693		break;
 694	}
 695
 696	/* make sure clock divisor programmed correctly */
 697	clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE,
 698				 i2c_dev->hw->clk_divisor_hs_mode) |
 699		      FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode);
 700	i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
 701
 702	if (i2c_dev->hw->has_interface_timing_reg) {
 703		val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) |
 704		      FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow);
 705		i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0);
 706	}
 707
 708	/*
 709	 * Configure setup and hold times only when tsu_thd is non-zero.
 710	 * Otherwise, preserve the chip default values.
 711	 */
 712	if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
 713		i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
 714
 715	clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1);
 716
 717	err = clk_set_rate(i2c_dev->div_clk,
 718			   t->bus_freq_hz * clk_multiplier);
 719	if (err) {
 720		dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err);
 721		return err;
 722	}
 723
 724	if (!IS_DVC(i2c_dev) && !IS_VI(i2c_dev)) {
 725		u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
 726
 727		sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
 728		i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
 729		i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
 730		i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
 731	}
 732
 733	err = tegra_i2c_flush_fifos(i2c_dev);
 734	if (err)
 735		return err;
 736
 737	if (i2c_dev->multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
 738		i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
 739
 740	err = tegra_i2c_wait_for_config_load(i2c_dev);
 741	if (err)
 742		return err;
 743
 744	return 0;
 745}
 746
 747static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev)
 748{
 749	u32 cnfg;
 750
 751	/*
 752	 * NACK interrupt is generated before the I2C controller generates
 753	 * the STOP condition on the bus.  So, wait for 2 clock periods
 754	 * before disabling the controller so that the STOP condition has
 755	 * been delivered properly.
 756	 */
 757	udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->timings.bus_freq_hz));
 758
 759	cnfg = i2c_readl(i2c_dev, I2C_CNFG);
 760	if (cnfg & I2C_CNFG_PACKET_MODE_EN)
 761		i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG);
 762
 763	return tegra_i2c_wait_for_config_load(i2c_dev);
 764}
 765
 766static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
 767{
 768	size_t buf_remaining = i2c_dev->msg_buf_remaining;
 769	unsigned int words_to_transfer, rx_fifo_avail;
 770	u8 *buf = i2c_dev->msg_buf;
 771	u32 val;
 772
 773	/*
 774	 * Catch overflow due to message fully sent before the check for
 775	 * RX FIFO availability.
 776	 */
 777	if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining)))
 778		return -EINVAL;
 779
 780	if (i2c_dev->hw->has_mst_fifo) {
 781		val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
 782		rx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_RX, val);
 783	} else {
 784		val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 785		rx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_RX, val);
 786	}
 787
 788	/* round down to exclude partial word at the end of buffer */
 789	words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 790	if (words_to_transfer > rx_fifo_avail)
 791		words_to_transfer = rx_fifo_avail;
 792
 793	i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
 794
 795	buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 796	buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 797	rx_fifo_avail -= words_to_transfer;
 798
 799	/*
 800	 * If there is a partial word at the end of buffer, handle it
 801	 * manually to prevent overwriting past the end of buffer.
 802	 */
 803	if (rx_fifo_avail > 0 && buf_remaining > 0) {
 804		/*
 805		 * buf_remaining > 3 check not needed as rx_fifo_avail == 0
 806		 * when (words_to_transfer was > rx_fifo_avail) earlier
 807		 * in this function.
 808		 */
 809		val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 810		val = cpu_to_le32(val);
 811		memcpy(buf, &val, buf_remaining);
 812		buf_remaining = 0;
 813		rx_fifo_avail--;
 814	}
 815
 816	/* RX FIFO must be drained, otherwise it's an Overflow case. */
 817	if (WARN_ON_ONCE(rx_fifo_avail))
 818		return -EINVAL;
 819
 820	i2c_dev->msg_buf_remaining = buf_remaining;
 821	i2c_dev->msg_buf = buf;
 822
 823	return 0;
 824}
 825
 826static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 827{
 828	size_t buf_remaining = i2c_dev->msg_buf_remaining;
 829	unsigned int words_to_transfer, tx_fifo_avail;
 830	u8 *buf = i2c_dev->msg_buf;
 831	u32 val;
 832
 833	if (i2c_dev->hw->has_mst_fifo) {
 834		val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
 835		tx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_TX, val);
 836	} else {
 837		val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 838		tx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_TX, val);
 839	}
 840
 841	/* round down to exclude partial word at the end of buffer */
 842	words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 843
 844	/*
 845	 * This hunk pushes 4 bytes at a time into the TX FIFO.
 846	 *
 847	 * It's very common to have < 4 bytes, hence there is no word
 848	 * to push if we have less than 4 bytes to transfer.
 849	 */
 850	if (words_to_transfer) {
 851		if (words_to_transfer > tx_fifo_avail)
 852			words_to_transfer = tx_fifo_avail;
 853
 854		/*
 855		 * Update state before writing to FIFO.  Note that this may
 856		 * cause us to finish writing all bytes (AKA buf_remaining
 857		 * goes to 0), hence we have a potential for an interrupt
 858		 * (PACKET_XFER_COMPLETE is not maskable), but GIC interrupt
 859		 * is disabled at this point.
 860		 */
 861		buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 862		tx_fifo_avail -= words_to_transfer;
 863
 864		i2c_dev->msg_buf_remaining = buf_remaining;
 865		i2c_dev->msg_buf = buf + words_to_transfer * BYTES_PER_FIFO_WORD;
 866
 867		if (IS_VI(i2c_dev))
 868			i2c_writesl_vi(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
 869		else
 870			i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
 871
 872		buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 873	}
 874
 875	/*
 876	 * If there is a partial word at the end of buffer, handle it manually
 877	 * to prevent reading past the end of buffer, which could cross a page
 878	 * boundary and fault.
 879	 */
 880	if (tx_fifo_avail > 0 && buf_remaining > 0) {
 881		/*
 882		 * buf_remaining > 3 check not needed as tx_fifo_avail == 0
 883		 * when (words_to_transfer was > tx_fifo_avail) earlier
 884		 * in this function for non-zero words_to_transfer.
 885		 */
 886		memcpy(&val, buf, buf_remaining);
 887		val = le32_to_cpu(val);
 888
 889		i2c_dev->msg_buf_remaining = 0;
 890		i2c_dev->msg_buf = NULL;
 891
 892		i2c_writel(i2c_dev, val, I2C_TX_FIFO);
 893	}
 894
 895	return 0;
 896}
 897
 898static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 899{
 900	const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 901	struct tegra_i2c_dev *i2c_dev = dev_id;
 902	u32 status;
 903
 904	status = i2c_readl(i2c_dev, I2C_INT_STATUS);
 905
 906	if (status == 0) {
 907		dev_warn(i2c_dev->dev, "IRQ status 0 %08x %08x %08x\n",
 908			 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
 909			 i2c_readl(i2c_dev, I2C_STATUS),
 910			 i2c_readl(i2c_dev, I2C_CNFG));
 911		i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 912		goto err;
 913	}
 914
 915	if (status & status_err) {
 916		tegra_i2c_disable_packet_mode(i2c_dev);
 917		if (status & I2C_INT_NO_ACK)
 918			i2c_dev->msg_err |= I2C_ERR_NO_ACK;
 919		if (status & I2C_INT_ARBITRATION_LOST)
 920			i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
 921		goto err;
 922	}
 923
 924	/*
 925	 * I2C transfer is terminated during the bus clear, so skip
 926	 * processing the other interrupts.
 927	 */
 928	if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE))
 929		goto err;
 930
 931	if (!i2c_dev->dma_mode) {
 932		if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
 933			if (tegra_i2c_empty_rx_fifo(i2c_dev)) {
 934				/*
 935				 * Overflow error condition: message fully sent,
 936				 * with no XFER_COMPLETE interrupt but hardware
 937				 * asks to transfer more.
 938				 */
 939				i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW;
 940				goto err;
 941			}
 942		}
 943
 944		if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
 945			if (i2c_dev->msg_buf_remaining)
 946				tegra_i2c_fill_tx_fifo(i2c_dev);
 947			else
 948				tegra_i2c_mask_irq(i2c_dev,
 949						   I2C_INT_TX_FIFO_DATA_REQ);
 950		}
 951	}
 952
 953	i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 954	if (IS_DVC(i2c_dev))
 955		dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 956
 957	/*
 958	 * During message read XFER_COMPLETE interrupt is triggered prior to
 959	 * DMA completion and during message write XFER_COMPLETE interrupt is
 960	 * triggered after DMA completion.
 961	 *
 962	 * PACKETS_XFER_COMPLETE indicates completion of all bytes of transfer,
 963	 * so forcing msg_buf_remaining to 0 in DMA mode.
 964	 */
 965	if (status & I2C_INT_PACKET_XFER_COMPLETE) {
 966		if (i2c_dev->dma_mode)
 967			i2c_dev->msg_buf_remaining = 0;
 968		/*
 969		 * Underflow error condition: XFER_COMPLETE before message
 970		 * fully sent.
 971		 */
 972		if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) {
 973			i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 974			goto err;
 975		}
 976		complete(&i2c_dev->msg_complete);
 977	}
 978	goto done;
 979err:
 980	/* mask all interrupts on error */
 981	tegra_i2c_mask_irq(i2c_dev,
 982			   I2C_INT_NO_ACK |
 983			   I2C_INT_ARBITRATION_LOST |
 984			   I2C_INT_PACKET_XFER_COMPLETE |
 985			   I2C_INT_TX_FIFO_DATA_REQ |
 986			   I2C_INT_RX_FIFO_DATA_REQ);
 987
 988	if (i2c_dev->hw->supports_bus_clear)
 989		tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
 990
 991	i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 992
 993	if (IS_DVC(i2c_dev))
 994		dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 995
 996	if (i2c_dev->dma_mode) {
 997		dmaengine_terminate_async(i2c_dev->dma_chan);
 998		complete(&i2c_dev->dma_complete);
 999	}
1000
1001	complete(&i2c_dev->msg_complete);
1002done:
1003	return IRQ_HANDLED;
1004}
1005
1006static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev,
1007				       size_t len)
1008{
1009	struct dma_slave_config slv_config = {0};
1010	u32 val, reg, dma_burst, reg_offset;
1011	int err;
1012
1013	if (i2c_dev->hw->has_mst_fifo)
1014		reg = I2C_MST_FIFO_CONTROL;
1015	else
1016		reg = I2C_FIFO_CONTROL;
1017
1018	if (i2c_dev->dma_mode) {
1019		if (len & 0xF)
1020			dma_burst = 1;
1021		else if (len & 0x10)
1022			dma_burst = 4;
1023		else
1024			dma_burst = 8;
1025
1026		if (i2c_dev->msg_read) {
1027			reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO);
1028
1029			slv_config.src_addr = i2c_dev->base_phys + reg_offset;
1030			slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1031			slv_config.src_maxburst = dma_burst;
1032
1033			if (i2c_dev->hw->has_mst_fifo)
1034				val = I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst);
1035			else
1036				val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst);
1037		} else {
1038			reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO);
1039
1040			slv_config.dst_addr = i2c_dev->base_phys + reg_offset;
1041			slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1042			slv_config.dst_maxburst = dma_burst;
1043
1044			if (i2c_dev->hw->has_mst_fifo)
1045				val = I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst);
1046			else
1047				val = I2C_FIFO_CONTROL_TX_TRIG(dma_burst);
1048		}
1049
1050		slv_config.device_fc = true;
1051		err = dmaengine_slave_config(i2c_dev->dma_chan, &slv_config);
1052		if (err) {
1053			dev_err(i2c_dev->dev, "DMA config failed: %d\n", err);
1054			dev_err(i2c_dev->dev, "falling back to PIO\n");
1055
1056			tegra_i2c_release_dma(i2c_dev);
1057			i2c_dev->dma_mode = false;
1058		} else {
1059			goto out;
1060		}
1061	}
1062
1063	if (i2c_dev->hw->has_mst_fifo)
1064		val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) |
1065		      I2C_MST_FIFO_CONTROL_RX_TRIG(1);
1066	else
1067		val = I2C_FIFO_CONTROL_TX_TRIG(8) |
1068		      I2C_FIFO_CONTROL_RX_TRIG(1);
1069out:
1070	i2c_writel(i2c_dev, val, reg);
1071}
1072
1073static unsigned long tegra_i2c_poll_completion(struct tegra_i2c_dev *i2c_dev,
1074					       struct completion *complete,
1075					       unsigned int timeout_ms)
1076{
1077	ktime_t ktime = ktime_get();
1078	ktime_t ktimeout = ktime_add_ms(ktime, timeout_ms);
1079
1080	do {
1081		u32 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
1082
1083		if (status)
1084			tegra_i2c_isr(i2c_dev->irq, i2c_dev);
1085
1086		if (completion_done(complete)) {
1087			s64 delta = ktime_ms_delta(ktimeout, ktime);
1088
1089			return msecs_to_jiffies(delta) ?: 1;
1090		}
1091
1092		ktime = ktime_get();
1093
1094	} while (ktime_before(ktime, ktimeout));
1095
1096	return 0;
1097}
1098
1099static unsigned long tegra_i2c_wait_completion(struct tegra_i2c_dev *i2c_dev,
1100					       struct completion *complete,
1101					       unsigned int timeout_ms)
1102{
1103	unsigned long ret;
1104
1105	if (i2c_dev->atomic_mode) {
1106		ret = tegra_i2c_poll_completion(i2c_dev, complete, timeout_ms);
1107	} else {
1108		enable_irq(i2c_dev->irq);
1109		ret = wait_for_completion_timeout(complete,
1110						  msecs_to_jiffies(timeout_ms));
1111		disable_irq(i2c_dev->irq);
1112
1113		/*
1114		 * Under some rare circumstances (like running KASAN +
1115		 * NFS root) CPU, which handles interrupt, may stuck in
1116		 * uninterruptible state for a significant time.  In this
1117		 * case we will get timeout if I2C transfer is running on
1118		 * a sibling CPU, despite of IRQ being raised.
1119		 *
1120		 * In order to handle this rare condition, the IRQ status
1121		 * needs to be checked after timeout.
1122		 */
1123		if (ret == 0)
1124			ret = tegra_i2c_poll_completion(i2c_dev, complete, 0);
1125	}
1126
1127	return ret;
1128}
1129
1130static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap)
1131{
1132	struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1133	u32 val, time_left;
1134	int err;
1135
1136	reinit_completion(&i2c_dev->msg_complete);
1137
1138	val = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND |
1139	      I2C_BC_TERMINATE;
1140	i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG);
1141
1142	err = tegra_i2c_wait_for_config_load(i2c_dev);
1143	if (err)
1144		return err;
1145
1146	val |= I2C_BC_ENABLE;
1147	i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG);
1148	tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1149
1150	time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 50);
1151	tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1152
1153	if (time_left == 0) {
1154		dev_err(i2c_dev->dev, "failed to clear bus\n");
1155		return -ETIMEDOUT;
1156	}
1157
1158	val = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS);
1159	if (!(val & I2C_BC_STATUS)) {
1160		dev_err(i2c_dev->dev, "un-recovered arbitration lost\n");
1161		return -EIO;
1162	}
1163
1164	return -EAGAIN;
1165}
1166
1167static void tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev,
1168					 struct i2c_msg *msg,
1169					 enum msg_end_type end_state)
1170{
1171	u32 *dma_buf = i2c_dev->dma_buf;
1172	u32 packet_header;
1173
1174	packet_header = FIELD_PREP(PACKET_HEADER0_HEADER_SIZE, 0) |
1175			FIELD_PREP(PACKET_HEADER0_PROTOCOL,
1176				   PACKET_HEADER0_PROTOCOL_I2C) |
1177			FIELD_PREP(PACKET_HEADER0_CONT_ID, i2c_dev->cont_id) |
1178			FIELD_PREP(PACKET_HEADER0_PACKET_ID, 1);
1179
1180	if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1181		*dma_buf++ = packet_header;
1182	else
1183		i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1184
1185	packet_header = i2c_dev->msg_len - 1;
1186
1187	if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1188		*dma_buf++ = packet_header;
1189	else
1190		i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1191
1192	packet_header = I2C_HEADER_IE_ENABLE;
1193
1194	if (end_state == MSG_END_CONTINUE)
1195		packet_header |= I2C_HEADER_CONTINUE_XFER;
1196	else if (end_state == MSG_END_REPEAT_START)
1197		packet_header |= I2C_HEADER_REPEAT_START;
1198
1199	if (msg->flags & I2C_M_TEN) {
1200		packet_header |= msg->addr;
1201		packet_header |= I2C_HEADER_10BIT_ADDR;
1202	} else {
1203		packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
1204	}
1205
1206	if (msg->flags & I2C_M_IGNORE_NAK)
1207		packet_header |= I2C_HEADER_CONT_ON_NAK;
1208
1209	if (msg->flags & I2C_M_RD)
1210		packet_header |= I2C_HEADER_READ;
1211
1212	if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1213		*dma_buf++ = packet_header;
1214	else
1215		i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1216}
1217
1218static int tegra_i2c_error_recover(struct tegra_i2c_dev *i2c_dev,
1219				   struct i2c_msg *msg)
1220{
1221	if (i2c_dev->msg_err == I2C_ERR_NONE)
1222		return 0;
1223
1224	tegra_i2c_init(i2c_dev);
1225
1226	/* start recovery upon arbitration loss in single master mode */
1227	if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) {
1228		if (!i2c_dev->multimaster_mode)
1229			return i2c_recover_bus(&i2c_dev->adapter);
1230
1231		return -EAGAIN;
1232	}
1233
1234	if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
1235		if (msg->flags & I2C_M_IGNORE_NAK)
1236			return 0;
1237
1238		return -EREMOTEIO;
1239	}
1240
1241	return -EIO;
1242}
1243
1244static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
1245			      struct i2c_msg *msg,
1246			      enum msg_end_type end_state)
1247{
1248	unsigned long time_left, xfer_time = 100;
1249	size_t xfer_size;
1250	u32 int_mask;
1251	int err;
1252
1253	err = tegra_i2c_flush_fifos(i2c_dev);
1254	if (err)
1255		return err;
1256
1257	i2c_dev->msg_buf = msg->buf;
1258	i2c_dev->msg_len = msg->len;
1259
1260	i2c_dev->msg_err = I2C_ERR_NONE;
1261	i2c_dev->msg_read = !!(msg->flags & I2C_M_RD);
1262	reinit_completion(&i2c_dev->msg_complete);
1263
1264	/*
1265	 * For SMBUS block read command, read only 1 byte in the first transfer.
1266	 * Adjust that 1 byte for the next transfer in the msg buffer and msg
1267	 * length.
1268	 */
1269	if (msg->flags & I2C_M_RECV_LEN) {
1270		if (end_state == MSG_END_CONTINUE) {
1271			i2c_dev->msg_len = 1;
1272		} else {
1273			i2c_dev->msg_buf += 1;
1274			i2c_dev->msg_len -= 1;
1275		}
1276	}
1277
1278	i2c_dev->msg_buf_remaining = i2c_dev->msg_len;
1279
1280	if (i2c_dev->msg_read)
1281		xfer_size = i2c_dev->msg_len;
1282	else
1283		xfer_size = i2c_dev->msg_len + I2C_PACKET_HEADER_SIZE;
1284
1285	xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD);
1286
1287	i2c_dev->dma_mode = xfer_size > I2C_PIO_MODE_PREFERRED_LEN &&
1288			    i2c_dev->dma_buf && !i2c_dev->atomic_mode;
1289
1290	tegra_i2c_config_fifo_trig(i2c_dev, xfer_size);
1291
1292	/*
1293	 * Transfer time in mSec = Total bits / transfer rate
1294	 * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits
1295	 */
1296	xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC,
1297				       i2c_dev->timings.bus_freq_hz);
1298
1299	int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
1300	tegra_i2c_unmask_irq(i2c_dev, int_mask);
1301
1302	if (i2c_dev->dma_mode) {
1303		if (i2c_dev->msg_read) {
1304			err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1305			if (err)
1306				return err;
1307		}
1308	}
1309
1310	tegra_i2c_push_packet_header(i2c_dev, msg, end_state);
1311
1312	if (!i2c_dev->msg_read) {
1313		if (i2c_dev->dma_mode) {
1314			memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE,
1315			       msg->buf, i2c_dev->msg_len);
1316			err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1317			if (err)
1318				return err;
1319		} else {
1320			tegra_i2c_fill_tx_fifo(i2c_dev);
1321		}
1322	}
1323
1324	if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
1325		int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
1326
1327	if (!i2c_dev->dma_mode) {
1328		if (msg->flags & I2C_M_RD)
1329			int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
1330		else if (i2c_dev->msg_buf_remaining)
1331			int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
1332	}
1333
1334	tegra_i2c_unmask_irq(i2c_dev, int_mask);
1335	dev_dbg(i2c_dev->dev, "unmasked IRQ: %02x\n",
1336		i2c_readl(i2c_dev, I2C_INT_MASK));
1337
1338	if (i2c_dev->dma_mode) {
1339		time_left = tegra_i2c_wait_completion(i2c_dev,
1340						      &i2c_dev->dma_complete,
1341						      xfer_time);
1342
1343		/*
1344		 * Synchronize DMA first, since dmaengine_terminate_sync()
1345		 * performs synchronization after the transfer's termination
1346		 * and we want to get a completion if transfer succeeded.
1347		 */
1348		dmaengine_synchronize(i2c_dev->dma_chan);
1349		dmaengine_terminate_sync(i2c_dev->dma_chan);
1350
1351		if (!time_left && !completion_done(&i2c_dev->dma_complete)) {
1352			tegra_i2c_init(i2c_dev);
1353			return -ETIMEDOUT;
1354		}
1355
1356		if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE)
1357			memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, i2c_dev->msg_len);
1358	}
1359
1360	time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete,
1361					      xfer_time);
1362
1363	tegra_i2c_mask_irq(i2c_dev, int_mask);
1364
1365	if (time_left == 0) {
1366		tegra_i2c_init(i2c_dev);
1367		return -ETIMEDOUT;
1368	}
1369
1370	dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
1371		time_left, completion_done(&i2c_dev->msg_complete),
1372		i2c_dev->msg_err);
1373
1374	i2c_dev->dma_mode = false;
1375
1376	err = tegra_i2c_error_recover(i2c_dev, msg);
1377	if (err)
1378		return err;
1379
1380	return 0;
1381}
1382
1383static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
1384			  int num)
1385{
1386	struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1387	int i, ret;
1388
1389	ret = pm_runtime_get_sync(i2c_dev->dev);
1390	if (ret < 0) {
1391		dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret);
1392		pm_runtime_put_noidle(i2c_dev->dev);
1393		return ret;
1394	}
1395
1396	for (i = 0; i < num; i++) {
1397		enum msg_end_type end_type = MSG_END_STOP;
1398
1399		if (i < (num - 1)) {
1400			/* check whether follow up message is coming */
1401			if (msgs[i + 1].flags & I2C_M_NOSTART)
1402				end_type = MSG_END_CONTINUE;
1403			else
1404				end_type = MSG_END_REPEAT_START;
1405		}
1406		/* If M_RECV_LEN use ContinueXfer to read the first byte */
1407		if (msgs[i].flags & I2C_M_RECV_LEN) {
1408			ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], MSG_END_CONTINUE);
1409			if (ret)
1410				break;
1411
1412			/* Validate message length before proceeding */
1413			if (msgs[i].buf[0] == 0 || msgs[i].buf[0] > I2C_SMBUS_BLOCK_MAX)
1414				break;
1415
1416			/* Set the msg length from first byte */
1417			msgs[i].len += msgs[i].buf[0];
1418			dev_dbg(i2c_dev->dev, "reading %d bytes\n", msgs[i].len);
1419		}
1420		ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
1421		if (ret)
1422			break;
1423	}
1424
1425	pm_runtime_put(i2c_dev->dev);
1426
1427	return ret ?: i;
1428}
1429
1430static int tegra_i2c_xfer_atomic(struct i2c_adapter *adap,
1431				 struct i2c_msg msgs[], int num)
1432{
1433	struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1434	int ret;
1435
1436	i2c_dev->atomic_mode = true;
1437	ret = tegra_i2c_xfer(adap, msgs, num);
1438	i2c_dev->atomic_mode = false;
1439
1440	return ret;
1441}
1442
1443static u32 tegra_i2c_func(struct i2c_adapter *adap)
1444{
1445	struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1446	u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
1447		  I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
1448
1449	if (i2c_dev->hw->has_continue_xfer_support)
1450		ret |= I2C_FUNC_NOSTART | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
1451
1452	return ret;
1453}
1454
1455static const struct i2c_algorithm tegra_i2c_algo = {
1456	.xfer = tegra_i2c_xfer,
1457	.xfer_atomic = tegra_i2c_xfer_atomic,
1458	.functionality = tegra_i2c_func,
1459};
1460
1461/* payload size is only 12 bit */
1462static const struct i2c_adapter_quirks tegra_i2c_quirks = {
1463	.flags = I2C_AQ_NO_ZERO_LEN,
1464	.max_read_len = SZ_4K,
1465	.max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE,
1466};
1467
1468static const struct i2c_adapter_quirks tegra194_i2c_quirks = {
1469	.flags = I2C_AQ_NO_ZERO_LEN,
1470	.max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE,
1471};
1472
1473static struct i2c_bus_recovery_info tegra_i2c_recovery_info = {
1474	.recover_bus = tegra_i2c_issue_bus_clear,
1475};
1476
1477static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
1478	.has_continue_xfer_support = false,
1479	.has_per_pkt_xfer_complete_irq = false,
1480	.clk_divisor_hs_mode = 3,
1481	.clk_divisor_std_mode = 0,
1482	.clk_divisor_fast_mode = 0,
1483	.clk_divisor_fast_plus_mode = 0,
1484	.has_config_load_reg = false,
1485	.has_multi_master_mode = false,
1486	.has_slcg_override_reg = false,
1487	.has_mst_fifo = false,
1488	.has_mst_reset = false,
1489	.quirks = &tegra_i2c_quirks,
1490	.supports_bus_clear = false,
1491	.has_apb_dma = true,
1492	.tlow_std_mode = 0x4,
1493	.thigh_std_mode = 0x2,
1494	.tlow_fast_fastplus_mode = 0x4,
1495	.thigh_fast_fastplus_mode = 0x2,
1496	.setup_hold_time_std_mode = 0x0,
1497	.setup_hold_time_fast_fast_plus_mode = 0x0,
1498	.setup_hold_time_hs_mode = 0x0,
1499	.has_interface_timing_reg = false,
1500};
1501
1502static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
1503	.has_continue_xfer_support = true,
1504	.has_per_pkt_xfer_complete_irq = false,
1505	.clk_divisor_hs_mode = 3,
1506	.clk_divisor_std_mode = 0,
1507	.clk_divisor_fast_mode = 0,
1508	.clk_divisor_fast_plus_mode = 0,
1509	.has_config_load_reg = false,
1510	.has_multi_master_mode = false,
1511	.has_slcg_override_reg = false,
1512	.has_mst_fifo = false,
1513	.has_mst_reset = false,
1514	.quirks = &tegra_i2c_quirks,
1515	.supports_bus_clear = false,
1516	.has_apb_dma = true,
1517	.tlow_std_mode = 0x4,
1518	.thigh_std_mode = 0x2,
1519	.tlow_fast_fastplus_mode = 0x4,
1520	.thigh_fast_fastplus_mode = 0x2,
1521	.setup_hold_time_std_mode = 0x0,
1522	.setup_hold_time_fast_fast_plus_mode = 0x0,
1523	.setup_hold_time_hs_mode = 0x0,
1524	.has_interface_timing_reg = false,
1525};
1526
1527static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
1528	.has_continue_xfer_support = true,
1529	.has_per_pkt_xfer_complete_irq = true,
1530	.clk_divisor_hs_mode = 1,
1531	.clk_divisor_std_mode = 0x19,
1532	.clk_divisor_fast_mode = 0x19,
1533	.clk_divisor_fast_plus_mode = 0x10,
1534	.has_config_load_reg = false,
1535	.has_multi_master_mode = false,
1536	.has_slcg_override_reg = false,
1537	.has_mst_fifo = false,
1538	.has_mst_reset = false,
1539	.quirks = &tegra_i2c_quirks,
1540	.supports_bus_clear = true,
1541	.has_apb_dma = true,
1542	.tlow_std_mode = 0x4,
1543	.thigh_std_mode = 0x2,
1544	.tlow_fast_fastplus_mode = 0x4,
1545	.thigh_fast_fastplus_mode = 0x2,
1546	.setup_hold_time_std_mode = 0x0,
1547	.setup_hold_time_fast_fast_plus_mode = 0x0,
1548	.setup_hold_time_hs_mode = 0x0,
1549	.has_interface_timing_reg = false,
1550};
1551
1552static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
1553	.has_continue_xfer_support = true,
1554	.has_per_pkt_xfer_complete_irq = true,
1555	.clk_divisor_hs_mode = 1,
1556	.clk_divisor_std_mode = 0x19,
1557	.clk_divisor_fast_mode = 0x19,
1558	.clk_divisor_fast_plus_mode = 0x10,
1559	.has_config_load_reg = true,
1560	.has_multi_master_mode = false,
1561	.has_slcg_override_reg = true,
1562	.has_mst_fifo = false,
1563	.has_mst_reset = false,
1564	.quirks = &tegra_i2c_quirks,
1565	.supports_bus_clear = true,
1566	.has_apb_dma = true,
1567	.tlow_std_mode = 0x4,
1568	.thigh_std_mode = 0x2,
1569	.tlow_fast_fastplus_mode = 0x4,
1570	.thigh_fast_fastplus_mode = 0x2,
1571	.setup_hold_time_std_mode = 0x0,
1572	.setup_hold_time_fast_fast_plus_mode = 0x0,
1573	.setup_hold_time_hs_mode = 0x0,
1574	.has_interface_timing_reg = true,
1575};
1576
1577static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
1578	.has_continue_xfer_support = true,
1579	.has_per_pkt_xfer_complete_irq = true,
1580	.clk_divisor_hs_mode = 1,
1581	.clk_divisor_std_mode = 0x19,
1582	.clk_divisor_fast_mode = 0x19,
1583	.clk_divisor_fast_plus_mode = 0x10,
1584	.has_config_load_reg = true,
1585	.has_multi_master_mode = false,
1586	.has_slcg_override_reg = true,
1587	.has_mst_fifo = false,
1588	.has_mst_reset = false,
1589	.quirks = &tegra_i2c_quirks,
1590	.supports_bus_clear = true,
1591	.has_apb_dma = true,
1592	.tlow_std_mode = 0x4,
1593	.thigh_std_mode = 0x2,
1594	.tlow_fast_fastplus_mode = 0x4,
1595	.thigh_fast_fastplus_mode = 0x2,
1596	.setup_hold_time_std_mode = 0,
1597	.setup_hold_time_fast_fast_plus_mode = 0,
1598	.setup_hold_time_hs_mode = 0,
1599	.has_interface_timing_reg = true,
1600};
1601
1602static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {
1603	.has_continue_xfer_support = true,
1604	.has_per_pkt_xfer_complete_irq = true,
1605	.clk_divisor_hs_mode = 1,
1606	.clk_divisor_std_mode = 0x16,
1607	.clk_divisor_fast_mode = 0x19,
1608	.clk_divisor_fast_plus_mode = 0x10,
1609	.has_config_load_reg = true,
1610	.has_multi_master_mode = false,
1611	.has_slcg_override_reg = true,
1612	.has_mst_fifo = false,
1613	.has_mst_reset = false,
1614	.quirks = &tegra_i2c_quirks,
1615	.supports_bus_clear = true,
1616	.has_apb_dma = false,
1617	.tlow_std_mode = 0x4,
1618	.thigh_std_mode = 0x3,
1619	.tlow_fast_fastplus_mode = 0x4,
1620	.thigh_fast_fastplus_mode = 0x2,
1621	.setup_hold_time_std_mode = 0,
1622	.setup_hold_time_fast_fast_plus_mode = 0,
1623	.setup_hold_time_hs_mode = 0,
1624	.has_interface_timing_reg = true,
1625};
1626
1627static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
1628	.has_continue_xfer_support = true,
1629	.has_per_pkt_xfer_complete_irq = true,
1630	.clk_divisor_hs_mode = 1,
1631	.clk_divisor_std_mode = 0x4f,
1632	.clk_divisor_fast_mode = 0x3c,
1633	.clk_divisor_fast_plus_mode = 0x16,
1634	.has_config_load_reg = true,
1635	.has_multi_master_mode = true,
1636	.has_slcg_override_reg = true,
1637	.has_mst_fifo = true,
1638	.has_mst_reset = true,
1639	.quirks = &tegra194_i2c_quirks,
1640	.supports_bus_clear = true,
1641	.has_apb_dma = false,
1642	.tlow_std_mode = 0x8,
1643	.thigh_std_mode = 0x7,
1644	.tlow_fast_fastplus_mode = 0x2,
1645	.thigh_fast_fastplus_mode = 0x2,
1646	.setup_hold_time_std_mode = 0x08080808,
1647	.setup_hold_time_fast_fast_plus_mode = 0x02020202,
1648	.setup_hold_time_hs_mode = 0x090909,
1649	.has_interface_timing_reg = true,
1650};
1651
1652static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
1653	.has_continue_xfer_support = true,
1654	.has_per_pkt_xfer_complete_irq = true,
1655	.clk_divisor_hs_mode = 7,
1656	.clk_divisor_std_mode = 0x7a,
1657	.clk_divisor_fast_mode = 0x40,
1658	.clk_divisor_fast_plus_mode = 0x19,
1659	.has_config_load_reg = true,
1660	.has_multi_master_mode = true,
1661	.has_slcg_override_reg = true,
1662	.has_mst_fifo = true,
1663	.has_mst_reset = true,
1664	.quirks = &tegra194_i2c_quirks,
1665	.supports_bus_clear = true,
1666	.has_apb_dma = false,
1667	.tlow_std_mode = 0x8,
1668	.thigh_std_mode = 0x7,
1669	.tlow_fast_fastplus_mode = 0x3,
1670	.thigh_fast_fastplus_mode = 0x3,
1671	.setup_hold_time_std_mode = 0x08080808,
1672	.setup_hold_time_fast_fast_plus_mode = 0x02020202,
1673	.setup_hold_time_hs_mode = 0x090909,
1674	.has_interface_timing_reg = true,
1675};
1676
1677static const struct of_device_id tegra_i2c_of_match[] = {
1678	{ .compatible = "nvidia,tegra256-i2c", .data = &tegra256_i2c_hw, },
1679	{ .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
1680	{ .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },
1681#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
1682	{ .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_i2c_hw, },
1683#endif
1684	{ .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
1685	{ .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
1686	{ .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
1687	{ .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
1688	{ .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
1689#if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)
1690	{ .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
1691#endif
1692	{},
1693};
1694MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
1695
1696static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
1697{
1698	struct device_node *np = i2c_dev->dev->of_node;
1699	bool multi_mode;
1700
1701	i2c_parse_fw_timings(i2c_dev->dev, &i2c_dev->timings, true);
1702
1703	multi_mode = device_property_read_bool(i2c_dev->dev, "multi-master");
1704	i2c_dev->multimaster_mode = multi_mode;
1705
1706	if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
1707	    of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc"))
1708		i2c_dev->is_dvc = true;
1709
1710	if (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) &&
1711	    of_device_is_compatible(np, "nvidia,tegra210-i2c-vi"))
1712		i2c_dev->is_vi = true;
1713}
1714
1715static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev)
1716{
1717	int err;
1718
1719	if (ACPI_HANDLE(i2c_dev->dev))
1720		return 0;
1721
1722	i2c_dev->clocks[i2c_dev->nclocks++].id = "div-clk";
1723
1724	if (i2c_dev->hw == &tegra20_i2c_hw || i2c_dev->hw == &tegra30_i2c_hw)
1725		i2c_dev->clocks[i2c_dev->nclocks++].id = "fast-clk";
1726
1727	if (IS_VI(i2c_dev))
1728		i2c_dev->clocks[i2c_dev->nclocks++].id = "slow";
1729
1730	err = devm_clk_bulk_get(i2c_dev->dev, i2c_dev->nclocks,
1731				i2c_dev->clocks);
1732	if (err)
1733		return err;
1734
1735	err = clk_bulk_prepare(i2c_dev->nclocks, i2c_dev->clocks);
1736	if (err)
1737		return err;
1738
1739	i2c_dev->div_clk = i2c_dev->clocks[0].clk;
1740
1741	if (!i2c_dev->multimaster_mode)
1742		return 0;
1743
1744	err = clk_enable(i2c_dev->div_clk);
1745	if (err) {
1746		dev_err(i2c_dev->dev, "failed to enable div-clk: %d\n", err);
1747		goto unprepare_clocks;
1748	}
1749
1750	return 0;
1751
1752unprepare_clocks:
1753	clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks);
1754
1755	return err;
1756}
1757
1758static void tegra_i2c_release_clocks(struct tegra_i2c_dev *i2c_dev)
1759{
1760	if (i2c_dev->multimaster_mode)
1761		clk_disable(i2c_dev->div_clk);
1762
1763	clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks);
1764}
1765
1766static int tegra_i2c_init_hardware(struct tegra_i2c_dev *i2c_dev)
1767{
1768	int ret;
1769
1770	ret = pm_runtime_get_sync(i2c_dev->dev);
1771	if (ret < 0)
1772		dev_err(i2c_dev->dev, "runtime resume failed: %d\n", ret);
1773	else
1774		ret = tegra_i2c_init(i2c_dev);
1775
1776	pm_runtime_put_sync(i2c_dev->dev);
1777
1778	return ret;
1779}
1780
1781static int tegra_i2c_probe(struct platform_device *pdev)
1782{
1783	struct tegra_i2c_dev *i2c_dev;
1784	struct resource *res;
1785	int err;
1786
1787	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
1788	if (!i2c_dev)
1789		return -ENOMEM;
1790
1791	platform_set_drvdata(pdev, i2c_dev);
1792
1793	init_completion(&i2c_dev->msg_complete);
1794	init_completion(&i2c_dev->dma_complete);
1795
1796	i2c_dev->hw = device_get_match_data(&pdev->dev);
1797	i2c_dev->cont_id = pdev->id;
1798	i2c_dev->dev = &pdev->dev;
1799
1800	i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1801	if (IS_ERR(i2c_dev->base))
1802		return PTR_ERR(i2c_dev->base);
1803
1804	i2c_dev->base_phys = res->start;
1805
1806	err = platform_get_irq(pdev, 0);
1807	if (err < 0)
1808		return err;
1809
1810	i2c_dev->irq = err;
1811
1812	/* interrupt will be enabled during of transfer time */
1813	irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN);
1814
1815	err = devm_request_threaded_irq(i2c_dev->dev, i2c_dev->irq,
1816					NULL, tegra_i2c_isr,
1817					IRQF_NO_SUSPEND | IRQF_ONESHOT,
1818					dev_name(i2c_dev->dev), i2c_dev);
1819	if (err)
1820		return err;
1821
1822	tegra_i2c_parse_dt(i2c_dev);
1823
1824	err = tegra_i2c_init_clocks(i2c_dev);
1825	if (err)
1826		return err;
1827
1828	err = tegra_i2c_init_dma(i2c_dev);
1829	if (err)
1830		goto release_clocks;
1831
1832	/*
1833	 * VI I2C is in VE power domain which is not always ON and not
1834	 * IRQ-safe.  Thus, IRQ-safe device shouldn't be attached to a
1835	 * non IRQ-safe domain because this prevents powering off the power
1836	 * domain.
1837	 *
1838	 * VI I2C device shouldn't be marked as IRQ-safe because VI I2C won't
1839	 * be used for atomic transfers. ACPI device is not IRQ safe also.
1840	 *
1841	 * Devices with pinctrl states cannot be marked IRQ-safe as the pinctrl
1842	 * state transitions during runtime PM require mutexes.
1843	 */
1844	if (!IS_VI(i2c_dev) && !has_acpi_companion(i2c_dev->dev) && !i2c_dev->dev->pins)
1845		pm_runtime_irq_safe(i2c_dev->dev);
1846
1847	pm_runtime_enable(i2c_dev->dev);
1848
1849	err = tegra_i2c_init_hardware(i2c_dev);
1850	if (err)
1851		goto release_rpm;
1852
1853	i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
1854	i2c_dev->adapter.dev.of_node = i2c_dev->dev->of_node;
1855	i2c_dev->adapter.dev.parent = i2c_dev->dev;
1856	i2c_dev->adapter.retries = 1;
1857	i2c_dev->adapter.timeout = 6 * HZ;
1858	i2c_dev->adapter.quirks = i2c_dev->hw->quirks;
1859	i2c_dev->adapter.owner = THIS_MODULE;
1860	i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
1861	i2c_dev->adapter.algo = &tegra_i2c_algo;
1862	i2c_dev->adapter.nr = pdev->id;
1863	ACPI_COMPANION_SET(&i2c_dev->adapter.dev, ACPI_COMPANION(&pdev->dev));
1864
1865	if (i2c_dev->hw->supports_bus_clear)
1866		i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info;
1867
1868	strscpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev),
1869		sizeof(i2c_dev->adapter.name));
1870
1871	err = i2c_add_numbered_adapter(&i2c_dev->adapter);
1872	if (err)
1873		goto release_rpm;
1874
1875	return 0;
1876
1877release_rpm:
1878	pm_runtime_disable(i2c_dev->dev);
1879
1880	tegra_i2c_release_dma(i2c_dev);
1881release_clocks:
1882	tegra_i2c_release_clocks(i2c_dev);
1883
1884	return err;
1885}
1886
1887static void tegra_i2c_remove(struct platform_device *pdev)
1888{
1889	struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1890
1891	i2c_del_adapter(&i2c_dev->adapter);
1892	pm_runtime_force_suspend(i2c_dev->dev);
1893
1894	tegra_i2c_release_dma(i2c_dev);
1895	tegra_i2c_release_clocks(i2c_dev);
1896}
1897
1898static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev)
1899{
1900	struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1901	int err;
1902
1903	err = pinctrl_pm_select_default_state(dev);
1904	if (err)
1905		return err;
1906
1907	err = clk_bulk_enable(i2c_dev->nclocks, i2c_dev->clocks);
1908	if (err)
1909		return err;
1910
1911	/*
1912	 * VI I2C device is attached to VE power domain which goes through
1913	 * power ON/OFF during runtime PM resume/suspend, meaning that
1914	 * controller needs to be re-initialized after power ON.
1915	 */
1916	if (IS_VI(i2c_dev)) {
1917		err = tegra_i2c_init(i2c_dev);
1918		if (err)
1919			goto disable_clocks;
1920	}
1921
1922	return 0;
1923
1924disable_clocks:
1925	clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks);
1926
1927	return err;
1928}
1929
1930static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev)
1931{
1932	struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1933
1934	clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks);
1935
1936	return pinctrl_pm_select_idle_state(dev);
1937}
1938
1939static int __maybe_unused tegra_i2c_suspend(struct device *dev)
1940{
1941	struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1942	int err;
1943
1944	i2c_mark_adapter_suspended(&i2c_dev->adapter);
1945
1946	if (!pm_runtime_status_suspended(dev)) {
1947		err = tegra_i2c_runtime_suspend(dev);
1948		if (err)
1949			return err;
1950	}
1951
1952	return 0;
1953}
1954
1955static int __maybe_unused tegra_i2c_resume(struct device *dev)
1956{
1957	struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1958	int err;
1959
1960	/*
1961	 * We need to ensure that clocks are enabled so that registers can be
1962	 * restored in tegra_i2c_init().
1963	 */
1964	err = tegra_i2c_runtime_resume(dev);
1965	if (err)
1966		return err;
1967
1968	err = tegra_i2c_init(i2c_dev);
1969	if (err)
1970		return err;
1971
1972	/*
1973	 * In case we are runtime suspended, disable clocks again so that we
1974	 * don't unbalance the clock reference counts during the next runtime
1975	 * resume transition.
1976	 */
1977	if (pm_runtime_status_suspended(dev)) {
1978		err = tegra_i2c_runtime_suspend(dev);
1979		if (err)
1980			return err;
1981	}
1982
1983	i2c_mark_adapter_resumed(&i2c_dev->adapter);
1984
1985	return 0;
1986}
1987
1988static const struct dev_pm_ops tegra_i2c_pm = {
1989	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume)
1990	SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume,
1991			   NULL)
1992};
1993
1994static const struct acpi_device_id tegra_i2c_acpi_match[] = {
1995	{.id = "NVDA0101", .driver_data = (kernel_ulong_t)&tegra210_i2c_hw},
1996	{.id = "NVDA0201", .driver_data = (kernel_ulong_t)&tegra186_i2c_hw},
1997	{.id = "NVDA0301", .driver_data = (kernel_ulong_t)&tegra194_i2c_hw},
1998	{ }
1999};
2000MODULE_DEVICE_TABLE(acpi, tegra_i2c_acpi_match);
2001
2002static struct platform_driver tegra_i2c_driver = {
2003	.probe = tegra_i2c_probe,
2004	.remove = tegra_i2c_remove,
2005	.driver = {
2006		.name = "tegra-i2c",
2007		.of_match_table = tegra_i2c_of_match,
2008		.acpi_match_table = tegra_i2c_acpi_match,
2009		.pm = &tegra_i2c_pm,
2010	},
2011};
2012module_platform_driver(tegra_i2c_driver);
2013
2014MODULE_DESCRIPTION("NVIDIA Tegra I2C Bus Controller driver");
2015MODULE_AUTHOR("Colin Cross");
2016MODULE_LICENSE("GPL v2");