i2c-stm32f7.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Driver for STMicroelectronics STM32F7 I2C controller
   4 *
   5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
   6 * reference manual.
   7 * Please see below a link to the documentation:
   8 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
   9 *
  10 * Copyright (C) M'boumba Cedric Madianga 2017
  11 * Copyright (C) STMicroelectronics 2017
  12 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
  13 *
  14 * This driver is based on i2c-stm32f4.c
  15 *
  16 */
  17#include <linux/clk.h>
  18#include <linux/delay.h>
  19#include <linux/err.h>
  20#include <linux/i2c.h>
  21#include <linux/i2c-smbus.h>
  22#include <linux/interrupt.h>
  23#include <linux/io.h>
  24#include <linux/iopoll.h>
  25#include <linux/mfd/syscon.h>
  26#include <linux/module.h>
  27#include <linux/of.h>
  28#include <linux/of_address.h>
  29#include <linux/of_platform.h>
  30#include <linux/platform_device.h>
  31#include <linux/pinctrl/consumer.h>
  32#include <linux/pm_runtime.h>
  33#include <linux/pm_wakeirq.h>
  34#include <linux/regmap.h>
  35#include <linux/reset.h>
  36#include <linux/slab.h>
  37#include <linux/string_choices.h>
  38
  39#include "i2c-stm32.h"
  40
  41/* STM32F7 I2C registers */
  42#define STM32F7_I2C_CR1				0x00
  43#define STM32F7_I2C_CR2				0x04
  44#define STM32F7_I2C_OAR1			0x08
  45#define STM32F7_I2C_OAR2			0x0C
  46#define STM32F7_I2C_PECR			0x20
  47#define STM32F7_I2C_TIMINGR			0x10
  48#define STM32F7_I2C_ISR				0x18
  49#define STM32F7_I2C_ICR				0x1C
  50#define STM32F7_I2C_RXDR			0x24
  51#define STM32F7_I2C_TXDR			0x28
  52
  53/* STM32F7 I2C control 1 */
  54#define STM32_I2C_CR1_FMP			BIT(24)
  55#define STM32F7_I2C_CR1_PECEN			BIT(23)
  56#define STM32F7_I2C_CR1_ALERTEN			BIT(22)
  57#define STM32F7_I2C_CR1_SMBHEN			BIT(20)
  58#define STM32F7_I2C_CR1_WUPEN			BIT(18)
  59#define STM32F7_I2C_CR1_SBC			BIT(16)
  60#define STM32F7_I2C_CR1_RXDMAEN			BIT(15)
  61#define STM32F7_I2C_CR1_TXDMAEN			BIT(14)
  62#define STM32F7_I2C_CR1_ANFOFF			BIT(12)
  63#define STM32F7_I2C_CR1_DNF_MASK		GENMASK(11, 8)
  64#define STM32F7_I2C_CR1_DNF(n)			(((n) & 0xf) << 8)
  65#define STM32F7_I2C_CR1_ERRIE			BIT(7)
  66#define STM32F7_I2C_CR1_TCIE			BIT(6)
  67#define STM32F7_I2C_CR1_STOPIE			BIT(5)
  68#define STM32F7_I2C_CR1_NACKIE			BIT(4)
  69#define STM32F7_I2C_CR1_ADDRIE			BIT(3)
  70#define STM32F7_I2C_CR1_RXIE			BIT(2)
  71#define STM32F7_I2C_CR1_TXIE			BIT(1)
  72#define STM32F7_I2C_CR1_PE			BIT(0)
  73#define STM32F7_I2C_ALL_IRQ_MASK		(STM32F7_I2C_CR1_ERRIE \
  74						| STM32F7_I2C_CR1_TCIE \
  75						| STM32F7_I2C_CR1_STOPIE \
  76						| STM32F7_I2C_CR1_NACKIE \
  77						| STM32F7_I2C_CR1_RXIE \
  78						| STM32F7_I2C_CR1_TXIE)
  79#define STM32F7_I2C_XFER_IRQ_MASK		(STM32F7_I2C_CR1_TCIE \
  80						| STM32F7_I2C_CR1_STOPIE \
  81						| STM32F7_I2C_CR1_NACKIE \
  82						| STM32F7_I2C_CR1_RXIE \
  83						| STM32F7_I2C_CR1_TXIE)
  84
  85/* STM32F7 I2C control 2 */
  86#define STM32F7_I2C_CR2_PECBYTE			BIT(26)
  87#define STM32F7_I2C_CR2_RELOAD			BIT(24)
  88#define STM32F7_I2C_CR2_NBYTES_MASK		GENMASK(23, 16)
  89#define STM32F7_I2C_CR2_NBYTES(n)		(((n) & 0xff) << 16)
  90#define STM32F7_I2C_CR2_NACK			BIT(15)
  91#define STM32F7_I2C_CR2_STOP			BIT(14)
  92#define STM32F7_I2C_CR2_START			BIT(13)
  93#define STM32F7_I2C_CR2_HEAD10R			BIT(12)
  94#define STM32F7_I2C_CR2_ADD10			BIT(11)
  95#define STM32F7_I2C_CR2_RD_WRN			BIT(10)
  96#define STM32F7_I2C_CR2_SADD10_MASK		GENMASK(9, 0)
  97#define STM32F7_I2C_CR2_SADD10(n)		(((n) & \
  98						STM32F7_I2C_CR2_SADD10_MASK))
  99#define STM32F7_I2C_CR2_SADD7_MASK		GENMASK(7, 1)
 100#define STM32F7_I2C_CR2_SADD7(n)		(((n) & 0x7f) << 1)
 101
 102/* STM32F7 I2C Own Address 1 */
 103#define STM32F7_I2C_OAR1_OA1EN			BIT(15)
 104#define STM32F7_I2C_OAR1_OA1MODE		BIT(10)
 105#define STM32F7_I2C_OAR1_OA1_10_MASK		GENMASK(9, 0)
 106#define STM32F7_I2C_OAR1_OA1_10(n)		(((n) & \
 107						STM32F7_I2C_OAR1_OA1_10_MASK))
 108#define STM32F7_I2C_OAR1_OA1_7_MASK		GENMASK(7, 1)
 109#define STM32F7_I2C_OAR1_OA1_7(n)		(((n) & 0x7f) << 1)
 110#define STM32F7_I2C_OAR1_MASK			(STM32F7_I2C_OAR1_OA1_7_MASK \
 111						| STM32F7_I2C_OAR1_OA1_10_MASK \
 112						| STM32F7_I2C_OAR1_OA1EN \
 113						| STM32F7_I2C_OAR1_OA1MODE)
 114
 115/* STM32F7 I2C Own Address 2 */
 116#define STM32F7_I2C_OAR2_OA2EN			BIT(15)
 117#define STM32F7_I2C_OAR2_OA2MSK_MASK		GENMASK(10, 8)
 118#define STM32F7_I2C_OAR2_OA2MSK(n)		(((n) & 0x7) << 8)
 119#define STM32F7_I2C_OAR2_OA2_7_MASK		GENMASK(7, 1)
 120#define STM32F7_I2C_OAR2_OA2_7(n)		(((n) & 0x7f) << 1)
 121#define STM32F7_I2C_OAR2_MASK			(STM32F7_I2C_OAR2_OA2MSK_MASK \
 122						| STM32F7_I2C_OAR2_OA2_7_MASK \
 123						| STM32F7_I2C_OAR2_OA2EN)
 124
 125/* STM32F7 I2C Interrupt Status */
 126#define STM32F7_I2C_ISR_ADDCODE_MASK		GENMASK(23, 17)
 127#define STM32F7_I2C_ISR_ADDCODE_GET(n) \
 128				(((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
 129#define STM32F7_I2C_ISR_DIR			BIT(16)
 130#define STM32F7_I2C_ISR_BUSY			BIT(15)
 131#define STM32F7_I2C_ISR_ALERT			BIT(13)
 132#define STM32F7_I2C_ISR_PECERR			BIT(11)
 133#define STM32F7_I2C_ISR_ARLO			BIT(9)
 134#define STM32F7_I2C_ISR_BERR			BIT(8)
 135#define STM32F7_I2C_ISR_TCR			BIT(7)
 136#define STM32F7_I2C_ISR_TC			BIT(6)
 137#define STM32F7_I2C_ISR_STOPF			BIT(5)
 138#define STM32F7_I2C_ISR_NACKF			BIT(4)
 139#define STM32F7_I2C_ISR_ADDR			BIT(3)
 140#define STM32F7_I2C_ISR_RXNE			BIT(2)
 141#define STM32F7_I2C_ISR_TXIS			BIT(1)
 142#define STM32F7_I2C_ISR_TXE			BIT(0)
 143
 144/* STM32F7 I2C Interrupt Clear */
 145#define STM32F7_I2C_ICR_ALERTCF			BIT(13)
 146#define STM32F7_I2C_ICR_PECCF			BIT(11)
 147#define STM32F7_I2C_ICR_ARLOCF			BIT(9)
 148#define STM32F7_I2C_ICR_BERRCF			BIT(8)
 149#define STM32F7_I2C_ICR_STOPCF			BIT(5)
 150#define STM32F7_I2C_ICR_NACKCF			BIT(4)
 151#define STM32F7_I2C_ICR_ADDRCF			BIT(3)
 152
 153/* STM32F7 I2C Timing */
 154#define STM32F7_I2C_TIMINGR_PRESC(n)		(((n) & 0xf) << 28)
 155#define STM32F7_I2C_TIMINGR_SCLDEL(n)		(((n) & 0xf) << 20)
 156#define STM32F7_I2C_TIMINGR_SDADEL(n)		(((n) & 0xf) << 16)
 157#define STM32F7_I2C_TIMINGR_SCLH(n)		(((n) & 0xff) << 8)
 158#define STM32F7_I2C_TIMINGR_SCLL(n)		((n) & 0xff)
 159
 160#define STM32F7_I2C_MAX_LEN			0xff
 161#define STM32F7_I2C_DMA_LEN_MIN			0x16
 162enum {
 163	STM32F7_SLAVE_HOSTNOTIFY,
 164	STM32F7_SLAVE_7_10_BITS_ADDR,
 165	STM32F7_SLAVE_7_BITS_ADDR,
 166	STM32F7_I2C_MAX_SLAVE
 167};
 168
 169#define STM32F7_I2C_DNF_DEFAULT			0
 170#define STM32F7_I2C_DNF_MAX			15
 171
 172#define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN	50	/* ns */
 173#define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX	260	/* ns */
 174
 175#define STM32F7_I2C_RISE_TIME_DEFAULT		25	/* ns */
 176#define STM32F7_I2C_FALL_TIME_DEFAULT		10	/* ns */
 177
 178#define STM32F7_PRESC_MAX			BIT(4)
 179#define STM32F7_SCLDEL_MAX			BIT(4)
 180#define STM32F7_SDADEL_MAX			BIT(4)
 181#define STM32F7_SCLH_MAX			BIT(8)
 182#define STM32F7_SCLL_MAX			BIT(8)
 183
 184#define STM32F7_AUTOSUSPEND_DELAY		(HZ / 100)
 185
 186/**
 187 * struct stm32f7_i2c_regs - i2c f7 registers backup
 188 * @cr1: Control register 1
 189 * @cr2: Control register 2
 190 * @oar1: Own address 1 register
 191 * @oar2: Own address 2 register
 192 * @tmgr: Timing register
 193 */
 194struct stm32f7_i2c_regs {
 195	u32 cr1;
 196	u32 cr2;
 197	u32 oar1;
 198	u32 oar2;
 199	u32 tmgr;
 200};
 201
 202/**
 203 * struct stm32f7_i2c_spec - private i2c specification timing
 204 * @rate: I2C bus speed (Hz)
 205 * @fall_max: Max fall time of both SDA and SCL signals (ns)
 206 * @rise_max: Max rise time of both SDA and SCL signals (ns)
 207 * @hddat_min: Min data hold time (ns)
 208 * @vddat_max: Max data valid time (ns)
 209 * @sudat_min: Min data setup time (ns)
 210 * @l_min: Min low period of the SCL clock (ns)
 211 * @h_min: Min high period of the SCL clock (ns)
 212 */
 213struct stm32f7_i2c_spec {
 214	u32 rate;
 215	u32 fall_max;
 216	u32 rise_max;
 217	u32 hddat_min;
 218	u32 vddat_max;
 219	u32 sudat_min;
 220	u32 l_min;
 221	u32 h_min;
 222};
 223
 224/**
 225 * struct stm32f7_i2c_setup - private I2C timing setup parameters
 226 * @speed_freq: I2C speed frequency  (Hz)
 227 * @clock_src: I2C clock source frequency (Hz)
 228 * @rise_time: Rise time (ns)
 229 * @fall_time: Fall time (ns)
 230 * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
 231 * @single_it_line: Only a single IT line is used for both events/errors
 232 * @fmp_cr1_bit: Fast Mode Plus control is done via a bit in CR1
 233 */
 234struct stm32f7_i2c_setup {
 235	u32 speed_freq;
 236	u32 clock_src;
 237	u32 rise_time;
 238	u32 fall_time;
 239	u32 fmp_clr_offset;
 240	bool single_it_line;
 241	bool fmp_cr1_bit;
 242};
 243
 244/**
 245 * struct stm32f7_i2c_timings - private I2C output parameters
 246 * @node: List entry
 247 * @presc: Prescaler value
 248 * @scldel: Data setup time
 249 * @sdadel: Data hold time
 250 * @sclh: SCL high period (master mode)
 251 * @scll: SCL low period (master mode)
 252 */
 253struct stm32f7_i2c_timings {
 254	struct list_head node;
 255	u8 presc;
 256	u8 scldel;
 257	u8 sdadel;
 258	u8 sclh;
 259	u8 scll;
 260};
 261
 262/**
 263 * struct stm32f7_i2c_msg - client specific data
 264 * @addr: 8-bit or 10-bit slave addr, including r/w bit
 265 * @count: number of bytes to be transferred
 266 * @buf: data buffer
 267 * @result: result of the transfer
 268 * @stop: last I2C msg to be sent, i.e. STOP to be generated
 269 * @smbus: boolean to know if the I2C IP is used in SMBus mode
 270 * @size: type of SMBus protocol
 271 * @read_write: direction of SMBus protocol
 272 * SMBus block read and SMBus block write - block read process call protocols
 273 * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
 274 * contain a maximum of 32 bytes of data + byte command + byte count + PEC
 275 * This buffer has to be 32-bit aligned to be compliant with memory address
 276 * register in DMA mode.
 277 */
 278struct stm32f7_i2c_msg {
 279	u16 addr;
 280	u32 count;
 281	u8 *buf;
 282	int result;
 283	bool stop;
 284	bool smbus;
 285	int size;
 286	char read_write;
 287	u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
 288};
 289
 290/**
 291 * struct stm32f7_i2c_alert - SMBus alert specific data
 292 * @setup: platform data for the smbus_alert i2c client
 293 * @ara: I2C slave device used to respond to the SMBus Alert with Alert
 294 * Response Address
 295 */
 296struct stm32f7_i2c_alert {
 297	struct i2c_smbus_alert_setup setup;
 298	struct i2c_client *ara;
 299};
 300
 301/**
 302 * struct stm32f7_i2c_dev - private data of the controller
 303 * @adap: I2C adapter for this controller
 304 * @dev: device for this controller
 305 * @base: virtual memory area
 306 * @complete: completion of I2C message
 307 * @clk: hw i2c clock
 308 * @bus_rate: I2C clock frequency of the controller
 309 * @msg: Pointer to data to be written
 310 * @msg_num: number of I2C messages to be executed
 311 * @msg_id: message identifiant
 312 * @f7_msg: customized i2c msg for driver usage
 313 * @setup: I2C timing input setup
 314 * @timing: I2C computed timings
 315 * @slave: list of slave devices registered on the I2C bus
 316 * @slave_running: slave device currently used
 317 * @backup_regs: backup of i2c controller registers (for suspend/resume)
 318 * @slave_dir: transfer direction for the current slave device
 319 * @master_mode: boolean to know in which mode the I2C is running (master or
 320 * slave)
 321 * @dma: dma data
 322 * @use_dma: boolean to know if dma is used in the current transfer
 323 * @regmap: holds SYSCFG phandle for Fast Mode Plus bits
 324 * @fmp_sreg: register address for setting Fast Mode Plus bits
 325 * @fmp_creg: register address for clearing Fast Mode Plus bits
 326 * @fmp_mask: mask for Fast Mode Plus bits in set register
 327 * @wakeup_src: boolean to know if the device is a wakeup source
 328 * @smbus_mode: states that the controller is configured in SMBus mode
 329 * @host_notify_client: SMBus host-notify client
 330 * @analog_filter: boolean to indicate enabling of the analog filter
 331 * @dnf_dt: value of digital filter requested via dt
 332 * @dnf: value of digital filter to apply
 333 * @alert: SMBus alert specific data
 334 * @atomic: boolean indicating that current transfer is atomic
 335 */
 336struct stm32f7_i2c_dev {
 337	struct i2c_adapter adap;
 338	struct device *dev;
 339	void __iomem *base;
 340	struct completion complete;
 341	struct clk *clk;
 342	unsigned int bus_rate;
 343	struct i2c_msg *msg;
 344	unsigned int msg_num;
 345	unsigned int msg_id;
 346	struct stm32f7_i2c_msg f7_msg;
 347	struct stm32f7_i2c_setup setup;
 348	struct stm32f7_i2c_timings timing;
 349	struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
 350	struct i2c_client *slave_running;
 351	struct stm32f7_i2c_regs backup_regs;
 352	u32 slave_dir;
 353	bool master_mode;
 354	struct stm32_i2c_dma *dma;
 355	bool use_dma;
 356	struct regmap *regmap;
 357	u32 fmp_sreg;
 358	u32 fmp_creg;
 359	u32 fmp_mask;
 360	bool wakeup_src;
 361	bool smbus_mode;
 362	struct i2c_client *host_notify_client;
 363	bool analog_filter;
 364	u32 dnf_dt;
 365	u32 dnf;
 366	struct stm32f7_i2c_alert *alert;
 367	bool atomic;
 368};
 369
 370/*
 371 * All these values are coming from I2C Specification, Version 6.0, 4th of
 372 * April 2014.
 373 *
 374 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
 375 * and Fast-mode Plus I2C-bus devices
 376 */
 377static struct stm32f7_i2c_spec stm32f7_i2c_specs[] = {
 378	{
 379		.rate = I2C_MAX_STANDARD_MODE_FREQ,
 380		.fall_max = 300,
 381		.rise_max = 1000,
 382		.hddat_min = 0,
 383		.vddat_max = 3450,
 384		.sudat_min = 250,
 385		.l_min = 4700,
 386		.h_min = 4000,
 387	},
 388	{
 389		.rate = I2C_MAX_FAST_MODE_FREQ,
 390		.fall_max = 300,
 391		.rise_max = 300,
 392		.hddat_min = 0,
 393		.vddat_max = 900,
 394		.sudat_min = 100,
 395		.l_min = 1300,
 396		.h_min = 600,
 397	},
 398	{
 399		.rate = I2C_MAX_FAST_MODE_PLUS_FREQ,
 400		.fall_max = 100,
 401		.rise_max = 120,
 402		.hddat_min = 0,
 403		.vddat_max = 450,
 404		.sudat_min = 50,
 405		.l_min = 500,
 406		.h_min = 260,
 407	},
 408};
 409
 410static const struct stm32f7_i2c_setup stm32f7_setup = {
 411	.rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
 412	.fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
 413};
 414
 415static const struct stm32f7_i2c_setup stm32mp15_setup = {
 416	.rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
 417	.fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
 418	.fmp_clr_offset = 0x40,
 419};
 420
 421static const struct stm32f7_i2c_setup stm32mp13_setup = {
 422	.rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
 423	.fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
 424	.fmp_clr_offset = 0x4,
 425};
 426
 427static const struct stm32f7_i2c_setup stm32mp25_setup = {
 428	.rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
 429	.fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
 430	.single_it_line = true,
 431	.fmp_cr1_bit = true,
 432};
 433
 434static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
 435{
 436	writel_relaxed(readl_relaxed(reg) | mask, reg);
 437}
 438
 439static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
 440{
 441	writel_relaxed(readl_relaxed(reg) & ~mask, reg);
 442}
 443
 444static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
 445{
 446	stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
 447}
 448
 449static struct stm32f7_i2c_spec *stm32f7_get_specs(u32 rate)
 450{
 451	int i;
 452
 453	for (i = 0; i < ARRAY_SIZE(stm32f7_i2c_specs); i++)
 454		if (rate <= stm32f7_i2c_specs[i].rate)
 455			return &stm32f7_i2c_specs[i];
 456
 457	return ERR_PTR(-EINVAL);
 458}
 459
 460#define	RATE_MIN(rate)	((rate) * 8 / 10)
 461static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
 462				      struct stm32f7_i2c_setup *setup,
 463				      struct stm32f7_i2c_timings *output)
 464{
 465	struct stm32f7_i2c_spec *specs;
 466	u32 p_prev = STM32F7_PRESC_MAX;
 467	u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
 468				       setup->clock_src);
 469	u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
 470				       setup->speed_freq);
 471	u32 clk_error_prev = i2cbus;
 472	u32 tsync;
 473	u32 af_delay_min, af_delay_max;
 474	u32 dnf_delay;
 475	u32 clk_min, clk_max;
 476	int sdadel_min, sdadel_max;
 477	int scldel_min;
 478	struct stm32f7_i2c_timings *v, *_v, *s;
 479	struct list_head solutions;
 480	u16 p, l, a, h;
 481	int ret = 0;
 482
 483	specs = stm32f7_get_specs(setup->speed_freq);
 484	if (specs == ERR_PTR(-EINVAL)) {
 485		dev_err(i2c_dev->dev, "speed out of bound {%d}\n",
 486			setup->speed_freq);
 487		return -EINVAL;
 488	}
 489
 490	if ((setup->rise_time > specs->rise_max) ||
 491	    (setup->fall_time > specs->fall_max)) {
 492		dev_err(i2c_dev->dev,
 493			"timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
 494			setup->rise_time, specs->rise_max,
 495			setup->fall_time, specs->fall_max);
 496		return -EINVAL;
 497	}
 498
 499	i2c_dev->dnf = DIV_ROUND_CLOSEST(i2c_dev->dnf_dt, i2cclk);
 500	if (i2c_dev->dnf > STM32F7_I2C_DNF_MAX) {
 501		dev_err(i2c_dev->dev,
 502			"DNF out of bound %d/%d\n",
 503			i2c_dev->dnf * i2cclk, STM32F7_I2C_DNF_MAX * i2cclk);
 504		return -EINVAL;
 505	}
 506
 507	/*  Analog and Digital Filters */
 508	af_delay_min =
 509		(i2c_dev->analog_filter ?
 510		 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
 511	af_delay_max =
 512		(i2c_dev->analog_filter ?
 513		 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
 514	dnf_delay = i2c_dev->dnf * i2cclk;
 515
 516	sdadel_min = specs->hddat_min + setup->fall_time -
 517		af_delay_min - (i2c_dev->dnf + 3) * i2cclk;
 518
 519	sdadel_max = specs->vddat_max - setup->rise_time -
 520		af_delay_max - (i2c_dev->dnf + 4) * i2cclk;
 521
 522	scldel_min = setup->rise_time + specs->sudat_min;
 523
 524	if (sdadel_min < 0)
 525		sdadel_min = 0;
 526	if (sdadel_max < 0)
 527		sdadel_max = 0;
 528
 529	dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
 530		sdadel_min, sdadel_max, scldel_min);
 531
 532	INIT_LIST_HEAD(&solutions);
 533	/* Compute possible values for PRESC, SCLDEL and SDADEL */
 534	for (p = 0; p < STM32F7_PRESC_MAX; p++) {
 535		for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
 536			u32 scldel = (l + 1) * (p + 1) * i2cclk;
 537
 538			if (scldel < scldel_min)
 539				continue;
 540
 541			for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
 542				u32 sdadel = (a * (p + 1) + 1) * i2cclk;
 543
 544				if (((sdadel >= sdadel_min) &&
 545				     (sdadel <= sdadel_max)) &&
 546				    (p != p_prev)) {
 547					v = kmalloc(sizeof(*v), GFP_KERNEL);
 548					if (!v) {
 549						ret = -ENOMEM;
 550						goto exit;
 551					}
 552
 553					v->presc = p;
 554					v->scldel = l;
 555					v->sdadel = a;
 556					p_prev = p;
 557
 558					list_add_tail(&v->node,
 559						      &solutions);
 560					break;
 561				}
 562			}
 563
 564			if (p_prev == p)
 565				break;
 566		}
 567	}
 568
 569	if (list_empty(&solutions)) {
 570		dev_err(i2c_dev->dev, "no Prescaler solution\n");
 571		ret = -EPERM;
 572		goto exit;
 573	}
 574
 575	tsync = af_delay_min + dnf_delay + (2 * i2cclk);
 576	s = NULL;
 577	clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq);
 578	clk_min = NSEC_PER_SEC / setup->speed_freq;
 579
 580	/*
 581	 * Among Prescaler possibilities discovered above figures out SCL Low
 582	 * and High Period. Provided:
 583	 * - SCL Low Period has to be higher than SCL Clock Low Period
 584	 *   defined by I2C Specification. I2C Clock has to be lower than
 585	 *   (SCL Low Period - Analog/Digital filters) / 4.
 586	 * - SCL High Period has to be lower than SCL Clock High Period
 587	 *   defined by I2C Specification
 588	 * - I2C Clock has to be lower than SCL High Period
 589	 */
 590	list_for_each_entry(v, &solutions, node) {
 591		u32 prescaler = (v->presc + 1) * i2cclk;
 592
 593		for (l = 0; l < STM32F7_SCLL_MAX; l++) {
 594			u32 tscl_l = (l + 1) * prescaler + tsync;
 595
 596			if ((tscl_l < specs->l_min) ||
 597			    (i2cclk >=
 598			     ((tscl_l - af_delay_min - dnf_delay) / 4))) {
 599				continue;
 600			}
 601
 602			for (h = 0; h < STM32F7_SCLH_MAX; h++) {
 603				u32 tscl_h = (h + 1) * prescaler + tsync;
 604				u32 tscl = tscl_l + tscl_h +
 605					setup->rise_time + setup->fall_time;
 606
 607				if ((tscl >= clk_min) && (tscl <= clk_max) &&
 608				    (tscl_h >= specs->h_min) &&
 609				    (i2cclk < tscl_h)) {
 610					int clk_error = tscl - i2cbus;
 611
 612					if (clk_error < 0)
 613						clk_error = -clk_error;
 614
 615					if (clk_error < clk_error_prev) {
 616						clk_error_prev = clk_error;
 617						v->scll = l;
 618						v->sclh = h;
 619						s = v;
 620					}
 621				}
 622			}
 623		}
 624	}
 625
 626	if (!s) {
 627		dev_err(i2c_dev->dev, "no solution at all\n");
 628		ret = -EPERM;
 629		goto exit;
 630	}
 631
 632	output->presc = s->presc;
 633	output->scldel = s->scldel;
 634	output->sdadel = s->sdadel;
 635	output->scll = s->scll;
 636	output->sclh = s->sclh;
 637
 638	dev_dbg(i2c_dev->dev,
 639		"Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
 640		output->presc,
 641		output->scldel, output->sdadel,
 642		output->scll, output->sclh);
 643
 644exit:
 645	/* Release list and memory */
 646	list_for_each_entry_safe(v, _v, &solutions, node) {
 647		list_del(&v->node);
 648		kfree(v);
 649	}
 650
 651	return ret;
 652}
 653
 654static u32 stm32f7_get_lower_rate(u32 rate)
 655{
 656	int i = ARRAY_SIZE(stm32f7_i2c_specs);
 657
 658	while (--i)
 659		if (stm32f7_i2c_specs[i].rate < rate)
 660			break;
 661
 662	return stm32f7_i2c_specs[i].rate;
 663}
 664
 665static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
 666				    struct stm32f7_i2c_setup *setup)
 667{
 668	struct i2c_timings timings, *t = &timings;
 669	int ret = 0;
 670
 671	t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
 672	t->scl_rise_ns = i2c_dev->setup.rise_time;
 673	t->scl_fall_ns = i2c_dev->setup.fall_time;
 674
 675	i2c_parse_fw_timings(i2c_dev->dev, t, false);
 676
 677	if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) {
 678		dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n",
 679			t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ);
 680		return -EINVAL;
 681	}
 682
 683	setup->speed_freq = t->bus_freq_hz;
 684	i2c_dev->setup.rise_time = t->scl_rise_ns;
 685	i2c_dev->setup.fall_time = t->scl_fall_ns;
 686	i2c_dev->dnf_dt = t->digital_filter_width_ns;
 687	setup->clock_src = clk_get_rate(i2c_dev->clk);
 688
 689	if (!setup->clock_src) {
 690		dev_err(i2c_dev->dev, "clock rate is 0\n");
 691		return -EINVAL;
 692	}
 693
 694	if (!of_property_read_bool(i2c_dev->dev->of_node, "i2c-digital-filter"))
 695		i2c_dev->dnf_dt = STM32F7_I2C_DNF_DEFAULT;
 696
 697	do {
 698		ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
 699						 &i2c_dev->timing);
 700		if (ret) {
 701			dev_err(i2c_dev->dev,
 702				"failed to compute I2C timings.\n");
 703			if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ)
 704				break;
 705			setup->speed_freq =
 706				stm32f7_get_lower_rate(setup->speed_freq);
 707			dev_warn(i2c_dev->dev,
 708				 "downgrade I2C Speed Freq to (%i)\n",
 709				 setup->speed_freq);
 710		}
 711	} while (ret);
 712
 713	if (ret) {
 714		dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
 715		return ret;
 716	}
 717
 718	i2c_dev->analog_filter = of_property_read_bool(i2c_dev->dev->of_node,
 719						       "i2c-analog-filter");
 720
 721	dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n",
 722		setup->speed_freq, setup->clock_src);
 723	dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
 724		setup->rise_time, setup->fall_time);
 725	dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
 726		str_on_off(i2c_dev->analog_filter), i2c_dev->dnf);
 727
 728	i2c_dev->bus_rate = setup->speed_freq;
 729
 730	return 0;
 731}
 732
 733static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
 734{
 735	void __iomem *base = i2c_dev->base;
 736	u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
 737
 738	stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
 739}
 740
 741static void stm32f7_i2c_dma_callback(void *arg)
 742{
 743	struct stm32f7_i2c_dev *i2c_dev = arg;
 744	struct stm32_i2c_dma *dma = i2c_dev->dma;
 745	struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 746
 747	stm32f7_i2c_disable_dma_req(i2c_dev);
 748	dmaengine_terminate_async(dma->chan_using);
 749	dma_unmap_single(i2c_dev->dev, dma->dma_buf, dma->dma_len,
 750			 dma->dma_data_dir);
 751	if (!f7_msg->smbus)
 752		i2c_put_dma_safe_msg_buf(f7_msg->buf, i2c_dev->msg, true);
 753	complete(&dma->dma_complete);
 754}
 755
 756static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
 757{
 758	struct stm32f7_i2c_timings *t = &i2c_dev->timing;
 759	u32 timing = 0;
 760
 761	/* Timing settings */
 762	timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
 763	timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
 764	timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
 765	timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
 766	timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
 767	writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
 768
 769	/* Configure the Analog Filter */
 770	if (i2c_dev->analog_filter)
 771		stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
 772				     STM32F7_I2C_CR1_ANFOFF);
 773	else
 774		stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
 775				     STM32F7_I2C_CR1_ANFOFF);
 776
 777	/* Program the Digital Filter */
 778	stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
 779			     STM32F7_I2C_CR1_DNF_MASK);
 780	stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
 781			     STM32F7_I2C_CR1_DNF(i2c_dev->dnf));
 782
 783	stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
 784			     STM32F7_I2C_CR1_PE);
 785}
 786
 787static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
 788{
 789	struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 790	void __iomem *base = i2c_dev->base;
 791
 792	if (f7_msg->count) {
 793		writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
 794		f7_msg->count--;
 795	}
 796}
 797
 798static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
 799{
 800	struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 801	void __iomem *base = i2c_dev->base;
 802
 803	if (f7_msg->count) {
 804		*f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
 805		f7_msg->count--;
 806	} else {
 807		/* Flush RX buffer has no data is expected */
 808		readb_relaxed(base + STM32F7_I2C_RXDR);
 809	}
 810}
 811
 812static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
 813{
 814	struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 815	u32 cr2;
 816
 817	if (i2c_dev->use_dma)
 818		f7_msg->count -= STM32F7_I2C_MAX_LEN;
 819
 820	cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
 821
 822	cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
 823	if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
 824		cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
 825	} else {
 826		cr2 &= ~STM32F7_I2C_CR2_RELOAD;
 827		cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 828	}
 829
 830	writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
 831}
 832
 833static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
 834{
 835	struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 836	u32 cr2;
 837	u8 *val;
 838
 839	/*
 840	 * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
 841	 * data received inform us how many data will follow.
 842	 */
 843	stm32f7_i2c_read_rx_data(i2c_dev);
 844
 845	/*
 846	 * Update NBYTES with the value read to continue the transfer
 847	 */
 848	val = f7_msg->buf - sizeof(u8);
 849	f7_msg->count = *val;
 850	cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
 851	cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
 852	cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 853	writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
 854}
 855
 856static void stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
 857{
 858	struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
 859
 860	stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
 861			     STM32F7_I2C_CR1_PE);
 862
 863	stm32f7_i2c_hw_config(i2c_dev);
 864}
 865
 866static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
 867{
 868	u32 status;
 869	int ret;
 870
 871	ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
 872					 status,
 873					 !(status & STM32F7_I2C_ISR_BUSY),
 874					 10, 1000);
 875	if (!ret)
 876		return 0;
 877
 878	stm32f7_i2c_release_bus(&i2c_dev->adap);
 879
 880	return -EBUSY;
 881}
 882
 883static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
 884				 struct i2c_msg *msg)
 885{
 886	struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 887	void __iomem *base = i2c_dev->base;
 888	u8 *dma_buf;
 889	u32 cr1, cr2;
 890	int ret;
 891
 892	f7_msg->addr = msg->addr;
 893	f7_msg->buf = msg->buf;
 894	f7_msg->count = msg->len;
 895	f7_msg->result = 0;
 896	f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
 897
 898	reinit_completion(&i2c_dev->complete);
 899
 900	cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
 901	cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
 902
 903	/* Set transfer direction */
 904	cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 905	if (msg->flags & I2C_M_RD)
 906		cr2 |= STM32F7_I2C_CR2_RD_WRN;
 907
 908	/* Set slave address */
 909	cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
 910	if (msg->flags & I2C_M_TEN) {
 911		cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
 912		cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
 913		cr2 |= STM32F7_I2C_CR2_ADD10;
 914	} else {
 915		cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
 916		cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
 917	}
 918
 919	/* Set nb bytes to transfer and reload if needed */
 920	cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
 921	if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
 922		cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
 923		cr2 |= STM32F7_I2C_CR2_RELOAD;
 924	} else {
 925		cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 926	}
 927
 928	/* Enable NACK, STOP, error and transfer complete interrupts */
 929	cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
 930		STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
 931
 932	/* Clear DMA req and TX/RX interrupt */
 933	cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
 934			STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
 935
 936	/* Configure DMA or enable RX/TX interrupt */
 937	i2c_dev->use_dma = false;
 938	if (i2c_dev->dma && !i2c_dev->atomic) {
 939		dma_buf = i2c_get_dma_safe_msg_buf(msg, STM32F7_I2C_DMA_LEN_MIN);
 940		if (dma_buf) {
 941			f7_msg->buf = dma_buf;
 942			ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
 943						      msg->flags & I2C_M_RD,
 944						      f7_msg->count, f7_msg->buf,
 945						      stm32f7_i2c_dma_callback,
 946						      i2c_dev);
 947			if (ret) {
 948				dev_warn(i2c_dev->dev, "can't use DMA\n");
 949				i2c_put_dma_safe_msg_buf(f7_msg->buf, msg, false);
 950				f7_msg->buf = msg->buf;
 951			} else {
 952				i2c_dev->use_dma = true;
 953			}
 954		}
 955	}
 956
 957	if (!i2c_dev->use_dma) {
 958		if (msg->flags & I2C_M_RD)
 959			cr1 |= STM32F7_I2C_CR1_RXIE;
 960		else
 961			cr1 |= STM32F7_I2C_CR1_TXIE;
 962	} else {
 963		if (msg->flags & I2C_M_RD)
 964			cr1 |= STM32F7_I2C_CR1_RXDMAEN;
 965		else
 966			cr1 |= STM32F7_I2C_CR1_TXDMAEN;
 967	}
 968
 969	if (i2c_dev->atomic)
 970		cr1 &= ~STM32F7_I2C_ALL_IRQ_MASK; /* Disable all interrupts */
 971
 972	/* Configure Start/Repeated Start */
 973	cr2 |= STM32F7_I2C_CR2_START;
 974
 975	i2c_dev->master_mode = true;
 976
 977	/* Write configurations registers */
 978	writel_relaxed(cr1, base + STM32F7_I2C_CR1);
 979	writel_relaxed(cr2, base + STM32F7_I2C_CR2);
 980}
 981
 982static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
 983				      unsigned short flags, u8 command,
 984				      union i2c_smbus_data *data)
 985{
 986	struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 987	struct device *dev = i2c_dev->dev;
 988	void __iomem *base = i2c_dev->base;
 989	u32 cr1, cr2;
 990	int i, ret;
 991
 992	f7_msg->result = 0;
 993	reinit_completion(&i2c_dev->complete);
 994
 995	cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
 996	cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
 997
 998	/* Set transfer direction */
 999	cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1000	if (f7_msg->read_write)
1001		cr2 |= STM32F7_I2C_CR2_RD_WRN;
1002
1003	/* Set slave address */
1004	cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
1005	cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
1006
1007	f7_msg->smbus_buf[0] = command;
1008	switch (f7_msg->size) {
1009	case I2C_SMBUS_QUICK:
1010		f7_msg->stop = true;
1011		f7_msg->count = 0;
1012		break;
1013	case I2C_SMBUS_BYTE:
1014		f7_msg->stop = true;
1015		f7_msg->count = 1;
1016		break;
1017	case I2C_SMBUS_BYTE_DATA:
1018		if (f7_msg->read_write) {
1019			f7_msg->stop = false;
1020			f7_msg->count = 1;
1021			cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1022		} else {
1023			f7_msg->stop = true;
1024			f7_msg->count = 2;
1025			f7_msg->smbus_buf[1] = data->byte;
1026		}
1027		break;
1028	case I2C_SMBUS_WORD_DATA:
1029		if (f7_msg->read_write) {
1030			f7_msg->stop = false;
1031			f7_msg->count = 1;
1032			cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1033		} else {
1034			f7_msg->stop = true;
1035			f7_msg->count = 3;
1036			f7_msg->smbus_buf[1] = data->word & 0xff;
1037			f7_msg->smbus_buf[2] = data->word >> 8;
1038		}
1039		break;
1040	case I2C_SMBUS_BLOCK_DATA:
1041		if (f7_msg->read_write) {
1042			f7_msg->stop = false;
1043			f7_msg->count = 1;
1044			cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1045		} else {
1046			f7_msg->stop = true;
1047			if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
1048			    !data->block[0]) {
1049				dev_err(dev, "Invalid block write size %d\n",
1050					data->block[0]);
1051				return -EINVAL;
1052			}
1053			f7_msg->count = data->block[0] + 2;
1054			for (i = 1; i < f7_msg->count; i++)
1055				f7_msg->smbus_buf[i] = data->block[i - 1];
1056		}
1057		break;
1058	case I2C_SMBUS_PROC_CALL:
1059		f7_msg->stop = false;
1060		f7_msg->count = 3;
1061		f7_msg->smbus_buf[1] = data->word & 0xff;
1062		f7_msg->smbus_buf[2] = data->word >> 8;
1063		cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1064		f7_msg->read_write = I2C_SMBUS_READ;
1065		break;
1066	case I2C_SMBUS_BLOCK_PROC_CALL:
1067		f7_msg->stop = false;
1068		if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
1069			dev_err(dev, "Invalid block write size %d\n",
1070				data->block[0]);
1071			return -EINVAL;
1072		}
1073		f7_msg->count = data->block[0] + 2;
1074		for (i = 1; i < f7_msg->count; i++)
1075			f7_msg->smbus_buf[i] = data->block[i - 1];
1076		cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1077		f7_msg->read_write = I2C_SMBUS_READ;
1078		break;
1079	case I2C_SMBUS_I2C_BLOCK_DATA:
1080		/* Rely on emulated i2c transfer (through master_xfer) */
1081		return -EOPNOTSUPP;
1082	default:
1083		dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
1084		return -EOPNOTSUPP;
1085	}
1086
1087	f7_msg->buf = f7_msg->smbus_buf;
1088
1089	/* Configure PEC */
1090	if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
1091		cr1 |= STM32F7_I2C_CR1_PECEN;
1092		if (!f7_msg->read_write) {
1093			cr2 |= STM32F7_I2C_CR2_PECBYTE;
1094			f7_msg->count++;
1095		}
1096	} else {
1097		cr1 &= ~STM32F7_I2C_CR1_PECEN;
1098		cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
1099	}
1100
1101	/* Set number of bytes to be transferred */
1102	cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
1103	cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1104
1105	/* Enable NACK, STOP, error and transfer complete interrupts */
1106	cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
1107		STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
1108
1109	/* Clear DMA req and TX/RX interrupt */
1110	cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1111			STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1112
1113	/* Configure DMA or enable RX/TX interrupt */
1114	i2c_dev->use_dma = false;
1115	if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
1116		ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1117					      cr2 & STM32F7_I2C_CR2_RD_WRN,
1118					      f7_msg->count, f7_msg->buf,
1119					      stm32f7_i2c_dma_callback,
1120					      i2c_dev);
1121		if (!ret)
1122			i2c_dev->use_dma = true;
1123		else
1124			dev_warn(i2c_dev->dev, "can't use DMA\n");
1125	}
1126
1127	if (!i2c_dev->use_dma) {
1128		if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1129			cr1 |= STM32F7_I2C_CR1_RXIE;
1130		else
1131			cr1 |= STM32F7_I2C_CR1_TXIE;
1132	} else {
1133		if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1134			cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1135		else
1136			cr1 |= STM32F7_I2C_CR1_TXDMAEN;
1137	}
1138
1139	/* Set Start bit */
1140	cr2 |= STM32F7_I2C_CR2_START;
1141
1142	i2c_dev->master_mode = true;
1143
1144	/* Write configurations registers */
1145	writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1146	writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1147
1148	return 0;
1149}
1150
1151static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1152{
1153	struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1154	void __iomem *base = i2c_dev->base;
1155	u32 cr1, cr2;
1156	int ret;
1157
1158	cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1159	cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1160
1161	/* Set transfer direction */
1162	cr2 |= STM32F7_I2C_CR2_RD_WRN;
1163
1164	switch (f7_msg->size) {
1165	case I2C_SMBUS_BYTE_DATA:
1166		f7_msg->count = 1;
1167		break;
1168	case I2C_SMBUS_WORD_DATA:
1169	case I2C_SMBUS_PROC_CALL:
1170		f7_msg->count = 2;
1171		break;
1172	case I2C_SMBUS_BLOCK_DATA:
1173	case I2C_SMBUS_BLOCK_PROC_CALL:
1174		f7_msg->count = 1;
1175		cr2 |= STM32F7_I2C_CR2_RELOAD;
1176		break;
1177	}
1178
1179	f7_msg->buf = f7_msg->smbus_buf;
1180	f7_msg->stop = true;
1181
1182	/* Add one byte for PEC if needed */
1183	if (cr1 & STM32F7_I2C_CR1_PECEN) {
1184		cr2 |= STM32F7_I2C_CR2_PECBYTE;
1185		f7_msg->count++;
1186	}
1187
1188	/* Set number of bytes to be transferred */
1189	cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1190	cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1191
1192	/*
1193	 * Configure RX/TX interrupt:
1194	 */
1195	cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1196	cr1 |= STM32F7_I2C_CR1_RXIE;
1197
1198	/*
1199	 * Configure DMA or enable RX/TX interrupt:
1200	 * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
1201	 * dma as we don't know in advance how many data will be received
1202	 */
1203	cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1204		 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1205
1206	i2c_dev->use_dma = false;
1207	if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1208	    f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
1209	    f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
1210		ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1211					      cr2 & STM32F7_I2C_CR2_RD_WRN,
1212					      f7_msg->count, f7_msg->buf,
1213					      stm32f7_i2c_dma_callback,
1214					      i2c_dev);
1215
1216		if (!ret)
1217			i2c_dev->use_dma = true;
1218		else
1219			dev_warn(i2c_dev->dev, "can't use DMA\n");
1220	}
1221
1222	if (!i2c_dev->use_dma)
1223		cr1 |= STM32F7_I2C_CR1_RXIE;
1224	else
1225		cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1226
1227	/* Configure Repeated Start */
1228	cr2 |= STM32F7_I2C_CR2_START;
1229
1230	/* Write configurations registers */
1231	writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1232	writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1233}
1234
1235static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
1236{
1237	struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1238	u8 count, internal_pec, received_pec;
1239
1240	internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1241
1242	switch (f7_msg->size) {
1243	case I2C_SMBUS_BYTE:
1244	case I2C_SMBUS_BYTE_DATA:
1245		received_pec = f7_msg->smbus_buf[1];
1246		break;
1247	case I2C_SMBUS_WORD_DATA:
1248	case I2C_SMBUS_PROC_CALL:
1249		received_pec = f7_msg->smbus_buf[2];
1250		break;
1251	case I2C_SMBUS_BLOCK_DATA:
1252	case I2C_SMBUS_BLOCK_PROC_CALL:
1253		count = f7_msg->smbus_buf[0];
1254		received_pec = f7_msg->smbus_buf[count];
1255		break;
1256	default:
1257		dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1258		return -EINVAL;
1259	}
1260
1261	if (internal_pec != received_pec) {
1262		dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1263			internal_pec, received_pec);
1264		return -EBADMSG;
1265	}
1266
1267	return 0;
1268}
1269
1270static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
1271{
1272	u32 addr;
1273
1274	if (!slave)
1275		return false;
1276
1277	if (slave->flags & I2C_CLIENT_TEN) {
1278		/*
1279		 * For 10-bit addr, addcode = 11110XY with
1280		 * X = Bit 9 of slave address
1281		 * Y = Bit 8 of slave address
1282		 */
1283		addr = slave->addr >> 8;
1284		addr |= 0x78;
1285		if (addr == addcode)
1286			return true;
1287	} else {
1288		addr = slave->addr & 0x7f;
1289		if (addr == addcode)
1290			return true;
1291	}
1292
1293	return false;
1294}
1295
1296static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1297{
1298	struct i2c_client *slave = i2c_dev->slave_running;
1299	void __iomem *base = i2c_dev->base;
1300	u32 mask;
1301	u8 value = 0;
1302
1303	if (i2c_dev->slave_dir) {
1304		/* Notify i2c slave that new read transfer is starting */
1305		i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1306
1307		/*
1308		 * Disable slave TX config in case of I2C combined message
1309		 * (I2C Write followed by I2C Read)
1310		 */
1311		mask = STM32F7_I2C_CR2_RELOAD;
1312		stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
1313		mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1314		       STM32F7_I2C_CR1_TCIE;
1315		stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1316
1317		/* Enable TX empty, STOP, NACK interrupts */
1318		mask =  STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1319			STM32F7_I2C_CR1_TXIE;
1320		stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1321
1322		/* Write 1st data byte */
1323		writel_relaxed(value, base + STM32F7_I2C_TXDR);
1324	} else {
1325		/* Notify i2c slave that new write transfer is starting */
1326		i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1327
1328		/* Set reload mode to be able to ACK/NACK each received byte */
1329		mask = STM32F7_I2C_CR2_RELOAD;
1330		stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1331
1332		/*
1333		 * Set STOP, NACK, RX empty and transfer complete interrupts.*
1334		 * Set Slave Byte Control to be able to ACK/NACK each data
1335		 * byte received
1336		 */
1337		mask =  STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1338			STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1339			STM32F7_I2C_CR1_TCIE;
1340		stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1341	}
1342}
1343
1344static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1345{
1346	void __iomem *base = i2c_dev->base;
1347	u32 isr, addcode, dir, mask;
1348	int i;
1349
1350	isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1351	addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
1352	dir = isr & STM32F7_I2C_ISR_DIR;
1353
1354	for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1355		if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
1356			i2c_dev->slave_running = i2c_dev->slave[i];
1357			i2c_dev->slave_dir = dir;
1358
1359			/* Start I2C slave processing */
1360			stm32f7_i2c_slave_start(i2c_dev);
1361
1362			/* Clear ADDR flag */
1363			mask = STM32F7_I2C_ICR_ADDRCF;
1364			writel_relaxed(mask, base + STM32F7_I2C_ICR);
1365			break;
1366		}
1367	}
1368}
1369
1370static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1371				    struct i2c_client *slave, int *id)
1372{
1373	int i;
1374
1375	for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1376		if (i2c_dev->slave[i] == slave) {
1377			*id = i;
1378			return 0;
1379		}
1380	}
1381
1382	dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1383
1384	return -ENODEV;
1385}
1386
1387static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1388					 struct i2c_client *slave, int *id)
1389{
1390	struct device *dev = i2c_dev->dev;
1391	int i;
1392
1393	/*
1394	 * slave[STM32F7_SLAVE_HOSTNOTIFY] support only SMBus Host address (0x8)
1395	 * slave[STM32F7_SLAVE_7_10_BITS_ADDR] supports 7-bit and 10-bit slave address
1396	 * slave[STM32F7_SLAVE_7_BITS_ADDR] supports 7-bit slave address only
1397	 */
1398	if (i2c_dev->smbus_mode && (slave->addr == 0x08)) {
1399		if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY])
1400			goto fail;
1401		*id = STM32F7_SLAVE_HOSTNOTIFY;
1402		return 0;
1403	}
1404
1405	for (i = STM32F7_I2C_MAX_SLAVE - 1; i > STM32F7_SLAVE_HOSTNOTIFY; i--) {
1406		if ((i == STM32F7_SLAVE_7_BITS_ADDR) &&
1407		    (slave->flags & I2C_CLIENT_TEN))
1408			continue;
1409		if (!i2c_dev->slave[i]) {
1410			*id = i;
1411			return 0;
1412		}
1413	}
1414
1415fail:
1416	dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
1417
1418	return -EINVAL;
1419}
1420
1421static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1422{
1423	int i;
1424
1425	for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1426		if (i2c_dev->slave[i])
1427			return true;
1428	}
1429
1430	return false;
1431}
1432
1433static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1434{
1435	int i, busy;
1436
1437	busy = 0;
1438	for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1439		if (i2c_dev->slave[i])
1440			busy++;
1441	}
1442
1443	return i == busy;
1444}
1445
1446static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev, u32 status)
1447{
1448	void __iomem *base = i2c_dev->base;
1449	u32 cr2, mask;
1450	u8 val;
1451	int ret;
1452
1453	/* Slave transmitter mode */
1454	if (status & STM32F7_I2C_ISR_TXIS) {
1455		i2c_slave_event(i2c_dev->slave_running,
1456				I2C_SLAVE_READ_PROCESSED,
1457				&val);
1458
1459		/* Write data byte */
1460		writel_relaxed(val, base + STM32F7_I2C_TXDR);
1461	}
1462
1463	/* Transfer Complete Reload for Slave receiver mode */
1464	if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
1465		/*
1466		 * Read data byte then set NBYTES to receive next byte or NACK
1467		 * the current received byte
1468		 */
1469		val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1470		ret = i2c_slave_event(i2c_dev->slave_running,
1471				      I2C_SLAVE_WRITE_RECEIVED,
1472				      &val);
1473		if (!ret) {
1474			cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1475			cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1476			writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1477		} else {
1478			mask = STM32F7_I2C_CR2_NACK;
1479			stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1480		}
1481	}
1482
1483	/* NACK received */
1484	if (status & STM32F7_I2C_ISR_NACKF) {
1485		dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1486		writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1487	}
1488
1489	/* STOP received */
1490	if (status & STM32F7_I2C_ISR_STOPF) {
1491		/* Disable interrupts */
1492		stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1493
1494		if (i2c_dev->slave_dir) {
1495			/*
1496			 * Flush TX buffer in order to not used the byte in
1497			 * TXDR for the next transfer
1498			 */
1499			mask = STM32F7_I2C_ISR_TXE;
1500			stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
1501		}
1502
1503		/* Clear STOP flag */
1504		writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1505
1506		/* Notify i2c slave that a STOP flag has been detected */
1507		i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
1508
1509		i2c_dev->slave_running = NULL;
1510	}
1511
1512	/* Address match received */
1513	if (status & STM32F7_I2C_ISR_ADDR)
1514		stm32f7_i2c_slave_addr(i2c_dev);
1515
1516	return IRQ_HANDLED;
1517}
1518
1519static irqreturn_t stm32f7_i2c_handle_isr_errs(struct stm32f7_i2c_dev *i2c_dev, u32 status)
1520{
1521	struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1522	u16 addr = f7_msg->addr;
1523	void __iomem *base = i2c_dev->base;
1524	struct device *dev = i2c_dev->dev;
1525
1526	/* Bus error */
1527	if (status & STM32F7_I2C_ISR_BERR) {
1528		dev_err(dev, "Bus error accessing addr 0x%x\n", addr);
1529		writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
1530		stm32f7_i2c_release_bus(&i2c_dev->adap);
1531		f7_msg->result = -EIO;
1532	}
1533
1534	/* Arbitration loss */
1535	if (status & STM32F7_I2C_ISR_ARLO) {
1536		dev_dbg(dev, "Arbitration loss accessing addr 0x%x\n", addr);
1537		writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
1538		f7_msg->result = -EAGAIN;
1539	}
1540
1541	if (status & STM32F7_I2C_ISR_PECERR) {
1542		dev_err(dev, "PEC error in reception accessing addr 0x%x\n", addr);
1543		writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
1544		f7_msg->result = -EINVAL;
1545	}
1546
1547	if (status & STM32F7_I2C_ISR_ALERT) {
1548		dev_dbg(dev, "SMBus alert received\n");
1549		writel_relaxed(STM32F7_I2C_ICR_ALERTCF, base + STM32F7_I2C_ICR);
1550		i2c_handle_smbus_alert(i2c_dev->alert->ara);
1551		return IRQ_HANDLED;
1552	}
1553
1554	if (!i2c_dev->slave_running) {
1555		u32 mask;
1556		/* Disable interrupts */
1557		if (stm32f7_i2c_is_slave_registered(i2c_dev))
1558			mask = STM32F7_I2C_XFER_IRQ_MASK;
1559		else
1560			mask = STM32F7_I2C_ALL_IRQ_MASK;
1561		stm32f7_i2c_disable_irq(i2c_dev, mask);
1562	}
1563
1564	/* Disable dma */
1565	if (i2c_dev->use_dma)
1566		stm32f7_i2c_dma_callback(i2c_dev);
1567
1568	i2c_dev->master_mode = false;
1569	complete(&i2c_dev->complete);
1570
1571	return IRQ_HANDLED;
1572}
1573
1574#define STM32F7_ERR_EVENTS (STM32F7_I2C_ISR_BERR | STM32F7_I2C_ISR_ARLO |\
1575			    STM32F7_I2C_ISR_PECERR | STM32F7_I2C_ISR_ALERT)
1576static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
1577{
1578	struct stm32f7_i2c_dev *i2c_dev = data;
1579	u32 status;
1580
1581	status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1582
1583	/*
1584	 * Check if the interrupt is for a slave device or related
1585	 * to errors flags (in case of single it line mode)
1586	 */
1587	if (!i2c_dev->master_mode ||
1588	    (i2c_dev->setup.single_it_line && (status & STM32F7_ERR_EVENTS)))
1589		return IRQ_WAKE_THREAD;
1590
1591	/* Tx empty */
1592	if (status & STM32F7_I2C_ISR_TXIS)
1593		stm32f7_i2c_write_tx_data(i2c_dev);
1594
1595	/* RX not empty */
1596	if (status & STM32F7_I2C_ISR_RXNE)
1597		stm32f7_i2c_read_rx_data(i2c_dev);
1598
1599	/* Wake up the thread if other flags are raised */
1600	if (status &
1601	    (STM32F7_I2C_ISR_NACKF | STM32F7_I2C_ISR_STOPF |
1602	     STM32F7_I2C_ISR_TC | STM32F7_I2C_ISR_TCR))
1603		return IRQ_WAKE_THREAD;
1604
1605	return IRQ_HANDLED;
1606}
1607
1608static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
1609{
1610	struct stm32f7_i2c_dev *i2c_dev = data;
1611	struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1612	void __iomem *base = i2c_dev->base;
1613	u32 status, mask;
1614	int ret;
1615
1616	status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1617
1618	if (!i2c_dev->master_mode)
1619		return stm32f7_i2c_slave_isr_event(i2c_dev, status);
1620
1621	/* Handle errors in case of this handler is used for events/errors */
1622	if (i2c_dev->setup.single_it_line && (status & STM32F7_ERR_EVENTS))
1623		return stm32f7_i2c_handle_isr_errs(i2c_dev, status);
1624
1625	/* NACK received */
1626	if (status & STM32F7_I2C_ISR_NACKF) {
1627		dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n",
1628			__func__, f7_msg->addr);
1629		writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1630		if (i2c_dev->use_dma)
1631			stm32f7_i2c_dma_callback(i2c_dev);
1632		f7_msg->result = -ENXIO;
1633	}
1634
1635	if (status & STM32F7_I2C_ISR_TCR) {
1636		if (f7_msg->smbus)
1637			stm32f7_i2c_smbus_reload(i2c_dev);
1638		else
1639			stm32f7_i2c_reload(i2c_dev);
1640	}
1641
1642	/* Transfer complete */
1643	if (status & STM32F7_I2C_ISR_TC) {
1644		/* Wait for dma transfer completion before sending next message */
1645		if (i2c_dev->use_dma && !f7_msg->result) {
1646			ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
1647			if (!ret) {
1648				dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1649				stm32f7_i2c_dma_callback(i2c_dev);
1650				f7_msg->result = -ETIMEDOUT;
1651			}
1652		}
1653		if (f7_msg->stop) {
1654			mask = STM32F7_I2C_CR2_STOP;
1655			stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1656		} else if (f7_msg->smbus) {
1657			stm32f7_i2c_smbus_rep_start(i2c_dev);
1658		} else {
1659			i2c_dev->msg_id++;
1660			i2c_dev->msg++;
1661			stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1662		}
1663	}
1664
1665	/* STOP detection flag */
1666	if (status & STM32F7_I2C_ISR_STOPF) {
1667		/* Disable interrupts */
1668		if (stm32f7_i2c_is_slave_registered(i2c_dev))
1669			mask = STM32F7_I2C_XFER_IRQ_MASK;
1670		else
1671			mask = STM32F7_I2C_ALL_IRQ_MASK;
1672		stm32f7_i2c_disable_irq(i2c_dev, mask);
1673
1674		/* Clear STOP flag */
1675		writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1676
1677		i2c_dev->master_mode = false;
1678		complete(&i2c_dev->complete);
1679	}
1680
1681	return IRQ_HANDLED;
1682}
1683
1684static irqreturn_t stm32f7_i2c_isr_error_thread(int irq, void *data)
1685{
1686	struct stm32f7_i2c_dev *i2c_dev = data;
1687	u32 status;
1688
1689	status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1690
1691	return stm32f7_i2c_handle_isr_errs(i2c_dev, status);
1692}
1693
1694static int stm32f7_i2c_wait_polling(struct stm32f7_i2c_dev *i2c_dev)
1695{
1696	ktime_t timeout = ktime_add_ms(ktime_get(), i2c_dev->adap.timeout);
1697
1698	while (ktime_compare(ktime_get(), timeout) < 0) {
1699		udelay(5);
1700		stm32f7_i2c_isr_event(0, i2c_dev);
1701
1702		if (completion_done(&i2c_dev->complete))
1703			return 1;
1704	}
1705
1706	return 0;
1707}
1708
1709static int stm32f7_i2c_xfer_core(struct i2c_adapter *i2c_adap,
1710			    struct i2c_msg msgs[], int num)
1711{
1712	struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1713	struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1714	struct stm32_i2c_dma *dma = i2c_dev->dma;
1715	unsigned long time_left;
1716	int ret;
1717
1718	i2c_dev->msg = msgs;
1719	i2c_dev->msg_num = num;
1720	i2c_dev->msg_id = 0;
1721	f7_msg->smbus = false;
1722
1723	ret = pm_runtime_resume_and_get(i2c_dev->dev);
1724	if (ret < 0)
1725		return ret;
1726
1727	ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1728	if (ret)
1729		goto pm_free;
1730
1731	stm32f7_i2c_xfer_msg(i2c_dev, msgs);
1732
1733	if (!i2c_dev->atomic)
1734		time_left = wait_for_completion_timeout(&i2c_dev->complete,
1735							i2c_dev->adap.timeout);
1736	else
1737		time_left = stm32f7_i2c_wait_polling(i2c_dev);
1738
1739	ret = f7_msg->result;
1740	if (ret) {
1741		if (i2c_dev->use_dma)
1742			dmaengine_synchronize(dma->chan_using);
1743
1744		/*
1745		 * It is possible that some unsent data have already been
1746		 * written into TXDR. To avoid sending old data in a
1747		 * further transfer, flush TXDR in case of any error
1748		 */
1749		writel_relaxed(STM32F7_I2C_ISR_TXE,
1750			       i2c_dev->base + STM32F7_I2C_ISR);
1751		goto pm_free;
1752	}
1753
1754	if (!time_left) {
1755		dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
1756			i2c_dev->msg->addr);
1757		if (i2c_dev->use_dma)
1758			dmaengine_terminate_sync(dma->chan_using);
1759		stm32f7_i2c_wait_free_bus(i2c_dev);
1760		ret = -ETIMEDOUT;
1761	}
1762
1763pm_free:
1764	pm_runtime_put_autosuspend(i2c_dev->dev);
1765
1766	return (ret < 0) ? ret : num;
1767}
1768
1769static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
1770			    struct i2c_msg msgs[], int num)
1771{
1772	struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1773
1774	i2c_dev->atomic = false;
1775	return stm32f7_i2c_xfer_core(i2c_adap, msgs, num);
1776}
1777
1778static int stm32f7_i2c_xfer_atomic(struct i2c_adapter *i2c_adap,
1779			    struct i2c_msg msgs[], int num)
1780{
1781	struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1782
1783	i2c_dev->atomic = true;
1784	return stm32f7_i2c_xfer_core(i2c_adap, msgs, num);
1785}
1786
1787static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
1788				  unsigned short flags, char read_write,
1789				  u8 command, int size,
1790				  union i2c_smbus_data *data)
1791{
1792	struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
1793	struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1794	struct stm32_i2c_dma *dma = i2c_dev->dma;
1795	struct device *dev = i2c_dev->dev;
1796	unsigned long time_left;
1797	int i, ret;
1798
1799	f7_msg->addr = addr;
1800	f7_msg->size = size;
1801	f7_msg->read_write = read_write;
1802	f7_msg->smbus = true;
1803
1804	ret = pm_runtime_resume_and_get(dev);
1805	if (ret < 0)
1806		return ret;
1807
1808	ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1809	if (ret)
1810		goto pm_free;
1811
1812	ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1813	if (ret)
1814		goto pm_free;
1815
1816	time_left = wait_for_completion_timeout(&i2c_dev->complete,
1817						i2c_dev->adap.timeout);
1818	ret = f7_msg->result;
1819	if (ret) {
1820		if (i2c_dev->use_dma)
1821			dmaengine_synchronize(dma->chan_using);
1822
1823		/*
1824		 * It is possible that some unsent data have already been
1825		 * written into TXDR. To avoid sending old data in a
1826		 * further transfer, flush TXDR in case of any error
1827		 */
1828		writel_relaxed(STM32F7_I2C_ISR_TXE,
1829			       i2c_dev->base + STM32F7_I2C_ISR);
1830		goto pm_free;
1831	}
1832
1833	if (!time_left) {
1834		dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
1835		if (i2c_dev->use_dma)
1836			dmaengine_terminate_sync(dma->chan_using);
1837		stm32f7_i2c_wait_free_bus(i2c_dev);
1838		ret = -ETIMEDOUT;
1839		goto pm_free;
1840	}
1841
1842	/* Check PEC */
1843	if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1844		ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1845		if (ret)
1846			goto pm_free;
1847	}
1848
1849	if (read_write && size != I2C_SMBUS_QUICK) {
1850		switch (size) {
1851		case I2C_SMBUS_BYTE:
1852		case I2C_SMBUS_BYTE_DATA:
1853			data->byte = f7_msg->smbus_buf[0];
1854		break;
1855		case I2C_SMBUS_WORD_DATA:
1856		case I2C_SMBUS_PROC_CALL:
1857			data->word = f7_msg->smbus_buf[0] |
1858				(f7_msg->smbus_buf[1] << 8);
1859		break;
1860		case I2C_SMBUS_BLOCK_DATA:
1861		case I2C_SMBUS_BLOCK_PROC_CALL:
1862		for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
1863			data->block[i] = f7_msg->smbus_buf[i];
1864		break;
1865		default:
1866			dev_err(dev, "Unsupported smbus transaction\n");
1867			ret = -EINVAL;
1868		}
1869	}
1870
1871pm_free:
1872	pm_runtime_put_autosuspend(dev);
1873	return ret;
1874}
1875
1876static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev,
1877				      bool enable)
1878{
1879	void __iomem *base = i2c_dev->base;
1880	u32 mask = STM32F7_I2C_CR1_WUPEN;
1881
1882	if (!i2c_dev->wakeup_src)
1883		return;
1884
1885	if (enable) {
1886		device_set_wakeup_enable(i2c_dev->dev, true);
1887		stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1888	} else {
1889		device_set_wakeup_enable(i2c_dev->dev, false);
1890		stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1891	}
1892}
1893
1894static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
1895{
1896	struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1897	void __iomem *base = i2c_dev->base;
1898	struct device *dev = i2c_dev->dev;
1899	u32 oar1, oar2, mask;
1900	int id, ret;
1901
1902	if (slave->flags & I2C_CLIENT_PEC) {
1903		dev_err(dev, "SMBus PEC not supported in slave mode\n");
1904		return -EINVAL;
1905	}
1906
1907	if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1908		dev_err(dev, "Too much slave registered\n");
1909		return -EBUSY;
1910	}
1911
1912	ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
1913	if (ret)
1914		return ret;
1915
1916	ret = pm_runtime_resume_and_get(dev);
1917	if (ret < 0)
1918		return ret;
1919
1920	if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1921		stm32f7_i2c_enable_wakeup(i2c_dev, true);
1922
1923	switch (id) {
1924	case 0:
1925		/* Slave SMBus Host */
1926		i2c_dev->slave[id] = slave;
1927		break;
1928
1929	case 1:
1930		/* Configure Own Address 1 */
1931		oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1932		oar1 &= ~STM32F7_I2C_OAR1_MASK;
1933		if (slave->flags & I2C_CLIENT_TEN) {
1934			oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
1935			oar1 |= STM32F7_I2C_OAR1_OA1MODE;
1936		} else {
1937			oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
1938		}
1939		oar1 |= STM32F7_I2C_OAR1_OA1EN;
1940		i2c_dev->slave[id] = slave;
1941		writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
1942		break;
1943
1944	case 2:
1945		/* Configure Own Address 2 */
1946		oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1947		oar2 &= ~STM32F7_I2C_OAR2_MASK;
1948		if (slave->flags & I2C_CLIENT_TEN) {
1949			ret = -EOPNOTSUPP;
1950			goto pm_free;
1951		}
1952
1953		oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
1954		oar2 |= STM32F7_I2C_OAR2_OA2EN;
1955		i2c_dev->slave[id] = slave;
1956		writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1957		break;
1958
1959	default:
1960		dev_err(dev, "I2C slave id not supported\n");
1961		ret = -ENODEV;
1962		goto pm_free;
1963	}
1964
1965	/* Enable ACK */
1966	stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
1967
1968	/* Enable Address match interrupt, error interrupt and enable I2C  */
1969	mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
1970		STM32F7_I2C_CR1_PE;
1971	stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1972
1973	ret = 0;
1974pm_free:
1975	if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1976		stm32f7_i2c_enable_wakeup(i2c_dev, false);
1977
1978	pm_runtime_put_autosuspend(dev);
1979
1980	return ret;
1981}
1982
1983static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
1984{
1985	struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1986	void __iomem *base = i2c_dev->base;
1987	u32 mask;
1988	int id, ret;
1989
1990	ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
1991	if (ret)
1992		return ret;
1993
1994	WARN_ON(!i2c_dev->slave[id]);
1995
1996	ret = pm_runtime_resume_and_get(i2c_dev->dev);
1997	if (ret < 0)
1998		return ret;
1999
2000	if (id == 1) {
2001		mask = STM32F7_I2C_OAR1_OA1EN;
2002		stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
2003	} else if (id == 2) {
2004		mask = STM32F7_I2C_OAR2_OA2EN;
2005		stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
2006	}
2007
2008	i2c_dev->slave[id] = NULL;
2009
2010	if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2011		stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
2012		stm32f7_i2c_enable_wakeup(i2c_dev, false);
2013	}
2014
2015	pm_runtime_put_autosuspend(i2c_dev->dev);
2016
2017	return 0;
2018}
2019
2020static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev,
2021					  bool enable)
2022{
2023	int ret = 0;
2024
2025	if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ ||
2026	    (!i2c_dev->setup.fmp_cr1_bit && IS_ERR_OR_NULL(i2c_dev->regmap)))
2027		/* Optional */
2028		return 0;
2029
2030	if (i2c_dev->setup.fmp_cr1_bit) {
2031		if (enable)
2032			stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1, STM32_I2C_CR1_FMP);
2033		else
2034			stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, STM32_I2C_CR1_FMP);
2035	} else {
2036		if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg)
2037			ret = regmap_update_bits(i2c_dev->regmap, i2c_dev->fmp_sreg,
2038						 i2c_dev->fmp_mask, enable ? i2c_dev->fmp_mask : 0);
2039		else
2040			ret = regmap_write(i2c_dev->regmap,
2041					   enable ? i2c_dev->fmp_sreg : i2c_dev->fmp_creg,
2042					   i2c_dev->fmp_mask);
2043	}
2044
2045	return ret;
2046}
2047
2048static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev,
2049					  struct stm32f7_i2c_dev *i2c_dev)
2050{
2051	struct device_node *np = pdev->dev.of_node;
2052	int ret;
2053
2054	i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp");
2055	if (IS_ERR(i2c_dev->regmap))
2056		/* Optional */
2057		return 0;
2058
2059	ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1,
2060					 &i2c_dev->fmp_sreg);
2061	if (ret)
2062		return ret;
2063
2064	i2c_dev->fmp_creg = i2c_dev->fmp_sreg +
2065			       i2c_dev->setup.fmp_clr_offset;
2066
2067	return of_property_read_u32_index(np, "st,syscfg-fmp", 2,
2068					  &i2c_dev->fmp_mask);
2069}
2070
2071static int stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
2072{
2073	struct i2c_adapter *adap = &i2c_dev->adap;
2074	void __iomem *base = i2c_dev->base;
2075	struct i2c_client *client;
2076
2077	client = i2c_new_slave_host_notify_device(adap);
2078	if (IS_ERR(client))
2079		return PTR_ERR(client);
2080
2081	i2c_dev->host_notify_client = client;
2082
2083	/* Enable SMBus Host address */
2084	stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN);
2085
2086	return 0;
2087}
2088
2089static void stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
2090{
2091	void __iomem *base = i2c_dev->base;
2092
2093	if (i2c_dev->host_notify_client) {
2094		/* Disable SMBus Host address */
2095		stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
2096				     STM32F7_I2C_CR1_SMBHEN);
2097		i2c_free_slave_host_notify_device(i2c_dev->host_notify_client);
2098	}
2099}
2100
2101static int stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
2102{
2103	struct stm32f7_i2c_alert *alert;
2104	struct i2c_adapter *adap = &i2c_dev->adap;
2105	struct device *dev = i2c_dev->dev;
2106	void __iomem *base = i2c_dev->base;
2107
2108	alert = devm_kzalloc(dev, sizeof(*alert), GFP_KERNEL);
2109	if (!alert)
2110		return -ENOMEM;
2111
2112	alert->ara = i2c_new_smbus_alert_device(adap, &alert->setup);
2113	if (IS_ERR(alert->ara))
2114		return PTR_ERR(alert->ara);
2115
2116	i2c_dev->alert = alert;
2117
2118	/* Enable SMBus Alert */
2119	stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN);
2120
2121	return 0;
2122}
2123
2124static void stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
2125{
2126	struct stm32f7_i2c_alert *alert = i2c_dev->alert;
2127	void __iomem *base = i2c_dev->base;
2128
2129	if (alert) {
2130		/* Disable SMBus Alert */
2131		stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
2132				     STM32F7_I2C_CR1_ALERTEN);
2133		i2c_unregister_device(alert->ara);
2134	}
2135}
2136
2137static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
2138{
2139	struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
2140
2141	u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
2142		   I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
2143		   I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
2144		   I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
2145		   I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC |
2146		   I2C_FUNC_SMBUS_I2C_BLOCK;
2147
2148	if (i2c_dev->smbus_mode)
2149		func |= I2C_FUNC_SMBUS_HOST_NOTIFY;
2150
2151	return func;
2152}
2153
2154static const struct i2c_algorithm stm32f7_i2c_algo = {
2155	.xfer = stm32f7_i2c_xfer,
2156	.xfer_atomic = stm32f7_i2c_xfer_atomic,
2157	.smbus_xfer = stm32f7_i2c_smbus_xfer,
2158	.functionality = stm32f7_i2c_func,
2159	.reg_slave = stm32f7_i2c_reg_slave,
2160	.unreg_slave = stm32f7_i2c_unreg_slave,
2161};
2162
2163static int stm32f7_i2c_probe(struct platform_device *pdev)
2164{
2165	struct stm32f7_i2c_dev *i2c_dev;
2166	const struct stm32f7_i2c_setup *setup;
2167	struct resource *res;
2168	struct i2c_adapter *adap;
2169	struct reset_control *rst;
2170	dma_addr_t phy_addr;
2171	int irq_error, irq_event, ret;
2172
2173	i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
2174	if (!i2c_dev)
2175		return -ENOMEM;
2176
2177	setup = of_device_get_match_data(&pdev->dev);
2178	if (!setup) {
2179		dev_err(&pdev->dev, "Can't get device data\n");
2180		return -ENODEV;
2181	}
2182	i2c_dev->setup = *setup;
2183
2184	i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2185	if (IS_ERR(i2c_dev->base))
2186		return PTR_ERR(i2c_dev->base);
2187	phy_addr = (dma_addr_t)res->start;
2188
2189	irq_event = platform_get_irq(pdev, 0);
2190	if (irq_event < 0)
2191		return irq_event;
2192
2193	i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node,
2194						    "wakeup-source");
2195
2196	i2c_dev->clk = devm_clk_get_enabled(&pdev->dev, NULL);
2197	if (IS_ERR(i2c_dev->clk))
2198		return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk),
2199				     "Failed to enable controller clock\n");
2200
2201	rst = devm_reset_control_get(&pdev->dev, NULL);
2202	if (IS_ERR(rst))
2203		return dev_err_probe(&pdev->dev, PTR_ERR(rst),
2204				     "Error: Missing reset ctrl\n");
2205
2206	reset_control_assert(rst);
2207	udelay(2);
2208	reset_control_deassert(rst);
2209
2210	i2c_dev->dev = &pdev->dev;
2211
2212	ret = devm_request_threaded_irq(&pdev->dev, irq_event,
2213					stm32f7_i2c_isr_event,
2214					stm32f7_i2c_isr_event_thread,
2215					IRQF_ONESHOT,
2216					pdev->name, i2c_dev);
2217	if (ret)
2218		return dev_err_probe(&pdev->dev, ret, "Failed to request irq event\n");
2219
2220	if (!i2c_dev->setup.single_it_line) {
2221		irq_error = platform_get_irq(pdev, 1);
2222		if (irq_error < 0)
2223			return irq_error;
2224
2225		ret = devm_request_threaded_irq(&pdev->dev, irq_error,
2226						NULL,
2227						stm32f7_i2c_isr_error_thread,
2228						IRQF_ONESHOT,
2229						pdev->name, i2c_dev);
2230		if (ret)
2231			return dev_err_probe(&pdev->dev, ret, "Failed to request irq error\n");
2232	}
2233
2234	ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
2235	if (ret)
2236		return ret;
2237
2238	/* Setup Fast mode plus if necessary */
2239	if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) {
2240		if (!i2c_dev->setup.fmp_cr1_bit) {
2241			ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);
2242			if (ret)
2243				return ret;
2244		}
2245
2246		ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2247		if (ret)
2248			return ret;
2249	}
2250
2251	adap = &i2c_dev->adap;
2252	i2c_set_adapdata(adap, i2c_dev);
2253	snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
2254		 &res->start);
2255	adap->owner = THIS_MODULE;
2256	adap->timeout = 2 * HZ;
2257	adap->retries = 3;
2258	adap->algo = &stm32f7_i2c_algo;
2259	adap->dev.parent = &pdev->dev;
2260	adap->dev.of_node = pdev->dev.of_node;
2261
2262	init_completion(&i2c_dev->complete);
2263
2264	/* Init DMA config if supported */
2265	i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
2266					     STM32F7_I2C_TXDR,
2267					     STM32F7_I2C_RXDR);
2268	if (IS_ERR(i2c_dev->dma)) {
2269		ret = PTR_ERR(i2c_dev->dma);
2270		/* DMA support is optional, only report other errors */
2271		if (ret != -ENODEV)
2272			goto fmp_clear;
2273		dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n");
2274		i2c_dev->dma = NULL;
2275	}
2276
2277	if (i2c_dev->wakeup_src) {
2278		device_set_wakeup_capable(i2c_dev->dev, true);
2279
2280		ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event);
2281		if (ret) {
2282			dev_err(i2c_dev->dev, "Failed to set wake up irq\n");
2283			goto clr_wakeup_capable;
2284		}
2285	}
2286
2287	platform_set_drvdata(pdev, i2c_dev);
2288
2289	pm_runtime_set_autosuspend_delay(i2c_dev->dev,
2290					 STM32F7_AUTOSUSPEND_DELAY);
2291	pm_runtime_use_autosuspend(i2c_dev->dev);
2292	pm_runtime_set_active(i2c_dev->dev);
2293	pm_runtime_enable(i2c_dev->dev);
2294
2295	pm_runtime_get_noresume(&pdev->dev);
2296
2297	stm32f7_i2c_hw_config(i2c_dev);
2298
2299	i2c_dev->smbus_mode = of_property_read_bool(pdev->dev.of_node, "smbus");
2300
2301	ret = i2c_add_adapter(adap);
2302	if (ret)
2303		goto pm_disable;
2304
2305	if (i2c_dev->smbus_mode) {
2306		ret = stm32f7_i2c_enable_smbus_host(i2c_dev);
2307		if (ret) {
2308			dev_err(i2c_dev->dev,
2309				"failed to enable SMBus Host-Notify protocol (%d)\n",
2310				ret);
2311			goto i2c_adapter_remove;
2312		}
2313	}
2314
2315	if (of_property_read_bool(pdev->dev.of_node, "smbus-alert")) {
2316		ret = stm32f7_i2c_enable_smbus_alert(i2c_dev);
2317		if (ret) {
2318			dev_err(i2c_dev->dev,
2319				"failed to enable SMBus alert protocol (%d)\n",
2320				ret);
2321			goto i2c_disable_smbus_host;
2322		}
2323	}
2324
2325	dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
2326
2327	pm_runtime_put_autosuspend(i2c_dev->dev);
2328
2329	return 0;
2330
2331i2c_disable_smbus_host:
2332	stm32f7_i2c_disable_smbus_host(i2c_dev);
2333
2334i2c_adapter_remove:
2335	i2c_del_adapter(adap);
2336
2337pm_disable:
2338	pm_runtime_put_noidle(i2c_dev->dev);
2339	pm_runtime_disable(i2c_dev->dev);
2340	pm_runtime_set_suspended(i2c_dev->dev);
2341	pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2342
2343	if (i2c_dev->wakeup_src)
2344		dev_pm_clear_wake_irq(i2c_dev->dev);
2345
2346clr_wakeup_capable:
2347	if (i2c_dev->wakeup_src)
2348		device_set_wakeup_capable(i2c_dev->dev, false);
2349
2350	if (i2c_dev->dma) {
2351		stm32_i2c_dma_free(i2c_dev->dma);
2352		i2c_dev->dma = NULL;
2353	}
2354
2355fmp_clear:
2356	stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2357
2358	return ret;
2359}
2360
2361static void stm32f7_i2c_remove(struct platform_device *pdev)
2362{
2363	struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
2364
2365	stm32f7_i2c_disable_smbus_alert(i2c_dev);
2366	stm32f7_i2c_disable_smbus_host(i2c_dev);
2367
2368	i2c_del_adapter(&i2c_dev->adap);
2369	pm_runtime_get_sync(i2c_dev->dev);
2370
2371	if (i2c_dev->wakeup_src) {
2372		dev_pm_clear_wake_irq(i2c_dev->dev);
2373		/*
2374		 * enforce that wakeup is disabled and that the device
2375		 * is marked as non wakeup capable
2376		 */
2377		device_init_wakeup(i2c_dev->dev, false);
2378	}
2379
2380	pm_runtime_put_noidle(i2c_dev->dev);
2381	pm_runtime_disable(i2c_dev->dev);
2382	pm_runtime_set_suspended(i2c_dev->dev);
2383	pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2384
2385	if (i2c_dev->dma) {
2386		stm32_i2c_dma_free(i2c_dev->dma);
2387		i2c_dev->dma = NULL;
2388	}
2389
2390	stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2391}
2392
2393static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev)
2394{
2395	struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2396
2397	if (!stm32f7_i2c_is_slave_registered(i2c_dev))
2398		clk_disable(i2c_dev->clk);
2399
2400	return 0;
2401}
2402
2403static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev)
2404{
2405	struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2406	int ret;
2407
2408	if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2409		ret = clk_enable(i2c_dev->clk);
2410		if (ret) {
2411			dev_err(dev, "failed to enable clock\n");
2412			return ret;
2413		}
2414	}
2415
2416	return 0;
2417}
2418
2419static int __maybe_unused stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev)
2420{
2421	int ret;
2422	struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2423
2424	ret = pm_runtime_resume_and_get(i2c_dev->dev);
2425	if (ret < 0)
2426		return ret;
2427
2428	backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2429	backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
2430	backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
2431	backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
2432	backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR);
2433	stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2434
2435	pm_runtime_put_sync(i2c_dev->dev);
2436
2437	return ret;
2438}
2439
2440static int __maybe_unused stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev)
2441{
2442	u32 cr1;
2443	int ret;
2444	struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2445
2446	ret = pm_runtime_resume_and_get(i2c_dev->dev);
2447	if (ret < 0)
2448		return ret;
2449
2450	cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2451	if (cr1 & STM32F7_I2C_CR1_PE)
2452		stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
2453				     STM32F7_I2C_CR1_PE);
2454
2455	writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR);
2456	writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE,
2457		       i2c_dev->base + STM32F7_I2C_CR1);
2458	if (backup_regs->cr1 & STM32F7_I2C_CR1_PE)
2459		stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
2460				     STM32F7_I2C_CR1_PE);
2461	writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);
2462	writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1);
2463	writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2);
2464	stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2465
2466	pm_runtime_put_sync(i2c_dev->dev);
2467
2468	return ret;
2469}
2470
2471static int __maybe_unused stm32f7_i2c_suspend(struct device *dev)
2472{
2473	struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2474	int ret;
2475
2476	i2c_mark_adapter_suspended(&i2c_dev->adap);
2477
2478	if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) {
2479		ret = stm32f7_i2c_regs_backup(i2c_dev);
2480		if (ret < 0) {
2481			i2c_mark_adapter_resumed(&i2c_dev->adap);
2482			return ret;
2483		}
2484
2485		pinctrl_pm_select_sleep_state(dev);
2486		pm_runtime_force_suspend(dev);
2487	}
2488
2489	return 0;
2490}
2491
2492static int __maybe_unused stm32f7_i2c_resume(struct device *dev)
2493{
2494	struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2495	int ret;
2496
2497	if (!device_may_wakeup(dev) && !device_wakeup_path(dev)) {
2498		ret = pm_runtime_force_resume(dev);
2499		if (ret < 0)
2500			return ret;
2501		pinctrl_pm_select_default_state(dev);
2502
2503		ret = stm32f7_i2c_regs_restore(i2c_dev);
2504		if (ret < 0)
2505			return ret;
2506	}
2507
2508	i2c_mark_adapter_resumed(&i2c_dev->adap);
2509
2510	return 0;
2511}
2512
2513static const struct dev_pm_ops stm32f7_i2c_pm_ops = {
2514	SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend,
2515			   stm32f7_i2c_runtime_resume, NULL)
2516	SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume)
2517};
2518
2519static const struct of_device_id stm32f7_i2c_match[] = {
2520	{ .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
2521	{ .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup},
2522	{ .compatible = "st,stm32mp13-i2c", .data = &stm32mp13_setup},
2523	{ .compatible = "st,stm32mp25-i2c", .data = &stm32mp25_setup},
2524	{},
2525};
2526MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
2527
2528static struct platform_driver stm32f7_i2c_driver = {
2529	.driver = {
2530		.name = "stm32f7-i2c",
2531		.of_match_table = stm32f7_i2c_match,
2532		.pm = &stm32f7_i2c_pm_ops,
2533	},
2534	.probe = stm32f7_i2c_probe,
2535	.remove = stm32f7_i2c_remove,
2536};
2537
2538module_platform_driver(stm32f7_i2c_driver);
2539
2540MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
2541MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
2542MODULE_LICENSE("GPL v2");