i2c-pnx.c

  1/*
  2 * Provides I2C support for Philips PNX010x/PNX4008 boards.
  3 *
  4 * Authors: Dennis Kovalev <dkovalev@ru.mvista.com>
  5 *	    Vitaly Wool <vwool@ru.mvista.com>
  6 *
  7 * 2004-2006 (c) MontaVista Software, Inc. This file is licensed under
  8 * the terms of the GNU General Public License version 2. This program
  9 * is licensed "as is" without any warranty of any kind, whether express
 10 * or implied.
 11 */
 12
 13#include <linux/module.h>
 14#include <linux/interrupt.h>
 15#include <linux/ioport.h>
 16#include <linux/delay.h>
 17#include <linux/i2c.h>
 18#include <linux/completion.h>
 19#include <linux/platform_device.h>
 20#include <linux/io.h>
 21#include <linux/err.h>
 22#include <linux/clk.h>
 23#include <linux/slab.h>
 24#include <linux/of.h>
 25
 26#define I2C_PNX_TIMEOUT_DEFAULT		10 /* msec */
 27#define I2C_PNX_SPEED_KHZ_DEFAULT	100
 28#define I2C_PNX_REGION_SIZE		0x100
 29
 30struct i2c_pnx_mif {
 31	int			ret;		/* Return value */
 32	int			mode;		/* Interface mode */
 33	struct completion	complete;	/* I/O completion */
 34	u8 *			buf;		/* Data buffer */
 35	int			len;		/* Length of data buffer */
 36	int			order;		/* RX Bytes to order via TX */
 37};
 38
 39struct i2c_pnx_algo_data {
 40	void __iomem		*ioaddr;
 41	struct i2c_pnx_mif	mif;
 42	int			last;
 43	struct clk		*clk;
 44	struct i2c_adapter	adapter;
 45	int			irq;
 46	u32			timeout;
 47};
 48
 49enum {
 50	mstatus_tdi = 0x00000001,
 51	mstatus_afi = 0x00000002,
 52	mstatus_nai = 0x00000004,
 53	mstatus_drmi = 0x00000008,
 54	mstatus_active = 0x00000020,
 55	mstatus_scl = 0x00000040,
 56	mstatus_sda = 0x00000080,
 57	mstatus_rff = 0x00000100,
 58	mstatus_rfe = 0x00000200,
 59	mstatus_tff = 0x00000400,
 60	mstatus_tfe = 0x00000800,
 61};
 62
 63enum {
 64	mcntrl_tdie = 0x00000001,
 65	mcntrl_afie = 0x00000002,
 66	mcntrl_naie = 0x00000004,
 67	mcntrl_drmie = 0x00000008,
 68	mcntrl_drsie = 0x00000010,
 69	mcntrl_rffie = 0x00000020,
 70	mcntrl_daie = 0x00000040,
 71	mcntrl_tffie = 0x00000080,
 72	mcntrl_reset = 0x00000100,
 73	mcntrl_cdbmode = 0x00000400,
 74};
 75
 76enum {
 77	rw_bit = 1 << 0,
 78	start_bit = 1 << 8,
 79	stop_bit = 1 << 9,
 80};
 81
 82#define I2C_REG_RX(a)	((a)->ioaddr)		/* Rx FIFO reg (RO) */
 83#define I2C_REG_TX(a)	((a)->ioaddr)		/* Tx FIFO reg (WO) */
 84#define I2C_REG_STS(a)	((a)->ioaddr + 0x04)	/* Status reg (RO) */
 85#define I2C_REG_CTL(a)	((a)->ioaddr + 0x08)	/* Ctl reg */
 86#define I2C_REG_CKL(a)	((a)->ioaddr + 0x0c)	/* Clock divider low */
 87#define I2C_REG_CKH(a)	((a)->ioaddr + 0x10)	/* Clock divider high */
 88#define I2C_REG_ADR(a)	((a)->ioaddr + 0x14)	/* I2C address */
 89#define I2C_REG_RFL(a)	((a)->ioaddr + 0x18)	/* Rx FIFO level (RO) */
 90#define I2C_REG_TFL(a)	((a)->ioaddr + 0x1c)	/* Tx FIFO level (RO) */
 91#define I2C_REG_RXB(a)	((a)->ioaddr + 0x20)	/* Num of bytes Rx-ed (RO) */
 92#define I2C_REG_TXB(a)	((a)->ioaddr + 0x24)	/* Num of bytes Tx-ed (RO) */
 93#define I2C_REG_TXS(a)	((a)->ioaddr + 0x28)	/* Tx slave FIFO (RO) */
 94#define I2C_REG_STFL(a)	((a)->ioaddr + 0x2c)	/* Tx slave FIFO level (RO) */
 95
 96static inline int wait_timeout(struct i2c_pnx_algo_data *data)
 97{
 98	long timeout = jiffies_to_msecs(data->timeout);
 99	while (timeout > 0 &&
100			(ioread32(I2C_REG_STS(data)) & mstatus_active)) {
101		mdelay(1);
102		timeout--;
103	}
104	return (timeout <= 0);
105}
106
107static inline int wait_reset(struct i2c_pnx_algo_data *data)
108{
109	long timeout = jiffies_to_msecs(data->timeout);
110	while (timeout > 0 &&
111			(ioread32(I2C_REG_CTL(data)) & mcntrl_reset)) {
112		mdelay(1);
113		timeout--;
114	}
115	return (timeout <= 0);
116}
117
118/**
119 * i2c_pnx_start - start a device
120 * @slave_addr:		slave address
121 * @alg_data:		pointer to local driver data structure
122 *
123 * Generate a START signal in the desired mode.
124 */
125static int i2c_pnx_start(unsigned char slave_addr,
126	struct i2c_pnx_algo_data *alg_data)
127{
128	dev_dbg(&alg_data->adapter.dev, "%s(): addr 0x%x mode %d\n", __func__,
129		slave_addr, alg_data->mif.mode);
130
131	/* Check for 7 bit slave addresses only */
132	if (slave_addr & ~0x7f) {
133		dev_err(&alg_data->adapter.dev,
134			"%s: Invalid slave address %x. Only 7-bit addresses are supported\n",
135			alg_data->adapter.name, slave_addr);
136		return -EINVAL;
137	}
138
139	/* First, make sure bus is idle */
140	if (wait_timeout(alg_data)) {
141		/* Somebody else is monopolizing the bus */
142		dev_err(&alg_data->adapter.dev,
143			"%s: Bus busy. Slave addr = %02x, cntrl = %x, stat = %x\n",
144			alg_data->adapter.name, slave_addr,
145			ioread32(I2C_REG_CTL(alg_data)),
146			ioread32(I2C_REG_STS(alg_data)));
147		return -EBUSY;
148	} else if (ioread32(I2C_REG_STS(alg_data)) & mstatus_afi) {
149		/* Sorry, we lost the bus */
150		dev_err(&alg_data->adapter.dev,
151		        "%s: Arbitration failure. Slave addr = %02x\n",
152			alg_data->adapter.name, slave_addr);
153		return -EIO;
154	}
155
156	/*
157	 * OK, I2C is enabled and we have the bus.
158	 * Clear the current TDI and AFI status flags.
159	 */
160	iowrite32(ioread32(I2C_REG_STS(alg_data)) | mstatus_tdi | mstatus_afi,
161		  I2C_REG_STS(alg_data));
162
163	dev_dbg(&alg_data->adapter.dev, "%s(): sending %#x\n", __func__,
164		(slave_addr << 1) | start_bit | alg_data->mif.mode);
165
166	/* Write the slave address, START bit and R/W bit */
167	iowrite32((slave_addr << 1) | start_bit | alg_data->mif.mode,
168		  I2C_REG_TX(alg_data));
169
170	dev_dbg(&alg_data->adapter.dev, "%s(): exit\n", __func__);
171
172	return 0;
173}
174
175/**
176 * i2c_pnx_stop - stop a device
177 * @alg_data:		pointer to local driver data structure
178 *
179 * Generate a STOP signal to terminate the master transaction.
180 */
181static void i2c_pnx_stop(struct i2c_pnx_algo_data *alg_data)
182{
183	/* Only 1 msec max timeout due to interrupt context */
184	long timeout = 1000;
185
186	dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
187		__func__, ioread32(I2C_REG_STS(alg_data)));
188
189	/* Write a STOP bit to TX FIFO */
190	iowrite32(0xff | stop_bit, I2C_REG_TX(alg_data));
191
192	/* Wait until the STOP is seen. */
193	while (timeout > 0 &&
194	       (ioread32(I2C_REG_STS(alg_data)) & mstatus_active)) {
195		/* may be called from interrupt context */
196		udelay(1);
197		timeout--;
198	}
199
200	dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
201		__func__, ioread32(I2C_REG_STS(alg_data)));
202}
203
204/**
205 * i2c_pnx_master_xmit - transmit data to slave
206 * @alg_data:		pointer to local driver data structure
207 *
208 * Sends one byte of data to the slave
209 */
210static int i2c_pnx_master_xmit(struct i2c_pnx_algo_data *alg_data)
211{
212	u32 val;
213
214	dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
215		__func__, ioread32(I2C_REG_STS(alg_data)));
216
217	if (alg_data->mif.len > 0) {
218		/* We still have something to talk about... */
219		val = *alg_data->mif.buf++;
220
221		if (alg_data->mif.len == 1)
222			val |= stop_bit;
223
224		alg_data->mif.len--;
225		iowrite32(val, I2C_REG_TX(alg_data));
226
227		dev_dbg(&alg_data->adapter.dev, "%s(): xmit %#x [%d]\n",
228			__func__, val, alg_data->mif.len + 1);
229
230		if (alg_data->mif.len == 0) {
231			if (alg_data->last) {
232				/* Wait until the STOP is seen. */
233				if (wait_timeout(alg_data))
234					dev_err(&alg_data->adapter.dev,
235						"The bus is still active after timeout\n");
236			}
237			/* Disable master interrupts */
238			iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
239				~(mcntrl_afie | mcntrl_naie | mcntrl_drmie),
240				  I2C_REG_CTL(alg_data));
241
242			dev_dbg(&alg_data->adapter.dev,
243				"%s(): Waking up xfer routine.\n",
244				__func__);
245
246			complete(&alg_data->mif.complete);
247		}
248	} else if (alg_data->mif.len == 0) {
249		/* zero-sized transfer */
250		i2c_pnx_stop(alg_data);
251
252		/* Disable master interrupts. */
253		iowrite32(ioread32(I2C_REG_CTL(alg_data)) &
254			~(mcntrl_afie | mcntrl_naie | mcntrl_drmie),
255			  I2C_REG_CTL(alg_data));
256
257		dev_dbg(&alg_data->adapter.dev,
258			"%s(): Waking up xfer routine after zero-xfer.\n",
259			__func__);
260
261		complete(&alg_data->mif.complete);
262	}
263
264	dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
265		__func__, ioread32(I2C_REG_STS(alg_data)));
266
267	return 0;
268}
269
270/**
271 * i2c_pnx_master_rcv - receive data from slave
272 * @alg_data:		pointer to local driver data structure
273 *
274 * Reads one byte data from the slave
275 */
276static int i2c_pnx_master_rcv(struct i2c_pnx_algo_data *alg_data)
277{
278	unsigned int val = 0;
279	u32 ctl = 0;
280
281	dev_dbg(&alg_data->adapter.dev, "%s(): entering: stat = %04x.\n",
282		__func__, ioread32(I2C_REG_STS(alg_data)));
283
284	/* Check, whether there is already data,
285	 * or we didn't 'ask' for it yet.
286	 */
287	if (ioread32(I2C_REG_STS(alg_data)) & mstatus_rfe) {
288		/* 'Asking' is done asynchronously, e.g. dummy TX of several
289		 * bytes is done before the first actual RX arrives in FIFO.
290		 * Therefore, ordered bytes (via TX) are counted separately.
291		 */
292		if (alg_data->mif.order) {
293			dev_dbg(&alg_data->adapter.dev,
294				"%s(): Write dummy data to fill Rx-fifo...\n",
295				__func__);
296
297			if (alg_data->mif.order == 1) {
298				/* Last byte, do not acknowledge next rcv. */
299				val |= stop_bit;
300
301				/*
302				 * Enable interrupt RFDAIE (data in Rx fifo),
303				 * and disable DRMIE (need data for Tx)
304				 */
305				ctl = ioread32(I2C_REG_CTL(alg_data));
306				ctl |= mcntrl_rffie | mcntrl_daie;
307				ctl &= ~mcntrl_drmie;
308				iowrite32(ctl, I2C_REG_CTL(alg_data));
309			}
310
311			/*
312			 * Now we'll 'ask' for data:
313			 * For each byte we want to receive, we must
314			 * write a (dummy) byte to the Tx-FIFO.
315			 */
316			iowrite32(val, I2C_REG_TX(alg_data));
317			alg_data->mif.order--;
318		}
319		return 0;
320	}
321
322	/* Handle data. */
323	if (alg_data->mif.len > 0) {
324		val = ioread32(I2C_REG_RX(alg_data));
325		*alg_data->mif.buf++ = (u8) (val & 0xff);
326		dev_dbg(&alg_data->adapter.dev, "%s(): rcv 0x%x [%d]\n",
327			__func__, val, alg_data->mif.len);
328
329		alg_data->mif.len--;
330		if (alg_data->mif.len == 0) {
331			if (alg_data->last)
332				/* Wait until the STOP is seen. */
333				if (wait_timeout(alg_data))
334					dev_err(&alg_data->adapter.dev,
335						"The bus is still active after timeout\n");
336
337			/* Disable master interrupts */
338			ctl = ioread32(I2C_REG_CTL(alg_data));
339			ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
340				 mcntrl_drmie | mcntrl_daie);
341			iowrite32(ctl, I2C_REG_CTL(alg_data));
342
343			complete(&alg_data->mif.complete);
344		}
345	}
346
347	dev_dbg(&alg_data->adapter.dev, "%s(): exiting: stat = %04x.\n",
348		__func__, ioread32(I2C_REG_STS(alg_data)));
349
350	return 0;
351}
352
353static irqreturn_t i2c_pnx_interrupt(int irq, void *dev_id)
354{
355	struct i2c_pnx_algo_data *alg_data = dev_id;
356	u32 stat, ctl;
357
358	dev_dbg(&alg_data->adapter.dev,
359		"%s(): mstat = %x mctrl = %x, mode = %d\n",
360		__func__,
361		ioread32(I2C_REG_STS(alg_data)),
362		ioread32(I2C_REG_CTL(alg_data)),
363		alg_data->mif.mode);
364	stat = ioread32(I2C_REG_STS(alg_data));
365
366	/* let's see what kind of event this is */
367	if (stat & mstatus_afi) {
368		/* We lost arbitration in the midst of a transfer */
369		alg_data->mif.ret = -EIO;
370
371		/* Disable master interrupts. */
372		ctl = ioread32(I2C_REG_CTL(alg_data));
373		ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
374			 mcntrl_drmie);
375		iowrite32(ctl, I2C_REG_CTL(alg_data));
376
377		complete(&alg_data->mif.complete);
378	} else if (stat & mstatus_nai) {
379		/* Slave did not acknowledge, generate a STOP */
380		dev_dbg(&alg_data->adapter.dev,
381			"%s(): Slave did not acknowledge, generating a STOP.\n",
382			__func__);
383		i2c_pnx_stop(alg_data);
384
385		/* Disable master interrupts. */
386		ctl = ioread32(I2C_REG_CTL(alg_data));
387		ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie |
388			 mcntrl_drmie);
389		iowrite32(ctl, I2C_REG_CTL(alg_data));
390
391		/* Our return value. */
392		alg_data->mif.ret = -EIO;
393
394		complete(&alg_data->mif.complete);
395	} else {
396		/*
397		 * Two options:
398		 * - Master Tx needs data.
399		 * - There is data in the Rx-fifo
400		 * The latter is only the case if we have requested for data,
401		 * via a dummy write. (See 'i2c_pnx_master_rcv'.)
402		 * We therefore check, as a sanity check, whether that interrupt
403		 * has been enabled.
404		 */
405		if ((stat & mstatus_drmi) || !(stat & mstatus_rfe)) {
406			if (alg_data->mif.mode == I2C_SMBUS_WRITE) {
407				i2c_pnx_master_xmit(alg_data);
408			} else if (alg_data->mif.mode == I2C_SMBUS_READ) {
409				i2c_pnx_master_rcv(alg_data);
410			}
411		}
412	}
413
414	/* Clear TDI and AFI bits */
415	stat = ioread32(I2C_REG_STS(alg_data));
416	iowrite32(stat | mstatus_tdi | mstatus_afi, I2C_REG_STS(alg_data));
417
418	dev_dbg(&alg_data->adapter.dev,
419		"%s(): exiting, stat = %x ctrl = %x.\n",
420		 __func__, ioread32(I2C_REG_STS(alg_data)),
421		 ioread32(I2C_REG_CTL(alg_data)));
422
423	return IRQ_HANDLED;
424}
425
426static void i2c_pnx_timeout(struct i2c_pnx_algo_data *alg_data)
427{
428	u32 ctl;
429
430	dev_err(&alg_data->adapter.dev,
431		"Master timed out. stat = %04x, cntrl = %04x. Resetting master...\n",
432		ioread32(I2C_REG_STS(alg_data)),
433		ioread32(I2C_REG_CTL(alg_data)));
434
435	/* Reset master and disable interrupts */
436	ctl = ioread32(I2C_REG_CTL(alg_data));
437	ctl &= ~(mcntrl_afie | mcntrl_naie | mcntrl_rffie | mcntrl_drmie);
438	iowrite32(ctl, I2C_REG_CTL(alg_data));
439
440	ctl |= mcntrl_reset;
441	iowrite32(ctl, I2C_REG_CTL(alg_data));
442	wait_reset(alg_data);
443	alg_data->mif.ret = -EIO;
444}
445
446static inline void bus_reset_if_active(struct i2c_pnx_algo_data *alg_data)
447{
448	u32 stat;
449
450	if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_active) {
451		dev_err(&alg_data->adapter.dev,
452			"%s: Bus is still active after xfer. Reset it...\n",
453			alg_data->adapter.name);
454		iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
455			  I2C_REG_CTL(alg_data));
456		wait_reset(alg_data);
457	} else if (!(stat & mstatus_rfe) || !(stat & mstatus_tfe)) {
458		/* If there is data in the fifo's after transfer,
459		 * flush fifo's by reset.
460		 */
461		iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
462			  I2C_REG_CTL(alg_data));
463		wait_reset(alg_data);
464	} else if (stat & mstatus_nai) {
465		iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_reset,
466			  I2C_REG_CTL(alg_data));
467		wait_reset(alg_data);
468	}
469}
470
471/**
472 * i2c_pnx_xfer - generic transfer entry point
473 * @adap:		pointer to I2C adapter structure
474 * @msgs:		array of messages
475 * @num:		number of messages
476 *
477 * Initiates the transfer
478 */
479static int
480i2c_pnx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
481{
482	struct i2c_msg *pmsg;
483	int rc = 0, completed = 0, i;
484	struct i2c_pnx_algo_data *alg_data = adap->algo_data;
485	unsigned long time_left;
486	u32 stat;
487
488	dev_dbg(&alg_data->adapter.dev,
489		"%s(): entering: %d messages, stat = %04x.\n",
490		__func__, num, ioread32(I2C_REG_STS(alg_data)));
491
492	bus_reset_if_active(alg_data);
493
494	/* Process transactions in a loop. */
495	for (i = 0; rc >= 0 && i < num; i++) {
496		u8 addr;
497
498		pmsg = &msgs[i];
499		addr = pmsg->addr;
500
501		if (pmsg->flags & I2C_M_TEN) {
502			dev_err(&alg_data->adapter.dev,
503				"%s: 10 bits addr not supported!\n",
504				alg_data->adapter.name);
505			rc = -EINVAL;
506			break;
507		}
508
509		alg_data->mif.buf = pmsg->buf;
510		alg_data->mif.len = pmsg->len;
511		alg_data->mif.order = pmsg->len;
512		alg_data->mif.mode = (pmsg->flags & I2C_M_RD) ?
513			I2C_SMBUS_READ : I2C_SMBUS_WRITE;
514		alg_data->mif.ret = 0;
515		alg_data->last = (i == num - 1);
516
517		dev_dbg(&alg_data->adapter.dev, "%s(): mode %d, %d bytes\n",
518			__func__, alg_data->mif.mode, alg_data->mif.len);
519
520
521		/* initialize the completion var */
522		init_completion(&alg_data->mif.complete);
523
524		/* Enable master interrupt */
525		iowrite32(ioread32(I2C_REG_CTL(alg_data)) | mcntrl_afie |
526				mcntrl_naie | mcntrl_drmie,
527			  I2C_REG_CTL(alg_data));
528
529		/* Put start-code and slave-address on the bus. */
530		rc = i2c_pnx_start(addr, alg_data);
531		if (rc < 0)
532			break;
533
534		/* Wait for completion */
535		time_left = wait_for_completion_timeout(&alg_data->mif.complete,
536							alg_data->timeout);
537		if (time_left == 0)
538			i2c_pnx_timeout(alg_data);
539
540		if (!(rc = alg_data->mif.ret))
541			completed++;
542		dev_dbg(&alg_data->adapter.dev,
543			"%s(): Complete, return code = %d.\n",
544			__func__, rc);
545
546		/* Clear TDI and AFI bits in case they are set. */
547		if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_tdi) {
548			dev_dbg(&alg_data->adapter.dev,
549				"%s: TDI still set... clearing now.\n",
550				alg_data->adapter.name);
551			iowrite32(stat, I2C_REG_STS(alg_data));
552		}
553		if ((stat = ioread32(I2C_REG_STS(alg_data))) & mstatus_afi) {
554			dev_dbg(&alg_data->adapter.dev,
555				"%s: AFI still set... clearing now.\n",
556				alg_data->adapter.name);
557			iowrite32(stat, I2C_REG_STS(alg_data));
558		}
559	}
560
561	bus_reset_if_active(alg_data);
562
563	/* Cleanup to be sure... */
564	alg_data->mif.buf = NULL;
565	alg_data->mif.len = 0;
566	alg_data->mif.order = 0;
567
568	dev_dbg(&alg_data->adapter.dev, "%s(): exiting, stat = %x\n",
569		__func__, ioread32(I2C_REG_STS(alg_data)));
570
571	if (completed != num)
572		return ((rc < 0) ? rc : -EREMOTEIO);
573
574	return num;
575}
576
577static u32 i2c_pnx_func(struct i2c_adapter *adapter)
578{
579	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
580}
581
582static const struct i2c_algorithm pnx_algorithm = {
583	.xfer = i2c_pnx_xfer,
584	.functionality = i2c_pnx_func,
585};
586
587static int i2c_pnx_controller_suspend(struct device *dev)
588{
589	struct i2c_pnx_algo_data *alg_data = dev_get_drvdata(dev);
590
591	clk_disable_unprepare(alg_data->clk);
592
593	return 0;
594}
595
596static int i2c_pnx_controller_resume(struct device *dev)
597{
598	struct i2c_pnx_algo_data *alg_data = dev_get_drvdata(dev);
599
600	return clk_prepare_enable(alg_data->clk);
601}
602
603static DEFINE_SIMPLE_DEV_PM_OPS(i2c_pnx_pm,
604				i2c_pnx_controller_suspend,
605				i2c_pnx_controller_resume);
606
607static int i2c_pnx_probe(struct platform_device *pdev)
608{
609	unsigned long tmp;
610	int ret = 0;
611	struct i2c_pnx_algo_data *alg_data;
612	unsigned long freq;
613	struct resource *res;
614	u32 speed = I2C_PNX_SPEED_KHZ_DEFAULT * 1000;
615
616	alg_data = devm_kzalloc(&pdev->dev, sizeof(*alg_data), GFP_KERNEL);
617	if (!alg_data)
618		return -ENOMEM;
619
620	platform_set_drvdata(pdev, alg_data);
621
622	alg_data->adapter.dev.parent = &pdev->dev;
623	alg_data->adapter.algo = &pnx_algorithm;
624	alg_data->adapter.algo_data = alg_data;
625	alg_data->adapter.nr = pdev->id;
626
627	alg_data->timeout = msecs_to_jiffies(I2C_PNX_TIMEOUT_DEFAULT);
628	if (alg_data->timeout <= 1)
629		alg_data->timeout = 2;
630
631#ifdef CONFIG_OF
632	alg_data->adapter.dev.of_node = of_node_get(pdev->dev.of_node);
633	if (pdev->dev.of_node) {
634		of_property_read_u32(pdev->dev.of_node, "clock-frequency",
635				     &speed);
636		/*
637		 * At this point, it is planned to add an OF timeout property.
638		 * As soon as there is a consensus about how to call and handle
639		 * this, sth. like the following can be put here:
640		 *
641		 * of_property_read_u32(pdev->dev.of_node, "timeout",
642		 *                      &alg_data->timeout);
643		 */
644	}
645#endif
646	alg_data->clk = devm_clk_get(&pdev->dev, NULL);
647	if (IS_ERR(alg_data->clk))
648		return PTR_ERR(alg_data->clk);
649
650	snprintf(alg_data->adapter.name, sizeof(alg_data->adapter.name),
651		 "%s", pdev->name);
652
653	/* Register I/O resource */
654	alg_data->ioaddr = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
655	if (IS_ERR(alg_data->ioaddr))
656		return PTR_ERR(alg_data->ioaddr);
657
658	ret = clk_prepare_enable(alg_data->clk);
659	if (ret)
660		return ret;
661
662	freq = clk_get_rate(alg_data->clk);
663
664	/*
665	 * Clock Divisor High This value is the number of system clocks
666	 * the serial clock (SCL) will be high.
667	 * For example, if the system clock period is 50 ns and the maximum
668	 * desired serial period is 10000 ns (100 kHz), then CLKHI would be
669	 * set to 0.5*(f_sys/f_i2c)-2=0.5*(20e6/100e3)-2=98. The actual value
670	 * programmed into CLKHI will vary from this slightly due to
671	 * variations in the output pad's rise and fall times as well as
672	 * the deglitching filter length.
673	 */
674
675	tmp = (freq / speed) / 2 - 2;
676	if (tmp > 0x3FF)
677		tmp = 0x3FF;
678	iowrite32(tmp, I2C_REG_CKH(alg_data));
679	iowrite32(tmp, I2C_REG_CKL(alg_data));
680
681	iowrite32(mcntrl_reset, I2C_REG_CTL(alg_data));
682	if (wait_reset(alg_data)) {
683		ret = -ENODEV;
684		goto out_clock;
685	}
686	init_completion(&alg_data->mif.complete);
687
688	alg_data->irq = platform_get_irq(pdev, 0);
689	if (alg_data->irq < 0) {
690		ret = alg_data->irq;
691		goto out_clock;
692	}
693	ret = devm_request_irq(&pdev->dev, alg_data->irq, i2c_pnx_interrupt,
694			       0, pdev->name, alg_data);
695	if (ret)
696		goto out_clock;
697
698	/* Register this adapter with the I2C subsystem */
699	ret = i2c_add_numbered_adapter(&alg_data->adapter);
700	if (ret < 0)
701		goto out_clock;
702
703	dev_dbg(&pdev->dev, "%s: Master at %pap, irq %d.\n",
704		alg_data->adapter.name, &res->start, alg_data->irq);
705
706	return 0;
707
708out_clock:
709	clk_disable_unprepare(alg_data->clk);
710	return ret;
711}
712
713static void i2c_pnx_remove(struct platform_device *pdev)
714{
715	struct i2c_pnx_algo_data *alg_data = platform_get_drvdata(pdev);
716
717	i2c_del_adapter(&alg_data->adapter);
718	clk_disable_unprepare(alg_data->clk);
719}
720
721#ifdef CONFIG_OF
722static const struct of_device_id i2c_pnx_of_match[] = {
723	{ .compatible = "nxp,pnx-i2c" },
724	{ }
725};
726MODULE_DEVICE_TABLE(of, i2c_pnx_of_match);
727#endif
728
729static struct platform_driver i2c_pnx_driver = {
730	.driver = {
731		.name = "pnx-i2c",
732		.of_match_table = of_match_ptr(i2c_pnx_of_match),
733		.pm = pm_sleep_ptr(&i2c_pnx_pm),
734	},
735	.probe = i2c_pnx_probe,
736	.remove = i2c_pnx_remove,
737};
738
739static int __init i2c_adap_pnx_init(void)
740{
741	return platform_driver_register(&i2c_pnx_driver);
742}
743
744static void __exit i2c_adap_pnx_exit(void)
745{
746	platform_driver_unregister(&i2c_pnx_driver);
747}
748
749MODULE_AUTHOR("Vitaly Wool");
750MODULE_AUTHOR("Dennis Kovalev <source@mvista.com>");
751MODULE_DESCRIPTION("I2C driver for Philips IP3204-based I2C busses");
752MODULE_LICENSE("GPL");
753MODULE_ALIAS("platform:pnx-i2c");
754
755/* We need to make sure I2C is initialized before USB */
756subsys_initcall(i2c_adap_pnx_init);
757module_exit(i2c_adap_pnx_exit);