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i2c-piix4.c
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linux-6.19.14/drivers/i2c/busses/i2c-piix4.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and 4 Philip Edelbrock <phil@netroedge.com> 5 6*/ 7 8/* 9 Supports: 10 Intel PIIX4, 440MX 11 Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100 12 ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800 13 AMD Hudson-2, ML, CZ 14 Hygon CZ 15 SMSC Victory66 16 17 Note: we assume there can only be one device, with one or more 18 SMBus interfaces. 19 The device can register multiple i2c_adapters (up to PIIX4_MAX_ADAPTERS). 20 For devices supporting multiple ports the i2c_adapter should provide 21 an i2c_algorithm to access them. 22*/ 23 24#include <linux/module.h> 25#include <linux/moduleparam.h> 26#include <linux/pci.h> 27#include <linux/kernel.h> 28#include <linux/delay.h> 29#include <linux/stddef.h> 30#include <linux/ioport.h> 31#include <linux/i2c.h> 32#include <linux/i2c-smbus.h> 33#include <linux/slab.h> 34#include <linux/dmi.h> 35#include <linux/acpi.h> 36#include <linux/io.h> 37#include <linux/platform_data/x86/amd-fch.h> 38 39#include "i2c-piix4.h" 40 41/* count for request_region */ 42#define SMBIOSIZE 9 43 44/* PCI Address Constants */ 45#define SMBBA 0x090 46#define SMBHSTCFG 0x0D2 47#define SMBSLVC 0x0D3 48#define SMBSHDW1 0x0D4 49#define SMBSHDW2 0x0D5 50#define SMBREV 0x0D6 51 52/* Other settings */ 53#define MAX_TIMEOUT 500 54#define ENABLE_INT9 0 55 56/* PIIX4 constants */ 57#define PIIX4_QUICK 0x00 58#define PIIX4_BYTE 0x04 59#define PIIX4_BYTE_DATA 0x08 60#define PIIX4_WORD_DATA 0x0C 61 62/* Multi-port constants */ 63#define PIIX4_MAX_ADAPTERS 4 64#define HUDSON2_MAIN_PORTS 2 /* HUDSON2, KERNCZ reserves ports 3, 4 */ 65 66/* SB800 constants */ 67#define SB800_PIIX4_SMB_IDX 0xcd6 68#define SB800_PIIX4_SMB_MAP_SIZE 2 69 70#define KERNCZ_IMC_IDX 0x3e 71#define KERNCZ_IMC_DATA 0x3f 72 73/* 74 * SB800 port is selected by bits 2:1 of the smb_en register (0x2c) 75 * or the smb_sel register (0x2e), depending on bit 0 of register 0x2f. 76 * Hudson-2/Bolton port is always selected by bits 2:1 of register 0x2f. 77 */ 78#define SB800_PIIX4_PORT_IDX 0x2c 79#define SB800_PIIX4_PORT_IDX_ALT 0x2e 80#define SB800_PIIX4_PORT_IDX_SEL 0x2f 81#define SB800_PIIX4_PORT_IDX_MASK 0x06 82#define SB800_PIIX4_PORT_IDX_SHIFT 1 83 84/* SmBus0Sel is at bit 20:19 of PMx00 DecodeEn */ 85#define SB800_PIIX4_PORT_IDX_KERNCZ (FCH_PM_DECODEEN + 0x02) 86#define SB800_PIIX4_PORT_IDX_MASK_KERNCZ (FCH_PM_DECODEEN_SMBUS0SEL >> 16) 87#define SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ 3 88 89#define SB800_PIIX4_FCH_PM_SIZE 8 90#define SB800_ASF_ACPI_PATH "\\_SB.ASFC" 91 92/* insmod parameters */ 93 94/* If force is set to anything different from 0, we forcibly enable the 95 PIIX4. DANGEROUS! */ 96static int force; 97module_param (force, int, 0); 98MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!"); 99 100/* If force_addr is set to anything different from 0, we forcibly enable 101 the PIIX4 at the given address. VERY DANGEROUS! */ 102static int force_addr; 103module_param_hw(force_addr, int, ioport, 0); 104MODULE_PARM_DESC(force_addr, 105 "Forcibly enable the PIIX4 at the given address. " 106 "EXTREMELY DANGEROUS!"); 107 108static int srvrworks_csb5_delay; 109static struct pci_driver piix4_driver; 110 111static const struct dmi_system_id piix4_dmi_blacklist[] = { 112 { 113 .ident = "Sapphire AM2RD790", 114 .matches = { 115 DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."), 116 DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"), 117 }, 118 }, 119 { 120 .ident = "DFI Lanparty UT 790FX", 121 .matches = { 122 DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."), 123 DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"), 124 }, 125 }, 126 { } 127}; 128 129/* The IBM entry is in a separate table because we only check it 130 on Intel-based systems */ 131static const struct dmi_system_id piix4_dmi_ibm[] = { 132 { 133 .ident = "IBM", 134 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), }, 135 }, 136 { } 137}; 138 139/* 140 * SB800 globals 141 */ 142static u8 piix4_port_sel_sb800; 143static u8 piix4_port_mask_sb800; 144static u8 piix4_port_shift_sb800; 145static const char *piix4_main_port_names_sb800[PIIX4_MAX_ADAPTERS] = { 146 " port 0", " port 2", " port 3", " port 4" 147}; 148static const char *piix4_aux_port_name_sb800 = " port 1"; 149 150struct i2c_piix4_adapdata { 151 unsigned short smba; 152 153 /* SB800 */ 154 bool sb800_main; 155 bool notify_imc; 156 u8 port; /* Port number, shifted */ 157 struct sb800_mmio_cfg mmio_cfg; 158}; 159 160int piix4_sb800_region_request(struct device *dev, struct sb800_mmio_cfg *mmio_cfg) 161{ 162 if (mmio_cfg->use_mmio) { 163 void __iomem *addr; 164 165 if (!request_mem_region_muxed(FCH_PM_BASE, 166 SB800_PIIX4_FCH_PM_SIZE, 167 "sb800_piix4_smb")) { 168 dev_err(dev, 169 "SMBus base address memory region 0x%x already in use.\n", 170 FCH_PM_BASE); 171 return -EBUSY; 172 } 173 174 addr = ioremap(FCH_PM_BASE, 175 SB800_PIIX4_FCH_PM_SIZE); 176 if (!addr) { 177 release_mem_region(FCH_PM_BASE, 178 SB800_PIIX4_FCH_PM_SIZE); 179 dev_err(dev, "SMBus base address mapping failed.\n"); 180 return -ENOMEM; 181 } 182 183 mmio_cfg->addr = addr; 184 185 return 0; 186 } 187 188 if (!request_muxed_region(SB800_PIIX4_SMB_IDX, SB800_PIIX4_SMB_MAP_SIZE, 189 "sb800_piix4_smb")) { 190 dev_err(dev, 191 "SMBus base address index region 0x%x already in use.\n", 192 SB800_PIIX4_SMB_IDX); 193 return -EBUSY; 194 } 195 196 return 0; 197} 198EXPORT_SYMBOL_NS_GPL(piix4_sb800_region_request, "PIIX4_SMBUS"); 199 200void piix4_sb800_region_release(struct device *dev, struct sb800_mmio_cfg *mmio_cfg) 201{ 202 if (mmio_cfg->use_mmio) { 203 iounmap(mmio_cfg->addr); 204 release_mem_region(FCH_PM_BASE, 205 SB800_PIIX4_FCH_PM_SIZE); 206 return; 207 } 208 209 release_region(SB800_PIIX4_SMB_IDX, SB800_PIIX4_SMB_MAP_SIZE); 210} 211EXPORT_SYMBOL_NS_GPL(piix4_sb800_region_release, "PIIX4_SMBUS"); 212 213static bool piix4_sb800_use_mmio(struct pci_dev *PIIX4_dev) 214{ 215 /* 216 * cd6h/cd7h port I/O accesses can be disabled on AMD processors 217 * w/ SMBus PCI revision ID 0x51 or greater. MMIO is supported on 218 * the same processors and is the recommended access method. 219 */ 220 return (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD && 221 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS && 222 PIIX4_dev->revision >= 0x51); 223} 224 225static int piix4_setup(struct pci_dev *PIIX4_dev, 226 const struct pci_device_id *id) 227{ 228 unsigned char temp; 229 unsigned short piix4_smba; 230 231 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) && 232 (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5)) 233 srvrworks_csb5_delay = 1; 234 235 /* On some motherboards, it was reported that accessing the SMBus 236 caused severe hardware problems */ 237 if (dmi_check_system(piix4_dmi_blacklist)) { 238 dev_err(&PIIX4_dev->dev, 239 "Accessing the SMBus on this system is unsafe!\n"); 240 return -EPERM; 241 } 242 243 /* Don't access SMBus on IBM systems which get corrupted eeproms */ 244 if (dmi_check_system(piix4_dmi_ibm) && 245 PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) { 246 dev_err(&PIIX4_dev->dev, "IBM system detected; this module " 247 "may corrupt your serial eeprom! Refusing to load " 248 "module!\n"); 249 return -EPERM; 250 } 251 252 /* Determine the address of the SMBus areas */ 253 if (force_addr) { 254 piix4_smba = force_addr & 0xfff0; 255 force = 0; 256 } else { 257 pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba); 258 piix4_smba &= 0xfff0; 259 if(piix4_smba == 0) { 260 dev_err(&PIIX4_dev->dev, "SMBus base address " 261 "uninitialized - upgrade BIOS or use " 262 "force_addr=0xaddr\n"); 263 return -ENODEV; 264 } 265 } 266 267 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) 268 return -ENODEV; 269 270 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { 271 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n", 272 piix4_smba); 273 return -EBUSY; 274 } 275 276 pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp); 277 278 /* If force_addr is set, we program the new address here. Just to make 279 sure, we disable the PIIX4 first. */ 280 if (force_addr) { 281 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe); 282 pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba); 283 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01); 284 dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to " 285 "new address %04x!\n", piix4_smba); 286 } else if ((temp & 1) == 0) { 287 if (force) { 288 /* This should never need to be done, but has been 289 * noted that many Dell machines have the SMBus 290 * interface on the PIIX4 disabled!? NOTE: This assumes 291 * I/O space and other allocations WERE done by the 292 * Bios! Don't complain if your hardware does weird 293 * things after enabling this. :') Check for Bios 294 * updates before resorting to this. 295 */ 296 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, 297 temp | 1); 298 dev_notice(&PIIX4_dev->dev, 299 "WARNING: SMBus interface has been FORCEFULLY ENABLED!\n"); 300 } else { 301 dev_err(&PIIX4_dev->dev, 302 "SMBus Host Controller not enabled!\n"); 303 release_region(piix4_smba, SMBIOSIZE); 304 return -ENODEV; 305 } 306 } 307 308 if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2)) 309 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n"); 310 else if ((temp & 0x0E) == 0) 311 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n"); 312 else 313 dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration " 314 "(or code out of date)!\n"); 315 316 pci_read_config_byte(PIIX4_dev, SMBREV, &temp); 317 dev_info(&PIIX4_dev->dev, 318 "SMBus Host Controller at 0x%x, revision %d\n", 319 piix4_smba, temp); 320 321 return piix4_smba; 322} 323 324static int piix4_setup_sb800_smba(struct pci_dev *PIIX4_dev, 325 u8 smb_en, 326 u8 aux, 327 u8 *smb_en_status, 328 unsigned short *piix4_smba) 329{ 330 struct sb800_mmio_cfg mmio_cfg; 331 u8 smba_en_lo; 332 u8 smba_en_hi; 333 int retval; 334 335 mmio_cfg.use_mmio = piix4_sb800_use_mmio(PIIX4_dev); 336 retval = piix4_sb800_region_request(&PIIX4_dev->dev, &mmio_cfg); 337 if (retval) 338 return retval; 339 340 if (mmio_cfg.use_mmio) { 341 smba_en_lo = ioread8(mmio_cfg.addr); 342 smba_en_hi = ioread8(mmio_cfg.addr + 1); 343 } else { 344 outb_p(smb_en, SB800_PIIX4_SMB_IDX); 345 smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1); 346 outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX); 347 smba_en_hi = inb_p(SB800_PIIX4_SMB_IDX + 1); 348 } 349 350 piix4_sb800_region_release(&PIIX4_dev->dev, &mmio_cfg); 351 352 if (!smb_en) { 353 *smb_en_status = smba_en_lo & 0x10; 354 *piix4_smba = smba_en_hi << 8; 355 if (aux) 356 *piix4_smba |= 0x20; 357 } else { 358 *smb_en_status = smba_en_lo & 0x01; 359 *piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0; 360 } 361 362 if (!*smb_en_status) { 363 dev_err(&PIIX4_dev->dev, 364 "SMBus Host Controller not enabled!\n"); 365 return -ENODEV; 366 } 367 368 return 0; 369} 370 371static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, 372 const struct pci_device_id *id, u8 aux) 373{ 374 unsigned short piix4_smba; 375 u8 smb_en, smb_en_status, port_sel; 376 u8 i2ccfg, i2ccfg_offset = 0x10; 377 struct sb800_mmio_cfg mmio_cfg; 378 int retval; 379 380 /* SB800 and later SMBus does not support forcing address */ 381 if (force || force_addr) { 382 dev_err(&PIIX4_dev->dev, "SMBus does not support " 383 "forcing address!\n"); 384 return -EINVAL; 385 } 386 387 /* Determine the address of the SMBus areas */ 388 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_AMD && 389 PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS && 390 PIIX4_dev->revision >= 0x41) || 391 (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD && 392 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS && 393 PIIX4_dev->revision >= 0x49) || 394 (PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON && 395 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS)) 396 smb_en = 0x00; 397 else 398 smb_en = (aux) ? 0x28 : 0x2c; 399 400 retval = piix4_setup_sb800_smba(PIIX4_dev, smb_en, aux, &smb_en_status, 401 &piix4_smba); 402 403 if (retval) 404 return retval; 405 406 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) 407 return -ENODEV; 408 409 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { 410 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n", 411 piix4_smba); 412 return -EBUSY; 413 } 414 415 /* Aux SMBus does not support IRQ information */ 416 if (aux) { 417 dev_info(&PIIX4_dev->dev, 418 "Auxiliary SMBus Host Controller at 0x%x\n", 419 piix4_smba); 420 return piix4_smba; 421 } 422 423 /* Request the SMBus I2C bus config region */ 424 if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) { 425 dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region " 426 "0x%x already in use!\n", piix4_smba + i2ccfg_offset); 427 release_region(piix4_smba, SMBIOSIZE); 428 return -EBUSY; 429 } 430 i2ccfg = inb_p(piix4_smba + i2ccfg_offset); 431 release_region(piix4_smba + i2ccfg_offset, 1); 432 433 if (i2ccfg & 1) 434 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n"); 435 else 436 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n"); 437 438 dev_info(&PIIX4_dev->dev, 439 "SMBus Host Controller at 0x%x, revision %d\n", 440 piix4_smba, i2ccfg >> 4); 441 442 /* Find which register is used for port selection */ 443 if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD || 444 PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON) { 445 if (PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS || 446 (PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS && 447 PIIX4_dev->revision >= 0x1F)) { 448 piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_KERNCZ; 449 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK_KERNCZ; 450 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ; 451 } else { 452 piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_ALT; 453 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK; 454 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT; 455 } 456 } else { 457 mmio_cfg.use_mmio = piix4_sb800_use_mmio(PIIX4_dev); 458 retval = piix4_sb800_region_request(&PIIX4_dev->dev, &mmio_cfg); 459 if (retval) { 460 release_region(piix4_smba, SMBIOSIZE); 461 return retval; 462 } 463 464 outb_p(SB800_PIIX4_PORT_IDX_SEL, SB800_PIIX4_SMB_IDX); 465 port_sel = inb_p(SB800_PIIX4_SMB_IDX + 1); 466 piix4_port_sel_sb800 = (port_sel & 0x01) ? 467 SB800_PIIX4_PORT_IDX_ALT : 468 SB800_PIIX4_PORT_IDX; 469 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK; 470 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT; 471 piix4_sb800_region_release(&PIIX4_dev->dev, &mmio_cfg); 472 } 473 474 dev_info(&PIIX4_dev->dev, 475 "Using register 0x%02x for SMBus port selection\n", 476 (unsigned int)piix4_port_sel_sb800); 477 478 return piix4_smba; 479} 480 481static int piix4_setup_aux(struct pci_dev *PIIX4_dev, 482 const struct pci_device_id *id, 483 unsigned short base_reg_addr) 484{ 485 /* Set up auxiliary SMBus controllers found on some 486 * AMD chipsets e.g. SP5100 (SB700 derivative) */ 487 488 unsigned short piix4_smba; 489 490 /* Read address of auxiliary SMBus controller */ 491 pci_read_config_word(PIIX4_dev, base_reg_addr, &piix4_smba); 492 if ((piix4_smba & 1) == 0) { 493 dev_dbg(&PIIX4_dev->dev, 494 "Auxiliary SMBus controller not enabled\n"); 495 return -ENODEV; 496 } 497 498 piix4_smba &= 0xfff0; 499 if (piix4_smba == 0) { 500 dev_dbg(&PIIX4_dev->dev, 501 "Auxiliary SMBus base address uninitialized\n"); 502 return -ENODEV; 503 } 504 505 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) 506 return -ENODEV; 507 508 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { 509 dev_err(&PIIX4_dev->dev, "Auxiliary SMBus region 0x%x " 510 "already in use!\n", piix4_smba); 511 return -EBUSY; 512 } 513 514 dev_info(&PIIX4_dev->dev, 515 "Auxiliary SMBus Host Controller at 0x%x\n", 516 piix4_smba); 517 518 return piix4_smba; 519} 520 521int piix4_transaction(struct i2c_adapter *piix4_adapter, unsigned short piix4_smba) 522{ 523 int temp; 524 int result = 0; 525 int timeout = 0; 526 527 dev_dbg(&piix4_adapter->dev, "Transaction (pre): CNT=%02x, CMD=%02x, " 528 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), 529 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), 530 inb_p(SMBHSTDAT1)); 531 532 /* Make sure the SMBus host is ready to start transmitting */ 533 if ((temp = inb_p(SMBHSTSTS)) != 0x00) { 534 dev_dbg(&piix4_adapter->dev, "SMBus busy (%02x). " 535 "Resetting...\n", temp); 536 outb_p(temp, SMBHSTSTS); 537 if ((temp = inb_p(SMBHSTSTS)) != 0x00) { 538 dev_err(&piix4_adapter->dev, "Failed! (%02x)\n", temp); 539 return -EBUSY; 540 } else { 541 dev_dbg(&piix4_adapter->dev, "Successful!\n"); 542 } 543 } 544 545 /* start the transaction by setting bit 6 */ 546 outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT); 547 548 /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */ 549 if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */ 550 usleep_range(2000, 2100); 551 else 552 usleep_range(250, 500); 553 554 while ((++timeout < MAX_TIMEOUT) && 555 ((temp = inb_p(SMBHSTSTS)) & 0x01)) 556 usleep_range(250, 500); 557 558 /* If the SMBus is still busy, we give up */ 559 if (timeout == MAX_TIMEOUT) { 560 dev_err(&piix4_adapter->dev, "SMBus Timeout!\n"); 561 result = -ETIMEDOUT; 562 } 563 564 if (temp & 0x10) { 565 result = -EIO; 566 dev_err(&piix4_adapter->dev, "Error: Failed bus transaction\n"); 567 } 568 569 if (temp & 0x08) { 570 result = -EIO; 571 dev_dbg(&piix4_adapter->dev, "Bus collision! SMBus may be " 572 "locked until next hard reset. (sorry!)\n"); 573 /* Clock stops and target is stuck in mid-transmission */ 574 } 575 576 if (temp & 0x04) { 577 result = -ENXIO; 578 dev_dbg(&piix4_adapter->dev, "Error: no response!\n"); 579 } 580 581 if (inb_p(SMBHSTSTS) != 0x00) 582 outb_p(inb(SMBHSTSTS), SMBHSTSTS); 583 584 if ((temp = inb_p(SMBHSTSTS)) != 0x00) { 585 dev_err(&piix4_adapter->dev, "Failed reset at end of " 586 "transaction (%02x)\n", temp); 587 } 588 dev_dbg(&piix4_adapter->dev, "Transaction (post): CNT=%02x, CMD=%02x, " 589 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), 590 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), 591 inb_p(SMBHSTDAT1)); 592 return result; 593} 594EXPORT_SYMBOL_NS_GPL(piix4_transaction, "PIIX4_SMBUS"); 595 596/* Return negative errno on error. */ 597static s32 piix4_access(struct i2c_adapter * adap, u16 addr, 598 unsigned short flags, char read_write, 599 u8 command, int size, union i2c_smbus_data * data) 600{ 601 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); 602 unsigned short piix4_smba = adapdata->smba; 603 int i, len; 604 int status; 605 606 switch (size) { 607 case I2C_SMBUS_QUICK: 608 outb_p((addr << 1) | read_write, 609 SMBHSTADD); 610 size = PIIX4_QUICK; 611 break; 612 case I2C_SMBUS_BYTE: 613 outb_p((addr << 1) | read_write, 614 SMBHSTADD); 615 if (read_write == I2C_SMBUS_WRITE) 616 outb_p(command, SMBHSTCMD); 617 size = PIIX4_BYTE; 618 break; 619 case I2C_SMBUS_BYTE_DATA: 620 outb_p((addr << 1) | read_write, 621 SMBHSTADD); 622 outb_p(command, SMBHSTCMD); 623 if (read_write == I2C_SMBUS_WRITE) 624 outb_p(data->byte, SMBHSTDAT0); 625 size = PIIX4_BYTE_DATA; 626 break; 627 case I2C_SMBUS_WORD_DATA: 628 outb_p((addr << 1) | read_write, 629 SMBHSTADD); 630 outb_p(command, SMBHSTCMD); 631 if (read_write == I2C_SMBUS_WRITE) { 632 outb_p(data->word & 0xff, SMBHSTDAT0); 633 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1); 634 } 635 size = PIIX4_WORD_DATA; 636 break; 637 case I2C_SMBUS_BLOCK_DATA: 638 outb_p((addr << 1) | read_write, 639 SMBHSTADD); 640 outb_p(command, SMBHSTCMD); 641 if (read_write == I2C_SMBUS_WRITE) { 642 len = data->block[0]; 643 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX) 644 return -EINVAL; 645 outb_p(len, SMBHSTDAT0); 646 inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */ 647 for (i = 1; i <= len; i++) 648 outb_p(data->block[i], SMBBLKDAT); 649 } 650 size = PIIX4_BLOCK_DATA; 651 break; 652 default: 653 dev_warn(&adap->dev, "Unsupported transaction %d\n", size); 654 return -EOPNOTSUPP; 655 } 656 657 outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT); 658 659 status = piix4_transaction(adap, piix4_smba); 660 if (status) 661 return status; 662 663 if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK)) 664 return 0; 665 666 667 switch (size) { 668 case PIIX4_BYTE: 669 case PIIX4_BYTE_DATA: 670 data->byte = inb_p(SMBHSTDAT0); 671 break; 672 case PIIX4_WORD_DATA: 673 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8); 674 break; 675 case PIIX4_BLOCK_DATA: 676 data->block[0] = inb_p(SMBHSTDAT0); 677 if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX) 678 return -EPROTO; 679 inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */ 680 for (i = 1; i <= data->block[0]; i++) 681 data->block[i] = inb_p(SMBBLKDAT); 682 break; 683 } 684 return 0; 685} 686 687static uint8_t piix4_imc_read(uint8_t idx) 688{ 689 outb_p(idx, KERNCZ_IMC_IDX); 690 return inb_p(KERNCZ_IMC_DATA); 691} 692 693static void piix4_imc_write(uint8_t idx, uint8_t value) 694{ 695 outb_p(idx, KERNCZ_IMC_IDX); 696 outb_p(value, KERNCZ_IMC_DATA); 697} 698 699static int piix4_imc_sleep(void) 700{ 701 int timeout = MAX_TIMEOUT; 702 703 if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc")) 704 return -EBUSY; 705 706 /* clear response register */ 707 piix4_imc_write(0x82, 0x00); 708 /* request ownership flag */ 709 piix4_imc_write(0x83, 0xB4); 710 /* kick off IMC Mailbox command 96 */ 711 piix4_imc_write(0x80, 0x96); 712 713 while (timeout--) { 714 if (piix4_imc_read(0x82) == 0xfa) { 715 release_region(KERNCZ_IMC_IDX, 2); 716 return 0; 717 } 718 usleep_range(1000, 2000); 719 } 720 721 release_region(KERNCZ_IMC_IDX, 2); 722 return -ETIMEDOUT; 723} 724 725static void piix4_imc_wakeup(void) 726{ 727 int timeout = MAX_TIMEOUT; 728 729 if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc")) 730 return; 731 732 /* clear response register */ 733 piix4_imc_write(0x82, 0x00); 734 /* release ownership flag */ 735 piix4_imc_write(0x83, 0xB5); 736 /* kick off IMC Mailbox command 96 */ 737 piix4_imc_write(0x80, 0x96); 738 739 while (timeout--) { 740 if (piix4_imc_read(0x82) == 0xfa) 741 break; 742 usleep_range(1000, 2000); 743 } 744 745 release_region(KERNCZ_IMC_IDX, 2); 746} 747 748int piix4_sb800_port_sel(u8 port, struct sb800_mmio_cfg *mmio_cfg) 749{ 750 u8 smba_en_lo, val; 751 752 if (mmio_cfg->use_mmio) { 753 smba_en_lo = ioread8(mmio_cfg->addr + piix4_port_sel_sb800); 754 val = (smba_en_lo & ~piix4_port_mask_sb800) | port; 755 if (smba_en_lo != val) 756 iowrite8(val, mmio_cfg->addr + piix4_port_sel_sb800); 757 758 return (smba_en_lo & piix4_port_mask_sb800); 759 } 760 761 outb_p(piix4_port_sel_sb800, SB800_PIIX4_SMB_IDX); 762 smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1); 763 764 val = (smba_en_lo & ~piix4_port_mask_sb800) | port; 765 if (smba_en_lo != val) 766 outb_p(val, SB800_PIIX4_SMB_IDX + 1); 767 768 return (smba_en_lo & piix4_port_mask_sb800); 769} 770EXPORT_SYMBOL_NS_GPL(piix4_sb800_port_sel, "PIIX4_SMBUS"); 771 772/* 773 * Handles access to multiple SMBus ports on the SB800. 774 * The port is selected by bits 2:1 of the smb_en register (0x2c). 775 * Returns negative errno on error. 776 * 777 * Note: The selected port must be returned to the initial selection to avoid 778 * problems on certain systems. 779 */ 780static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr, 781 unsigned short flags, char read_write, 782 u8 command, int size, union i2c_smbus_data *data) 783{ 784 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); 785 unsigned short piix4_smba = adapdata->smba; 786 int retries = MAX_TIMEOUT; 787 int smbslvcnt; 788 u8 prev_port; 789 int retval; 790 791 retval = piix4_sb800_region_request(&adap->dev, &adapdata->mmio_cfg); 792 if (retval) 793 return retval; 794 795 /* Request the SMBUS semaphore, avoid conflicts with the IMC */ 796 smbslvcnt = inb_p(SMBSLVCNT); 797 do { 798 outb_p(smbslvcnt | 0x10, SMBSLVCNT); 799 800 /* Check the semaphore status */ 801 smbslvcnt = inb_p(SMBSLVCNT); 802 if (smbslvcnt & 0x10) 803 break; 804 805 usleep_range(1000, 2000); 806 } while (--retries); 807 /* SMBus is still owned by the IMC, we give up */ 808 if (!retries) { 809 retval = -EBUSY; 810 goto release; 811 } 812 813 /* 814 * Notify the IMC (Integrated Micro Controller) if required. 815 * Among other responsibilities, the IMC is in charge of monitoring 816 * the System fans and temperature sensors, and act accordingly. 817 * All this is done through SMBus and can/will collide 818 * with our transactions if they are long (BLOCK_DATA). 819 * Therefore we need to request the ownership flag during those 820 * transactions. 821 */ 822 if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc) { 823 int ret; 824 825 ret = piix4_imc_sleep(); 826 switch (ret) { 827 case -EBUSY: 828 dev_warn(&adap->dev, 829 "IMC base address index region 0x%x already in use.\n", 830 KERNCZ_IMC_IDX); 831 break; 832 case -ETIMEDOUT: 833 dev_warn(&adap->dev, 834 "Failed to communicate with the IMC.\n"); 835 break; 836 default: 837 break; 838 } 839 840 /* If IMC communication fails do not retry */ 841 if (ret) { 842 dev_warn(&adap->dev, 843 "Continuing without IMC notification.\n"); 844 adapdata->notify_imc = false; 845 } 846 } 847 848 prev_port = piix4_sb800_port_sel(adapdata->port, &adapdata->mmio_cfg); 849 850 retval = piix4_access(adap, addr, flags, read_write, 851 command, size, data); 852 853 piix4_sb800_port_sel(prev_port, &adapdata->mmio_cfg); 854 855 /* Release the semaphore */ 856 outb_p(smbslvcnt | 0x20, SMBSLVCNT); 857 858 if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc) 859 piix4_imc_wakeup(); 860 861release: 862 piix4_sb800_region_release(&adap->dev, &adapdata->mmio_cfg); 863 return retval; 864} 865 866static u32 piix4_func(struct i2c_adapter *adapter) 867{ 868 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 869 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 870 I2C_FUNC_SMBUS_BLOCK_DATA; 871} 872 873static const struct i2c_algorithm smbus_algorithm = { 874 .smbus_xfer = piix4_access, 875 .functionality = piix4_func, 876}; 877 878static const struct i2c_algorithm piix4_smbus_algorithm_sb800 = { 879 .smbus_xfer = piix4_access_sb800, 880 .functionality = piix4_func, 881}; 882 883static const struct pci_device_id piix4_ids[] = { 884 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) }, 885 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) }, 886 { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) }, 887 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) }, 888 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) }, 889 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) }, 890 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) }, 891 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) }, 892 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) }, 893 { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) }, 894 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 895 PCI_DEVICE_ID_SERVERWORKS_OSB4) }, 896 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 897 PCI_DEVICE_ID_SERVERWORKS_CSB5) }, 898 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 899 PCI_DEVICE_ID_SERVERWORKS_CSB6) }, 900 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 901 PCI_DEVICE_ID_SERVERWORKS_HT1000SB) }, 902 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 903 PCI_DEVICE_ID_SERVERWORKS_HT1100LD) }, 904 { 0, } 905}; 906 907MODULE_DEVICE_TABLE (pci, piix4_ids); 908 909static struct i2c_adapter *piix4_main_adapters[PIIX4_MAX_ADAPTERS]; 910static struct i2c_adapter *piix4_aux_adapter; 911static int piix4_adapter_count; 912 913static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba, 914 bool sb800_main, u8 port, bool notify_imc, 915 u8 hw_port_nr, const char *name, 916 struct i2c_adapter **padap) 917{ 918 struct i2c_adapter *adap; 919 struct i2c_piix4_adapdata *adapdata; 920 int retval; 921 922 adap = kzalloc(sizeof(*adap), GFP_KERNEL); 923 if (adap == NULL) { 924 release_region(smba, SMBIOSIZE); 925 return -ENOMEM; 926 } 927 928 adap->owner = THIS_MODULE; 929 adap->class = I2C_CLASS_HWMON; 930 adap->algo = sb800_main ? &piix4_smbus_algorithm_sb800 931 : &smbus_algorithm; 932 933 adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL); 934 if (adapdata == NULL) { 935 kfree(adap); 936 release_region(smba, SMBIOSIZE); 937 return -ENOMEM; 938 } 939 940 adapdata->mmio_cfg.use_mmio = piix4_sb800_use_mmio(dev); 941 adapdata->smba = smba; 942 adapdata->sb800_main = sb800_main; 943 adapdata->port = port << piix4_port_shift_sb800; 944 adapdata->notify_imc = notify_imc; 945 946 /* set up the sysfs linkage to our parent device */ 947 adap->dev.parent = &dev->dev; 948 949 if (has_acpi_companion(&dev->dev)) { 950 acpi_preset_companion(&adap->dev, 951 ACPI_COMPANION(&dev->dev), 952 hw_port_nr); 953 } 954 955 snprintf(adap->name, sizeof(adap->name), 956 "SMBus PIIX4 adapter%s at %04x", name, smba); 957 958 i2c_set_adapdata(adap, adapdata); 959 960 retval = i2c_add_adapter(adap); 961 if (retval) { 962 kfree(adapdata); 963 kfree(adap); 964 release_region(smba, SMBIOSIZE); 965 return retval; 966 } 967 968 /* 969 * The AUX bus can not be probed as on some platforms it reports all 970 * devices present and all reads return "0". 971 * This would allow the ee1004 to be probed incorrectly. 972 */ 973 if (port == 0) 974 i2c_register_spd_write_enable(adap); 975 976 *padap = adap; 977 return 0; 978} 979 980static int piix4_add_adapters_sb800(struct pci_dev *dev, unsigned short smba, 981 bool notify_imc) 982{ 983 struct i2c_piix4_adapdata *adapdata; 984 int port; 985 int retval; 986 987 if (dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS || 988 (dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS && 989 dev->revision >= 0x1F)) { 990 piix4_adapter_count = HUDSON2_MAIN_PORTS; 991 } else { 992 piix4_adapter_count = PIIX4_MAX_ADAPTERS; 993 } 994 995 for (port = 0; port < piix4_adapter_count; port++) { 996 u8 hw_port_nr = port == 0 ? 0 : port + 1; 997 998 retval = piix4_add_adapter(dev, smba, true, port, notify_imc, 999 hw_port_nr, 1000 piix4_main_port_names_sb800[port], 1001 &piix4_main_adapters[port]); 1002 if (retval < 0) 1003 goto error; 1004 } 1005 1006 return retval; 1007 1008error: 1009 dev_err(&dev->dev, 1010 "Error setting up SB800 adapters. Unregistering!\n"); 1011 while (--port >= 0) { 1012 adapdata = i2c_get_adapdata(piix4_main_adapters[port]); 1013 if (adapdata->smba) { 1014 i2c_del_adapter(piix4_main_adapters[port]); 1015 kfree(adapdata); 1016 kfree(piix4_main_adapters[port]); 1017 piix4_main_adapters[port] = NULL; 1018 } 1019 } 1020 1021 return retval; 1022} 1023 1024static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id) 1025{ 1026 int retval; 1027 bool is_sb800 = false; 1028 bool is_asf = false; 1029 acpi_status status; 1030 acpi_handle handle; 1031 1032 if ((dev->vendor == PCI_VENDOR_ID_ATI && 1033 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS && 1034 dev->revision >= 0x40) || 1035 dev->vendor == PCI_VENDOR_ID_AMD || 1036 dev->vendor == PCI_VENDOR_ID_HYGON) { 1037 bool notify_imc = false; 1038 is_sb800 = true; 1039 1040 if ((dev->vendor == PCI_VENDOR_ID_AMD || 1041 dev->vendor == PCI_VENDOR_ID_HYGON) && 1042 dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) { 1043 u8 imc; 1044 1045 /* 1046 * Detect if IMC is active or not, this method is 1047 * described on coreboot's AMD IMC notes 1048 */ 1049 pci_bus_read_config_byte(dev->bus, PCI_DEVFN(0x14, 3), 1050 0x40, &imc); 1051 if (imc & 0x80) 1052 notify_imc = true; 1053 } 1054 1055 /* base address location etc changed in SB800 */ 1056 retval = piix4_setup_sb800(dev, id, 0); 1057 if (retval < 0) 1058 return retval; 1059 1060 /* 1061 * Try to register multiplexed main SMBus adapter, 1062 * give up if we can't 1063 */ 1064 retval = piix4_add_adapters_sb800(dev, retval, notify_imc); 1065 if (retval < 0) 1066 return retval; 1067 } else { 1068 retval = piix4_setup(dev, id); 1069 if (retval < 0) 1070 return retval; 1071 1072 /* Try to register main SMBus adapter, give up if we can't */ 1073 retval = piix4_add_adapter(dev, retval, false, 0, false, 0, 1074 "", &piix4_main_adapters[0]); 1075 if (retval < 0) 1076 return retval; 1077 piix4_adapter_count = 1; 1078 } 1079 1080 /* Check for auxiliary SMBus on some AMD chipsets */ 1081 retval = -ENODEV; 1082 1083 if (dev->vendor == PCI_VENDOR_ID_ATI && 1084 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) { 1085 if (dev->revision < 0x40) { 1086 retval = piix4_setup_aux(dev, id, 0x58); 1087 } else { 1088 /* SB800 added aux bus too */ 1089 retval = piix4_setup_sb800(dev, id, 1); 1090 } 1091 } 1092 1093 status = acpi_get_handle(NULL, (acpi_string)SB800_ASF_ACPI_PATH, &handle); 1094 if (ACPI_SUCCESS(status)) 1095 is_asf = true; 1096 1097 if (dev->vendor == PCI_VENDOR_ID_AMD && 1098 (dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS || 1099 dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS)) { 1100 /* Do not setup AUX port if ASF is enabled */ 1101 if (!is_asf) 1102 retval = piix4_setup_sb800(dev, id, 1); 1103 } 1104 1105 if (retval > 0) { 1106 /* Try to add the aux adapter if it exists, 1107 * piix4_add_adapter will clean up if this fails */ 1108 piix4_add_adapter(dev, retval, false, 0, false, 1, 1109 is_sb800 ? piix4_aux_port_name_sb800 : "", 1110 &piix4_aux_adapter); 1111 } 1112 1113 return 0; 1114} 1115 1116static void piix4_adap_remove(struct i2c_adapter *adap) 1117{ 1118 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); 1119 1120 if (adapdata->smba) { 1121 i2c_del_adapter(adap); 1122 if (adapdata->port == (0 << piix4_port_shift_sb800)) 1123 release_region(adapdata->smba, SMBIOSIZE); 1124 kfree(adapdata); 1125 kfree(adap); 1126 } 1127} 1128 1129static void piix4_remove(struct pci_dev *dev) 1130{ 1131 int port = piix4_adapter_count; 1132 1133 while (--port >= 0) { 1134 if (piix4_main_adapters[port]) { 1135 piix4_adap_remove(piix4_main_adapters[port]); 1136 piix4_main_adapters[port] = NULL; 1137 } 1138 } 1139 1140 if (piix4_aux_adapter) { 1141 piix4_adap_remove(piix4_aux_adapter); 1142 piix4_aux_adapter = NULL; 1143 } 1144} 1145 1146static struct pci_driver piix4_driver = { 1147 .name = "piix4_smbus", 1148 .id_table = piix4_ids, 1149 .probe = piix4_probe, 1150 .remove = piix4_remove, 1151}; 1152 1153module_pci_driver(piix4_driver); 1154 1155MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl>"); 1156MODULE_AUTHOR("Philip Edelbrock <phil@netroedge.com>"); 1157MODULE_DESCRIPTION("PIIX4 SMBus driver"); 1158MODULE_LICENSE("GPL");
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