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i2c-octeon-core.c
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linux-6.19.14/drivers/i2c/busses/i2c-octeon-core.c
1/* 2 * (C) Copyright 2009-2010 3 * Nokia Siemens Networks, michael.lawnick.ext@nsn.com 4 * 5 * Portions Copyright (C) 2010 - 2016 Cavium, Inc. 6 * 7 * This file contains the shared part of the driver for the i2c adapter in 8 * Cavium Networks' OCTEON processors and ThunderX SOCs. 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 */ 14 15#include <linux/delay.h> 16#include <linux/i2c.h> 17#include <linux/interrupt.h> 18#include <linux/kernel.h> 19#include <linux/module.h> 20#include <linux/pci.h> 21 22#include "i2c-octeon-core.h" 23 24#define INITIAL_DELTA_HZ 1000000 25#define TWSI_MASTER_CLK_REG_DEF_VAL 0x18 26#define TWSI_MASTER_CLK_REG_OTX2_VAL 0x3 27 28/* interrupt service routine */ 29irqreturn_t octeon_i2c_isr(int irq, void *dev_id) 30{ 31 struct octeon_i2c *i2c = dev_id; 32 33 i2c->int_disable(i2c); 34 wake_up(&i2c->queue); 35 36 return IRQ_HANDLED; 37} 38 39static bool octeon_i2c_test_iflg(struct octeon_i2c *i2c) 40{ 41 return (octeon_i2c_ctl_read(i2c) & TWSI_CTL_IFLG); 42} 43 44/** 45 * octeon_i2c_wait - wait for the IFLG to be set 46 * @i2c: The struct octeon_i2c 47 * 48 * Returns: 0 on success, otherwise a negative errno. 49 */ 50static int octeon_i2c_wait(struct octeon_i2c *i2c) 51{ 52 long time_left; 53 54 /* 55 * Some chip revisions don't assert the irq in the interrupt 56 * controller. So we must poll for the IFLG change. 57 */ 58 if (i2c->broken_irq_mode) { 59 u64 end = get_jiffies_64() + i2c->adap.timeout; 60 61 while (!octeon_i2c_test_iflg(i2c) && 62 time_before64(get_jiffies_64(), end)) 63 usleep_range(I2C_OCTEON_EVENT_WAIT / 2, I2C_OCTEON_EVENT_WAIT); 64 65 return octeon_i2c_test_iflg(i2c) ? 0 : -ETIMEDOUT; 66 } 67 68 i2c->int_enable(i2c); 69 time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_iflg(i2c), 70 i2c->adap.timeout); 71 i2c->int_disable(i2c); 72 73 if (i2c->broken_irq_check && !time_left && 74 octeon_i2c_test_iflg(i2c)) { 75 dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n"); 76 i2c->broken_irq_mode = true; 77 return 0; 78 } 79 80 if (!time_left) 81 return -ETIMEDOUT; 82 83 return 0; 84} 85 86static bool octeon_i2c_hlc_test_valid(struct octeon_i2c *i2c) 87{ 88 return (__raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)) & SW_TWSI_V) == 0; 89} 90 91static void octeon_i2c_hlc_int_clear(struct octeon_i2c *i2c) 92{ 93 /* clear ST/TS events, listen for neither */ 94 octeon_i2c_write_int(i2c, TWSI_INT_ST_INT | TWSI_INT_TS_INT); 95} 96 97/* 98 * Cleanup low-level state & enable high-level controller. 99 */ 100static void octeon_i2c_hlc_enable(struct octeon_i2c *i2c) 101{ 102 int try = 0; 103 u64 val; 104 105 if (i2c->hlc_enabled) 106 return; 107 i2c->hlc_enabled = true; 108 109 while (1) { 110 val = octeon_i2c_ctl_read(i2c); 111 if (!(val & (TWSI_CTL_STA | TWSI_CTL_STP))) 112 break; 113 114 /* clear IFLG event */ 115 if (val & TWSI_CTL_IFLG) 116 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB); 117 118 if (try++ > 100) { 119 pr_err("%s: giving up\n", __func__); 120 break; 121 } 122 123 /* spin until any start/stop has finished */ 124 udelay(10); 125 } 126 octeon_i2c_ctl_write(i2c, TWSI_CTL_CE | TWSI_CTL_AAK | TWSI_CTL_ENAB); 127} 128 129static void octeon_i2c_hlc_disable(struct octeon_i2c *i2c) 130{ 131 if (!i2c->hlc_enabled) 132 return; 133 134 i2c->hlc_enabled = false; 135 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB); 136} 137 138static void octeon_i2c_block_enable(struct octeon_i2c *i2c) 139{ 140 u64 mode; 141 142 if (i2c->block_enabled || !OCTEON_REG_BLOCK_CTL(i2c)) 143 return; 144 145 i2c->block_enabled = true; 146 mode = __raw_readq(i2c->twsi_base + OCTEON_REG_MODE(i2c)); 147 mode |= TWSX_MODE_BLOCK_MODE; 148 octeon_i2c_writeq_flush(mode, i2c->twsi_base + OCTEON_REG_MODE(i2c)); 149} 150 151static void octeon_i2c_block_disable(struct octeon_i2c *i2c) 152{ 153 u64 mode; 154 155 if (!i2c->block_enabled || !OCTEON_REG_BLOCK_CTL(i2c)) 156 return; 157 158 i2c->block_enabled = false; 159 mode = __raw_readq(i2c->twsi_base + OCTEON_REG_MODE(i2c)); 160 mode &= ~TWSX_MODE_BLOCK_MODE; 161 octeon_i2c_writeq_flush(mode, i2c->twsi_base + OCTEON_REG_MODE(i2c)); 162} 163 164/** 165 * octeon_i2c_hlc_wait - wait for an HLC operation to complete 166 * @i2c: The struct octeon_i2c 167 * 168 * Returns: 0 on success, otherwise -ETIMEDOUT. 169 */ 170static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c) 171{ 172 int time_left; 173 174 /* 175 * Some cn38xx boards don't assert the irq in the interrupt 176 * controller. So we must poll for the valid bit change. 177 */ 178 if (i2c->broken_irq_mode) { 179 u64 end = get_jiffies_64() + i2c->adap.timeout; 180 181 while (!octeon_i2c_hlc_test_valid(i2c) && 182 time_before64(get_jiffies_64(), end)) 183 usleep_range(I2C_OCTEON_EVENT_WAIT / 2, I2C_OCTEON_EVENT_WAIT); 184 185 return octeon_i2c_hlc_test_valid(i2c) ? 0 : -ETIMEDOUT; 186 } 187 188 i2c->hlc_int_enable(i2c); 189 time_left = wait_event_timeout(i2c->queue, 190 octeon_i2c_hlc_test_valid(i2c), 191 i2c->adap.timeout); 192 i2c->hlc_int_disable(i2c); 193 if (!time_left) 194 octeon_i2c_hlc_int_clear(i2c); 195 196 if (i2c->broken_irq_check && !time_left && 197 octeon_i2c_hlc_test_valid(i2c)) { 198 dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n"); 199 i2c->broken_irq_mode = true; 200 return 0; 201 } 202 203 if (!time_left) 204 return -ETIMEDOUT; 205 return 0; 206} 207 208static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read) 209{ 210 u8 stat; 211 u64 mode; 212 213 /* 214 * This is ugly... in HLC mode the status is not in the status register 215 * but in the lower 8 bits of OCTEON_REG_SW_TWSI. 216 */ 217 if (i2c->hlc_enabled) 218 stat = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); 219 else 220 stat = octeon_i2c_stat_read(i2c); 221 222 switch (stat) { 223 /* Everything is fine */ 224 case STAT_IDLE: 225 case STAT_AD2W_ACK: 226 case STAT_RXADDR_ACK: 227 case STAT_TXADDR_ACK: 228 case STAT_TXDATA_ACK: 229 return 0; 230 231 /* ACK allowed on pre-terminal bytes only */ 232 case STAT_RXDATA_ACK: 233 if (!final_read) 234 return 0; 235 return -EIO; 236 237 /* NAK allowed on terminal byte only */ 238 case STAT_RXDATA_NAK: 239 if (final_read) 240 return 0; 241 return -EIO; 242 243 /* Arbitration lost */ 244 case STAT_LOST_ARB_38: 245 case STAT_LOST_ARB_68: 246 case STAT_LOST_ARB_78: 247 case STAT_LOST_ARB_B0: 248 return -EAGAIN; 249 250 /* Being addressed as local target, should back off & listen */ 251 case STAT_SLAVE_60: 252 case STAT_SLAVE_70: 253 case STAT_GENDATA_ACK: 254 case STAT_GENDATA_NAK: 255 return -EOPNOTSUPP; 256 257 /* Core busy as local target */ 258 case STAT_SLAVE_80: 259 case STAT_SLAVE_88: 260 case STAT_SLAVE_A0: 261 case STAT_SLAVE_A8: 262 case STAT_SLAVE_LOST: 263 case STAT_SLAVE_NAK: 264 case STAT_SLAVE_ACK: 265 return -EOPNOTSUPP; 266 267 case STAT_TXDATA_NAK: 268 case STAT_BUS_ERROR: 269 return -EIO; 270 case STAT_TXADDR_NAK: 271 case STAT_RXADDR_NAK: 272 case STAT_AD2W_NAK: 273 return -ENXIO; 274 275 case STAT_WDOG_TOUT: 276 mode = __raw_readq(i2c->twsi_base + OCTEON_REG_MODE(i2c)); 277 /* Set BUS_MON_RST to reset bus monitor */ 278 mode |= BUS_MON_RST_MASK; 279 octeon_i2c_writeq_flush(mode, i2c->twsi_base + OCTEON_REG_MODE(i2c)); 280 return -EIO; 281 default: 282 dev_err(i2c->dev, "unhandled state: %d\n", stat); 283 return -EIO; 284 } 285} 286 287static int octeon_i2c_recovery(struct octeon_i2c *i2c) 288{ 289 int ret; 290 291 ret = i2c_recover_bus(&i2c->adap); 292 if (ret) 293 /* recover failed, try hardware re-init */ 294 ret = octeon_i2c_init_lowlevel(i2c); 295 return ret; 296} 297 298/** 299 * octeon_i2c_start - send START to the bus 300 * @i2c: The struct octeon_i2c 301 * 302 * Returns: 0 on success, otherwise a negative errno. 303 */ 304static int octeon_i2c_start(struct octeon_i2c *i2c) 305{ 306 int ret; 307 u8 stat; 308 309 octeon_i2c_hlc_disable(i2c); 310 octeon_i2c_block_disable(i2c); 311 312 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STA); 313 ret = octeon_i2c_wait(i2c); 314 if (ret) 315 goto error; 316 317 stat = octeon_i2c_stat_read(i2c); 318 if (stat == STAT_START || stat == STAT_REP_START) 319 /* START successful, bail out */ 320 return 0; 321 322error: 323 /* START failed, try to recover */ 324 ret = octeon_i2c_recovery(i2c); 325 return (ret) ? ret : -EAGAIN; 326} 327 328/* send STOP to the bus */ 329static void octeon_i2c_stop(struct octeon_i2c *i2c) 330{ 331 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STP); 332} 333 334/** 335 * octeon_i2c_read - receive data from the bus via low-level controller 336 * @i2c: The struct octeon_i2c 337 * @target: Target address 338 * @data: Pointer to the location to store the data 339 * @rlength: Length of the data 340 * @recv_len: flag for length byte 341 * 342 * The address is sent over the bus, then the data is read. 343 * 344 * Returns: 0 on success, otherwise a negative errno. 345 */ 346static int octeon_i2c_read(struct octeon_i2c *i2c, int target, 347 u8 *data, u16 *rlength, bool recv_len) 348{ 349 int i, result, length = *rlength; 350 bool final_read = false; 351 352 octeon_i2c_data_write(i2c, (target << 1) | 1); 353 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB); 354 355 result = octeon_i2c_wait(i2c); 356 if (result) 357 return result; 358 359 /* address OK ? */ 360 result = octeon_i2c_check_status(i2c, false); 361 if (result) 362 return result; 363 364 for (i = 0; i < length; i++) { 365 /* 366 * For the last byte to receive TWSI_CTL_AAK must not be set. 367 * 368 * A special case is I2C_M_RECV_LEN where we don't know the 369 * additional length yet. If recv_len is set we assume we're 370 * not reading the final byte and therefore need to set 371 * TWSI_CTL_AAK. 372 */ 373 if ((i + 1 == length) && !(recv_len && i == 0)) 374 final_read = true; 375 376 /* clear iflg to allow next event */ 377 if (final_read) 378 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB); 379 else 380 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_AAK); 381 382 result = octeon_i2c_wait(i2c); 383 if (result) 384 return result; 385 386 data[i] = octeon_i2c_data_read(i2c, &result); 387 if (result) 388 return result; 389 if (recv_len && i == 0) { 390 if (data[i] > I2C_SMBUS_BLOCK_MAX) 391 return -EPROTO; 392 length += data[i]; 393 } 394 395 result = octeon_i2c_check_status(i2c, final_read); 396 if (result) 397 return result; 398 } 399 *rlength = length; 400 return 0; 401} 402 403/** 404 * octeon_i2c_write - send data to the bus via low-level controller 405 * @i2c: The struct octeon_i2c 406 * @target: Target address 407 * @data: Pointer to the data to be sent 408 * @length: Length of the data 409 * 410 * The address is sent over the bus, then the data. 411 * 412 * Returns: 0 on success, otherwise a negative errno. 413 */ 414static int octeon_i2c_write(struct octeon_i2c *i2c, int target, 415 const u8 *data, int length) 416{ 417 int i, result; 418 419 octeon_i2c_data_write(i2c, target << 1); 420 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB); 421 422 result = octeon_i2c_wait(i2c); 423 if (result) 424 return result; 425 426 for (i = 0; i < length; i++) { 427 result = octeon_i2c_check_status(i2c, false); 428 if (result) 429 return result; 430 431 octeon_i2c_data_write(i2c, data[i]); 432 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB); 433 434 result = octeon_i2c_wait(i2c); 435 if (result) 436 return result; 437 } 438 439 return 0; 440} 441 442/* high-level-controller pure read of up to 8 bytes */ 443static int octeon_i2c_hlc_read(struct octeon_i2c *i2c, struct i2c_msg *msgs) 444{ 445 int i, j, ret = 0; 446 u64 cmd; 447 448 octeon_i2c_hlc_enable(i2c); 449 octeon_i2c_hlc_int_clear(i2c); 450 451 cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR | SW_TWSI_OP_7; 452 /* SIZE */ 453 cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT; 454 /* A */ 455 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT; 456 457 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); 458 ret = octeon_i2c_hlc_wait(i2c); 459 if (ret) 460 goto err; 461 462 cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); 463 if ((cmd & SW_TWSI_R) == 0) 464 return octeon_i2c_check_status(i2c, false); 465 466 for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--) 467 msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff; 468 469 if (msgs[0].len > 4) { 470 cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c)); 471 for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--) 472 msgs[0].buf[j] = (cmd >> (8 * i)) & 0xff; 473 } 474 475err: 476 return ret; 477} 478 479/* high-level-controller pure write of up to 8 bytes */ 480static int octeon_i2c_hlc_write(struct octeon_i2c *i2c, struct i2c_msg *msgs) 481{ 482 int i, j, ret = 0; 483 u64 cmd; 484 485 octeon_i2c_hlc_enable(i2c); 486 octeon_i2c_hlc_int_clear(i2c); 487 488 cmd = SW_TWSI_V | SW_TWSI_SOVR | SW_TWSI_OP_7; 489 /* SIZE */ 490 cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT; 491 /* A */ 492 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT; 493 494 for (i = 0, j = msgs[0].len - 1; i < msgs[0].len && i < 4; i++, j--) 495 cmd |= (u64)msgs[0].buf[j] << (8 * i); 496 497 if (msgs[0].len > 4) { 498 u64 ext = 0; 499 500 for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--) 501 ext |= (u64)msgs[0].buf[j] << (8 * i); 502 octeon_i2c_writeq_flush(ext, i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c)); 503 } 504 505 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); 506 ret = octeon_i2c_hlc_wait(i2c); 507 if (ret) 508 goto err; 509 510 cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); 511 if ((cmd & SW_TWSI_R) == 0) 512 return octeon_i2c_check_status(i2c, false); 513 514err: 515 return ret; 516} 517 518/* Process hlc transaction */ 519static int octeon_i2c_hlc_cmd_send(struct octeon_i2c *i2c, u64 cmd) 520{ 521 octeon_i2c_hlc_int_clear(i2c); 522 octeon_i2c_writeq_flush(cmd, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); 523 524 return octeon_i2c_hlc_wait(i2c); 525} 526 527/* Generic consideration for extended internal addresses in i2c hlc r/w ops */ 528static bool octeon_i2c_hlc_ext(struct octeon_i2c *i2c, struct i2c_msg msg, u64 *cmd_in, u64 *ext) 529{ 530 bool set_ext = false; 531 u64 cmd = 0; 532 533 if (msg.len == 2) { 534 cmd |= SW_TWSI_EIA; 535 *ext = (u64)msg.buf[0] << SW_TWSI_IA_SHIFT; 536 cmd |= (u64)msg.buf[1] << SW_TWSI_IA_SHIFT; 537 set_ext = true; 538 } else { 539 cmd |= (u64)msg.buf[0] << SW_TWSI_IA_SHIFT; 540 } 541 542 *cmd_in |= cmd; 543 return set_ext; 544} 545 546/* Construct and send i2c transaction core cmd for read ops */ 547static int octeon_i2c_hlc_read_cmd(struct octeon_i2c *i2c, struct i2c_msg msg, u64 cmd) 548{ 549 u64 ext = 0; 550 551 if (octeon_i2c_hlc_ext(i2c, msg, &cmd, &ext)) 552 octeon_i2c_writeq_flush(ext, i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c)); 553 554 return octeon_i2c_hlc_cmd_send(i2c, cmd); 555} 556 557/* high-level-controller composite write+read, msg0=addr, msg1=data */ 558static int octeon_i2c_hlc_comp_read(struct octeon_i2c *i2c, struct i2c_msg *msgs) 559{ 560 int i, j, ret = 0; 561 u64 cmd; 562 563 octeon_i2c_hlc_enable(i2c); 564 565 cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR | SW_TWSI_OP_7_IA; 566 /* SIZE */ 567 cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT; 568 /* A */ 569 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT; 570 571 /* Send core command */ 572 ret = octeon_i2c_hlc_read_cmd(i2c, msgs[0], cmd); 573 if (ret) 574 goto err; 575 576 cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); 577 if ((cmd & SW_TWSI_R) == 0) 578 return octeon_i2c_check_status(i2c, false); 579 580 for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--) 581 msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff; 582 583 if (msgs[1].len > 4) { 584 cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c)); 585 for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--) 586 msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff; 587 } 588 589err: 590 return ret; 591} 592 593/* high-level-controller composite write+write, m[0]len<=2, m[1]len<=8 */ 594static int octeon_i2c_hlc_comp_write(struct octeon_i2c *i2c, struct i2c_msg *msgs) 595{ 596 bool set_ext = false; 597 int i, j, ret = 0; 598 u64 cmd, ext = 0; 599 600 octeon_i2c_hlc_enable(i2c); 601 602 cmd = SW_TWSI_V | SW_TWSI_SOVR | SW_TWSI_OP_7_IA; 603 /* SIZE */ 604 cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT; 605 /* A */ 606 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT; 607 608 /* Set parameters for extended message (if required) */ 609 set_ext = octeon_i2c_hlc_ext(i2c, msgs[0], &cmd, &ext); 610 611 for (i = 0, j = msgs[1].len - 1; i < msgs[1].len && i < 4; i++, j--) 612 cmd |= (u64)msgs[1].buf[j] << (8 * i); 613 614 if (msgs[1].len > 4) { 615 for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--) 616 ext |= (u64)msgs[1].buf[j] << (8 * i); 617 set_ext = true; 618 } 619 if (set_ext) 620 octeon_i2c_writeq_flush(ext, i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c)); 621 622 ret = octeon_i2c_hlc_cmd_send(i2c, cmd); 623 if (ret) 624 goto err; 625 626 cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); 627 if ((cmd & SW_TWSI_R) == 0) 628 return octeon_i2c_check_status(i2c, false); 629 630err: 631 return ret; 632} 633 634/** 635 * octeon_i2c_hlc_block_comp_read - high-level-controller composite block read 636 * @i2c: The struct octeon_i2c 637 * @msgs: msg[0] contains address, place read data into msg[1] 638 * 639 * i2c core command is constructed and written into the SW_TWSI register. 640 * The execution of the command will result in requested data being 641 * placed into a FIFO buffer, ready to be read. 642 * Used in the case where the i2c xfer is for greater than 8 bytes of read data. 643 * 644 * Returns: 0 on success, otherwise a negative errno. 645 */ 646static int octeon_i2c_hlc_block_comp_read(struct octeon_i2c *i2c, struct i2c_msg *msgs) 647{ 648 int ret; 649 u16 len, i; 650 u64 cmd; 651 652 octeon_i2c_hlc_enable(i2c); 653 octeon_i2c_block_enable(i2c); 654 655 /* Write (size - 1) into block control register */ 656 len = msgs[1].len - 1; 657 octeon_i2c_writeq_flush((u64)len, i2c->twsi_base + OCTEON_REG_BLOCK_CTL(i2c)); 658 659 /* Prepare core command */ 660 cmd = SW_TWSI_V | SW_TWSI_R | SW_TWSI_SOVR | SW_TWSI_OP_7_IA; 661 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT; 662 663 /* Send core command */ 664 ret = octeon_i2c_hlc_read_cmd(i2c, msgs[0], cmd); 665 if (ret) 666 goto err; 667 668 cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); 669 if ((cmd & SW_TWSI_R) == 0) { 670 octeon_i2c_block_disable(i2c); 671 return octeon_i2c_check_status(i2c, false); 672 } 673 674 /* read data in FIFO */ 675 octeon_i2c_writeq_flush(TWSX_BLOCK_STS_RESET_PTR, 676 i2c->twsi_base + OCTEON_REG_BLOCK_STS(i2c)); 677 for (i = 0; i <= len; i += 8) { 678 /* Byte-swap FIFO data and copy into msg buffer */ 679 __be64 rd = cpu_to_be64(__raw_readq(i2c->twsi_base + OCTEON_REG_BLOCK_FIFO(i2c))); 680 681 memcpy(&msgs[1].buf[i], &rd, min(8, msgs[1].len - i)); 682 } 683 684err: 685 octeon_i2c_block_disable(i2c); 686 return ret; 687} 688 689/** 690 * octeon_i2c_hlc_block_comp_write - high-level-controller composite block write 691 * @i2c: The struct octeon_i2c 692 * @msgs: msg[0] contains address, msg[1] contains data to be written 693 * 694 * i2c core command is constructed and write data is written into the FIFO buffer. 695 * The execution of the command will result in HW write, using the data in FIFO. 696 * Used in the case where the i2c xfer is for greater than 8 bytes of write data. 697 * 698 * Returns: 0 on success, otherwise a negative errno. 699 */ 700static int octeon_i2c_hlc_block_comp_write(struct octeon_i2c *i2c, struct i2c_msg *msgs) 701{ 702 bool set_ext; 703 int ret; 704 u16 len, i; 705 u64 cmd, ext = 0; 706 707 octeon_i2c_hlc_enable(i2c); 708 octeon_i2c_block_enable(i2c); 709 710 /* Write (size - 1) into block control register */ 711 len = msgs[1].len - 1; 712 octeon_i2c_writeq_flush((u64)len, i2c->twsi_base + OCTEON_REG_BLOCK_CTL(i2c)); 713 714 /* Prepare core command */ 715 cmd = SW_TWSI_V | SW_TWSI_SOVR | SW_TWSI_OP_7_IA; 716 cmd |= (u64)(msgs[0].addr & 0x7full) << SW_TWSI_ADDR_SHIFT; 717 718 /* Set parameters for extended message (if required) */ 719 set_ext = octeon_i2c_hlc_ext(i2c, msgs[0], &cmd, &ext); 720 721 /* Write msg into FIFO buffer */ 722 octeon_i2c_writeq_flush(TWSX_BLOCK_STS_RESET_PTR, 723 i2c->twsi_base + OCTEON_REG_BLOCK_STS(i2c)); 724 for (i = 0; i <= len; i += 8) { 725 __be64 buf = 0; 726 727 /* Copy 8 bytes or remaining bytes from message buffer */ 728 memcpy(&buf, &msgs[1].buf[i], min(8, msgs[1].len - i)); 729 730 /* Byte-swap message data and write into FIFO */ 731 buf = cpu_to_be64(buf); 732 octeon_i2c_writeq_flush((u64)buf, i2c->twsi_base + OCTEON_REG_BLOCK_FIFO(i2c)); 733 } 734 if (set_ext) 735 octeon_i2c_writeq_flush(ext, i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c)); 736 737 /* Send command to core (send data in FIFO) */ 738 ret = octeon_i2c_hlc_cmd_send(i2c, cmd); 739 if (ret) 740 goto err; 741 742 cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)); 743 if ((cmd & SW_TWSI_R) == 0) { 744 octeon_i2c_block_disable(i2c); 745 return octeon_i2c_check_status(i2c, false); 746 } 747 748err: 749 octeon_i2c_block_disable(i2c); 750 return ret; 751} 752 753/** 754 * octeon_i2c_xfer - The driver's xfer function 755 * @adap: Pointer to the i2c_adapter structure 756 * @msgs: Pointer to the messages to be processed 757 * @num: Length of the MSGS array 758 * 759 * Returns: the number of messages processed, or a negative errno on failure. 760 */ 761int octeon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 762{ 763 struct octeon_i2c *i2c = i2c_get_adapdata(adap); 764 int i, ret = 0; 765 766 if (IS_LS_FREQ(i2c->twsi_freq)) { 767 if (num == 1) { 768 if (msgs[0].len > 0 && msgs[0].len <= 8) { 769 if (msgs[0].flags & I2C_M_RD) 770 ret = octeon_i2c_hlc_read(i2c, msgs); 771 else 772 ret = octeon_i2c_hlc_write(i2c, msgs); 773 goto out; 774 } 775 } else if (num == 2) { 776 if ((msgs[0].flags & I2C_M_RD) == 0 && 777 (msgs[1].flags & I2C_M_RECV_LEN) == 0 && 778 msgs[0].len > 0 && msgs[0].len <= 2 && 779 msgs[1].len > 0 && 780 msgs[0].addr == msgs[1].addr) { 781 if (msgs[1].len <= 8) { 782 if (msgs[1].flags & I2C_M_RD) 783 ret = octeon_i2c_hlc_comp_read(i2c, msgs); 784 else 785 ret = octeon_i2c_hlc_comp_write(i2c, msgs); 786 goto out; 787 } else if (msgs[1].len <= 1024 && OCTEON_REG_BLOCK_CTL(i2c)) { 788 if (msgs[1].flags & I2C_M_RD) 789 ret = octeon_i2c_hlc_block_comp_read(i2c, msgs); 790 else 791 ret = octeon_i2c_hlc_block_comp_write(i2c, msgs); 792 goto out; 793 } 794 } 795 } 796 } 797 798 for (i = 0; ret == 0 && i < num; i++) { 799 struct i2c_msg *pmsg = &msgs[i]; 800 801 /* zero-length messages are not supported */ 802 if (!pmsg->len) { 803 ret = -EOPNOTSUPP; 804 break; 805 } 806 807 ret = octeon_i2c_start(i2c); 808 if (ret) 809 return ret; 810 811 if (pmsg->flags & I2C_M_RD) 812 ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf, 813 &pmsg->len, pmsg->flags & I2C_M_RECV_LEN); 814 else 815 ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf, 816 pmsg->len); 817 } 818 octeon_i2c_stop(i2c); 819out: 820 return (ret != 0) ? ret : num; 821} 822 823/* calculate and set clock divisors */ 824void octeon_i2c_set_clock(struct octeon_i2c *i2c) 825{ 826 int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff; 827 bool is_plat_otx2; 828 /* 829 * Find divisors to produce target frequency, start with large delta 830 * to cover wider range of divisors, note thp = TCLK half period and 831 * ds is OSCL output frequency divisor. 832 */ 833 unsigned int thp, mdiv_min, mdiv = 2, ndiv = 0, ds = 10; 834 unsigned int delta_hz = INITIAL_DELTA_HZ; 835 836 is_plat_otx2 = octeon_i2c_is_otx2(to_pci_dev(i2c->dev)); 837 838 if (is_plat_otx2) { 839 thp = TWSI_MASTER_CLK_REG_OTX2_VAL; 840 mdiv_min = 0; 841 if (!IS_LS_FREQ(i2c->twsi_freq)) 842 ds = 15; 843 } else { 844 thp = TWSI_MASTER_CLK_REG_DEF_VAL; 845 mdiv_min = 2; 846 } 847 848 for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) { 849 /* 850 * An mdiv value of less than 2 seems to not work well 851 * with ds1337 RTCs, so we constrain it to larger values. 852 */ 853 for (mdiv_idx = 15; mdiv_idx >= mdiv_min && delta_hz != 0; mdiv_idx--) { 854 /* 855 * For given ndiv and mdiv values check the 856 * two closest thp values. 857 */ 858 tclk = i2c->twsi_freq * (mdiv_idx + 1) * ds; 859 tclk *= (1 << ndiv_idx); 860 if (is_plat_otx2) 861 thp_base = (i2c->sys_freq / tclk) - 2; 862 else 863 thp_base = (i2c->sys_freq / (tclk * 2)) - 1; 864 865 for (inc = 0; inc <= 1; inc++) { 866 thp_idx = thp_base + inc; 867 if (thp_idx < 5 || thp_idx > 0xff) 868 continue; 869 870 if (is_plat_otx2) 871 foscl = i2c->sys_freq / (thp_idx + 2); 872 else 873 foscl = i2c->sys_freq / 874 (2 * (thp_idx + 1)); 875 foscl = foscl / (1 << ndiv_idx); 876 foscl = foscl / (mdiv_idx + 1) / ds; 877 if (foscl > i2c->twsi_freq) 878 continue; 879 diff = abs(foscl - i2c->twsi_freq); 880 /* 881 * Diff holds difference between calculated frequency 882 * value vs desired frequency. 883 * Delta_hz is updated with last minimum diff. 884 */ 885 if (diff < delta_hz) { 886 delta_hz = diff; 887 thp = thp_idx; 888 mdiv = mdiv_idx; 889 ndiv = ndiv_idx; 890 } 891 } 892 } 893 } 894 octeon_i2c_reg_write(i2c, SW_TWSI_OP_TWSI_CLK, thp); 895 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv); 896 if (is_plat_otx2) { 897 u64 mode; 898 899 mode = __raw_readq(i2c->twsi_base + OCTEON_REG_MODE(i2c)); 900 /* Set REFCLK_SRC and HS_MODE in TWSX_MODE register */ 901 if (!IS_LS_FREQ(i2c->twsi_freq)) 902 mode |= TWSX_MODE_HS_MASK; 903 else 904 mode &= ~TWSX_MODE_HS_MASK; 905 octeon_i2c_writeq_flush(mode, i2c->twsi_base + OCTEON_REG_MODE(i2c)); 906 } 907} 908 909int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c) 910{ 911 u8 status = 0; 912 int tries; 913 914 /* reset controller */ 915 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0); 916 917 for (tries = 10; tries && status != STAT_IDLE; tries--) { 918 udelay(1); 919 status = octeon_i2c_stat_read(i2c); 920 if (status == STAT_IDLE) 921 break; 922 } 923 924 if (status != STAT_IDLE) { 925 dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n", 926 __func__, status); 927 return -EIO; 928 } 929 930 /* toggle twice to force both teardowns */ 931 octeon_i2c_hlc_enable(i2c); 932 octeon_i2c_hlc_disable(i2c); 933 return 0; 934} 935 936static int octeon_i2c_get_scl(struct i2c_adapter *adap) 937{ 938 struct octeon_i2c *i2c = i2c_get_adapdata(adap); 939 u64 state; 940 941 state = octeon_i2c_read_int(i2c); 942 return state & TWSI_INT_SCL; 943} 944 945static void octeon_i2c_set_scl(struct i2c_adapter *adap, int val) 946{ 947 struct octeon_i2c *i2c = i2c_get_adapdata(adap); 948 949 octeon_i2c_write_int(i2c, val ? 0 : TWSI_INT_SCL_OVR); 950} 951 952static int octeon_i2c_get_sda(struct i2c_adapter *adap) 953{ 954 struct octeon_i2c *i2c = i2c_get_adapdata(adap); 955 u64 state; 956 957 state = octeon_i2c_read_int(i2c); 958 return state & TWSI_INT_SDA; 959} 960 961static void octeon_i2c_prepare_recovery(struct i2c_adapter *adap) 962{ 963 struct octeon_i2c *i2c = i2c_get_adapdata(adap); 964 965 octeon_i2c_hlc_disable(i2c); 966 octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0); 967 /* wait for software reset to settle */ 968 udelay(5); 969 970 /* 971 * Bring control register to a good state regardless 972 * of HLC state. 973 */ 974 octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB); 975 976 octeon_i2c_write_int(i2c, 0); 977} 978 979static void octeon_i2c_unprepare_recovery(struct i2c_adapter *adap) 980{ 981 struct octeon_i2c *i2c = i2c_get_adapdata(adap); 982 983 /* 984 * Generate STOP to finish the unfinished transaction. 985 * Can't generate STOP via the TWSI CTL register 986 * since it could bring the TWSI controller into an inoperable state. 987 */ 988 octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR | TWSI_INT_SCL_OVR); 989 udelay(5); 990 octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR); 991 udelay(5); 992 octeon_i2c_write_int(i2c, 0); 993} 994 995struct i2c_bus_recovery_info octeon_i2c_recovery_info = { 996 .recover_bus = i2c_generic_scl_recovery, 997 .get_scl = octeon_i2c_get_scl, 998 .set_scl = octeon_i2c_set_scl, 999 .get_sda = octeon_i2c_get_sda, 1000 .prepare_recovery = octeon_i2c_prepare_recovery, 1001 .unprepare_recovery = octeon_i2c_unprepare_recovery, 1002};
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