i2c-npcm7xx.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Nuvoton NPCM7xx I2C Controller driver
   4 *
   5 * Copyright (C) 2020 Nuvoton Technologies tali.perry@nuvoton.com
   6 */
   7#include <linux/bitfield.h>
   8#include <linux/clk.h>
   9#include <linux/debugfs.h>
  10#include <linux/errno.h>
  11#include <linux/i2c.h>
  12#include <linux/interrupt.h>
  13#include <linux/iopoll.h>
  14#include <linux/irq.h>
  15#include <linux/jiffies.h>
  16#include <linux/kernel.h>
  17#include <linux/mfd/syscon.h>
  18#include <linux/module.h>
  19#include <linux/of.h>
  20#include <linux/platform_device.h>
  21#include <linux/regmap.h>
  22
  23enum i2c_mode {
  24	I2C_MASTER,
  25	I2C_SLAVE,
  26};
  27
  28/*
  29 * External I2C Interface driver xfer indication values, which indicate status
  30 * of the bus.
  31 */
  32enum i2c_state_ind {
  33	I2C_NO_STATUS_IND = 0,
  34	I2C_SLAVE_RCV_IND,
  35	I2C_SLAVE_XMIT_IND,
  36	I2C_SLAVE_XMIT_MISSING_DATA_IND,
  37	I2C_SLAVE_RESTART_IND,
  38	I2C_SLAVE_DONE_IND,
  39	I2C_MASTER_DONE_IND,
  40	I2C_NACK_IND,
  41	I2C_BUS_ERR_IND,
  42	I2C_WAKE_UP_IND,
  43	I2C_BLOCK_BYTES_ERR_IND,
  44	I2C_SLAVE_RCV_MISSING_DATA_IND,
  45};
  46
  47/*
  48 * Operation type values (used to define the operation currently running)
  49 * module is interrupt driven, on each interrupt the current operation is
  50 * checked to see if the module is currently reading or writing.
  51 */
  52enum i2c_oper {
  53	I2C_NO_OPER = 0,
  54	I2C_WRITE_OPER,
  55	I2C_READ_OPER,
  56};
  57
  58/* I2C Bank (module had 2 banks of registers) */
  59enum i2c_bank {
  60	I2C_BANK_0 = 0,
  61	I2C_BANK_1,
  62};
  63
  64/* Internal I2C states values (for the I2C module state machine). */
  65enum i2c_state {
  66	I2C_DISABLE = 0,
  67	I2C_IDLE,
  68	I2C_MASTER_START,
  69	I2C_SLAVE_MATCH,
  70	I2C_OPER_STARTED,
  71	I2C_STOP_PENDING,
  72};
  73
  74#if IS_ENABLED(CONFIG_I2C_SLAVE)
  75/* Module supports setting multiple own slave addresses */
  76enum i2c_addr {
  77	I2C_SLAVE_ADDR1 = 0,
  78	I2C_SLAVE_ADDR2,
  79	I2C_SLAVE_ADDR3,
  80	I2C_SLAVE_ADDR4,
  81	I2C_SLAVE_ADDR5,
  82	I2C_SLAVE_ADDR6,
  83	I2C_SLAVE_ADDR7,
  84	I2C_SLAVE_ADDR8,
  85	I2C_SLAVE_ADDR9,
  86	I2C_SLAVE_ADDR10,
  87	I2C_GC_ADDR,
  88	I2C_ARP_ADDR,
  89};
  90#endif
  91
  92/* init register and default value required to enable module */
  93#define NPCM_I2CSEGCTL			0xE4
  94
  95/* Common regs */
  96#define NPCM_I2CSDA			0x00
  97#define NPCM_I2CST			0x02
  98#define NPCM_I2CCST			0x04
  99#define NPCM_I2CCTL1			0x06
 100#define NPCM_I2CADDR1			0x08
 101#define NPCM_I2CCTL2			0x0A
 102#define NPCM_I2CADDR2			0x0C
 103#define NPCM_I2CCTL3			0x0E
 104#define NPCM_I2CCST2			0x18
 105#define NPCM_I2CCST3			0x19
 106#define I2C_VER				0x1F
 107
 108/* BANK 0 regs */
 109#define NPCM_I2CADDR3			0x10
 110#define NPCM_I2CADDR7			0x11
 111#define NPCM_I2CADDR4			0x12
 112#define NPCM_I2CADDR8			0x13
 113#define NPCM_I2CADDR5			0x14
 114#define NPCM_I2CADDR9			0x15
 115#define NPCM_I2CADDR6			0x16
 116#define NPCM_I2CADDR10			0x17
 117#define NPCM_I2CCTL4			0x1A
 118#define NPCM_I2CCTL5			0x1B
 119#define NPCM_I2CSCLLT			0x1C /* SCL Low Time */
 120#define NPCM_I2CFIF_CTL			0x1D /* FIFO Control */
 121#define NPCM_I2CSCLHT			0x1E /* SCL High Time */
 122
 123/* BANK 1 regs */
 124#define NPCM_I2CFIF_CTS			0x10 /* Both FIFOs Control and Status */
 125#define NPCM_I2CTXF_CTL			0x12 /* Tx-FIFO Control */
 126#define NPCM_I2CT_OUT			0x14 /* Bus T.O. */
 127#define NPCM_I2CPEC			0x16 /* PEC Data */
 128#define NPCM_I2CTXF_STS			0x1A /* Tx-FIFO Status */
 129#define NPCM_I2CRXF_STS			0x1C /* Rx-FIFO Status */
 130#define NPCM_I2CRXF_CTL			0x1E /* Rx-FIFO Control */
 131
 132#if IS_ENABLED(CONFIG_I2C_SLAVE)
 133/*
 134 * npcm_i2caddr array:
 135 * The module supports having multiple own slave addresses.
 136 * Since the addr regs are sprinkled all over the address space,
 137 * use this array to get the address or each register.
 138 */
 139#define I2C_NUM_OWN_ADDR 10
 140#define I2C_NUM_OWN_ADDR_SUPPORTED 2
 141
 142static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = {
 143	NPCM_I2CADDR1, NPCM_I2CADDR2, NPCM_I2CADDR3, NPCM_I2CADDR4,
 144	NPCM_I2CADDR5, NPCM_I2CADDR6, NPCM_I2CADDR7, NPCM_I2CADDR8,
 145	NPCM_I2CADDR9, NPCM_I2CADDR10,
 146};
 147#endif
 148
 149/* NPCM_I2CST reg fields */
 150#define NPCM_I2CST_XMIT			BIT(0)	/* Transmit mode */
 151#define NPCM_I2CST_MASTER		BIT(1)	/* Master mode */
 152#define NPCM_I2CST_NMATCH		BIT(2)	/* New match */
 153#define NPCM_I2CST_STASTR		BIT(3)	/* Stall after start */
 154#define NPCM_I2CST_NEGACK		BIT(4)	/* Negative ACK */
 155#define NPCM_I2CST_BER			BIT(5)	/* Bus error */
 156#define NPCM_I2CST_SDAST		BIT(6)	/* SDA status */
 157#define NPCM_I2CST_SLVSTP		BIT(7)	/* Slave stop */
 158
 159/* NPCM_I2CCST reg fields */
 160#define NPCM_I2CCST_BUSY		BIT(0)	/* Busy */
 161#define NPCM_I2CCST_BB			BIT(1)	/* Bus busy */
 162#define NPCM_I2CCST_MATCH		BIT(2)	/* Address match */
 163#define NPCM_I2CCST_GCMATCH		BIT(3)	/* Global call match */
 164#define NPCM_I2CCST_TSDA		BIT(4)	/* Test SDA line */
 165#define NPCM_I2CCST_TGSCL		BIT(5)	/* Toggle SCL line */
 166#define NPCM_I2CCST_MATCHAF		BIT(6)	/* Match address field */
 167#define NPCM_I2CCST_ARPMATCH		BIT(7)	/* ARP address match */
 168
 169/* NPCM_I2CCTL1 reg fields */
 170#define NPCM_I2CCTL1_START		BIT(0)	/* Generate start condition */
 171#define NPCM_I2CCTL1_STOP		BIT(1)	/* Generate stop condition */
 172#define NPCM_I2CCTL1_INTEN		BIT(2)	/* Interrupt enable */
 173#define NPCM_I2CCTL1_EOBINTE		BIT(3)
 174#define NPCM_I2CCTL1_ACK		BIT(4)
 175#define NPCM_I2CCTL1_GCMEN		BIT(5)	/* Global call match enable */
 176#define NPCM_I2CCTL1_NMINTE		BIT(6)	/* New match interrupt enable */
 177#define NPCM_I2CCTL1_STASTRE		BIT(7)	/* Stall after start enable */
 178
 179/* RW1S fields (inside a RW reg): */
 180#define NPCM_I2CCTL1_RWS   \
 181	(NPCM_I2CCTL1_START | NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK)
 182
 183/* npcm_i2caddr reg fields */
 184#define NPCM_I2CADDR_A			GENMASK(6, 0)	/* Address */
 185#define NPCM_I2CADDR_SAEN		BIT(7)		/* Slave address enable */
 186
 187/* NPCM_I2CCTL2 reg fields */
 188#define I2CCTL2_ENABLE			BIT(0)		/* Module enable */
 189#define I2CCTL2_SCLFRQ6_0		GENMASK(7, 1)	/* Bits 0:6 of frequency divisor */
 190
 191/* NPCM_I2CCTL3 reg fields */
 192#define I2CCTL3_SCLFRQ8_7		GENMASK(1, 0)	/* Bits 7:8 of frequency divisor */
 193#define I2CCTL3_ARPMEN			BIT(2)	/* ARP match enable */
 194#define I2CCTL3_IDL_START		BIT(3)
 195#define I2CCTL3_400K_MODE		BIT(4)
 196#define I2CCTL3_BNK_SEL			BIT(5)
 197#define I2CCTL3_SDA_LVL			BIT(6)
 198#define I2CCTL3_SCL_LVL			BIT(7)
 199
 200/* NPCM_I2CCST2 reg fields */
 201#define NPCM_I2CCST2_MATCHA1F		BIT(0)
 202#define NPCM_I2CCST2_MATCHA2F		BIT(1)
 203#define NPCM_I2CCST2_MATCHA3F		BIT(2)
 204#define NPCM_I2CCST2_MATCHA4F		BIT(3)
 205#define NPCM_I2CCST2_MATCHA5F		BIT(4)
 206#define NPCM_I2CCST2_MATCHA6F		BIT(5)
 207#define NPCM_I2CCST2_MATCHA7F		BIT(5)
 208#define NPCM_I2CCST2_INTSTS		BIT(7)
 209
 210/* NPCM_I2CCST3 reg fields */
 211#define NPCM_I2CCST3_MATCHA8F		BIT(0)
 212#define NPCM_I2CCST3_MATCHA9F		BIT(1)
 213#define NPCM_I2CCST3_MATCHA10F		BIT(2)
 214#define NPCM_I2CCST3_EO_BUSY		BIT(7)
 215
 216/* NPCM_I2CCTL4 reg fields */
 217#define I2CCTL4_HLDT			GENMASK(5, 0)
 218#define I2CCTL4_LVL_WE			BIT(7)
 219
 220/* NPCM_I2CCTL5 reg fields */
 221#define I2CCTL5_DBNCT			GENMASK(3, 0)
 222
 223/* NPCM_I2CFIF_CTS reg fields */
 224#define NPCM_I2CFIF_CTS_RXF_TXE		BIT(1)
 225#define NPCM_I2CFIF_CTS_RFTE_IE		BIT(3)
 226#define NPCM_I2CFIF_CTS_CLR_FIFO	BIT(6)
 227#define NPCM_I2CFIF_CTS_SLVRSTR		BIT(7)
 228
 229/* NPCM_I2CTXF_CTL reg field */
 230#define NPCM_I2CTXF_CTL_THR_TXIE	BIT(6)
 231
 232/* NPCM_I2CT_OUT reg fields */
 233#define NPCM_I2CT_OUT_TO_CKDIV		GENMASK(5, 0)
 234#define NPCM_I2CT_OUT_T_OUTIE		BIT(6)
 235#define NPCM_I2CT_OUT_T_OUTST		BIT(7)
 236
 237/* NPCM_I2CTXF_STS reg fields */
 238#define NPCM_I2CTXF_STS_TX_THST		BIT(6)
 239
 240/* NPCM_I2CRXF_STS reg fields */
 241#define NPCM_I2CRXF_STS_RX_THST		BIT(6)
 242
 243/* NPCM_I2CFIF_CTL reg fields */
 244#define NPCM_I2CFIF_CTL_FIFO_EN		BIT(4)
 245
 246/* NPCM_I2CRXF_CTL reg fields */
 247#define NPCM_I2CRXF_CTL_THR_RXIE	BIT(6)
 248
 249#define MAX_I2C_HW_FIFO_SIZE		32
 250
 251/* I2C_VER reg fields */
 252#define I2C_VER_VERSION			GENMASK(6, 0)
 253#define I2C_VER_FIFO_EN			BIT(7)
 254
 255/* stall/stuck timeout in us */
 256#define DEFAULT_STALL_COUNT		25
 257
 258/* SCLFRQ field position */
 259#define SCLFRQ_0_TO_6			GENMASK(6, 0)
 260#define SCLFRQ_7_TO_8			GENMASK(8, 7)
 261
 262/* supported clk settings. values in Hz. */
 263#define I2C_FREQ_MIN_HZ			10000
 264#define I2C_FREQ_MAX_HZ			I2C_MAX_FAST_MODE_PLUS_FREQ
 265
 266struct smb_timing_t {
 267	u32 core_clk;
 268	u8 hldt;
 269	u8 dbcnt;
 270	u16 sclfrq;
 271	u8 scllt;
 272	u8 sclht;
 273	bool fast_mode;
 274};
 275
 276static struct smb_timing_t smb_timing_100khz[] = {
 277	{
 278		.core_clk = 100000000, .hldt = 0x2A, .dbcnt = 0x4,
 279		.sclfrq = 0xFB, .scllt = 0x0, .sclht = 0x0,
 280		.fast_mode = false,
 281	},
 282	{
 283		.core_clk = 62500000, .hldt = 0x2A, .dbcnt = 0x1,
 284		.sclfrq = 0x9D, .scllt = 0x0, .sclht = 0x0,
 285		.fast_mode = false,
 286	},
 287	{
 288		.core_clk = 50000000, .hldt = 0x2A, .dbcnt = 0x1,
 289		.sclfrq = 0x7E, .scllt = 0x0, .sclht = 0x0,
 290		.fast_mode = false,
 291	},
 292	{
 293		.core_clk = 48000000, .hldt = 0x2A, .dbcnt = 0x1,
 294		.sclfrq = 0x79, .scllt = 0x0, .sclht = 0x0,
 295		.fast_mode = false,
 296	},
 297	{
 298		.core_clk = 40000000, .hldt = 0x2A, .dbcnt = 0x1,
 299		.sclfrq = 0x65, .scllt = 0x0, .sclht = 0x0,
 300		.fast_mode = false,
 301	},
 302	{
 303		.core_clk = 30000000, .hldt = 0x2A, .dbcnt = 0x1,
 304		.sclfrq = 0x4C, .scllt = 0x0, .sclht = 0x0,
 305		.fast_mode = false,
 306	},
 307	{
 308		.core_clk = 29000000, .hldt = 0x2A, .dbcnt = 0x1,
 309		.sclfrq = 0x49, .scllt = 0x0, .sclht = 0x0,
 310		.fast_mode = false,
 311	},
 312	{
 313		.core_clk = 26000000, .hldt = 0x2A, .dbcnt = 0x1,
 314		.sclfrq = 0x42, .scllt = 0x0, .sclht = 0x0,
 315		.fast_mode = false,
 316	},
 317	{
 318		.core_clk = 25000000, .hldt = 0x2A, .dbcnt = 0x1,
 319		.sclfrq = 0x3F, .scllt = 0x0, .sclht = 0x0,
 320		.fast_mode = false,
 321	},
 322	{
 323		.core_clk = 24000000, .hldt = 0x2A, .dbcnt = 0x1,
 324		.sclfrq = 0x3D, .scllt = 0x0, .sclht = 0x0,
 325		.fast_mode = false,
 326	},
 327	{
 328		.core_clk = 20000000, .hldt = 0x2A, .dbcnt = 0x1,
 329		.sclfrq = 0x33, .scllt = 0x0, .sclht = 0x0,
 330		.fast_mode = false,
 331	},
 332	{
 333		.core_clk = 16180000, .hldt = 0x2A, .dbcnt = 0x1,
 334		.sclfrq = 0x29, .scllt = 0x0, .sclht = 0x0,
 335		.fast_mode = false,
 336	},
 337	{
 338		.core_clk = 15000000, .hldt = 0x23, .dbcnt = 0x1,
 339		.sclfrq = 0x26, .scllt = 0x0, .sclht = 0x0,
 340		.fast_mode = false,
 341	},
 342	{
 343		.core_clk = 13000000, .hldt = 0x1D, .dbcnt = 0x1,
 344		.sclfrq = 0x21, .scllt = 0x0, .sclht = 0x0,
 345		.fast_mode = false,
 346	},
 347	{
 348		.core_clk = 12000000, .hldt = 0x1B, .dbcnt = 0x1,
 349		.sclfrq = 0x1F, .scllt = 0x0, .sclht = 0x0,
 350		.fast_mode = false,
 351	},
 352	{
 353		.core_clk = 10000000, .hldt = 0x18, .dbcnt = 0x1,
 354		.sclfrq = 0x1A, .scllt = 0x0, .sclht = 0x0,
 355		.fast_mode = false,
 356	},
 357	{
 358		.core_clk = 9000000, .hldt = 0x16, .dbcnt = 0x1,
 359		.sclfrq = 0x17, .scllt = 0x0, .sclht = 0x0,
 360		.fast_mode = false,
 361	},
 362	{
 363		.core_clk = 8090000, .hldt = 0x14, .dbcnt = 0x1,
 364		.sclfrq = 0x15, .scllt = 0x0, .sclht = 0x0,
 365		.fast_mode = false,
 366	},
 367	{
 368		.core_clk = 7500000, .hldt = 0x7, .dbcnt = 0x1,
 369		.sclfrq = 0x13, .scllt = 0x0, .sclht = 0x0,
 370		.fast_mode = false,
 371	},
 372	{
 373		.core_clk = 6500000, .hldt = 0xE, .dbcnt = 0x1,
 374		.sclfrq = 0x11, .scllt = 0x0, .sclht = 0x0,
 375		.fast_mode = false,
 376	},
 377	{
 378		.core_clk = 4000000, .hldt = 0x9, .dbcnt = 0x1,
 379		.sclfrq = 0xB, .scllt = 0x0, .sclht = 0x0,
 380		.fast_mode = false,
 381	},
 382};
 383
 384static struct smb_timing_t smb_timing_400khz[] = {
 385	{
 386		.core_clk = 100000000, .hldt = 0x2A, .dbcnt = 0x3,
 387		.sclfrq = 0x0, .scllt = 0x47, .sclht = 0x35,
 388		.fast_mode = true,
 389	},
 390	{
 391		.core_clk = 62500000, .hldt = 0x2A, .dbcnt = 0x2,
 392		.sclfrq = 0x0, .scllt = 0x2C, .sclht = 0x22,
 393		.fast_mode = true,
 394	},
 395	{
 396		.core_clk = 50000000, .hldt = 0x21, .dbcnt = 0x1,
 397		.sclfrq = 0x0, .scllt = 0x24, .sclht = 0x1B,
 398		.fast_mode = true,
 399	},
 400	{
 401		.core_clk = 48000000, .hldt = 0x1E, .dbcnt = 0x1,
 402		.sclfrq = 0x0, .scllt = 0x24, .sclht = 0x19,
 403		.fast_mode = true,
 404	},
 405	{
 406		.core_clk = 40000000, .hldt = 0x1B, .dbcnt = 0x1,
 407		.sclfrq = 0x0, .scllt = 0x1E, .sclht = 0x14,
 408		.fast_mode = true,
 409	},
 410	{
 411		.core_clk = 33000000, .hldt = 0x15, .dbcnt = 0x1,
 412		.sclfrq = 0x0, .scllt = 0x19, .sclht = 0x11,
 413		.fast_mode = true,
 414	},
 415	{
 416		.core_clk = 30000000, .hldt = 0x15, .dbcnt = 0x1,
 417		.sclfrq = 0x0, .scllt = 0x19, .sclht = 0xD,
 418		.fast_mode = true,
 419	},
 420	{
 421		.core_clk = 29000000, .hldt = 0x11, .dbcnt = 0x1,
 422		.sclfrq = 0x0, .scllt = 0x15, .sclht = 0x10,
 423		.fast_mode = true,
 424	},
 425	{
 426		.core_clk = 26000000, .hldt = 0x10, .dbcnt = 0x1,
 427		.sclfrq = 0x0, .scllt = 0x13, .sclht = 0xE,
 428		.fast_mode = true,
 429	},
 430	{
 431		.core_clk = 25000000, .hldt = 0xF, .dbcnt = 0x1,
 432		.sclfrq = 0x0, .scllt = 0x13, .sclht = 0xD,
 433		.fast_mode = true,
 434	},
 435	{
 436		.core_clk = 24000000, .hldt = 0xD, .dbcnt = 0x1,
 437		.sclfrq = 0x0, .scllt = 0x12, .sclht = 0xD,
 438		.fast_mode = true,
 439	},
 440	{
 441		.core_clk = 20000000, .hldt = 0xB, .dbcnt = 0x1,
 442		.sclfrq = 0x0, .scllt = 0xF, .sclht = 0xA,
 443		.fast_mode = true,
 444	},
 445	{
 446		.core_clk = 16180000, .hldt = 0xA, .dbcnt = 0x1,
 447		.sclfrq = 0x0, .scllt = 0xC, .sclht = 0x9,
 448		.fast_mode = true,
 449	},
 450	{
 451		.core_clk = 15000000, .hldt = 0x9, .dbcnt = 0x1,
 452		.sclfrq = 0x0, .scllt = 0xB, .sclht = 0x8,
 453		.fast_mode = true,
 454	},
 455	{
 456		.core_clk = 13000000, .hldt = 0x7, .dbcnt = 0x1,
 457		.sclfrq = 0x0, .scllt = 0xA, .sclht = 0x7,
 458		.fast_mode = true,
 459	},
 460	{
 461		.core_clk = 12000000, .hldt = 0x7, .dbcnt = 0x1,
 462		.sclfrq = 0x0, .scllt = 0xA, .sclht = 0x6,
 463		.fast_mode = true,
 464	},
 465	{
 466		.core_clk = 10000000, .hldt = 0x6, .dbcnt = 0x1,
 467		.sclfrq = 0x0, .scllt = 0x8, .sclht = 0x5,
 468		.fast_mode = true,
 469	},
 470};
 471
 472static struct smb_timing_t smb_timing_1000khz[] = {
 473	{
 474		.core_clk = 100000000, .hldt = 0x15, .dbcnt = 0x4,
 475		.sclfrq = 0x0, .scllt = 0x1C, .sclht = 0x15,
 476		.fast_mode = true,
 477	},
 478	{
 479		.core_clk = 62500000, .hldt = 0xF, .dbcnt = 0x3,
 480		.sclfrq = 0x0, .scllt = 0x11, .sclht = 0xE,
 481		.fast_mode = true,
 482	},
 483	{
 484		.core_clk = 50000000, .hldt = 0xA, .dbcnt = 0x2,
 485		.sclfrq = 0x0, .scllt = 0xE, .sclht = 0xB,
 486		.fast_mode = true,
 487	},
 488	{
 489		.core_clk = 48000000, .hldt = 0x9, .dbcnt = 0x2,
 490		.sclfrq = 0x0, .scllt = 0xD, .sclht = 0xB,
 491		.fast_mode = true,
 492	},
 493	{
 494		.core_clk = 41000000, .hldt = 0x9, .dbcnt = 0x2,
 495		.sclfrq = 0x0, .scllt = 0xC, .sclht = 0x9,
 496		.fast_mode = true,
 497	},
 498	{
 499		.core_clk = 40000000, .hldt = 0x8, .dbcnt = 0x2,
 500		.sclfrq = 0x0, .scllt = 0xB, .sclht = 0x9,
 501		.fast_mode = true,
 502	},
 503	{
 504		.core_clk = 33000000, .hldt = 0x7, .dbcnt = 0x1,
 505		.sclfrq = 0x0, .scllt = 0xA, .sclht = 0x7,
 506		.fast_mode = true,
 507	},
 508	{
 509		.core_clk = 25000000, .hldt = 0x4, .dbcnt = 0x1,
 510		.sclfrq = 0x0, .scllt = 0x7, .sclht = 0x6,
 511		.fast_mode = true,
 512	},
 513	{
 514		.core_clk = 24000000, .hldt = 0x7, .dbcnt = 0x1,
 515		.sclfrq = 0x0, .scllt = 0x8, .sclht = 0x5,
 516		.fast_mode = true,
 517	},
 518	{
 519		.core_clk = 20000000, .hldt = 0x4, .dbcnt = 0x1,
 520		.sclfrq = 0x0, .scllt = 0x6, .sclht = 0x4,
 521		.fast_mode = true,
 522	},
 523};
 524
 525struct npcm_i2c_data {
 526	u8 fifo_size;
 527	u32 segctl_init_val;
 528	u8 txf_sts_tx_bytes;
 529	u8 rxf_sts_rx_bytes;
 530	u8 rxf_ctl_last_pec;
 531};
 532
 533static const struct npcm_i2c_data npxm7xx_i2c_data = {
 534	.fifo_size = 16,
 535	.segctl_init_val = 0x0333F000,
 536	.txf_sts_tx_bytes = GENMASK(4, 0),
 537	.rxf_sts_rx_bytes = GENMASK(4, 0),
 538	.rxf_ctl_last_pec = BIT(5),
 539};
 540
 541static const struct npcm_i2c_data npxm8xx_i2c_data = {
 542	.fifo_size = 32,
 543	.segctl_init_val = 0x9333F000,
 544	.txf_sts_tx_bytes = GENMASK(5, 0),
 545	.rxf_sts_rx_bytes = GENMASK(5, 0),
 546	.rxf_ctl_last_pec = BIT(7),
 547};
 548
 549/* Status of one I2C module */
 550struct npcm_i2c {
 551	struct i2c_adapter adap;
 552	struct device *dev;
 553	unsigned char __iomem *reg;
 554	const struct npcm_i2c_data *data;
 555	spinlock_t lock;   /* IRQ synchronization */
 556	struct completion cmd_complete;
 557	int cmd_err;
 558	struct i2c_msg *msgs;
 559	int msgs_num;
 560	int num;
 561	u32 apb_clk;
 562	struct i2c_bus_recovery_info rinfo;
 563	enum i2c_state state;
 564	enum i2c_oper operation;
 565	enum i2c_mode master_or_slave;
 566	enum i2c_state_ind stop_ind;
 567	u8 dest_addr;
 568	u8 *rd_buf;
 569	u16 rd_size;
 570	u16 rd_ind;
 571	u8 *wr_buf;
 572	u16 wr_size;
 573	u16 wr_ind;
 574	bool fifo_use;
 575	u16 PEC_mask; /* PEC bit mask per slave address */
 576	bool PEC_use;
 577	bool read_block_use;
 578	unsigned long int_time_stamp;
 579	unsigned long bus_freq; /* in Hz */
 580#if IS_ENABLED(CONFIG_I2C_SLAVE)
 581	u8 own_slave_addr;
 582	struct i2c_client *slave;
 583	int slv_rd_size;
 584	int slv_rd_ind;
 585	int slv_wr_size;
 586	int slv_wr_ind;
 587	u8 slv_rd_buf[MAX_I2C_HW_FIFO_SIZE];
 588	u8 slv_wr_buf[MAX_I2C_HW_FIFO_SIZE];
 589#endif
 590	u64 ber_cnt;
 591	u64 rec_succ_cnt;
 592	u64 rec_fail_cnt;
 593	u64 nack_cnt;
 594	u64 timeout_cnt;
 595	u64 tx_complete_cnt;
 596	bool ber_state; /* Indicate the bus error state */
 597};
 598
 599static inline void npcm_i2c_select_bank(struct npcm_i2c *bus,
 600					enum i2c_bank bank)
 601{
 602	u8 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
 603
 604	if (bank == I2C_BANK_0)
 605		i2cctl3 = i2cctl3 & ~I2CCTL3_BNK_SEL;
 606	else
 607		i2cctl3 = i2cctl3 | I2CCTL3_BNK_SEL;
 608	iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
 609}
 610
 611static void npcm_i2c_init_params(struct npcm_i2c *bus)
 612{
 613	bus->stop_ind = I2C_NO_STATUS_IND;
 614	bus->rd_size = 0;
 615	bus->wr_size = 0;
 616	bus->rd_ind = 0;
 617	bus->wr_ind = 0;
 618	bus->read_block_use = false;
 619	bus->int_time_stamp = 0;
 620	bus->PEC_use = false;
 621	bus->PEC_mask = 0;
 622#if IS_ENABLED(CONFIG_I2C_SLAVE)
 623	if (bus->slave)
 624		bus->master_or_slave = I2C_SLAVE;
 625#endif
 626}
 627
 628static inline void npcm_i2c_wr_byte(struct npcm_i2c *bus, u8 data)
 629{
 630	iowrite8(data, bus->reg + NPCM_I2CSDA);
 631}
 632
 633static inline u8 npcm_i2c_rd_byte(struct npcm_i2c *bus)
 634{
 635	return ioread8(bus->reg + NPCM_I2CSDA);
 636}
 637
 638static int npcm_i2c_get_SCL(struct i2c_adapter *_adap)
 639{
 640	struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
 641
 642	return !!(I2CCTL3_SCL_LVL & ioread8(bus->reg + NPCM_I2CCTL3));
 643}
 644
 645static int npcm_i2c_get_SDA(struct i2c_adapter *_adap)
 646{
 647	struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
 648
 649	return !!(I2CCTL3_SDA_LVL & ioread8(bus->reg + NPCM_I2CCTL3));
 650}
 651
 652static inline u16 npcm_i2c_get_index(struct npcm_i2c *bus)
 653{
 654	if (bus->operation == I2C_READ_OPER)
 655		return bus->rd_ind;
 656	if (bus->operation == I2C_WRITE_OPER)
 657		return bus->wr_ind;
 658	return 0;
 659}
 660
 661/* quick protocol (just address) */
 662static inline bool npcm_i2c_is_quick(struct npcm_i2c *bus)
 663{
 664	return bus->wr_size == 0 && bus->rd_size == 0;
 665}
 666
 667static void npcm_i2c_disable(struct npcm_i2c *bus)
 668{
 669	u8 i2cctl2;
 670
 671#if IS_ENABLED(CONFIG_I2C_SLAVE)
 672	int i;
 673
 674	/* Slave addresses removal */
 675	for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++)
 676		iowrite8(0, bus->reg + npcm_i2caddr[i]);
 677
 678#endif
 679	/* Disable module */
 680	i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
 681	i2cctl2 = i2cctl2 & ~I2CCTL2_ENABLE;
 682	iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
 683
 684	bus->state = I2C_DISABLE;
 685}
 686
 687static void npcm_i2c_enable(struct npcm_i2c *bus)
 688{
 689	u8 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
 690
 691	i2cctl2 = i2cctl2 | I2CCTL2_ENABLE;
 692	iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
 693	bus->state = I2C_IDLE;
 694}
 695
 696/* enable\disable end of busy (EOB) interrupts */
 697static inline void npcm_i2c_eob_int(struct npcm_i2c *bus, bool enable)
 698{
 699	u8 val;
 700
 701	/* Clear EO_BUSY pending bit: */
 702	val = ioread8(bus->reg + NPCM_I2CCST3);
 703	val = val | NPCM_I2CCST3_EO_BUSY;
 704	iowrite8(val, bus->reg + NPCM_I2CCST3);
 705
 706	val = ioread8(bus->reg + NPCM_I2CCTL1);
 707	val &= ~NPCM_I2CCTL1_RWS;
 708	if (enable)
 709		val |= NPCM_I2CCTL1_EOBINTE;
 710	else
 711		val &= ~NPCM_I2CCTL1_EOBINTE;
 712	iowrite8(val, bus->reg + NPCM_I2CCTL1);
 713}
 714
 715static inline bool npcm_i2c_tx_fifo_empty(struct npcm_i2c *bus)
 716{
 717	u8 tx_fifo_sts;
 718
 719	tx_fifo_sts = ioread8(bus->reg + NPCM_I2CTXF_STS);
 720	/* check if TX FIFO is not empty */
 721	if ((tx_fifo_sts & bus->data->txf_sts_tx_bytes) == 0)
 722		return false;
 723
 724	/* check if TX FIFO status bit is set: */
 725	return !!FIELD_GET(NPCM_I2CTXF_STS_TX_THST, tx_fifo_sts);
 726}
 727
 728static inline bool npcm_i2c_rx_fifo_full(struct npcm_i2c *bus)
 729{
 730	u8 rx_fifo_sts;
 731
 732	rx_fifo_sts = ioread8(bus->reg + NPCM_I2CRXF_STS);
 733	/* check if RX FIFO is not empty: */
 734	if ((rx_fifo_sts & bus->data->rxf_sts_rx_bytes) == 0)
 735		return false;
 736
 737	/* check if rx fifo full status is set: */
 738	return !!FIELD_GET(NPCM_I2CRXF_STS_RX_THST, rx_fifo_sts);
 739}
 740
 741static inline void npcm_i2c_clear_fifo_int(struct npcm_i2c *bus)
 742{
 743	u8 val;
 744
 745	val = ioread8(bus->reg + NPCM_I2CFIF_CTS);
 746	val = (val & NPCM_I2CFIF_CTS_SLVRSTR) | NPCM_I2CFIF_CTS_RXF_TXE;
 747	iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
 748}
 749
 750static inline void npcm_i2c_clear_tx_fifo(struct npcm_i2c *bus)
 751{
 752	u8 val;
 753
 754	val = ioread8(bus->reg + NPCM_I2CTXF_STS);
 755	val = val | NPCM_I2CTXF_STS_TX_THST;
 756	iowrite8(val, bus->reg + NPCM_I2CTXF_STS);
 757}
 758
 759static inline void npcm_i2c_clear_rx_fifo(struct npcm_i2c *bus)
 760{
 761	u8 val;
 762
 763	val = ioread8(bus->reg + NPCM_I2CRXF_STS);
 764	val = val | NPCM_I2CRXF_STS_RX_THST;
 765	iowrite8(val, bus->reg + NPCM_I2CRXF_STS);
 766}
 767
 768static void npcm_i2c_int_enable(struct npcm_i2c *bus, bool enable)
 769{
 770	u8 val;
 771
 772	val = ioread8(bus->reg + NPCM_I2CCTL1);
 773	val &= ~NPCM_I2CCTL1_RWS;
 774	if (enable)
 775		val |= NPCM_I2CCTL1_INTEN;
 776	else
 777		val &= ~NPCM_I2CCTL1_INTEN;
 778	iowrite8(val, bus->reg + NPCM_I2CCTL1);
 779}
 780
 781static inline void npcm_i2c_master_start(struct npcm_i2c *bus)
 782{
 783	u8 val;
 784
 785	val = ioread8(bus->reg + NPCM_I2CCTL1);
 786	val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK);
 787	val |= NPCM_I2CCTL1_START;
 788	iowrite8(val, bus->reg + NPCM_I2CCTL1);
 789}
 790
 791static inline void npcm_i2c_master_stop(struct npcm_i2c *bus)
 792{
 793	u8 val;
 794
 795	/*
 796	 * override HW issue: I2C may fail to supply stop condition in Master
 797	 * Write operation.
 798	 * Need to delay at least 5 us from the last int, before issueing a stop
 799	 */
 800	udelay(10); /* function called from interrupt, can't sleep */
 801	val = ioread8(bus->reg + NPCM_I2CCTL1);
 802	val &= ~(NPCM_I2CCTL1_START | NPCM_I2CCTL1_ACK);
 803	val |= NPCM_I2CCTL1_STOP;
 804	iowrite8(val, bus->reg + NPCM_I2CCTL1);
 805
 806	if (!bus->fifo_use)
 807		return;
 808
 809	npcm_i2c_select_bank(bus, I2C_BANK_1);
 810
 811	if (bus->operation == I2C_READ_OPER)
 812		npcm_i2c_clear_rx_fifo(bus);
 813	else
 814		npcm_i2c_clear_tx_fifo(bus);
 815	npcm_i2c_clear_fifo_int(bus);
 816	iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
 817}
 818
 819static inline void npcm_i2c_stall_after_start(struct npcm_i2c *bus, bool stall)
 820{
 821	u8 val;
 822
 823	val = ioread8(bus->reg + NPCM_I2CCTL1);
 824	val &= ~NPCM_I2CCTL1_RWS;
 825	if (stall)
 826		val |= NPCM_I2CCTL1_STASTRE;
 827	else
 828		val &= ~NPCM_I2CCTL1_STASTRE;
 829	iowrite8(val, bus->reg + NPCM_I2CCTL1);
 830}
 831
 832static inline void npcm_i2c_nack(struct npcm_i2c *bus)
 833{
 834	u8 val;
 835
 836	val = ioread8(bus->reg + NPCM_I2CCTL1);
 837	val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_START);
 838	val |= NPCM_I2CCTL1_ACK;
 839	iowrite8(val, bus->reg + NPCM_I2CCTL1);
 840}
 841
 842static inline void npcm_i2c_clear_master_status(struct npcm_i2c *bus)
 843{
 844	u8 val;
 845
 846	/* Clear NEGACK, STASTR and BER bits */
 847	val = NPCM_I2CST_BER | NPCM_I2CST_NEGACK | NPCM_I2CST_STASTR;
 848	iowrite8(val, bus->reg + NPCM_I2CST);
 849}
 850
 851#if IS_ENABLED(CONFIG_I2C_SLAVE)
 852static void npcm_i2c_slave_int_enable(struct npcm_i2c *bus, bool enable)
 853{
 854	u8 i2cctl1;
 855
 856	/* enable interrupt on slave match: */
 857	i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
 858	i2cctl1 &= ~NPCM_I2CCTL1_RWS;
 859	if (enable)
 860		i2cctl1 |= NPCM_I2CCTL1_NMINTE;
 861	else
 862		i2cctl1 &= ~NPCM_I2CCTL1_NMINTE;
 863	iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
 864}
 865
 866static int npcm_i2c_slave_enable(struct npcm_i2c *bus, enum i2c_addr addr_type,
 867				 u8 addr, bool enable)
 868{
 869	u8 i2cctl1;
 870	u8 i2cctl3;
 871	u8 sa_reg;
 872
 873	sa_reg = (addr & 0x7F) | FIELD_PREP(NPCM_I2CADDR_SAEN, enable);
 874	if (addr_type == I2C_GC_ADDR) {
 875		i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
 876		if (enable)
 877			i2cctl1 |= NPCM_I2CCTL1_GCMEN;
 878		else
 879			i2cctl1 &= ~NPCM_I2CCTL1_GCMEN;
 880		iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
 881		return 0;
 882	} else if (addr_type == I2C_ARP_ADDR) {
 883		i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
 884		if (enable)
 885			i2cctl3 |= I2CCTL3_ARPMEN;
 886		else
 887			i2cctl3 &= ~I2CCTL3_ARPMEN;
 888		iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
 889		return 0;
 890	}
 891	if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10)
 892		dev_err(bus->dev, "try to enable more than 2 SA not supported\n");
 893
 894	if (addr_type >= I2C_ARP_ADDR)
 895		return -EFAULT;
 896
 897	/* Set and enable the address */
 898	iowrite8(sa_reg, bus->reg + npcm_i2caddr[addr_type]);
 899	npcm_i2c_slave_int_enable(bus, enable);
 900
 901	return 0;
 902}
 903#endif
 904
 905static void npcm_i2c_reset(struct npcm_i2c *bus)
 906{
 907	/*
 908	 * Save I2CCTL1 relevant bits. It is being cleared when the module
 909	 *  is disabled.
 910	 */
 911	u8 i2cctl1;
 912#if IS_ENABLED(CONFIG_I2C_SLAVE)
 913	u8 addr;
 914#endif
 915
 916	i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
 917
 918	npcm_i2c_disable(bus);
 919	npcm_i2c_enable(bus);
 920
 921	/* Restore NPCM_I2CCTL1 Status */
 922	i2cctl1 &= ~NPCM_I2CCTL1_RWS;
 923	iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
 924
 925	/* Clear BB (BUS BUSY) bit */
 926	iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
 927	iowrite8(0xFF, bus->reg + NPCM_I2CST);
 928
 929	/* Clear and disable EOB */
 930	npcm_i2c_eob_int(bus, false);
 931
 932	/* Clear all fifo bits: */
 933	iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
 934
 935#if IS_ENABLED(CONFIG_I2C_SLAVE)
 936	if (bus->slave) {
 937		addr = bus->slave->addr;
 938		npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, addr, true);
 939	}
 940#endif
 941
 942	/* Clear status bits for spurious interrupts */
 943	npcm_i2c_clear_master_status(bus);
 944
 945	bus->state = I2C_IDLE;
 946}
 947
 948static inline bool npcm_i2c_is_master(struct npcm_i2c *bus)
 949{
 950	return !!FIELD_GET(NPCM_I2CST_MASTER, ioread8(bus->reg + NPCM_I2CST));
 951}
 952
 953static void npcm_i2c_callback(struct npcm_i2c *bus,
 954			      enum i2c_state_ind op_status, u16 info)
 955{
 956	struct i2c_msg *msgs;
 957	int msgs_num;
 958	bool do_complete = false;
 959
 960	msgs = bus->msgs;
 961	msgs_num = bus->msgs_num;
 962	/*
 963	 * check that transaction was not timed-out, and msgs still
 964	 * holds a valid value.
 965	 */
 966	if (!msgs)
 967		return;
 968
 969	if (completion_done(&bus->cmd_complete))
 970		return;
 971
 972	switch (op_status) {
 973	case I2C_MASTER_DONE_IND:
 974		bus->cmd_err = bus->msgs_num;
 975		if (bus->tx_complete_cnt < ULLONG_MAX)
 976			bus->tx_complete_cnt++;
 977		fallthrough;
 978	case I2C_BLOCK_BYTES_ERR_IND:
 979		/* Master tx finished and all transmit bytes were sent */
 980		if (bus->msgs) {
 981			if (msgs[0].flags & I2C_M_RD)
 982				msgs[0].len = info;
 983			else if (msgs_num == 2 &&
 984				 msgs[1].flags & I2C_M_RD)
 985				msgs[1].len = info;
 986		}
 987		do_complete = true;
 988		break;
 989	case I2C_NACK_IND:
 990		/* MASTER transmit got a NACK before tx all bytes */
 991		bus->cmd_err = -ENXIO;
 992		do_complete = true;
 993		break;
 994	case I2C_BUS_ERR_IND:
 995		/* Bus error */
 996		bus->cmd_err = -EAGAIN;
 997		do_complete = true;
 998		break;
 999	case I2C_WAKE_UP_IND:
1000		/* I2C wake up */
1001		break;
1002	default:
1003		break;
1004	}
1005
1006	bus->operation = I2C_NO_OPER;
1007#if IS_ENABLED(CONFIG_I2C_SLAVE)
1008	if (bus->slave)
1009		bus->master_or_slave = I2C_SLAVE;
1010#endif
1011	if (do_complete)
1012		complete(&bus->cmd_complete);
1013}
1014
1015static u8 npcm_i2c_fifo_usage(struct npcm_i2c *bus)
1016{
1017	if (bus->operation == I2C_WRITE_OPER)
1018		return (bus->data->txf_sts_tx_bytes &
1019			ioread8(bus->reg + NPCM_I2CTXF_STS));
1020	if (bus->operation == I2C_READ_OPER)
1021		return (bus->data->rxf_sts_rx_bytes &
1022			ioread8(bus->reg + NPCM_I2CRXF_STS));
1023	return 0;
1024}
1025
1026static void npcm_i2c_write_to_fifo_master(struct npcm_i2c *bus, u16 max_bytes)
1027{
1028	u8 size_free_fifo;
1029
1030	/*
1031	 * Fill the FIFO, while the FIFO is not full and there are more bytes
1032	 * to write
1033	 */
1034	size_free_fifo = bus->data->fifo_size - npcm_i2c_fifo_usage(bus);
1035	while (max_bytes-- && size_free_fifo) {
1036		if (bus->wr_ind < bus->wr_size)
1037			npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
1038		else
1039			npcm_i2c_wr_byte(bus, 0xFF);
1040		size_free_fifo = bus->data->fifo_size - npcm_i2c_fifo_usage(bus);
1041	}
1042}
1043
1044/*
1045 * npcm_i2c_set_fifo:
1046 * configure the FIFO before using it. If nread is -1 RX FIFO will not be
1047 * configured. same for nwrite
1048 */
1049static void npcm_i2c_set_fifo(struct npcm_i2c *bus, int nread, int nwrite)
1050{
1051	u8 rxf_ctl = 0;
1052
1053	if (!bus->fifo_use)
1054		return;
1055	npcm_i2c_select_bank(bus, I2C_BANK_1);
1056	npcm_i2c_clear_tx_fifo(bus);
1057	npcm_i2c_clear_rx_fifo(bus);
1058
1059	/* configure RX FIFO */
1060	if (nread > 0) {
1061		rxf_ctl = min_t(int, nread, bus->data->fifo_size);
1062
1063		/* set LAST bit. if LAST is set next FIFO packet is nacked */
1064		if (nread <= bus->data->fifo_size)
1065			rxf_ctl |= bus->data->rxf_ctl_last_pec;
1066
1067		/*
1068		 * if we are about to read the first byte in blk rd mode,
1069		 * don't NACK it. If slave returns zero size HW can't NACK
1070		 * it immediately, it will read extra byte and then NACK.
1071		 */
1072		if (bus->rd_ind == 0 && bus->read_block_use) {
1073			/* set fifo to read one byte, no last: */
1074			rxf_ctl = 1;
1075		}
1076
1077		/* set fifo size: */
1078		iowrite8(rxf_ctl, bus->reg + NPCM_I2CRXF_CTL);
1079	}
1080
1081	/* configure TX FIFO */
1082	if (nwrite > 0) {
1083		if (nwrite > bus->data->fifo_size)
1084			/* data to send is more then FIFO size. */
1085			iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CTXF_CTL);
1086		else
1087			iowrite8(nwrite, bus->reg + NPCM_I2CTXF_CTL);
1088
1089		npcm_i2c_clear_tx_fifo(bus);
1090	}
1091}
1092
1093static void npcm_i2c_read_fifo(struct npcm_i2c *bus, u8 bytes_in_fifo)
1094{
1095	u8 data;
1096
1097	while (bytes_in_fifo--) {
1098		data = npcm_i2c_rd_byte(bus);
1099		if (bus->rd_ind < bus->rd_size)
1100			bus->rd_buf[bus->rd_ind++] = data;
1101	}
1102}
1103
1104static void npcm_i2c_master_abort(struct npcm_i2c *bus)
1105{
1106	/* Only current master is allowed to issue a stop condition */
1107	if (!npcm_i2c_is_master(bus))
1108		return;
1109
1110	npcm_i2c_eob_int(bus, true);
1111	npcm_i2c_master_stop(bus);
1112	npcm_i2c_clear_master_status(bus);
1113}
1114
1115#if IS_ENABLED(CONFIG_I2C_SLAVE)
1116static u8 npcm_i2c_get_slave_addr(struct npcm_i2c *bus, enum i2c_addr addr_type)
1117{
1118	if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10)
1119		dev_err(bus->dev, "get slave: try to use more than 2 SA not supported\n");
1120
1121	return ioread8(bus->reg + npcm_i2caddr[addr_type]);
1122}
1123
1124static int npcm_i2c_remove_slave_addr(struct npcm_i2c *bus, u8 slave_add)
1125{
1126	int i;
1127
1128	/* Set the enable bit */
1129	slave_add |= 0x80;
1130
1131	for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++) {
1132		if (ioread8(bus->reg + npcm_i2caddr[i]) == slave_add)
1133			iowrite8(0, bus->reg + npcm_i2caddr[i]);
1134	}
1135
1136	return 0;
1137}
1138
1139static void npcm_i2c_write_fifo_slave(struct npcm_i2c *bus, u16 max_bytes)
1140{
1141	/*
1142	 * Fill the FIFO, while the FIFO is not full and there are more bytes
1143	 * to write
1144	 */
1145	npcm_i2c_clear_fifo_int(bus);
1146	npcm_i2c_clear_tx_fifo(bus);
1147	iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1148	while (max_bytes-- && bus->data->fifo_size != npcm_i2c_fifo_usage(bus)) {
1149		if (bus->slv_wr_size <= 0)
1150			break;
1151		bus->slv_wr_ind = bus->slv_wr_ind & (bus->data->fifo_size - 1);
1152		npcm_i2c_wr_byte(bus, bus->slv_wr_buf[bus->slv_wr_ind]);
1153		bus->slv_wr_ind++;
1154		bus->slv_wr_ind = bus->slv_wr_ind & (bus->data->fifo_size - 1);
1155		bus->slv_wr_size--;
1156	}
1157}
1158
1159static void npcm_i2c_read_fifo_slave(struct npcm_i2c *bus, u8 bytes_in_fifo)
1160{
1161	u8 data;
1162
1163	if (!bus->slave)
1164		return;
1165
1166	while (bytes_in_fifo--) {
1167		data = npcm_i2c_rd_byte(bus);
1168
1169		bus->slv_rd_ind = bus->slv_rd_ind & (bus->data->fifo_size - 1);
1170		bus->slv_rd_buf[bus->slv_rd_ind] = data;
1171		bus->slv_rd_ind++;
1172
1173		/* 1st byte is length in block protocol: */
1174		if (bus->slv_rd_ind == 1 && bus->read_block_use)
1175			bus->slv_rd_size = data + bus->PEC_use + 1;
1176	}
1177}
1178
1179static int npcm_i2c_slave_get_wr_buf(struct npcm_i2c *bus)
1180{
1181	int i;
1182	u8 value;
1183	int ind;
1184	int ret = bus->slv_wr_ind;
1185
1186	/* fill a cyclic buffer */
1187	for (i = 0; i < bus->data->fifo_size; i++) {
1188		if (bus->slv_wr_size >= bus->data->fifo_size)
1189			break;
1190		if (bus->state == I2C_SLAVE_MATCH) {
1191			i2c_slave_event(bus->slave, I2C_SLAVE_READ_REQUESTED, &value);
1192			bus->state = I2C_OPER_STARTED;
1193		} else {
1194			i2c_slave_event(bus->slave, I2C_SLAVE_READ_PROCESSED, &value);
1195		}
1196		ind = (bus->slv_wr_ind + bus->slv_wr_size) & (bus->data->fifo_size - 1);
1197		bus->slv_wr_buf[ind] = value;
1198		bus->slv_wr_size++;
1199	}
1200	return bus->data->fifo_size - ret;
1201}
1202
1203static void npcm_i2c_slave_send_rd_buf(struct npcm_i2c *bus)
1204{
1205	int i;
1206
1207	for (i = 0; i < bus->slv_rd_ind; i++)
1208		i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_RECEIVED,
1209				&bus->slv_rd_buf[i]);
1210	/*
1211	 * once we send bytes up, need to reset the counter of the wr buf
1212	 * got data from master (new offset in device), ignore wr fifo:
1213	 */
1214	if (bus->slv_rd_ind) {
1215		bus->slv_wr_size = 0;
1216		bus->slv_wr_ind = 0;
1217	}
1218
1219	bus->slv_rd_ind = 0;
1220	bus->slv_rd_size = bus->adap.quirks->max_read_len;
1221
1222	npcm_i2c_clear_fifo_int(bus);
1223	npcm_i2c_clear_rx_fifo(bus);
1224}
1225
1226static void npcm_i2c_slave_receive(struct npcm_i2c *bus, u16 nread,
1227				   u8 *read_data)
1228{
1229	bus->state = I2C_OPER_STARTED;
1230	bus->operation = I2C_READ_OPER;
1231	bus->slv_rd_size = nread;
1232	bus->slv_rd_ind = 0;
1233
1234	iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1235	iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CRXF_CTL);
1236	npcm_i2c_clear_tx_fifo(bus);
1237	npcm_i2c_clear_rx_fifo(bus);
1238}
1239
1240static void npcm_i2c_slave_xmit(struct npcm_i2c *bus, u16 nwrite,
1241				u8 *write_data)
1242{
1243	if (nwrite == 0)
1244		return;
1245
1246	bus->operation = I2C_WRITE_OPER;
1247
1248	/* get the next buffer */
1249	npcm_i2c_slave_get_wr_buf(bus);
1250	npcm_i2c_write_fifo_slave(bus, nwrite);
1251}
1252
1253/*
1254 * npcm_i2c_slave_wr_buf_sync:
1255 * currently slave IF only supports single byte operations.
1256 * in order to utilize the npcm HW FIFO, the driver will ask for 16 bytes
1257 * at a time, pack them in buffer, and then transmit them all together
1258 * to the FIFO and onward to the bus.
1259 * NACK on read will be once reached to bus->adap->quirks->max_read_len.
1260 * sending a NACK wherever the backend requests for it is not supported.
1261 * the next two functions allow reading to local buffer before writing it all
1262 * to the HW FIFO.
1263 */
1264static void npcm_i2c_slave_wr_buf_sync(struct npcm_i2c *bus)
1265{
1266	int left_in_fifo;
1267
1268	left_in_fifo = bus->data->txf_sts_tx_bytes &
1269			ioread8(bus->reg + NPCM_I2CTXF_STS);
1270
1271	/* fifo already full: */
1272	if (left_in_fifo >= bus->data->fifo_size ||
1273	    bus->slv_wr_size >= bus->data->fifo_size)
1274		return;
1275
1276	/* update the wr fifo index back to the untransmitted bytes: */
1277	bus->slv_wr_ind = bus->slv_wr_ind - left_in_fifo;
1278	bus->slv_wr_size = bus->slv_wr_size + left_in_fifo;
1279
1280	if (bus->slv_wr_ind < 0)
1281		bus->slv_wr_ind += bus->data->fifo_size;
1282}
1283
1284static void npcm_i2c_slave_rd_wr(struct npcm_i2c *bus)
1285{
1286	if (NPCM_I2CST_XMIT & ioread8(bus->reg + NPCM_I2CST)) {
1287		/*
1288		 * Slave got an address match with direction bit 1 so it should
1289		 * transmit data. Write till the master will NACK
1290		 */
1291		bus->operation = I2C_WRITE_OPER;
1292		npcm_i2c_slave_xmit(bus, bus->adap.quirks->max_write_len,
1293				    bus->slv_wr_buf);
1294	} else {
1295		/*
1296		 * Slave got an address match with direction bit 0 so it should
1297		 * receive data.
1298		 * this module does not support saying no to bytes.
1299		 * it will always ACK.
1300		 */
1301		bus->operation = I2C_READ_OPER;
1302		npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
1303		bus->stop_ind = I2C_SLAVE_RCV_IND;
1304		npcm_i2c_slave_send_rd_buf(bus);
1305		npcm_i2c_slave_receive(bus, bus->adap.quirks->max_read_len,
1306				       bus->slv_rd_buf);
1307	}
1308}
1309
1310static irqreturn_t npcm_i2c_int_slave_handler(struct npcm_i2c *bus)
1311{
1312	u8 val;
1313	irqreturn_t ret = IRQ_NONE;
1314	u8 i2cst = ioread8(bus->reg + NPCM_I2CST);
1315
1316	/* Slave: A NACK has occurred */
1317	if (NPCM_I2CST_NEGACK & i2cst) {
1318		bus->stop_ind = I2C_NACK_IND;
1319		npcm_i2c_slave_wr_buf_sync(bus);
1320		if (bus->fifo_use)
1321			/* clear the FIFO */
1322			iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO,
1323				 bus->reg + NPCM_I2CFIF_CTS);
1324
1325		/* In slave write, NACK is OK, otherwise it is a problem */
1326		bus->stop_ind = I2C_NO_STATUS_IND;
1327		bus->operation = I2C_NO_OPER;
1328		bus->own_slave_addr = 0xFF;
1329
1330		/*
1331		 * Slave has to wait for STOP to decide this is the end
1332		 * of the transaction. tx is not yet considered as done
1333		 */
1334		iowrite8(NPCM_I2CST_NEGACK, bus->reg + NPCM_I2CST);
1335
1336		ret = IRQ_HANDLED;
1337	}
1338
1339	/* Slave mode: a Bus Error (BER) has been identified */
1340	if (NPCM_I2CST_BER & i2cst) {
1341		/*
1342		 * Check whether bus arbitration or Start or Stop during data
1343		 * xfer bus arbitration problem should not result in recovery
1344		 */
1345		bus->stop_ind = I2C_BUS_ERR_IND;
1346
1347		/* wait for bus busy before clear fifo */
1348		iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
1349
1350		bus->state = I2C_IDLE;
1351
1352		/*
1353		 * in BER case we might get 2 interrupts: one for slave one for
1354		 * master ( for a channel which is master\slave switching)
1355		 */
1356		if (completion_done(&bus->cmd_complete) == false) {
1357			bus->cmd_err = -EIO;
1358			complete(&bus->cmd_complete);
1359		}
1360		bus->own_slave_addr = 0xFF;
1361		iowrite8(NPCM_I2CST_BER, bus->reg + NPCM_I2CST);
1362		ret = IRQ_HANDLED;
1363	}
1364
1365	/* A Slave Stop Condition has been identified */
1366	if (NPCM_I2CST_SLVSTP & i2cst) {
1367		u8 bytes_in_fifo = npcm_i2c_fifo_usage(bus);
1368
1369		bus->stop_ind = I2C_SLAVE_DONE_IND;
1370
1371		if (bus->operation == I2C_READ_OPER)
1372			npcm_i2c_read_fifo_slave(bus, bytes_in_fifo);
1373
1374		/* if the buffer is empty nothing will be sent */
1375		npcm_i2c_slave_send_rd_buf(bus);
1376
1377		/* Slave done transmitting or receiving */
1378		bus->stop_ind = I2C_NO_STATUS_IND;
1379
1380		/*
1381		 * Note, just because we got here, it doesn't mean we through
1382		 * away the wr buffer.
1383		 * we keep it until the next received offset.
1384		 */
1385		bus->operation = I2C_NO_OPER;
1386		bus->own_slave_addr = 0xFF;
1387		i2c_slave_event(bus->slave, I2C_SLAVE_STOP, 0);
1388		iowrite8(NPCM_I2CST_SLVSTP, bus->reg + NPCM_I2CST);
1389		if (bus->fifo_use) {
1390			npcm_i2c_clear_fifo_int(bus);
1391			npcm_i2c_clear_rx_fifo(bus);
1392			npcm_i2c_clear_tx_fifo(bus);
1393
1394			iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO,
1395				 bus->reg + NPCM_I2CFIF_CTS);
1396		}
1397		bus->state = I2C_IDLE;
1398		ret = IRQ_HANDLED;
1399	}
1400
1401	/* restart condition occurred and Rx-FIFO was not empty */
1402	if (bus->fifo_use && FIELD_GET(NPCM_I2CFIF_CTS_SLVRSTR,
1403				       ioread8(bus->reg + NPCM_I2CFIF_CTS))) {
1404		bus->stop_ind = I2C_SLAVE_RESTART_IND;
1405		bus->master_or_slave = I2C_SLAVE;
1406		if (bus->operation == I2C_READ_OPER)
1407			npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
1408		bus->operation = I2C_WRITE_OPER;
1409		iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
1410		val = NPCM_I2CFIF_CTS_CLR_FIFO | NPCM_I2CFIF_CTS_SLVRSTR |
1411		      NPCM_I2CFIF_CTS_RXF_TXE;
1412		iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
1413		npcm_i2c_slave_rd_wr(bus);
1414		ret = IRQ_HANDLED;
1415	}
1416
1417	/* A Slave Address Match has been identified */
1418	if (NPCM_I2CST_NMATCH & i2cst) {
1419		u8 info = 0;
1420
1421		/* Address match automatically implies slave mode */
1422		bus->master_or_slave = I2C_SLAVE;
1423		npcm_i2c_clear_fifo_int(bus);
1424		npcm_i2c_clear_rx_fifo(bus);
1425		npcm_i2c_clear_tx_fifo(bus);
1426		iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1427		iowrite8(bus->data->fifo_size, bus->reg + NPCM_I2CRXF_CTL);
1428		if (NPCM_I2CST_XMIT & i2cst) {
1429			bus->operation = I2C_WRITE_OPER;
1430		} else {
1431			i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_REQUESTED,
1432					&info);
1433			bus->operation = I2C_READ_OPER;
1434		}
1435		if (bus->own_slave_addr == 0xFF) {
1436			/* Check which type of address match */
1437			val = ioread8(bus->reg + NPCM_I2CCST);
1438			if (NPCM_I2CCST_MATCH & val) {
1439				u16 addr;
1440				enum i2c_addr eaddr;
1441				u8 i2ccst2;
1442				u8 i2ccst3;
1443
1444				i2ccst3 = ioread8(bus->reg + NPCM_I2CCST3);
1445				i2ccst2 = ioread8(bus->reg + NPCM_I2CCST2);
1446
1447				/*
1448				 * the i2c module can response to 10 own SA.
1449				 * check which one was addressed by the master.
1450				 * respond to the first one.
1451				 */
1452				addr = ((i2ccst3 & 0x07) << 7) |
1453					(i2ccst2 & 0x7F);
1454				info = ffs(addr);
1455				eaddr = (enum i2c_addr)info;
1456				addr = npcm_i2c_get_slave_addr(bus, eaddr);
1457				addr &= 0x7F;
1458				bus->own_slave_addr = addr;
1459				if (bus->PEC_mask & BIT(info))
1460					bus->PEC_use = true;
1461				else
1462					bus->PEC_use = false;
1463			} else {
1464				if (NPCM_I2CCST_GCMATCH & val)
1465					bus->own_slave_addr = 0;
1466				if (NPCM_I2CCST_ARPMATCH & val)
1467					bus->own_slave_addr = 0x61;
1468			}
1469		} else {
1470			/*
1471			 *  Slave match can happen in two options:
1472			 *  1. Start, SA, read (slave read without further ado)
1473			 *  2. Start, SA, read, data, restart, SA, read,  ...
1474			 *     (slave read in fragmented mode)
1475			 *  3. Start, SA, write, data, restart, SA, read, ..
1476			 *     (regular write-read mode)
1477			 */
1478			if ((bus->state == I2C_OPER_STARTED &&
1479			     bus->operation == I2C_READ_OPER &&
1480			     bus->stop_ind == I2C_SLAVE_XMIT_IND) ||
1481			     bus->stop_ind == I2C_SLAVE_RCV_IND) {
1482				/* slave tx after slave rx w/o STOP */
1483				bus->stop_ind = I2C_SLAVE_RESTART_IND;
1484			}
1485		}
1486
1487		if (NPCM_I2CST_XMIT & i2cst)
1488			bus->stop_ind = I2C_SLAVE_XMIT_IND;
1489		else
1490			bus->stop_ind = I2C_SLAVE_RCV_IND;
1491		bus->state = I2C_SLAVE_MATCH;
1492		npcm_i2c_slave_rd_wr(bus);
1493		iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
1494		ret = IRQ_HANDLED;
1495	}
1496
1497	/* Slave SDA status is set - tx or rx */
1498	if ((NPCM_I2CST_SDAST & i2cst) ||
1499	    (bus->fifo_use &&
1500	    (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
1501		npcm_i2c_slave_rd_wr(bus);
1502		iowrite8(NPCM_I2CST_SDAST, bus->reg + NPCM_I2CST);
1503		ret = IRQ_HANDLED;
1504	} /* SDAST */
1505
1506	/*
1507	 * If irq is not one of the above, make sure EOB is disabled and all
1508	 * status bits are cleared.
1509	 */
1510	if (ret == IRQ_NONE) {
1511		npcm_i2c_eob_int(bus, false);
1512		npcm_i2c_clear_master_status(bus);
1513	}
1514
1515	return IRQ_HANDLED;
1516}
1517
1518static int npcm_i2c_reg_slave(struct i2c_client *client)
1519{
1520	unsigned long lock_flags;
1521	struct npcm_i2c *bus = i2c_get_adapdata(client->adapter);
1522
1523	bus->slave = client;
1524
1525	if (client->flags & I2C_CLIENT_TEN)
1526		return -EAFNOSUPPORT;
1527
1528	spin_lock_irqsave(&bus->lock, lock_flags);
1529
1530	npcm_i2c_init_params(bus);
1531	bus->slv_rd_size = 0;
1532	bus->slv_wr_size = 0;
1533	bus->slv_rd_ind = 0;
1534	bus->slv_wr_ind = 0;
1535	if (client->flags & I2C_CLIENT_PEC)
1536		bus->PEC_use = true;
1537
1538	dev_info(bus->dev, "i2c%d register slave SA=0x%x, PEC=%d\n", bus->num,
1539		 client->addr, bus->PEC_use);
1540
1541	npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, client->addr, true);
1542	npcm_i2c_clear_fifo_int(bus);
1543	npcm_i2c_clear_rx_fifo(bus);
1544	npcm_i2c_clear_tx_fifo(bus);
1545	npcm_i2c_slave_int_enable(bus, true);
1546
1547	spin_unlock_irqrestore(&bus->lock, lock_flags);
1548	return 0;
1549}
1550
1551static int npcm_i2c_unreg_slave(struct i2c_client *client)
1552{
1553	struct npcm_i2c *bus = client->adapter->algo_data;
1554	unsigned long lock_flags;
1555
1556	spin_lock_irqsave(&bus->lock, lock_flags);
1557	if (!bus->slave) {
1558		spin_unlock_irqrestore(&bus->lock, lock_flags);
1559		return -EINVAL;
1560	}
1561	npcm_i2c_slave_int_enable(bus, false);
1562	npcm_i2c_remove_slave_addr(bus, client->addr);
1563	bus->slave = NULL;
1564	spin_unlock_irqrestore(&bus->lock, lock_flags);
1565	return 0;
1566}
1567#endif /* CONFIG_I2C_SLAVE */
1568
1569static void npcm_i2c_master_fifo_read(struct npcm_i2c *bus)
1570{
1571	int rcount;
1572	int fifo_bytes;
1573	enum i2c_state_ind ind = I2C_MASTER_DONE_IND;
1574
1575	fifo_bytes = npcm_i2c_fifo_usage(bus);
1576	rcount = bus->rd_size - bus->rd_ind;
1577
1578	/*
1579	 * In order not to change the RX_TRH during transaction (we found that
1580	 * this might be problematic if it takes too much time to read the FIFO)
1581	 * we read the data in the following way. If the number of bytes to
1582	 * read == FIFO Size + C (where C < FIFO Size)then first read C bytes
1583	 * and in the next int we read rest of the data.
1584	 */
1585	if (rcount < (2 * bus->data->fifo_size) && rcount > bus->data->fifo_size)
1586		fifo_bytes = rcount - bus->data->fifo_size;
1587
1588	if (rcount <= fifo_bytes) {
1589		/* last bytes are about to be read - end of tx */
1590		bus->state = I2C_STOP_PENDING;
1591		bus->stop_ind = ind;
1592		npcm_i2c_eob_int(bus, true);
1593		/* Stop should be set before reading last byte. */
1594		npcm_i2c_master_stop(bus);
1595		npcm_i2c_read_fifo(bus, fifo_bytes);
1596	} else {
1597		npcm_i2c_read_fifo(bus, fifo_bytes);
1598		rcount = bus->rd_size - bus->rd_ind;
1599		npcm_i2c_set_fifo(bus, rcount, -1);
1600	}
1601}
1602
1603static void npcm_i2c_irq_master_handler_write(struct npcm_i2c *bus)
1604{
1605	u16 wcount;
1606
1607	if (bus->fifo_use)
1608		npcm_i2c_clear_tx_fifo(bus); /* clear the TX fifo status bit */
1609
1610	/* Master write operation - last byte handling */
1611	if (bus->wr_ind == bus->wr_size) {
1612		if (bus->fifo_use && npcm_i2c_fifo_usage(bus) > 0)
1613			/*
1614			 * No more bytes to send (to add to the FIFO),
1615			 * however the FIFO is not empty yet. It is
1616			 * still in the middle of tx. Currently there's nothing
1617			 * to do except for waiting to the end of the tx
1618			 * We will get an int when the FIFO will get empty.
1619			 */
1620			return;
1621
1622		if (bus->rd_size == 0) {
1623			/* all bytes have been written, in wr only operation */
1624			npcm_i2c_eob_int(bus, true);
1625			bus->state = I2C_STOP_PENDING;
1626			bus->stop_ind = I2C_MASTER_DONE_IND;
1627			npcm_i2c_master_stop(bus);
1628			/* Clear SDA Status bit (by writing dummy byte) */
1629			npcm_i2c_wr_byte(bus, 0xFF);
1630
1631		} else {
1632			/* last write-byte written on previous int - restart */
1633			npcm_i2c_set_fifo(bus, bus->rd_size, -1);
1634			/* Generate repeated start upon next write to SDA */
1635			npcm_i2c_master_start(bus);
1636
1637			/*
1638			 * Receiving one byte only - stall after successful
1639			 * completion of send address byte. If we NACK here, and
1640			 * slave doesn't ACK the address, we might
1641			 * unintentionally NACK the next multi-byte read.
1642			 */
1643			if (bus->rd_size == 1)
1644				npcm_i2c_stall_after_start(bus, true);
1645
1646			/* Next int will occur on read */
1647			bus->operation = I2C_READ_OPER;
1648			/* send the slave address in read direction */
1649			npcm_i2c_wr_byte(bus, bus->dest_addr | 0x1);
1650		}
1651	} else {
1652		/* write next byte not last byte and not slave address */
1653		if (!bus->fifo_use || bus->wr_size == 1) {
1654			npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
1655		} else {
1656			wcount = bus->wr_size - bus->wr_ind;
1657			npcm_i2c_set_fifo(bus, -1, wcount);
1658			if (wcount)
1659				npcm_i2c_write_to_fifo_master(bus, wcount);
1660		}
1661	}
1662}
1663
1664static void npcm_i2c_irq_master_handler_read(struct npcm_i2c *bus)
1665{
1666	u16 block_extra_bytes_size;
1667	u8 data;
1668
1669	/* added bytes to the packet: */
1670	block_extra_bytes_size = bus->read_block_use + bus->PEC_use;
1671
1672	/*
1673	 * Perform master read, distinguishing between last byte and the rest of
1674	 * the bytes. The last byte should be read when the clock is stopped
1675	 */
1676	if (bus->rd_ind == 0) { /* first byte handling: */
1677		if (bus->read_block_use) {
1678			/* first byte in block protocol is the size: */
1679			data = npcm_i2c_rd_byte(bus);
1680			data = clamp_val(data, 1, I2C_SMBUS_BLOCK_MAX);
1681			bus->rd_size = data + block_extra_bytes_size;
1682			bus->rd_buf[bus->rd_ind++] = data;
1683
1684			/* clear RX FIFO interrupt status: */
1685			if (bus->fifo_use) {
1686				data = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1687				data = data | NPCM_I2CFIF_CTS_RXF_TXE;
1688				iowrite8(data, bus->reg + NPCM_I2CFIF_CTS);
1689			}
1690
1691			npcm_i2c_set_fifo(bus, bus->rd_size - 1, -1);
1692			npcm_i2c_stall_after_start(bus, false);
1693		} else {
1694			npcm_i2c_clear_tx_fifo(bus);
1695			npcm_i2c_master_fifo_read(bus);
1696		}
1697	} else {
1698		if (bus->rd_size == block_extra_bytes_size &&
1699		    bus->read_block_use) {
1700			bus->state = I2C_STOP_PENDING;
1701			bus->stop_ind = I2C_BLOCK_BYTES_ERR_IND;
1702			bus->cmd_err = -EIO;
1703			npcm_i2c_eob_int(bus, true);
1704			npcm_i2c_master_stop(bus);
1705			npcm_i2c_read_fifo(bus, npcm_i2c_fifo_usage(bus));
1706		} else {
1707			npcm_i2c_master_fifo_read(bus);
1708		}
1709	}
1710}
1711
1712static void npcm_i2c_irq_handle_nmatch(struct npcm_i2c *bus)
1713{
1714	iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
1715	npcm_i2c_nack(bus);
1716	bus->stop_ind = I2C_BUS_ERR_IND;
1717	npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
1718}
1719
1720/* A NACK has occurred */
1721static void npcm_i2c_irq_handle_nack(struct npcm_i2c *bus)
1722{
1723	u8 val;
1724
1725	if (bus->nack_cnt < ULLONG_MAX)
1726		bus->nack_cnt++;
1727
1728	if (bus->fifo_use) {
1729		/*
1730		 * if there are still untransmitted bytes in TX FIFO
1731		 * reduce them from wr_ind
1732		 */
1733		if (bus->operation == I2C_WRITE_OPER)
1734			bus->wr_ind -= npcm_i2c_fifo_usage(bus);
1735
1736		/* clear the FIFO */
1737		iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
1738	}
1739
1740	/* In master write operation, got unexpected NACK */
1741	bus->stop_ind = I2C_NACK_IND;
1742	/* Only current master is allowed to issue Stop Condition */
1743	if (npcm_i2c_is_master(bus)) {
1744		/* stopping in the middle */
1745		npcm_i2c_eob_int(bus, false);
1746		npcm_i2c_master_stop(bus);
1747
1748		/* Clear SDA Status bit (by reading dummy byte) */
1749		npcm_i2c_rd_byte(bus);
1750
1751		/*
1752		 * The bus is released from stall only after the SW clears
1753		 * NEGACK bit. Then a Stop condition is sent.
1754		 */
1755		npcm_i2c_clear_master_status(bus);
1756		readx_poll_timeout_atomic(ioread8, bus->reg + NPCM_I2CCST, val,
1757					  !(val & NPCM_I2CCST_BUSY), 10, 200);
1758		/* Verify no status bits are still set after bus is released */
1759		npcm_i2c_clear_master_status(bus);
1760	}
1761	bus->state = I2C_IDLE;
1762
1763	/*
1764	 * In Master mode, NACK should be cleared only after STOP.
1765	 * In such case, the bus is released from stall only after the
1766	 * software clears NACK bit. Then a Stop condition is sent.
1767	 */
1768	npcm_i2c_callback(bus, bus->stop_ind, bus->wr_ind);
1769}
1770
1771	/* Master mode: a Bus Error has been identified */
1772static void npcm_i2c_irq_handle_ber(struct npcm_i2c *bus)
1773{
1774	if (bus->ber_cnt < ULLONG_MAX)
1775		bus->ber_cnt++;
1776	bus->stop_ind = I2C_BUS_ERR_IND;
1777	if (npcm_i2c_is_master(bus)) {
1778		npcm_i2c_master_abort(bus);
1779	} else {
1780		bus->ber_state = true;
1781		npcm_i2c_clear_master_status(bus);
1782
1783		/* Clear BB (BUS BUSY) bit */
1784		iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
1785
1786		bus->cmd_err = -EAGAIN;
1787		npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
1788	}
1789	bus->state = I2C_IDLE;
1790}
1791
1792	/* EOB: a master End Of Busy (meaning STOP completed) */
1793static void npcm_i2c_irq_handle_eob(struct npcm_i2c *bus)
1794{
1795	npcm_i2c_eob_int(bus, false);
1796	bus->state = I2C_IDLE;
1797	npcm_i2c_callback(bus, bus->stop_ind, bus->rd_ind);
1798}
1799
1800/* Address sent and requested stall occurred (Master mode) */
1801static void npcm_i2c_irq_handle_stall_after_start(struct npcm_i2c *bus)
1802{
1803	if (npcm_i2c_is_quick(bus)) {
1804		bus->state = I2C_STOP_PENDING;
1805		bus->stop_ind = I2C_MASTER_DONE_IND;
1806		npcm_i2c_eob_int(bus, true);
1807		npcm_i2c_master_stop(bus);
1808	} else if ((bus->rd_size == 1) && !bus->read_block_use) {
1809		/*
1810		 * Receiving one byte only - set NACK after ensuring
1811		 * slave ACKed the address byte.
1812		 */
1813		npcm_i2c_nack(bus);
1814	}
1815
1816	/* Reset stall-after-address-byte */
1817	npcm_i2c_stall_after_start(bus, false);
1818
1819	/* Clear stall only after setting STOP */
1820	iowrite8(NPCM_I2CST_STASTR, bus->reg + NPCM_I2CST);
1821}
1822
1823/* SDA status is set - TX or RX, master */
1824static void npcm_i2c_irq_handle_sda(struct npcm_i2c *bus, u8 i2cst)
1825{
1826	u8 fif_cts;
1827
1828	if (!npcm_i2c_is_master(bus))
1829		return;
1830
1831	if (bus->state == I2C_IDLE) {
1832		bus->stop_ind = I2C_WAKE_UP_IND;
1833
1834		if (npcm_i2c_is_quick(bus) || bus->read_block_use)
1835			/*
1836			 * Need to stall after successful
1837			 * completion of sending address byte
1838			 */
1839			npcm_i2c_stall_after_start(bus, true);
1840		else
1841			npcm_i2c_stall_after_start(bus, false);
1842
1843		/*
1844		 * Receiving one byte only - stall after successful completion
1845		 * of sending address byte If we NACK here, and slave doesn't
1846		 * ACK the address, we might unintentionally NACK the next
1847		 * multi-byte read
1848		 */
1849		if (bus->wr_size == 0 && bus->rd_size == 1)
1850			npcm_i2c_stall_after_start(bus, true);
1851
1852		/* Initiate I2C master tx */
1853
1854		/* select bank 1 for FIFO regs */
1855		npcm_i2c_select_bank(bus, I2C_BANK_1);
1856
1857		fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1858		fif_cts = fif_cts & ~NPCM_I2CFIF_CTS_SLVRSTR;
1859
1860		/* clear FIFO and relevant status bits. */
1861		fif_cts = fif_cts | NPCM_I2CFIF_CTS_CLR_FIFO;
1862		iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1863
1864		/* re-enable */
1865		fif_cts = fif_cts | NPCM_I2CFIF_CTS_RXF_TXE;
1866		iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1867
1868		/*
1869		 * Configure the FIFO threshold:
1870		 * according to the needed # of bytes to read.
1871		 * Note: due to HW limitation can't config the rx fifo before it
1872		 * got and ACK on the restart. LAST bit will not be reset unless
1873		 * RX completed. It will stay set on the next tx.
1874		 */
1875		if (bus->wr_size)
1876			npcm_i2c_set_fifo(bus, -1, bus->wr_size);
1877		else
1878			npcm_i2c_set_fifo(bus, bus->rd_size, -1);
1879
1880		bus->state = I2C_OPER_STARTED;
1881
1882		if (npcm_i2c_is_quick(bus) || bus->wr_size)
1883			npcm_i2c_wr_byte(bus, bus->dest_addr);
1884		else
1885			npcm_i2c_wr_byte(bus, bus->dest_addr | BIT(0));
1886	/* SDA interrupt, after start\restart */
1887	} else {
1888		if (bus->operation == I2C_WRITE_OPER)
1889			npcm_i2c_irq_master_handler_write(bus);
1890		else if (bus->operation == I2C_READ_OPER)
1891			npcm_i2c_irq_master_handler_read(bus);
1892	}
1893}
1894
1895static int npcm_i2c_int_master_handler(struct npcm_i2c *bus)
1896{
1897	u8 i2cst;
1898	int ret = -EIO;
1899
1900	i2cst = ioread8(bus->reg + NPCM_I2CST);
1901
1902	if (FIELD_GET(NPCM_I2CST_NMATCH, i2cst)) {
1903		npcm_i2c_irq_handle_nmatch(bus);
1904		return 0;
1905	}
1906	/* A NACK has occurred */
1907	if (FIELD_GET(NPCM_I2CST_NEGACK, i2cst)) {
1908		npcm_i2c_irq_handle_nack(bus);
1909		return 0;
1910	}
1911
1912	/* Master mode: a Bus Error has been identified */
1913	if (FIELD_GET(NPCM_I2CST_BER, i2cst)) {
1914		npcm_i2c_irq_handle_ber(bus);
1915		return 0;
1916	}
1917
1918	/* EOB: a master End Of Busy (meaning STOP completed) */
1919	if ((FIELD_GET(NPCM_I2CCTL1_EOBINTE,
1920		       ioread8(bus->reg + NPCM_I2CCTL1)) == 1) &&
1921	    (FIELD_GET(NPCM_I2CCST3_EO_BUSY,
1922		       ioread8(bus->reg + NPCM_I2CCST3)))) {
1923		npcm_i2c_irq_handle_eob(bus);
1924#if IS_ENABLED(CONFIG_I2C_SLAVE)
1925		/* reenable slave if it was enabled */
1926		if (bus->slave)
1927			iowrite8(bus->slave->addr | NPCM_I2CADDR_SAEN,
1928				 bus->reg + NPCM_I2CADDR1);
1929#endif
1930		return 0;
1931	}
1932
1933	/* Address sent and requested stall occurred (Master mode) */
1934	if (FIELD_GET(NPCM_I2CST_STASTR, i2cst)) {
1935		npcm_i2c_irq_handle_stall_after_start(bus);
1936		ret = 0;
1937	}
1938
1939	/* SDA status is set - TX or RX, master */
1940	if (FIELD_GET(NPCM_I2CST_SDAST, i2cst) ||
1941	    (bus->fifo_use &&
1942	    (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
1943		npcm_i2c_irq_handle_sda(bus, i2cst);
1944		ret = 0;
1945	}
1946
1947	return ret;
1948}
1949
1950/* recovery using TGCLK functionality of the module */
1951static int npcm_i2c_recovery_tgclk(struct i2c_adapter *_adap)
1952{
1953	u8               val;
1954	u8               fif_cts;
1955	bool             done = false;
1956	int              status = -ENOTRECOVERABLE;
1957	struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
1958	/* Allow 3 bytes (27 toggles) to be read from the slave: */
1959	int              iter = 27;
1960
1961	if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1)) {
1962		dev_dbg(bus->dev, "bus%d-0x%x recovery skipped, bus not stuck",
1963			bus->num, bus->dest_addr);
1964		npcm_i2c_reset(bus);
1965		bus->ber_state = false;
1966		return 0;
1967	}
1968
1969	npcm_i2c_int_enable(bus, false);
1970	npcm_i2c_disable(bus);
1971	npcm_i2c_enable(bus);
1972	iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
1973	npcm_i2c_clear_tx_fifo(bus);
1974	npcm_i2c_clear_rx_fifo(bus);
1975	iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
1976	iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1977	npcm_i2c_stall_after_start(bus, false);
1978
1979	/* select bank 1 for FIFO regs */
1980	npcm_i2c_select_bank(bus, I2C_BANK_1);
1981
1982	/* clear FIFO and relevant status bits. */
1983	fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1984	fif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR;
1985	fif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO;
1986	iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1987	npcm_i2c_set_fifo(bus, -1, 0);
1988
1989	/* Repeat the following sequence until SDA is released */
1990	do {
1991		/* Issue a single SCL toggle */
1992		iowrite8(NPCM_I2CCST_TGSCL, bus->reg + NPCM_I2CCST);
1993		usleep_range(20, 30);
1994		/* If SDA line is inactive (high), stop */
1995		if (npcm_i2c_get_SDA(_adap)) {
1996			done = true;
1997			status = 0;
1998		}
1999	} while (!done && iter--);
2000
2001	/* If SDA line is released: send start-addr-stop, to re-sync. */
2002	if (npcm_i2c_get_SDA(_adap)) {
2003		/* Send an address byte in write direction: */
2004		npcm_i2c_wr_byte(bus, bus->dest_addr);
2005		npcm_i2c_master_start(bus);
2006		/* Wait until START condition is sent */
2007		status = readx_poll_timeout(npcm_i2c_get_SCL, _adap, val, !val,
2008					    20, 200);
2009		/* If START condition was sent */
2010		if (npcm_i2c_is_master(bus) > 0) {
2011			usleep_range(20, 30);
2012			npcm_i2c_master_stop(bus);
2013			usleep_range(200, 500);
2014		}
2015	}
2016	npcm_i2c_reset(bus);
2017	npcm_i2c_int_enable(bus, true);
2018
2019	if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1))
2020		status = 0;
2021	else
2022		status = -ENOTRECOVERABLE;
2023	if (status) {
2024		if (bus->rec_fail_cnt < ULLONG_MAX)
2025			bus->rec_fail_cnt++;
2026	} else {
2027		if (bus->rec_succ_cnt < ULLONG_MAX)
2028			bus->rec_succ_cnt++;
2029	}
2030	bus->ber_state = false;
2031	return status;
2032}
2033
2034/* recovery using bit banging functionality of the module */
2035static void npcm_i2c_recovery_init(struct i2c_adapter *_adap)
2036{
2037	struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
2038	struct i2c_bus_recovery_info *rinfo = &bus->rinfo;
2039
2040	rinfo->recover_bus = npcm_i2c_recovery_tgclk;
2041
2042	/*
2043	 * npcm i2c HW allows direct reading of SCL and SDA.
2044	 * However, it does not support setting SCL and SDA directly.
2045	 * The recovery function can toggle SCL when SDA is low (but not set)
2046	 * Getter functions used internally, and can be used externally.
2047	 */
2048	rinfo->get_scl = npcm_i2c_get_SCL;
2049	rinfo->get_sda = npcm_i2c_get_SDA;
2050	_adap->bus_recovery_info = rinfo;
2051}
2052
2053/* SCLFRQ min/max field values */
2054#define SCLFRQ_MIN  10
2055#define SCLFRQ_MAX  511
2056#define clk_coef(freq, mul)	DIV_ROUND_UP((freq) * (mul), 1000000)
2057
2058/*
2059 * npcm_i2c_init_clk: init HW timing parameters.
2060 * NPCM7XX i2c module timing parameters are dependent on module core clk (APB)
2061 * and bus frequency.
2062 * 100kHz bus requires tSCL = 4 * SCLFRQ * tCLK. LT and HT are symmetric.
2063 * 400kHz bus requires asymmetric HT and LT. A different equation is recommended
2064 * by the HW designer, given core clock range (equations in comments below).
2065 *
2066 */
2067static int npcm_i2c_init_clk(struct npcm_i2c *bus, u32 bus_freq_hz)
2068{
2069	struct  smb_timing_t *smb_timing;
2070	u8   scl_table_cnt = 0, table_size = 0;
2071	u8   fast_mode = 0;
2072
2073	bus->bus_freq = bus_freq_hz;
2074
2075	switch (bus_freq_hz) {
2076	case I2C_MAX_STANDARD_MODE_FREQ:
2077		smb_timing = smb_timing_100khz;
2078		table_size = ARRAY_SIZE(smb_timing_100khz);
2079		break;
2080	case I2C_MAX_FAST_MODE_FREQ:
2081		smb_timing = smb_timing_400khz;
2082		table_size = ARRAY_SIZE(smb_timing_400khz);
2083		fast_mode = I2CCTL3_400K_MODE;
2084		break;
2085	case I2C_MAX_FAST_MODE_PLUS_FREQ:
2086		smb_timing = smb_timing_1000khz;
2087		table_size = ARRAY_SIZE(smb_timing_1000khz);
2088		fast_mode = I2CCTL3_400K_MODE;
2089		break;
2090	default:
2091		return -EINVAL;
2092	}
2093
2094	for (scl_table_cnt = 0; scl_table_cnt < table_size; scl_table_cnt++)
2095		if (bus->apb_clk >= smb_timing[scl_table_cnt].core_clk)
2096			break;
2097
2098	if (scl_table_cnt == table_size)
2099		return -EINVAL;
2100
2101	/* write sclfrq value. bits [6:0] are in I2CCTL2 reg */
2102	iowrite8(FIELD_PREP(I2CCTL2_SCLFRQ6_0, smb_timing[scl_table_cnt].sclfrq & 0x7F),
2103		 bus->reg + NPCM_I2CCTL2);
2104
2105	/* bits [8:7] are in I2CCTL3 reg */
2106	iowrite8(FIELD_PREP(I2CCTL3_SCLFRQ8_7, (smb_timing[scl_table_cnt].sclfrq >> 7) & 0x3) |
2107		 fast_mode,
2108		 bus->reg + NPCM_I2CCTL3);
2109
2110	/* Select Bank 0 to access NPCM_I2CCTL4/NPCM_I2CCTL5 */
2111	npcm_i2c_select_bank(bus, I2C_BANK_0);
2112
2113	if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) {
2114		/*
2115		 * Set SCL Low/High Time:
2116		 * k1 = 2 * SCLLT7-0 -> Low Time  = k1 / 2
2117		 * k2 = 2 * SCLLT7-0 -> High Time = k2 / 2
2118		 */
2119		iowrite8(smb_timing[scl_table_cnt].scllt, bus->reg + NPCM_I2CSCLLT);
2120		iowrite8(smb_timing[scl_table_cnt].sclht, bus->reg + NPCM_I2CSCLHT);
2121
2122		iowrite8(smb_timing[scl_table_cnt].dbcnt, bus->reg + NPCM_I2CCTL5);
2123	}
2124
2125	iowrite8(smb_timing[scl_table_cnt].hldt, bus->reg + NPCM_I2CCTL4);
2126
2127	/* Return to Bank 1, and stay there by default: */
2128	npcm_i2c_select_bank(bus, I2C_BANK_1);
2129
2130	return 0;
2131}
2132
2133static int npcm_i2c_init_module(struct npcm_i2c *bus, enum i2c_mode mode,
2134				u32 bus_freq_hz)
2135{
2136	u8 val;
2137	int ret;
2138
2139	/* Check whether module already enabled or frequency is out of bounds */
2140	if ((bus->state != I2C_DISABLE && bus->state != I2C_IDLE) ||
2141	    bus_freq_hz < I2C_FREQ_MIN_HZ || bus_freq_hz > I2C_FREQ_MAX_HZ)
2142		return -EINVAL;
2143
2144	npcm_i2c_int_enable(bus, false);
2145	npcm_i2c_disable(bus);
2146
2147	/* Configure FIFO mode : */
2148	if (FIELD_GET(I2C_VER_FIFO_EN, ioread8(bus->reg + I2C_VER))) {
2149		bus->fifo_use = true;
2150		npcm_i2c_select_bank(bus, I2C_BANK_0);
2151		val = ioread8(bus->reg + NPCM_I2CFIF_CTL);
2152		val |= NPCM_I2CFIF_CTL_FIFO_EN;
2153		iowrite8(val, bus->reg + NPCM_I2CFIF_CTL);
2154		npcm_i2c_select_bank(bus, I2C_BANK_1);
2155	} else {
2156		bus->fifo_use = false;
2157	}
2158
2159	/* Configure I2C module clock frequency */
2160	ret = npcm_i2c_init_clk(bus, bus_freq_hz);
2161	if (ret) {
2162		dev_err(bus->dev, "npcm_i2c_init_clk failed\n");
2163		return ret;
2164	}
2165
2166	/* Enable module (before configuring CTL1) */
2167	npcm_i2c_enable(bus);
2168	bus->state = I2C_IDLE;
2169	val = ioread8(bus->reg + NPCM_I2CCTL1);
2170	val = (val | NPCM_I2CCTL1_NMINTE) & ~NPCM_I2CCTL1_RWS;
2171	iowrite8(val, bus->reg + NPCM_I2CCTL1);
2172
2173	npcm_i2c_reset(bus);
2174
2175	/* Check HW is OK: SDA and SCL should be high at this point. */
2176	if ((npcm_i2c_get_SDA(&bus->adap) == 0) || (npcm_i2c_get_SCL(&bus->adap) == 0)) {
2177		dev_warn(bus->dev, " I2C%d SDA=%d SCL=%d, attempting to recover\n", bus->num,
2178				 npcm_i2c_get_SDA(&bus->adap), npcm_i2c_get_SCL(&bus->adap));
2179		if (npcm_i2c_recovery_tgclk(&bus->adap)) {
2180			dev_err(bus->dev, "I2C%d init fail: SDA=%d SCL=%d\n",
2181				bus->num, npcm_i2c_get_SDA(&bus->adap),
2182				npcm_i2c_get_SCL(&bus->adap));
2183			return -ENXIO;
2184		}
2185	}
2186
2187	npcm_i2c_int_enable(bus, true);
2188	return 0;
2189}
2190
2191static int __npcm_i2c_init(struct npcm_i2c *bus, struct platform_device *pdev)
2192{
2193	u32 clk_freq_hz;
2194	int ret;
2195
2196	/* Initialize the internal data structures */
2197	bus->state = I2C_DISABLE;
2198	bus->master_or_slave = I2C_SLAVE;
2199	bus->int_time_stamp = 0;
2200#if IS_ENABLED(CONFIG_I2C_SLAVE)
2201	bus->slave = NULL;
2202#endif
2203
2204	ret = device_property_read_u32(&pdev->dev, "clock-frequency",
2205				       &clk_freq_hz);
2206	if (ret) {
2207		dev_info(&pdev->dev, "Could not read clock-frequency property");
2208		clk_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
2209	}
2210
2211	ret = npcm_i2c_init_module(bus, I2C_MASTER, clk_freq_hz);
2212	if (ret) {
2213		dev_err(&pdev->dev, "npcm_i2c_init_module failed\n");
2214		return ret;
2215	}
2216
2217	return 0;
2218}
2219
2220static irqreturn_t npcm_i2c_bus_irq(int irq, void *dev_id)
2221{
2222	struct npcm_i2c *bus = dev_id;
2223
2224	if (npcm_i2c_is_master(bus))
2225		bus->master_or_slave = I2C_MASTER;
2226
2227	if (bus->master_or_slave == I2C_MASTER) {
2228		bus->int_time_stamp = jiffies;
2229		if (!npcm_i2c_int_master_handler(bus))
2230			return IRQ_HANDLED;
2231	}
2232#if IS_ENABLED(CONFIG_I2C_SLAVE)
2233	if (bus->slave) {
2234		bus->master_or_slave = I2C_SLAVE;
2235		if (npcm_i2c_int_slave_handler(bus))
2236			return IRQ_HANDLED;
2237	}
2238#endif
2239	/* Clear status bits for spurious interrupts */
2240	npcm_i2c_clear_master_status(bus);
2241
2242	return IRQ_HANDLED;
2243}
2244
2245static bool npcm_i2c_master_start_xmit(struct npcm_i2c *bus,
2246				       u16 nwrite, u16 nread,
2247				       u8 *write_data, u8 *read_data,
2248				       bool use_PEC, bool use_read_block)
2249{
2250	if (bus->state != I2C_IDLE) {
2251		bus->cmd_err = -EBUSY;
2252		return false;
2253	}
2254	bus->wr_buf = write_data;
2255	bus->wr_size = nwrite;
2256	bus->wr_ind = 0;
2257	bus->rd_buf = read_data;
2258	bus->rd_size = nread;
2259	bus->rd_ind = 0;
2260	bus->PEC_use = 0;
2261
2262	/* for tx PEC is appended to buffer from i2c IF. PEC flag is ignored */
2263	if (nread)
2264		bus->PEC_use = use_PEC;
2265
2266	bus->read_block_use = use_read_block;
2267	if (nread && !nwrite)
2268		bus->operation = I2C_READ_OPER;
2269	else
2270		bus->operation = I2C_WRITE_OPER;
2271	if (bus->fifo_use) {
2272		u8 i2cfif_cts;
2273
2274		npcm_i2c_select_bank(bus, I2C_BANK_1);
2275		/* clear FIFO and relevant status bits. */
2276		i2cfif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
2277		i2cfif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR;
2278		i2cfif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO;
2279		iowrite8(i2cfif_cts, bus->reg + NPCM_I2CFIF_CTS);
2280	}
2281
2282	bus->state = I2C_IDLE;
2283	npcm_i2c_stall_after_start(bus, true);
2284	npcm_i2c_master_start(bus);
2285	return true;
2286}
2287
2288static int npcm_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
2289				int num)
2290{
2291	struct npcm_i2c *bus = container_of(adap, struct npcm_i2c, adap);
2292	struct i2c_msg *msg0, *msg1;
2293	unsigned long time_left, flags;
2294	u16 nwrite, nread;
2295	u8 *write_data, *read_data;
2296	unsigned long timeout;
2297	bool read_block = false;
2298	bool read_PEC = false;
2299	u8 bus_busy;
2300	unsigned long timeout_usec;
2301
2302	if (bus->state == I2C_DISABLE) {
2303		dev_err(bus->dev, "I2C%d module is disabled", bus->num);
2304		return -EINVAL;
2305	}
2306
2307	msg0 = &msgs[0];
2308	if (msg0->flags & I2C_M_RD) { /* read */
2309		nwrite = 0;
2310		write_data = NULL;
2311		read_data = msg0->buf;
2312		if (msg0->flags & I2C_M_RECV_LEN) {
2313			nread = 1;
2314			read_block = true;
2315			if (msg0->flags & I2C_CLIENT_PEC)
2316				read_PEC = true;
2317		} else {
2318			nread = msg0->len;
2319		}
2320	} else { /* write */
2321		nwrite = msg0->len;
2322		write_data = msg0->buf;
2323		nread = 0;
2324		read_data = NULL;
2325		if (num == 2) {
2326			msg1 = &msgs[1];
2327			read_data = msg1->buf;
2328			if (msg1->flags & I2C_M_RECV_LEN) {
2329				nread = 1;
2330				read_block = true;
2331				if (msg1->flags & I2C_CLIENT_PEC)
2332					read_PEC = true;
2333			} else {
2334				nread = msg1->len;
2335				read_block = false;
2336			}
2337		}
2338	}
2339
2340	if (nwrite >= 32 * 1024 || nread >= 32 * 1024) {
2341		dev_err(bus->dev, "i2c%d buffer too big\n", bus->num);
2342		return -EINVAL;
2343	}
2344
2345	time_left = jiffies + bus->adap.timeout / bus->adap.retries + 1;
2346	do {
2347		/*
2348		 * we must clear slave address immediately when the bus is not
2349		 * busy, so we spinlock it, but we don't keep the lock for the
2350		 * entire while since it is too long.
2351		 */
2352		spin_lock_irqsave(&bus->lock, flags);
2353		bus_busy = ioread8(bus->reg + NPCM_I2CCST) & NPCM_I2CCST_BB;
2354#if IS_ENABLED(CONFIG_I2C_SLAVE)
2355		if (!bus_busy && bus->slave)
2356			iowrite8((bus->slave->addr & 0x7F),
2357				 bus->reg + NPCM_I2CADDR1);
2358#endif
2359		spin_unlock_irqrestore(&bus->lock, flags);
2360
2361	} while (time_is_after_jiffies(time_left) && bus_busy);
2362
2363	/*
2364	 * Store the address early in a global position to ensure it is
2365	 * accessible for a potential call to i2c_recover_bus().
2366	 *
2367	 * Since the transfer might be a read operation, remove the I2C_M_RD flag
2368	 * from the bus->dest_addr for the i2c_recover_bus() call later.
2369	 *
2370	 * The i2c_recover_bus() uses the address in a write direction to recover
2371	 * the i2c bus if some error condition occurs.
2372	 *
2373	 * Remove the I2C_M_RD flag from the address since npcm_i2c_master_start_xmit()
2374	 * handles the read/write operation internally.
2375	 */
2376	bus->dest_addr = i2c_8bit_addr_from_msg(msg0) & ~I2C_M_RD;
2377
2378	/*
2379	 * Check the BER (bus error) state, when ber_state is true, it means that the module
2380	 * detects the bus error which is caused by some factor like that the electricity
2381	 * noise occurs on the bus. Under this condition, the module is reset and the bus
2382	 * gets recovered.
2383	 *
2384	 * While ber_state is false, the module reset and bus recovery also get done as the
2385	 * bus is busy.
2386	 */
2387	if (bus_busy || bus->ber_state) {
2388		iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
2389		npcm_i2c_reset(bus);
2390		i2c_recover_bus(adap);
2391		return -EAGAIN;
2392	}
2393
2394	npcm_i2c_init_params(bus);
2395	bus->msgs = msgs;
2396	bus->msgs_num = num;
2397	bus->cmd_err = 0;
2398	bus->read_block_use = read_block;
2399
2400	reinit_completion(&bus->cmd_complete);
2401
2402	npcm_i2c_int_enable(bus, true);
2403
2404	if (npcm_i2c_master_start_xmit(bus, nwrite, nread,
2405				       write_data, read_data, read_PEC,
2406				       read_block)) {
2407		/*
2408		 * Adaptive TimeOut: estimated time in usec + 100% margin:
2409		 * 2: double the timeout for clock stretching case
2410		 * 9: bits per transaction (including the ack/nack)
2411		 */
2412		timeout_usec = (2 * 9 * USEC_PER_SEC / bus->bus_freq) * (2 + nread + nwrite);
2413		timeout = max_t(unsigned long, bus->adap.timeout / bus->adap.retries,
2414				usecs_to_jiffies(timeout_usec));
2415		time_left = wait_for_completion_timeout(&bus->cmd_complete,
2416							timeout);
2417
2418		if (time_left == 0) {
2419			if (bus->timeout_cnt < ULLONG_MAX)
2420				bus->timeout_cnt++;
2421			if (bus->master_or_slave == I2C_MASTER) {
2422				i2c_recover_bus(adap);
2423				bus->cmd_err = -EIO;
2424				bus->state = I2C_IDLE;
2425			}
2426		}
2427	}
2428
2429	/* if there was BER, check if need to recover the bus: */
2430	if (bus->cmd_err == -EAGAIN)
2431		bus->cmd_err = i2c_recover_bus(adap);
2432
2433	/*
2434	 * After any type of error, check if LAST bit is still set,
2435	 * due to a HW issue.
2436	 * It cannot be cleared without resetting the module.
2437	 */
2438	else if (bus->cmd_err &&
2439		 (bus->data->rxf_ctl_last_pec & ioread8(bus->reg + NPCM_I2CRXF_CTL)))
2440		npcm_i2c_reset(bus);
2441
2442	/* After any xfer, successful or not, stall and EOB must be disabled */
2443	npcm_i2c_stall_after_start(bus, false);
2444	npcm_i2c_eob_int(bus, false);
2445
2446#if IS_ENABLED(CONFIG_I2C_SLAVE)
2447	/* reenable slave if it was enabled */
2448	if (bus->slave)
2449		iowrite8((bus->slave->addr & 0x7F) | NPCM_I2CADDR_SAEN,
2450			 bus->reg + NPCM_I2CADDR1);
2451#else
2452	npcm_i2c_int_enable(bus, false);
2453#endif
2454	return bus->cmd_err;
2455}
2456
2457static u32 npcm_i2c_functionality(struct i2c_adapter *adap)
2458{
2459	return I2C_FUNC_I2C |
2460	       I2C_FUNC_SMBUS_EMUL |
2461	       I2C_FUNC_SMBUS_BLOCK_DATA |
2462	       I2C_FUNC_SMBUS_PEC |
2463	       I2C_FUNC_SLAVE;
2464}
2465
2466static const struct i2c_adapter_quirks npcm_i2c_quirks = {
2467	.max_read_len = 32768,
2468	.max_write_len = 32768,
2469	.flags = I2C_AQ_COMB_WRITE_THEN_READ,
2470};
2471
2472static const struct i2c_algorithm npcm_i2c_algo = {
2473	.xfer = npcm_i2c_master_xfer,
2474	.functionality = npcm_i2c_functionality,
2475#if IS_ENABLED(CONFIG_I2C_SLAVE)
2476	.reg_slave = npcm_i2c_reg_slave,
2477	.unreg_slave = npcm_i2c_unreg_slave,
2478#endif
2479};
2480
2481static void npcm_i2c_init_debugfs(struct platform_device *pdev,
2482				  struct npcm_i2c *bus)
2483{
2484	debugfs_create_u64("ber_cnt", 0444, bus->adap.debugfs, &bus->ber_cnt);
2485	debugfs_create_u64("nack_cnt", 0444, bus->adap.debugfs, &bus->nack_cnt);
2486	debugfs_create_u64("rec_succ_cnt", 0444, bus->adap.debugfs, &bus->rec_succ_cnt);
2487	debugfs_create_u64("rec_fail_cnt", 0444, bus->adap.debugfs, &bus->rec_fail_cnt);
2488	debugfs_create_u64("timeout_cnt", 0444, bus->adap.debugfs, &bus->timeout_cnt);
2489	debugfs_create_u64("tx_complete_cnt", 0444, bus->adap.debugfs, &bus->tx_complete_cnt);
2490}
2491
2492static int npcm_i2c_probe_bus(struct platform_device *pdev)
2493{
2494	struct device_node *np = pdev->dev.of_node;
2495	static struct regmap *gcr_regmap;
2496	struct device *dev = &pdev->dev;
2497	struct i2c_adapter *adap;
2498	struct npcm_i2c *bus;
2499	struct clk *i2c_clk;
2500	int irq;
2501	int ret;
2502
2503	bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
2504	if (!bus)
2505		return -ENOMEM;
2506
2507	bus->dev = &pdev->dev;
2508
2509	bus->data = of_device_get_match_data(dev);
2510	if (!bus->data) {
2511		dev_err(dev, "OF data missing\n");
2512		return -EINVAL;
2513	}
2514
2515	bus->num = of_alias_get_id(pdev->dev.of_node, "i2c");
2516	/* core clk must be acquired to calculate module timing settings */
2517	i2c_clk = devm_clk_get(&pdev->dev, NULL);
2518	if (IS_ERR(i2c_clk))
2519		return PTR_ERR(i2c_clk);
2520	bus->apb_clk = clk_get_rate(i2c_clk);
2521
2522	gcr_regmap = syscon_regmap_lookup_by_phandle(np, "nuvoton,sys-mgr");
2523	if (IS_ERR(gcr_regmap))
2524		gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
2525
2526	if (IS_ERR(gcr_regmap))
2527		return PTR_ERR(gcr_regmap);
2528	regmap_write(gcr_regmap, NPCM_I2CSEGCTL, bus->data->segctl_init_val);
2529
2530	bus->reg = devm_platform_ioremap_resource(pdev, 0);
2531	if (IS_ERR(bus->reg))
2532		return PTR_ERR(bus->reg);
2533
2534	spin_lock_init(&bus->lock);
2535	init_completion(&bus->cmd_complete);
2536
2537	adap = &bus->adap;
2538	adap->owner = THIS_MODULE;
2539	adap->retries = 3;
2540	/*
2541	 * The users want to connect a lot of masters on the same bus.
2542	 * This timeout is used to determine the time it takes to take bus ownership.
2543	 * The transactions are very long, so waiting 35ms is not enough.
2544	 */
2545	adap->timeout = 2 * HZ;
2546	adap->algo = &npcm_i2c_algo;
2547	adap->quirks = &npcm_i2c_quirks;
2548	adap->algo_data = bus;
2549	adap->dev.parent = &pdev->dev;
2550	adap->dev.of_node = pdev->dev.of_node;
2551	adap->nr = pdev->id;
2552
2553	irq = platform_get_irq(pdev, 0);
2554	if (irq < 0)
2555		return irq;
2556
2557	/*
2558	 * Disable the interrupt to avoid the interrupt handler being triggered
2559	 * incorrectly by the asynchronous interrupt status since the machine
2560	 * might do a warm reset during the last smbus/i2c transfer session.
2561	 */
2562	npcm_i2c_int_enable(bus, false);
2563
2564	ret = devm_request_irq(bus->dev, irq, npcm_i2c_bus_irq, 0,
2565			       dev_name(bus->dev), bus);
2566	if (ret)
2567		return ret;
2568
2569	ret = __npcm_i2c_init(bus, pdev);
2570	if (ret)
2571		return ret;
2572
2573	npcm_i2c_recovery_init(adap);
2574
2575	i2c_set_adapdata(adap, bus);
2576
2577	snprintf(bus->adap.name, sizeof(bus->adap.name), "npcm_i2c_%d",
2578		 bus->num);
2579	ret = i2c_add_numbered_adapter(&bus->adap);
2580	if (ret)
2581		return ret;
2582
2583	platform_set_drvdata(pdev, bus);
2584	npcm_i2c_init_debugfs(pdev, bus);
2585	return 0;
2586}
2587
2588static void npcm_i2c_remove_bus(struct platform_device *pdev)
2589{
2590	unsigned long lock_flags;
2591	struct npcm_i2c *bus = platform_get_drvdata(pdev);
2592
2593	spin_lock_irqsave(&bus->lock, lock_flags);
2594	npcm_i2c_disable(bus);
2595	spin_unlock_irqrestore(&bus->lock, lock_flags);
2596	i2c_del_adapter(&bus->adap);
2597}
2598
2599static const struct of_device_id npcm_i2c_bus_of_table[] = {
2600	{ .compatible = "nuvoton,npcm750-i2c", .data = &npxm7xx_i2c_data },
2601	{ .compatible = "nuvoton,npcm845-i2c", .data = &npxm8xx_i2c_data },
2602	{}
2603};
2604MODULE_DEVICE_TABLE(of, npcm_i2c_bus_of_table);
2605
2606static struct platform_driver npcm_i2c_bus_driver = {
2607	.probe = npcm_i2c_probe_bus,
2608	.remove = npcm_i2c_remove_bus,
2609	.driver = {
2610		.name = "nuvoton-i2c",
2611		.of_match_table = npcm_i2c_bus_of_table,
2612	}
2613};
2614
2615module_platform_driver(npcm_i2c_bus_driver);
2616
2617MODULE_AUTHOR("Avi Fishman <avi.fishman@gmail.com>");
2618MODULE_AUTHOR("Tali Perry <tali.perry@nuvoton.com>");
2619MODULE_AUTHOR("Tyrone Ting <kfting@nuvoton.com>");
2620MODULE_DESCRIPTION("Nuvoton I2C Bus Driver");
2621MODULE_LICENSE("GPL v2");