i2c-nomadik.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (C) 2009 ST-Ericsson SA
   4 * Copyright (C) 2009 STMicroelectronics
   5 *
   6 * I2C master mode controller driver, used in Nomadik 8815
   7 * and Ux500 platforms.
   8 *
   9 * The Mobileye EyeQ5 and EyeQ6H platforms are also supported; they use
  10 * the same Ux500/DB8500 IP block with two quirks:
  11 *  - The memory bus only supports 32-bit accesses.
  12 *  - (only EyeQ5) A register must be configured for the I2C speed mode;
  13 *    it is located in a shared register region called OLB.
  14 *
  15 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
  16 * Author: Sachin Verma <sachin.verma@st.com>
  17 */
  18#include <linux/amba/bus.h>
  19#include <linux/bitfield.h>
  20#include <linux/clk.h>
  21#include <linux/err.h>
  22#include <linux/i2c.h>
  23#include <linux/init.h>
  24#include <linux/interrupt.h>
  25#include <linux/io.h>
  26#include <linux/mfd/syscon.h>
  27#include <linux/module.h>
  28#include <linux/of.h>
  29#include <linux/of_device.h>
  30#include <linux/pinctrl/consumer.h>
  31#include <linux/pm_runtime.h>
  32#include <linux/regmap.h>
  33#include <linux/slab.h>
  34
  35#define DRIVER_NAME "nmk-i2c"
  36
  37/* I2C Controller register offsets */
  38#define I2C_CR		(0x000)
  39#define I2C_SCR		(0x004)
  40#define I2C_HSMCR	(0x008)
  41#define I2C_MCR		(0x00C)
  42#define I2C_TFR		(0x010)
  43#define I2C_SR		(0x014)
  44#define I2C_RFR		(0x018)
  45#define I2C_TFTR	(0x01C)
  46#define I2C_RFTR	(0x020)
  47#define I2C_DMAR	(0x024)
  48#define I2C_BRCR	(0x028)
  49#define I2C_IMSCR	(0x02C)
  50#define I2C_RISR	(0x030)
  51#define I2C_MISR	(0x034)
  52#define I2C_ICR		(0x038)
  53
  54/* Control registers */
  55#define I2C_CR_PE		BIT(0)		/* Peripheral Enable */
  56#define I2C_CR_OM		GENMASK(2, 1)	/* Operating mode */
  57#define I2C_CR_SAM		BIT(3)		/* Slave addressing mode */
  58#define I2C_CR_SM		GENMASK(5, 4)	/* Speed mode */
  59#define I2C_CR_SGCM		BIT(6)		/* Slave general call mode */
  60#define I2C_CR_FTX		BIT(7)		/* Flush Transmit */
  61#define I2C_CR_FRX		BIT(8)		/* Flush Receive */
  62#define I2C_CR_DMA_TX_EN	BIT(9)		/* DMA Tx enable */
  63#define I2C_CR_DMA_RX_EN	BIT(10)		/* DMA Rx Enable */
  64#define I2C_CR_DMA_SLE		BIT(11)		/* DMA sync. logic enable */
  65#define I2C_CR_LM		BIT(12)		/* Loopback mode */
  66#define I2C_CR_FON		GENMASK(14, 13)	/* Filtering on */
  67#define I2C_CR_FS		GENMASK(16, 15)	/* Force stop enable */
  68
  69/* Slave control register (SCR) */
  70#define I2C_SCR_SLSU		GENMASK(31, 16)	/* Slave data setup time */
  71
  72/* Master controller (MCR) register */
  73#define I2C_MCR_OP		BIT(0)		/* Operation */
  74#define I2C_MCR_A7		GENMASK(7, 1)	/* 7-bit address */
  75#define I2C_MCR_EA10		GENMASK(10, 8)	/* 10-bit Extended address */
  76#define I2C_MCR_SB		BIT(11)		/* Extended address */
  77#define I2C_MCR_AM		GENMASK(13, 12)	/* Address type */
  78#define I2C_MCR_STOP		BIT(14)		/* Stop condition */
  79#define I2C_MCR_LENGTH		GENMASK(25, 15)	/* Transaction length */
  80
  81/* Status register (SR) */
  82#define I2C_SR_OP		GENMASK(1, 0)	/* Operation */
  83#define I2C_SR_STATUS		GENMASK(3, 2)	/* controller status */
  84#define I2C_SR_CAUSE		GENMASK(6, 4)	/* Abort cause */
  85#define I2C_SR_TYPE		GENMASK(8, 7)	/* Receive type */
  86#define I2C_SR_LENGTH		GENMASK(19, 9)	/* Transfer length */
  87
  88/* Baud-rate counter register (BRCR) */
  89#define I2C_BRCR_BRCNT1		GENMASK(31, 16)	/* Baud-rate counter 1 */
  90#define I2C_BRCR_BRCNT2		GENMASK(15, 0)	/* Baud-rate counter 2 */
  91
  92/* Interrupt mask set/clear (IMSCR) bits */
  93#define I2C_IT_TXFE		BIT(0)
  94#define I2C_IT_TXFNE		BIT(1)
  95#define I2C_IT_TXFF		BIT(2)
  96#define I2C_IT_TXFOVR		BIT(3)
  97#define I2C_IT_RXFE		BIT(4)
  98#define I2C_IT_RXFNF		BIT(5)
  99#define I2C_IT_RXFF		BIT(6)
 100#define I2C_IT_RFSR		BIT(16)
 101#define I2C_IT_RFSE		BIT(17)
 102#define I2C_IT_WTSR		BIT(18)
 103#define I2C_IT_MTD		BIT(19)
 104#define I2C_IT_STD		BIT(20)
 105#define I2C_IT_MAL		BIT(24)
 106#define I2C_IT_BERR		BIT(25)
 107#define I2C_IT_MTDWS		BIT(28)
 108
 109/* some bits in ICR are reserved */
 110#define I2C_CLEAR_ALL_INTS	0x131f007f
 111
 112/* maximum threshold value */
 113#define MAX_I2C_FIFO_THRESHOLD	15
 114
 115enum i2c_freq_mode {
 116	I2C_FREQ_MODE_STANDARD,		/* up to 100 Kb/s */
 117	I2C_FREQ_MODE_FAST,		/* up to 400 Kb/s */
 118	I2C_FREQ_MODE_HIGH_SPEED,	/* up to 3.4 Mb/s */
 119	I2C_FREQ_MODE_FAST_PLUS,	/* up to 1 Mb/s */
 120};
 121
 122/* Mobileye EyeQ5 offset into a shared register region (called OLB) */
 123#define NMK_I2C_EYEQ5_OLB_IOCR2			0x0B8
 124
 125enum i2c_eyeq5_speed {
 126	I2C_EYEQ5_SPEED_FAST,
 127	I2C_EYEQ5_SPEED_FAST_PLUS,
 128	I2C_EYEQ5_SPEED_HIGH_SPEED,
 129};
 130
 131/**
 132 * struct i2c_vendor_data - per-vendor variations
 133 * @has_mtdws: variant has the MTDWS bit
 134 * @fifodepth: variant FIFO depth
 135 */
 136struct i2c_vendor_data {
 137	bool has_mtdws;
 138	u32 fifodepth;
 139};
 140
 141enum i2c_status {
 142	I2C_NOP,
 143	I2C_ON_GOING,
 144	I2C_OK,
 145	I2C_ABORT
 146};
 147
 148/* operation */
 149enum i2c_operation {
 150	I2C_NO_OPERATION = 0xff,
 151	I2C_WRITE = 0x00,
 152	I2C_READ = 0x01
 153};
 154
 155enum i2c_operating_mode {
 156	I2C_OM_SLAVE,
 157	I2C_OM_MASTER,
 158	I2C_OM_MASTER_OR_SLAVE,
 159};
 160
 161/**
 162 * struct i2c_nmk_client - client specific data
 163 * @slave_adr: 7-bit slave address
 164 * @count: no. bytes to be transferred
 165 * @buffer: client data buffer
 166 * @xfer_bytes: bytes transferred till now
 167 * @operation: current I2C operation
 168 */
 169struct i2c_nmk_client {
 170	unsigned short		slave_adr;
 171	unsigned long		count;
 172	unsigned char		*buffer;
 173	unsigned long		xfer_bytes;
 174	enum i2c_operation	operation;
 175};
 176
 177/**
 178 * struct nmk_i2c_dev - private data structure of the controller.
 179 * @vendor: vendor data for this variant.
 180 * @adev: parent amba device.
 181 * @adap: corresponding I2C adapter.
 182 * @irq: interrupt line for the controller.
 183 * @virtbase: virtual io memory area.
 184 * @clk: hardware i2c block clock.
 185 * @cli: holder of client specific data.
 186 * @clk_freq: clock frequency for the operation mode
 187 * @tft: Tx FIFO Threshold in bytes
 188 * @rft: Rx FIFO Threshold in bytes
 189 * @timeout_usecs: Slave response timeout
 190 * @sm: speed mode
 191 * @stop: stop condition.
 192 * @xfer_wq: xfer done wait queue.
 193 * @xfer_done: xfer done boolean.
 194 * @result: controller propogated result.
 195 * @has_32b_bus: controller is on a bus that only supports 32-bit accesses.
 196 */
 197struct nmk_i2c_dev {
 198	struct i2c_vendor_data		*vendor;
 199	struct amba_device		*adev;
 200	struct i2c_adapter		adap;
 201	int				irq;
 202	void __iomem			*virtbase;
 203	struct clk			*clk;
 204	struct i2c_nmk_client		cli;
 205	u32				clk_freq;
 206	unsigned char			tft;
 207	unsigned char			rft;
 208	u32				timeout_usecs;
 209	enum i2c_freq_mode		sm;
 210	int				stop;
 211	struct wait_queue_head		xfer_wq;
 212	bool				xfer_done;
 213	int				result;
 214	bool				has_32b_bus;
 215};
 216
 217/* controller's abort causes */
 218static const char *abort_causes[] = {
 219	"no ack received after address transmission",
 220	"no ack received during data phase",
 221	"ack received after xmission of master code",
 222	"master lost arbitration",
 223	"slave restarts",
 224	"slave reset",
 225	"overflow, maxsize is 2047 bytes",
 226};
 227
 228static inline void i2c_set_bit(void __iomem *reg, u32 mask)
 229{
 230	writel(readl(reg) | mask, reg);
 231}
 232
 233static inline void i2c_clr_bit(void __iomem *reg, u32 mask)
 234{
 235	writel(readl(reg) & ~mask, reg);
 236}
 237
 238static inline u8 nmk_i2c_readb(const struct nmk_i2c_dev *priv,
 239			       unsigned long reg)
 240{
 241	if (priv->has_32b_bus)
 242		return readl(priv->virtbase + reg);
 243	else
 244		return readb(priv->virtbase + reg);
 245}
 246
 247static inline void nmk_i2c_writeb(const struct nmk_i2c_dev *priv, u32 val,
 248				  unsigned long reg)
 249{
 250	if (priv->has_32b_bus)
 251		writel(val, priv->virtbase + reg);
 252	else
 253		writeb(val, priv->virtbase + reg);
 254}
 255
 256/**
 257 * flush_i2c_fifo() - This function flushes the I2C FIFO
 258 * @priv: private data of I2C Driver
 259 *
 260 * This function flushes the I2C Tx and Rx FIFOs. It returns
 261 * 0 on successful flushing of FIFO
 262 */
 263static int flush_i2c_fifo(struct nmk_i2c_dev *priv)
 264{
 265#define LOOP_ATTEMPTS 10
 266	ktime_t timeout;
 267	int i;
 268
 269	/*
 270	 * flush the transmit and receive FIFO. The flushing
 271	 * operation takes several cycles before to be completed.
 272	 * On the completion, the I2C internal logic clears these
 273	 * bits, until then no one must access Tx, Rx FIFO and
 274	 * should poll on these bits waiting for the completion.
 275	 */
 276	writel((I2C_CR_FTX | I2C_CR_FRX), priv->virtbase + I2C_CR);
 277
 278	for (i = 0; i < LOOP_ATTEMPTS; i++) {
 279		timeout = ktime_add_us(ktime_get(), priv->timeout_usecs);
 280
 281		while (ktime_after(timeout, ktime_get())) {
 282			if ((readl(priv->virtbase + I2C_CR) &
 283				(I2C_CR_FTX | I2C_CR_FRX)) == 0)
 284				return 0;
 285		}
 286	}
 287
 288	dev_err(&priv->adev->dev,
 289		"flushing operation timed out giving up after %d attempts",
 290		LOOP_ATTEMPTS);
 291
 292	return -ETIMEDOUT;
 293}
 294
 295/**
 296 * disable_all_interrupts() - Disable all interrupts of this I2c Bus
 297 * @priv: private data of I2C Driver
 298 */
 299static void disable_all_interrupts(struct nmk_i2c_dev *priv)
 300{
 301	writel(0, priv->virtbase + I2C_IMSCR);
 302}
 303
 304/**
 305 * clear_all_interrupts() - Clear all interrupts of I2C Controller
 306 * @priv: private data of I2C Driver
 307 */
 308static void clear_all_interrupts(struct nmk_i2c_dev *priv)
 309{
 310	writel(I2C_CLEAR_ALL_INTS, priv->virtbase + I2C_ICR);
 311}
 312
 313/**
 314 * init_hw() - initialize the I2C hardware
 315 * @priv: private data of I2C Driver
 316 */
 317static int init_hw(struct nmk_i2c_dev *priv)
 318{
 319	int stat;
 320
 321	stat = flush_i2c_fifo(priv);
 322	if (stat)
 323		goto exit;
 324
 325	/* disable the controller */
 326	i2c_clr_bit(priv->virtbase + I2C_CR, I2C_CR_PE);
 327
 328	disable_all_interrupts(priv);
 329
 330	clear_all_interrupts(priv);
 331
 332	priv->cli.operation = I2C_NO_OPERATION;
 333
 334exit:
 335	return stat;
 336}
 337
 338/* enable peripheral, master mode operation */
 339#define DEFAULT_I2C_REG_CR	(FIELD_PREP(I2C_CR_OM, I2C_OM_MASTER) | I2C_CR_PE)
 340
 341/* grab top three bits from extended I2C addresses */
 342#define ADR_3MSB_BITS		GENMASK(9, 7)
 343
 344/**
 345 * load_i2c_mcr_reg() - load the MCR register
 346 * @priv: private data of controller
 347 * @flags: message flags
 348 */
 349static u32 load_i2c_mcr_reg(struct nmk_i2c_dev *priv, u16 flags)
 350{
 351	u32 mcr = 0;
 352	unsigned short slave_adr_3msb_bits;
 353
 354	mcr |= FIELD_PREP(I2C_MCR_A7, priv->cli.slave_adr);
 355
 356	if (unlikely(flags & I2C_M_TEN)) {
 357		/* 10-bit address transaction */
 358		mcr |= FIELD_PREP(I2C_MCR_AM, 2);
 359		/*
 360		 * Get the top 3 bits.
 361		 * EA10 represents extended address in MCR. This includes
 362		 * the extension (MSB bits) of the 7 bit address loaded
 363		 * in A7
 364		 */
 365		slave_adr_3msb_bits = FIELD_GET(ADR_3MSB_BITS,
 366						priv->cli.slave_adr);
 367
 368		mcr |= FIELD_PREP(I2C_MCR_EA10, slave_adr_3msb_bits);
 369	} else {
 370		/* 7-bit address transaction */
 371		mcr |= FIELD_PREP(I2C_MCR_AM, 1);
 372	}
 373
 374	/* start byte procedure not applied */
 375	mcr |= FIELD_PREP(I2C_MCR_SB, 0);
 376
 377	/* check the operation, master read/write? */
 378	if (priv->cli.operation == I2C_WRITE)
 379		mcr |= FIELD_PREP(I2C_MCR_OP, I2C_WRITE);
 380	else
 381		mcr |= FIELD_PREP(I2C_MCR_OP, I2C_READ);
 382
 383	/* stop or repeated start? */
 384	if (priv->stop)
 385		mcr |= FIELD_PREP(I2C_MCR_STOP, 1);
 386	else
 387		mcr &= ~FIELD_PREP(I2C_MCR_STOP, 1);
 388
 389	mcr |= FIELD_PREP(I2C_MCR_LENGTH, priv->cli.count);
 390
 391	return mcr;
 392}
 393
 394/**
 395 * setup_i2c_controller() - setup the controller
 396 * @priv: private data of controller
 397 */
 398static void setup_i2c_controller(struct nmk_i2c_dev *priv)
 399{
 400	u32 brcr;
 401	u32 i2c_clk, div;
 402	u32 ns;
 403	u16 slsu;
 404
 405	writel(0x0, priv->virtbase + I2C_CR);
 406	writel(0x0, priv->virtbase + I2C_HSMCR);
 407	writel(0x0, priv->virtbase + I2C_TFTR);
 408	writel(0x0, priv->virtbase + I2C_RFTR);
 409	writel(0x0, priv->virtbase + I2C_DMAR);
 410
 411	i2c_clk = clk_get_rate(priv->clk);
 412
 413	/*
 414	 * set the slsu:
 415	 *
 416	 * slsu defines the data setup time after SCL clock
 417	 * stretching in terms of i2c clk cycles + 1 (zero means
 418	 * "wait one cycle"), the needed setup time for the three
 419	 * modes are 250ns, 100ns, 10ns respectively.
 420	 *
 421	 * As the time for one cycle T in nanoseconds is
 422	 * T = (1/f) * 1000000000 =>
 423	 * slsu = cycles / (1000000000 / f) + 1
 424	 */
 425	ns = DIV_ROUND_UP_ULL(1000000000ULL, i2c_clk);
 426	switch (priv->sm) {
 427	case I2C_FREQ_MODE_FAST:
 428	case I2C_FREQ_MODE_FAST_PLUS:
 429		slsu = DIV_ROUND_UP(100, ns); /* Fast */
 430		break;
 431	case I2C_FREQ_MODE_HIGH_SPEED:
 432		slsu = DIV_ROUND_UP(10, ns); /* High */
 433		break;
 434	case I2C_FREQ_MODE_STANDARD:
 435	default:
 436		slsu = DIV_ROUND_UP(250, ns); /* Standard */
 437		break;
 438	}
 439	slsu += 1;
 440
 441	dev_dbg(&priv->adev->dev, "calculated SLSU = %04x\n", slsu);
 442	writel(FIELD_PREP(I2C_SCR_SLSU, slsu), priv->virtbase + I2C_SCR);
 443
 444	/*
 445	 * The spec says, in case of std. mode the divider is
 446	 * 2 whereas it is 3 for fast and fastplus mode of
 447	 * operation.
 448	 */
 449	div = (priv->clk_freq > I2C_MAX_STANDARD_MODE_FREQ) ? 3 : 2;
 450
 451	/*
 452	 * generate the mask for baud rate counters. The controller
 453	 * has two baud rate counters. One is used for High speed
 454	 * operation, and the other is for std, fast mode, fast mode
 455	 * plus operation.
 456	 *
 457	 * BRCR is a clock divider amount. Pick highest value that
 458	 * leads to rate strictly below target. Eg when asking for
 459	 * 400kHz you want a bus rate <=400kHz (and not >=400kHz).
 460	 */
 461	brcr = DIV_ROUND_UP(i2c_clk, priv->clk_freq * div);
 462
 463	if (priv->sm == I2C_FREQ_MODE_HIGH_SPEED)
 464		brcr = FIELD_PREP(I2C_BRCR_BRCNT1, brcr);
 465	else
 466		brcr = FIELD_PREP(I2C_BRCR_BRCNT2, brcr);
 467
 468	/* set the baud rate counter register */
 469	writel(brcr, priv->virtbase + I2C_BRCR);
 470
 471	/* set the speed mode */
 472	writel(FIELD_PREP(I2C_CR_SM, priv->sm), priv->virtbase + I2C_CR);
 473
 474	/* set the Tx and Rx FIFO threshold */
 475	writel(priv->tft, priv->virtbase + I2C_TFTR);
 476	writel(priv->rft, priv->virtbase + I2C_RFTR);
 477}
 478
 479static bool nmk_i2c_wait_xfer_done(struct nmk_i2c_dev *priv)
 480{
 481	if (priv->timeout_usecs < jiffies_to_usecs(1)) {
 482		unsigned long timeout_usecs = priv->timeout_usecs;
 483		ktime_t timeout = ktime_set(0, timeout_usecs * NSEC_PER_USEC);
 484
 485		wait_event_hrtimeout(priv->xfer_wq, priv->xfer_done, timeout);
 486	} else {
 487		unsigned long timeout = usecs_to_jiffies(priv->timeout_usecs);
 488
 489		wait_event_timeout(priv->xfer_wq, priv->xfer_done, timeout);
 490	}
 491
 492	return priv->xfer_done;
 493}
 494
 495/**
 496 * read_i2c() - Read from I2C client device
 497 * @priv: private data of I2C Driver
 498 * @flags: message flags
 499 *
 500 * This function reads from i2c client device when controller is in
 501 * master mode. There is a completion timeout. If there is no transfer
 502 * before timeout error is returned.
 503 */
 504static int read_i2c(struct nmk_i2c_dev *priv, u16 flags)
 505{
 506	u32 mcr, irq_mask;
 507	int status = 0;
 508	bool xfer_done;
 509
 510	mcr = load_i2c_mcr_reg(priv, flags);
 511	writel(mcr, priv->virtbase + I2C_MCR);
 512
 513	/* load the current CR value */
 514	writel(readl(priv->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
 515	       priv->virtbase + I2C_CR);
 516
 517	/* enable the controller */
 518	i2c_set_bit(priv->virtbase + I2C_CR, I2C_CR_PE);
 519
 520	init_waitqueue_head(&priv->xfer_wq);
 521	priv->xfer_done = false;
 522
 523	/* enable interrupts by setting the mask */
 524	irq_mask = (I2C_IT_RXFNF | I2C_IT_RXFF |
 525			I2C_IT_MAL | I2C_IT_BERR);
 526
 527	if (priv->stop || !priv->vendor->has_mtdws)
 528		irq_mask |= I2C_IT_MTD;
 529	else
 530		irq_mask |= I2C_IT_MTDWS;
 531
 532	irq_mask &= I2C_CLEAR_ALL_INTS;
 533
 534	writel(readl(priv->virtbase + I2C_IMSCR) | irq_mask,
 535	       priv->virtbase + I2C_IMSCR);
 536
 537	xfer_done = nmk_i2c_wait_xfer_done(priv);
 538
 539	if (!xfer_done)
 540		status = -ETIMEDOUT;
 541
 542	return status;
 543}
 544
 545static void fill_tx_fifo(struct nmk_i2c_dev *priv, int no_bytes)
 546{
 547	int count;
 548
 549	for (count = (no_bytes - 2);
 550			(count > 0) &&
 551			(priv->cli.count != 0);
 552			count--) {
 553		/* write to the Tx FIFO */
 554		nmk_i2c_writeb(priv, *priv->cli.buffer, I2C_TFR);
 555		priv->cli.buffer++;
 556		priv->cli.count--;
 557		priv->cli.xfer_bytes++;
 558	}
 559
 560}
 561
 562/**
 563 * write_i2c() - Write data to I2C client.
 564 * @priv: private data of I2C Driver
 565 * @flags: message flags
 566 *
 567 * This function writes data to I2C client
 568 */
 569static int write_i2c(struct nmk_i2c_dev *priv, u16 flags)
 570{
 571	u32 mcr, irq_mask;
 572	u32 status = 0;
 573	bool xfer_done;
 574
 575	mcr = load_i2c_mcr_reg(priv, flags);
 576
 577	writel(mcr, priv->virtbase + I2C_MCR);
 578
 579	/* load the current CR value */
 580	writel(readl(priv->virtbase + I2C_CR) | DEFAULT_I2C_REG_CR,
 581	       priv->virtbase + I2C_CR);
 582
 583	/* enable the controller */
 584	i2c_set_bit(priv->virtbase + I2C_CR, I2C_CR_PE);
 585
 586	init_waitqueue_head(&priv->xfer_wq);
 587	priv->xfer_done = false;
 588
 589	/* enable interrupts by settings the masks */
 590	irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR);
 591
 592	/* Fill the TX FIFO with transmit data */
 593	fill_tx_fifo(priv, MAX_I2C_FIFO_THRESHOLD);
 594
 595	if (priv->cli.count != 0)
 596		irq_mask |= I2C_IT_TXFNE;
 597
 598	/*
 599	 * check if we want to transfer a single or multiple bytes, if so
 600	 * set the MTDWS bit (Master Transaction Done Without Stop)
 601	 * to start repeated start operation
 602	 */
 603	if (priv->stop || !priv->vendor->has_mtdws)
 604		irq_mask |= I2C_IT_MTD;
 605	else
 606		irq_mask |= I2C_IT_MTDWS;
 607
 608	irq_mask &= I2C_CLEAR_ALL_INTS;
 609
 610	writel(readl(priv->virtbase + I2C_IMSCR) | irq_mask,
 611	       priv->virtbase + I2C_IMSCR);
 612
 613	xfer_done = nmk_i2c_wait_xfer_done(priv);
 614
 615	if (!xfer_done) {
 616		/* Controller timed out */
 617		dev_err(&priv->adev->dev, "write to slave 0x%x timed out\n",
 618			priv->cli.slave_adr);
 619		status = -ETIMEDOUT;
 620	}
 621
 622	return status;
 623}
 624
 625/**
 626 * nmk_i2c_xfer_one() - transmit a single I2C message
 627 * @priv: device with a message encoded into it
 628 * @flags: message flags
 629 */
 630static int nmk_i2c_xfer_one(struct nmk_i2c_dev *priv, u16 flags)
 631{
 632	int status;
 633
 634	if (flags & I2C_M_RD) {
 635		/* read operation */
 636		priv->cli.operation = I2C_READ;
 637		status = read_i2c(priv, flags);
 638	} else {
 639		/* write operation */
 640		priv->cli.operation = I2C_WRITE;
 641		status = write_i2c(priv, flags);
 642	}
 643
 644	if (status || priv->result) {
 645		u32 i2c_sr;
 646		u32 cause;
 647
 648		i2c_sr = readl(priv->virtbase + I2C_SR);
 649		if (FIELD_GET(I2C_SR_STATUS, i2c_sr) == I2C_ABORT) {
 650			cause = FIELD_GET(I2C_SR_CAUSE, i2c_sr);
 651			dev_err(&priv->adev->dev, "%s\n",
 652				cause >= ARRAY_SIZE(abort_causes) ?
 653				"unknown reason" :
 654				abort_causes[cause]);
 655		}
 656
 657		init_hw(priv);
 658
 659		status = status ? status : priv->result;
 660	}
 661
 662	return status;
 663}
 664
 665/**
 666 * nmk_i2c_xfer() - I2C transfer function used by kernel framework
 667 * @i2c_adap: Adapter pointer to the controller
 668 * @msgs: Pointer to data to be written.
 669 * @num_msgs: Number of messages to be executed
 670 *
 671 * This is the function called by the generic kernel i2c_transfer()
 672 * or i2c_smbus...() API calls. Note that this code is protected by the
 673 * semaphore set in the kernel i2c_transfer() function.
 674 *
 675 * NOTE:
 676 * READ TRANSFER : We impose a restriction of the first message to be the
 677 *		index message for any read transaction.
 678 *		- a no index is coded as '0',
 679 *		- 2byte big endian index is coded as '3'
 680 *		!!! msg[0].buf holds the actual index.
 681 *		This is compatible with generic messages of smbus emulator
 682 *		that send a one byte index.
 683 *		eg. a I2C transation to read 2 bytes from index 0
 684 *			idx = 0;
 685 *			msg[0].addr = client->addr;
 686 *			msg[0].flags = 0x0;
 687 *			msg[0].len = 1;
 688 *			msg[0].buf = &idx;
 689 *
 690 *			msg[1].addr = client->addr;
 691 *			msg[1].flags = I2C_M_RD;
 692 *			msg[1].len = 2;
 693 *			msg[1].buf = rd_buff
 694 *			i2c_transfer(adap, msg, 2);
 695 *
 696 * WRITE TRANSFER : The I2C standard interface interprets all data as payload.
 697 *		If you want to emulate an SMBUS write transaction put the
 698 *		index as first byte(or first and second) in the payload.
 699 *		eg. a I2C transation to write 2 bytes from index 1
 700 *			wr_buff[0] = 0x1;
 701 *			wr_buff[1] = 0x23;
 702 *			wr_buff[2] = 0x46;
 703 *			msg[0].flags = 0x0;
 704 *			msg[0].len = 3;
 705 *			msg[0].buf = wr_buff;
 706 *			i2c_transfer(adap, msg, 1);
 707 *
 708 * To read or write a block of data (multiple bytes) using SMBUS emulation
 709 * please use the i2c_smbus_read_i2c_block_data()
 710 * or i2c_smbus_write_i2c_block_data() API
 711 */
 712static int nmk_i2c_xfer(struct i2c_adapter *i2c_adap,
 713		struct i2c_msg msgs[], int num_msgs)
 714{
 715	int status = 0;
 716	int i;
 717	struct nmk_i2c_dev *priv = i2c_get_adapdata(i2c_adap);
 718	int j;
 719
 720	pm_runtime_get_sync(&priv->adev->dev);
 721
 722	/* Attempt three times to send the message queue */
 723	for (j = 0; j < 3; j++) {
 724		/* setup the i2c controller */
 725		setup_i2c_controller(priv);
 726
 727		for (i = 0; i < num_msgs; i++) {
 728			priv->cli.slave_adr	= msgs[i].addr;
 729			priv->cli.buffer		= msgs[i].buf;
 730			priv->cli.count		= msgs[i].len;
 731			priv->stop = (i < (num_msgs - 1)) ? 0 : 1;
 732			priv->result = 0;
 733
 734			status = nmk_i2c_xfer_one(priv, msgs[i].flags);
 735			if (status != 0)
 736				break;
 737		}
 738		if (status == 0)
 739			break;
 740	}
 741
 742	pm_runtime_put_sync(&priv->adev->dev);
 743
 744	/* return the no. messages processed */
 745	if (status)
 746		return status;
 747	else
 748		return num_msgs;
 749}
 750
 751/**
 752 * disable_interrupts() - disable the interrupts
 753 * @priv: private data of controller
 754 * @irq: interrupt number
 755 */
 756static int disable_interrupts(struct nmk_i2c_dev *priv, u32 irq)
 757{
 758	irq &= I2C_CLEAR_ALL_INTS;
 759	writel(readl(priv->virtbase + I2C_IMSCR) & ~irq,
 760	       priv->virtbase + I2C_IMSCR);
 761	return 0;
 762}
 763
 764/**
 765 * i2c_irq_handler() - interrupt routine
 766 * @irq: interrupt number
 767 * @arg: data passed to the handler
 768 *
 769 * This is the interrupt handler for the i2c driver. Currently
 770 * it handles the major interrupts like Rx & Tx FIFO management
 771 * interrupts, master transaction interrupts, arbitration and
 772 * bus error interrupts. The rest of the interrupts are treated as
 773 * unhandled.
 774 */
 775static irqreturn_t i2c_irq_handler(int irq, void *arg)
 776{
 777	struct nmk_i2c_dev *priv = arg;
 778	struct device *dev = &priv->adev->dev;
 779	u32 tft, rft;
 780	u32 count;
 781	u32 misr, src;
 782
 783	/* load Tx FIFO and Rx FIFO threshold values */
 784	tft = readl(priv->virtbase + I2C_TFTR);
 785	rft = readl(priv->virtbase + I2C_RFTR);
 786
 787	/* read interrupt status register */
 788	misr = readl(priv->virtbase + I2C_MISR);
 789
 790	src = __ffs(misr);
 791	switch (BIT(src)) {
 792
 793	/* Transmit FIFO nearly empty interrupt */
 794	case I2C_IT_TXFNE:
 795	{
 796		if (priv->cli.operation == I2C_READ) {
 797			/*
 798			 * in read operation why do we care for writing?
 799			 * so disable the Transmit FIFO interrupt
 800			 */
 801			disable_interrupts(priv, I2C_IT_TXFNE);
 802		} else {
 803			fill_tx_fifo(priv, (MAX_I2C_FIFO_THRESHOLD - tft));
 804			/*
 805			 * if done, close the transfer by disabling the
 806			 * corresponding TXFNE interrupt
 807			 */
 808			if (priv->cli.count == 0)
 809				disable_interrupts(priv,	I2C_IT_TXFNE);
 810		}
 811	}
 812	break;
 813
 814	/*
 815	 * Rx FIFO nearly full interrupt.
 816	 * This is set when the numer of entries in Rx FIFO is
 817	 * greater or equal than the threshold value programmed
 818	 * in RFT
 819	 */
 820	case I2C_IT_RXFNF:
 821		for (count = rft; count > 0; count--) {
 822			/* Read the Rx FIFO */
 823			*priv->cli.buffer = nmk_i2c_readb(priv, I2C_RFR);
 824			priv->cli.buffer++;
 825		}
 826		priv->cli.count -= rft;
 827		priv->cli.xfer_bytes += rft;
 828		break;
 829
 830	/* Rx FIFO full */
 831	case I2C_IT_RXFF:
 832		for (count = MAX_I2C_FIFO_THRESHOLD; count > 0; count--) {
 833			*priv->cli.buffer = nmk_i2c_readb(priv, I2C_RFR);
 834			priv->cli.buffer++;
 835		}
 836		priv->cli.count -= MAX_I2C_FIFO_THRESHOLD;
 837		priv->cli.xfer_bytes += MAX_I2C_FIFO_THRESHOLD;
 838		break;
 839
 840	/* Master Transaction Done with/without stop */
 841	case I2C_IT_MTD:
 842	case I2C_IT_MTDWS:
 843		if (priv->cli.operation == I2C_READ) {
 844			while (!(readl(priv->virtbase + I2C_RISR)
 845				 & I2C_IT_RXFE)) {
 846				if (priv->cli.count == 0)
 847					break;
 848				*priv->cli.buffer =
 849					nmk_i2c_readb(priv, I2C_RFR);
 850				priv->cli.buffer++;
 851				priv->cli.count--;
 852				priv->cli.xfer_bytes++;
 853			}
 854		}
 855
 856		disable_all_interrupts(priv);
 857		clear_all_interrupts(priv);
 858
 859		if (priv->cli.count) {
 860			priv->result = -EIO;
 861			dev_err(dev, "%lu bytes still remain to be xfered\n",
 862				priv->cli.count);
 863			init_hw(priv);
 864		}
 865		priv->xfer_done = true;
 866		wake_up(&priv->xfer_wq);
 867
 868
 869		break;
 870
 871	/* Master Arbitration lost interrupt */
 872	case I2C_IT_MAL:
 873		priv->result = -EIO;
 874		init_hw(priv);
 875
 876		i2c_set_bit(priv->virtbase + I2C_ICR, I2C_IT_MAL);
 877		priv->xfer_done = true;
 878		wake_up(&priv->xfer_wq);
 879
 880
 881		break;
 882
 883	/*
 884	 * Bus Error interrupt.
 885	 * This happens when an unexpected start/stop condition occurs
 886	 * during the transaction.
 887	 */
 888	case I2C_IT_BERR:
 889	{
 890		u32 sr;
 891
 892		sr = readl(priv->virtbase + I2C_SR);
 893		priv->result = -EIO;
 894		if (FIELD_GET(I2C_SR_STATUS, sr) == I2C_ABORT)
 895			init_hw(priv);
 896
 897		i2c_set_bit(priv->virtbase + I2C_ICR, I2C_IT_BERR);
 898		priv->xfer_done = true;
 899		wake_up(&priv->xfer_wq);
 900
 901	}
 902	break;
 903
 904	/*
 905	 * Tx FIFO overrun interrupt.
 906	 * This is set when a write operation in Tx FIFO is performed and
 907	 * the Tx FIFO is full.
 908	 */
 909	case I2C_IT_TXFOVR:
 910		priv->result = -EIO;
 911		init_hw(priv);
 912
 913		dev_err(dev, "Tx Fifo Over run\n");
 914		priv->xfer_done = true;
 915		wake_up(&priv->xfer_wq);
 916
 917
 918		break;
 919
 920	/* unhandled interrupts by this driver - TODO*/
 921	case I2C_IT_TXFE:
 922	case I2C_IT_TXFF:
 923	case I2C_IT_RXFE:
 924	case I2C_IT_RFSR:
 925	case I2C_IT_RFSE:
 926	case I2C_IT_WTSR:
 927	case I2C_IT_STD:
 928		dev_err(dev, "unhandled Interrupt\n");
 929		break;
 930	default:
 931		dev_err(dev, "spurious Interrupt..\n");
 932		break;
 933	}
 934
 935	return IRQ_HANDLED;
 936}
 937
 938static int nmk_i2c_suspend_late(struct device *dev)
 939{
 940	int ret;
 941
 942	ret = pm_runtime_force_suspend(dev);
 943	if (ret)
 944		return ret;
 945
 946	pinctrl_pm_select_sleep_state(dev);
 947	return 0;
 948}
 949
 950static int nmk_i2c_resume_early(struct device *dev)
 951{
 952	return pm_runtime_force_resume(dev);
 953}
 954
 955static int nmk_i2c_runtime_suspend(struct device *dev)
 956{
 957	struct amba_device *adev = to_amba_device(dev);
 958	struct nmk_i2c_dev *priv = amba_get_drvdata(adev);
 959
 960	clk_disable_unprepare(priv->clk);
 961	pinctrl_pm_select_idle_state(dev);
 962	return 0;
 963}
 964
 965static int nmk_i2c_runtime_resume(struct device *dev)
 966{
 967	struct amba_device *adev = to_amba_device(dev);
 968	struct nmk_i2c_dev *priv = amba_get_drvdata(adev);
 969	int ret;
 970
 971	ret = clk_prepare_enable(priv->clk);
 972	if (ret) {
 973		dev_err(dev, "can't prepare_enable clock\n");
 974		return ret;
 975	}
 976
 977	pinctrl_pm_select_default_state(dev);
 978
 979	ret = init_hw(priv);
 980	if (ret) {
 981		clk_disable_unprepare(priv->clk);
 982		pinctrl_pm_select_idle_state(dev);
 983	}
 984
 985	return ret;
 986}
 987
 988static const struct dev_pm_ops nmk_i2c_pm = {
 989	LATE_SYSTEM_SLEEP_PM_OPS(nmk_i2c_suspend_late, nmk_i2c_resume_early)
 990	RUNTIME_PM_OPS(nmk_i2c_runtime_suspend, nmk_i2c_runtime_resume, NULL)
 991};
 992
 993static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap)
 994{
 995	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
 996}
 997
 998static const struct i2c_algorithm nmk_i2c_algo = {
 999	.xfer = nmk_i2c_xfer,
1000	.functionality = nmk_i2c_functionality
1001};
1002
1003static void nmk_i2c_of_probe(struct device_node *np,
1004			     struct nmk_i2c_dev *priv)
1005{
1006	u32 timeout_usecs;
1007
1008	/* Default to 100 kHz if no frequency is given in the node */
1009	if (of_property_read_u32(np, "clock-frequency", &priv->clk_freq))
1010		priv->clk_freq = I2C_MAX_STANDARD_MODE_FREQ;
1011
1012	if (priv->clk_freq <= I2C_MAX_STANDARD_MODE_FREQ)
1013		priv->sm = I2C_FREQ_MODE_STANDARD;
1014	else if (priv->clk_freq <= I2C_MAX_FAST_MODE_FREQ)
1015		priv->sm = I2C_FREQ_MODE_FAST;
1016	else if (priv->clk_freq <= I2C_MAX_FAST_MODE_PLUS_FREQ)
1017		priv->sm = I2C_FREQ_MODE_FAST_PLUS;
1018	else
1019		priv->sm = I2C_FREQ_MODE_HIGH_SPEED;
1020	priv->tft = 1; /* Tx FIFO threshold */
1021	priv->rft = 8; /* Rx FIFO threshold */
1022
1023	/* Slave response timeout */
1024	if (!of_property_read_u32(np, "i2c-transfer-timeout-us", &timeout_usecs))
1025		priv->timeout_usecs = timeout_usecs;
1026	else
1027		priv->timeout_usecs = 200 * USEC_PER_MSEC;
1028}
1029
1030static const unsigned int nmk_i2c_eyeq5_masks[] = {
1031	GENMASK(5, 4),
1032	GENMASK(7, 6),
1033	GENMASK(9, 8),
1034	GENMASK(11, 10),
1035	GENMASK(13, 12),
1036};
1037
1038static int nmk_i2c_eyeq5_probe(struct nmk_i2c_dev *priv)
1039{
1040	struct device *dev = &priv->adev->dev;
1041	struct device_node *np = dev->of_node;
1042	unsigned int mask, speed_mode;
1043	struct regmap *olb;
1044	unsigned int id;
1045
1046	olb = syscon_regmap_lookup_by_phandle_args(np, "mobileye,olb", 1, &id);
1047	if (IS_ERR(olb))
1048		return PTR_ERR(olb);
1049	if (id >= ARRAY_SIZE(nmk_i2c_eyeq5_masks))
1050		return -ENOENT;
1051
1052	if (priv->clk_freq <= 400000)
1053		speed_mode = I2C_EYEQ5_SPEED_FAST;
1054	else if (priv->clk_freq <= 1000000)
1055		speed_mode = I2C_EYEQ5_SPEED_FAST_PLUS;
1056	else
1057		speed_mode = I2C_EYEQ5_SPEED_HIGH_SPEED;
1058
1059	mask = nmk_i2c_eyeq5_masks[id];
1060	regmap_update_bits(olb, NMK_I2C_EYEQ5_OLB_IOCR2,
1061			   mask, speed_mode << __fls(mask));
1062
1063	return 0;
1064}
1065
1066#define NMK_I2C_EYEQ_FLAG_32B_BUS	BIT(0)
1067#define NMK_I2C_EYEQ_FLAG_IS_EYEQ5	BIT(1)
1068
1069static const struct of_device_id nmk_i2c_eyeq_match_table[] = {
1070	{
1071		.compatible = "mobileye,eyeq5-i2c",
1072		.data = (void *)(NMK_I2C_EYEQ_FLAG_32B_BUS | NMK_I2C_EYEQ_FLAG_IS_EYEQ5),
1073	},
1074	{
1075		.compatible = "mobileye,eyeq6h-i2c",
1076		.data = (void *)NMK_I2C_EYEQ_FLAG_32B_BUS,
1077	},
1078	{ /* sentinel */ }
1079};
1080
1081static int nmk_i2c_probe(struct amba_device *adev, const struct amba_id *id)
1082{
1083	struct i2c_vendor_data *vendor = id->data;
1084	u32 max_fifo_threshold = (vendor->fifodepth / 2) - 1;
1085	struct device_node *np = adev->dev.of_node;
1086	const struct of_device_id *match;
1087	struct device *dev = &adev->dev;
1088	unsigned long match_flags = 0;
1089	struct nmk_i2c_dev *priv;
1090	struct i2c_adapter *adap;
1091	int ret = 0;
1092
1093	/*
1094	 * We do not want to attach a .of_match_table to our amba driver.
1095	 * Do not convert to device_get_match_data().
1096	 */
1097	match = of_match_device(nmk_i2c_eyeq_match_table, dev);
1098	if (match)
1099		match_flags = (unsigned long)match->data;
1100
1101	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1102	if (!priv)
1103		return -ENOMEM;
1104
1105	priv->vendor = vendor;
1106	priv->adev = adev;
1107	priv->has_32b_bus = match_flags & NMK_I2C_EYEQ_FLAG_32B_BUS;
1108	nmk_i2c_of_probe(np, priv);
1109
1110	if (match_flags & NMK_I2C_EYEQ_FLAG_IS_EYEQ5) {
1111		ret = nmk_i2c_eyeq5_probe(priv);
1112		if (ret)
1113			return dev_err_probe(dev, ret, "failed OLB lookup\n");
1114	}
1115
1116	if (priv->tft > max_fifo_threshold) {
1117		dev_warn(dev, "requested TX FIFO threshold %u, adjusted down to %u\n",
1118			 priv->tft, max_fifo_threshold);
1119		priv->tft = max_fifo_threshold;
1120	}
1121
1122	if (priv->rft > max_fifo_threshold) {
1123		dev_warn(dev, "requested RX FIFO threshold %u, adjusted down to %u\n",
1124			 priv->rft, max_fifo_threshold);
1125		priv->rft = max_fifo_threshold;
1126	}
1127
1128	amba_set_drvdata(adev, priv);
1129
1130	priv->virtbase = devm_ioremap(dev, adev->res.start,
1131				      resource_size(&adev->res));
1132	if (!priv->virtbase)
1133		return -ENOMEM;
1134
1135	priv->irq = adev->irq[0];
1136	ret = devm_request_irq(dev, priv->irq, i2c_irq_handler, 0,
1137			       DRIVER_NAME, priv);
1138	if (ret)
1139		return dev_err_probe(dev, ret,
1140				     "cannot claim the irq %d\n", priv->irq);
1141
1142	priv->clk = devm_clk_get_enabled(dev, NULL);
1143	if (IS_ERR(priv->clk))
1144		return dev_err_probe(dev, PTR_ERR(priv->clk),
1145				     "could enable i2c clock\n");
1146
1147	init_hw(priv);
1148
1149	adap = &priv->adap;
1150	adap->dev.of_node = np;
1151	adap->dev.parent = dev;
1152	adap->owner = THIS_MODULE;
1153	adap->class = I2C_CLASS_DEPRECATED;
1154	adap->algo = &nmk_i2c_algo;
1155	adap->timeout = usecs_to_jiffies(priv->timeout_usecs);
1156	snprintf(adap->name, sizeof(adap->name),
1157		 "Nomadik I2C at %pR", &adev->res);
1158
1159	i2c_set_adapdata(adap, priv);
1160
1161	dev_info(dev,
1162		 "initialize %s on virtual base %p\n",
1163		 adap->name, priv->virtbase);
1164
1165	ret = i2c_add_adapter(adap);
1166	if (ret)
1167		return ret;
1168
1169	pm_runtime_put(dev);
1170
1171	return 0;
1172}
1173
1174static void nmk_i2c_remove(struct amba_device *adev)
1175{
1176	struct nmk_i2c_dev *priv = amba_get_drvdata(adev);
1177
1178	i2c_del_adapter(&priv->adap);
1179	flush_i2c_fifo(priv);
1180	disable_all_interrupts(priv);
1181	clear_all_interrupts(priv);
1182	/* disable the controller */
1183	i2c_clr_bit(priv->virtbase + I2C_CR, I2C_CR_PE);
1184}
1185
1186static struct i2c_vendor_data vendor_stn8815 = {
1187	.has_mtdws = false,
1188	.fifodepth = 16, /* Guessed from TFTR/RFTR = 7 */
1189};
1190
1191static struct i2c_vendor_data vendor_db8500 = {
1192	.has_mtdws = true,
1193	.fifodepth = 32, /* Guessed from TFTR/RFTR = 15 */
1194};
1195
1196static const struct amba_id nmk_i2c_ids[] = {
1197	{
1198		.id	= 0x00180024,
1199		.mask	= 0x00ffffff,
1200		.data	= &vendor_stn8815,
1201	},
1202	{
1203		.id	= 0x00380024,
1204		.mask	= 0x00ffffff,
1205		.data	= &vendor_db8500,
1206	},
1207	{},
1208};
1209
1210MODULE_DEVICE_TABLE(amba, nmk_i2c_ids);
1211
1212static struct amba_driver nmk_i2c_driver = {
1213	.drv = {
1214		.name = DRIVER_NAME,
1215		.pm = pm_ptr(&nmk_i2c_pm),
1216	},
1217	.id_table = nmk_i2c_ids,
1218	.probe = nmk_i2c_probe,
1219	.remove = nmk_i2c_remove,
1220};
1221
1222static int __init nmk_i2c_init(void)
1223{
1224	return amba_driver_register(&nmk_i2c_driver);
1225}
1226
1227static void __exit nmk_i2c_exit(void)
1228{
1229	amba_driver_unregister(&nmk_i2c_driver);
1230}
1231
1232subsys_initcall(nmk_i2c_init);
1233module_exit(nmk_i2c_exit);
1234
1235MODULE_AUTHOR("Sachin Verma");
1236MODULE_AUTHOR("Srinidhi KASAGAR");
1237MODULE_DESCRIPTION("Nomadik/Ux500 I2C driver");
1238MODULE_LICENSE("GPL");