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i2c-mlxbf.c
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linux-6.19.14/drivers/i2c/busses/i2c-mlxbf.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Mellanox BlueField I2C bus driver 4 * 5 * Copyright (C) 2020 Mellanox Technologies, Ltd. 6 */ 7 8#include <linux/acpi.h> 9#include <linux/bitfield.h> 10#include <linux/delay.h> 11#include <linux/err.h> 12#include <linux/interrupt.h> 13#include <linux/i2c.h> 14#include <linux/io.h> 15#include <linux/iopoll.h> 16#include <linux/kernel.h> 17#include <linux/module.h> 18#include <linux/mutex.h> 19#include <linux/of.h> 20#include <linux/platform_device.h> 21#include <linux/string.h> 22#include <linux/string_choices.h> 23 24/* Defines what functionality is present. */ 25#define MLXBF_I2C_FUNC_SMBUS_BLOCK \ 26 (I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL) 27 28#define MLXBF_I2C_FUNC_SMBUS_DEFAULT \ 29 (I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA | \ 30 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_I2C_BLOCK | \ 31 I2C_FUNC_SMBUS_PROC_CALL) 32 33#define MLXBF_I2C_FUNC_ALL \ 34 (MLXBF_I2C_FUNC_SMBUS_DEFAULT | MLXBF_I2C_FUNC_SMBUS_BLOCK | \ 35 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SLAVE) 36 37/* Shared resources info in BlueField platforms. */ 38 39#define MLXBF_I2C_COALESCE_TYU_ADDR 0x02801300 40#define MLXBF_I2C_COALESCE_TYU_SIZE 0x010 41 42#define MLXBF_I2C_GPIO_TYU_ADDR 0x02802000 43#define MLXBF_I2C_GPIO_TYU_SIZE 0x100 44 45#define MLXBF_I2C_COREPLL_TYU_ADDR 0x02800358 46#define MLXBF_I2C_COREPLL_TYU_SIZE 0x008 47 48#define MLXBF_I2C_COREPLL_YU_ADDR 0x02800c30 49#define MLXBF_I2C_COREPLL_YU_SIZE 0x00c 50 51#define MLXBF_I2C_COREPLL_RSH_YU_ADDR 0x13409824 52#define MLXBF_I2C_COREPLL_RSH_YU_SIZE 0x00c 53 54#define MLXBF_I2C_SHARED_RES_MAX 3 55 56/* 57 * Note that the following SMBus, CAUSE, GPIO and PLL register addresses 58 * refer to their respective offsets relative to the corresponding 59 * memory-mapped region whose addresses are specified in either the DT or 60 * the ACPI tables or above. 61 */ 62 63/* 64 * SMBus Master core clock frequency. Timing configurations are 65 * strongly dependent on the core clock frequency of the SMBus 66 * Master. Default value is set to 400MHz. 67 */ 68#define MLXBF_I2C_TYU_PLL_OUT_FREQ (400 * 1000 * 1000) 69/* Reference clock for Bluefield - 156 MHz. */ 70#define MLXBF_I2C_PLL_IN_FREQ 156250000ULL 71 72/* Constant used to determine the PLL frequency. */ 73#define MLNXBF_I2C_COREPLL_CONST 16384ULL 74 75#define MLXBF_I2C_FREQUENCY_1GHZ 1000000000ULL 76 77/* PLL registers. */ 78#define MLXBF_I2C_CORE_PLL_REG1 0x4 79#define MLXBF_I2C_CORE_PLL_REG2 0x8 80 81/* OR cause register. */ 82#define MLXBF_I2C_CAUSE_OR_EVTEN0 0x14 83#define MLXBF_I2C_CAUSE_OR_CLEAR 0x18 84 85/* Arbiter Cause Register. */ 86#define MLXBF_I2C_CAUSE_ARBITER 0x1c 87 88/* 89 * Cause Status flags. Note that those bits might be considered 90 * as interrupt enabled bits. 91 */ 92 93/* Transaction ended with STOP. */ 94#define MLXBF_I2C_CAUSE_TRANSACTION_ENDED BIT(0) 95/* Master arbitration lost. */ 96#define MLXBF_I2C_CAUSE_M_ARBITRATION_LOST BIT(1) 97/* Unexpected start detected. */ 98#define MLXBF_I2C_CAUSE_UNEXPECTED_START BIT(2) 99/* Unexpected stop detected. */ 100#define MLXBF_I2C_CAUSE_UNEXPECTED_STOP BIT(3) 101/* Wait for transfer continuation. */ 102#define MLXBF_I2C_CAUSE_WAIT_FOR_FW_DATA BIT(4) 103/* Failed to generate STOP. */ 104#define MLXBF_I2C_CAUSE_PUT_STOP_FAILED BIT(5) 105/* Failed to generate START. */ 106#define MLXBF_I2C_CAUSE_PUT_START_FAILED BIT(6) 107/* Clock toggle completed. */ 108#define MLXBF_I2C_CAUSE_CLK_TOGGLE_DONE BIT(7) 109/* Transfer timeout occurred. */ 110#define MLXBF_I2C_CAUSE_M_FW_TIMEOUT BIT(8) 111/* Master busy bit reset. */ 112#define MLXBF_I2C_CAUSE_M_GW_BUSY_FALL BIT(9) 113 114#define MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK GENMASK(9, 0) 115 116#define MLXBF_I2C_CAUSE_MASTER_STATUS_ERROR \ 117 (MLXBF_I2C_CAUSE_M_ARBITRATION_LOST | \ 118 MLXBF_I2C_CAUSE_UNEXPECTED_START | \ 119 MLXBF_I2C_CAUSE_UNEXPECTED_STOP | \ 120 MLXBF_I2C_CAUSE_PUT_STOP_FAILED | \ 121 MLXBF_I2C_CAUSE_PUT_START_FAILED | \ 122 MLXBF_I2C_CAUSE_CLK_TOGGLE_DONE | \ 123 MLXBF_I2C_CAUSE_M_FW_TIMEOUT) 124 125/* 126 * Slave cause status flags. Note that those bits might be considered 127 * as interrupt enabled bits. 128 */ 129 130/* Write transaction received successfully. */ 131#define MLXBF_I2C_CAUSE_WRITE_SUCCESS BIT(0) 132/* Read transaction received, waiting for response. */ 133#define MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE BIT(13) 134/* Slave busy bit reset. */ 135#define MLXBF_I2C_CAUSE_S_GW_BUSY_FALL BIT(18) 136 137/* Cause coalesce registers. */ 138#define MLXBF_I2C_CAUSE_COALESCE_0 0x00 139 140#define MLXBF_I2C_CAUSE_TYU_SLAVE_BIT 3 141#define MLXBF_I2C_CAUSE_YU_SLAVE_BIT 1 142 143/* Functional enable register. */ 144#define MLXBF_I2C_GPIO_0_FUNC_EN_0 0x28 145/* Force OE enable register. */ 146#define MLXBF_I2C_GPIO_0_FORCE_OE_EN 0x30 147/* 148 * Note that Smbus GWs are on GPIOs 30:25. Two pins are used to control 149 * SDA/SCL lines: 150 * 151 * SMBUS GW0 -> bits[26:25] 152 * SMBUS GW1 -> bits[28:27] 153 * SMBUS GW2 -> bits[30:29] 154 */ 155#define MLXBF_I2C_GPIO_SMBUS_GW_PINS(num) (25 + ((num) << 1)) 156 157/* Note that gw_id can be 0,1 or 2. */ 158#define MLXBF_I2C_GPIO_SMBUS_GW_MASK(num) \ 159 (0xffffffff & (~(0x3 << MLXBF_I2C_GPIO_SMBUS_GW_PINS(num)))) 160 161#define MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(num, val) \ 162 ((val) & MLXBF_I2C_GPIO_SMBUS_GW_MASK(num)) 163 164#define MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(num, val) \ 165 ((val) | (0x3 << MLXBF_I2C_GPIO_SMBUS_GW_PINS(num))) 166 167/* 168 * Defines SMBus operating frequency and core clock frequency. 169 * According to ADB files, default values are compliant to 100KHz SMBus 170 * @ 400MHz core clock. The driver should be able to calculate core 171 * frequency based on PLL parameters. 172 */ 173#define MLXBF_I2C_COREPLL_FREQ MLXBF_I2C_TYU_PLL_OUT_FREQ 174 175/* Core PLL TYU configuration. */ 176#define MLXBF_I2C_COREPLL_CORE_F_TYU_MASK GENMASK(15, 3) 177#define MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK GENMASK(19, 16) 178#define MLXBF_I2C_COREPLL_CORE_R_TYU_MASK GENMASK(25, 20) 179 180/* Core PLL YU configuration. */ 181#define MLXBF_I2C_COREPLL_CORE_F_YU_MASK GENMASK(25, 0) 182#define MLXBF_I2C_COREPLL_CORE_OD_YU_MASK GENMASK(3, 0) 183#define MLXBF_I2C_COREPLL_CORE_R_YU_MASK GENMASK(31, 26) 184 185/* SMBus timing parameters. */ 186#define MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH 0x00 187#define MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE 0x04 188#define MLXBF_I2C_SMBUS_TIMER_THOLD 0x08 189#define MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP 0x0c 190#define MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA 0x10 191#define MLXBF_I2C_SMBUS_THIGH_MAX_TBUF 0x14 192#define MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT 0x18 193 194#define MLXBF_I2C_SHIFT_0 0 195#define MLXBF_I2C_SHIFT_8 8 196#define MLXBF_I2C_SHIFT_16 16 197#define MLXBF_I2C_SHIFT_24 24 198 199#define MLXBF_I2C_MASK_8 GENMASK(7, 0) 200#define MLXBF_I2C_MASK_16 GENMASK(15, 0) 201#define MLXBF_I2C_MASK_32 GENMASK(31, 0) 202 203#define MLXBF_I2C_MST_ADDR_OFFSET 0x200 204 205/* SMBus Master GW. */ 206#define MLXBF_I2C_SMBUS_MASTER_GW 0x0 207/* Number of bytes received and sent. */ 208#define MLXBF_I2C_YU_SMBUS_RS_BYTES 0x100 209#define MLXBF_I2C_RSH_YU_SMBUS_RS_BYTES 0x10c 210/* Packet error check (PEC) value. */ 211#define MLXBF_I2C_SMBUS_MASTER_PEC 0x104 212/* Status bits (ACK/NACK/FW Timeout). */ 213#define MLXBF_I2C_SMBUS_MASTER_STATUS 0x108 214/* SMbus Master Finite State Machine. */ 215#define MLXBF_I2C_YU_SMBUS_MASTER_FSM 0x110 216#define MLXBF_I2C_RSH_YU_SMBUS_MASTER_FSM 0x100 217 218/* SMBus master GW control bits offset in MLXBF_I2C_SMBUS_MASTER_GW[31:3]. */ 219#define MLXBF_I2C_MASTER_LOCK_BIT BIT(31) /* Lock bit. */ 220#define MLXBF_I2C_MASTER_BUSY_BIT BIT(30) /* Busy bit. */ 221#define MLXBF_I2C_MASTER_START_BIT BIT(29) /* Control start. */ 222#define MLXBF_I2C_MASTER_CTL_WRITE_BIT BIT(28) /* Control write phase. */ 223#define MLXBF_I2C_MASTER_CTL_READ_BIT BIT(19) /* Control read phase. */ 224#define MLXBF_I2C_MASTER_STOP_BIT BIT(3) /* Control stop. */ 225 226#define MLXBF_I2C_MASTER_ENABLE \ 227 (MLXBF_I2C_MASTER_LOCK_BIT | MLXBF_I2C_MASTER_BUSY_BIT | \ 228 MLXBF_I2C_MASTER_START_BIT) 229 230#define MLXBF_I2C_MASTER_ENABLE_WRITE \ 231 (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_WRITE_BIT) 232 233#define MLXBF_I2C_MASTER_ENABLE_READ \ 234 (MLXBF_I2C_MASTER_ENABLE | MLXBF_I2C_MASTER_CTL_READ_BIT) 235 236#define MLXBF_I2C_MASTER_WRITE_SHIFT 21 /* Control write bytes */ 237#define MLXBF_I2C_MASTER_SEND_PEC_SHIFT 20 /* Send PEC byte when set to 1 */ 238#define MLXBF_I2C_MASTER_PARSE_EXP_SHIFT 11 /* Control parse expected bytes */ 239#define MLXBF_I2C_MASTER_SLV_ADDR_SHIFT 12 /* Slave address */ 240#define MLXBF_I2C_MASTER_READ_SHIFT 4 /* Control read bytes */ 241 242/* SMBus master GW Data descriptor. */ 243#define MLXBF_I2C_MASTER_DATA_DESC_ADDR 0x80 244#define MLXBF_I2C_MASTER_DATA_DESC_SIZE 0x80 /* Size in bytes. */ 245 246/* Maximum bytes to read/write per SMBus transaction. */ 247#define MLXBF_I2C_MASTER_DATA_R_LENGTH MLXBF_I2C_MASTER_DATA_DESC_SIZE 248#define MLXBF_I2C_MASTER_DATA_W_LENGTH (MLXBF_I2C_MASTER_DATA_DESC_SIZE - 1) 249 250/* All bytes were transmitted. */ 251#define MLXBF_I2C_SMBUS_STATUS_BYTE_CNT_DONE BIT(0) 252/* NACK received. */ 253#define MLXBF_I2C_SMBUS_STATUS_NACK_RCV BIT(1) 254/* Slave's byte count >128 bytes. */ 255#define MLXBF_I2C_SMBUS_STATUS_READ_ERR BIT(2) 256/* Timeout occurred. */ 257#define MLXBF_I2C_SMBUS_STATUS_FW_TIMEOUT BIT(3) 258 259#define MLXBF_I2C_SMBUS_MASTER_STATUS_MASK GENMASK(3, 0) 260 261#define MLXBF_I2C_SMBUS_MASTER_STATUS_ERROR \ 262 (MLXBF_I2C_SMBUS_STATUS_NACK_RCV | \ 263 MLXBF_I2C_SMBUS_STATUS_READ_ERR | \ 264 MLXBF_I2C_SMBUS_STATUS_FW_TIMEOUT) 265 266#define MLXBF_I2C_SMBUS_MASTER_FSM_STOP_MASK BIT(31) 267#define MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK BIT(15) 268 269#define MLXBF_I2C_SLV_ADDR_OFFSET 0x400 270 271/* SMBus slave GW. */ 272#define MLXBF_I2C_SMBUS_SLAVE_GW 0x0 273/* Number of bytes received and sent from/to master. */ 274#define MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES 0x100 275/* Packet error check (PEC) value. */ 276#define MLXBF_I2C_SMBUS_SLAVE_PEC 0x104 277/* SMBus slave Finite State Machine (FSM). */ 278#define MLXBF_I2C_SMBUS_SLAVE_FSM 0x110 279/* 280 * Should be set when all raised causes handled, and cleared by HW on 281 * every new cause. 282 */ 283#define MLXBF_I2C_SMBUS_SLAVE_READY 0x12c 284 285/* SMBus slave GW control bits offset in MLXBF_I2C_SMBUS_SLAVE_GW[31:19]. */ 286#define MLXBF_I2C_SLAVE_BUSY_BIT BIT(30) /* Busy bit. */ 287#define MLXBF_I2C_SLAVE_WRITE_BIT BIT(29) /* Control write enable. */ 288 289#define MLXBF_I2C_SLAVE_ENABLE \ 290 (MLXBF_I2C_SLAVE_BUSY_BIT | MLXBF_I2C_SLAVE_WRITE_BIT) 291 292#define MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT 22 /* Number of bytes to write. */ 293#define MLXBF_I2C_SLAVE_SEND_PEC_SHIFT 21 /* Send PEC byte shift. */ 294 295/* SMBus slave GW Data descriptor. */ 296#define MLXBF_I2C_SLAVE_DATA_DESC_ADDR 0x80 297#define MLXBF_I2C_SLAVE_DATA_DESC_SIZE 0x80 /* Size in bytes. */ 298 299/* SMbus slave configuration registers. */ 300#define MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG 0x114 301#define MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT 16 302#define MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT BIT(7) 303#define MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK GENMASK(6, 0) 304 305/* 306 * Timeout is given in microsends. Note also that timeout handling is not 307 * exact. 308 */ 309#define MLXBF_I2C_SMBUS_TIMEOUT (300 * 1000) /* 300ms */ 310#define MLXBF_I2C_SMBUS_LOCK_POLL_TIMEOUT (300 * 1000) /* 300ms */ 311 312/* Polling frequency in microseconds. */ 313#define MLXBF_I2C_POLL_FREQ_IN_USEC 200 314 315#define MLXBF_I2C_SMBUS_OP_CNT_1 1 316#define MLXBF_I2C_SMBUS_OP_CNT_2 2 317#define MLXBF_I2C_SMBUS_OP_CNT_3 3 318#define MLXBF_I2C_SMBUS_MAX_OP_CNT MLXBF_I2C_SMBUS_OP_CNT_3 319 320/* Helper macro to define an I2C resource parameters. */ 321#define MLXBF_I2C_RES_PARAMS(addr, size, str) \ 322 { \ 323 .start = (addr), \ 324 .end = (addr) + (size) - 1, \ 325 .name = (str) \ 326 } 327 328enum { 329 MLXBF_I2C_TIMING_100KHZ = 100000, 330 MLXBF_I2C_TIMING_400KHZ = 400000, 331 MLXBF_I2C_TIMING_1000KHZ = 1000000, 332}; 333 334enum { 335 MLXBF_I2C_F_READ = BIT(0), 336 MLXBF_I2C_F_WRITE = BIT(1), 337 MLXBF_I2C_F_NORESTART = BIT(3), 338 MLXBF_I2C_F_SMBUS_OPERATION = BIT(4), 339 MLXBF_I2C_F_SMBUS_BLOCK = BIT(5), 340 MLXBF_I2C_F_SMBUS_PEC = BIT(6), 341 MLXBF_I2C_F_SMBUS_PROCESS_CALL = BIT(7), 342 MLXBF_I2C_F_WRITE_WITHOUT_STOP = BIT(8), 343}; 344 345/* Mellanox BlueField chip type. */ 346enum mlxbf_i2c_chip_type { 347 MLXBF_I2C_CHIP_TYPE_1, /* Mellanox BlueField-1 chip. */ 348 MLXBF_I2C_CHIP_TYPE_2, /* Mellanox BlueField-2 chip. */ 349 MLXBF_I2C_CHIP_TYPE_3 /* Mellanox BlueField-3 chip. */ 350}; 351 352/* List of chip resources that are being accessed by the driver. */ 353enum { 354 MLXBF_I2C_SMBUS_RES, 355 MLXBF_I2C_MST_CAUSE_RES, 356 MLXBF_I2C_SLV_CAUSE_RES, 357 MLXBF_I2C_COALESCE_RES, 358 MLXBF_I2C_SMBUS_TIMER_RES, 359 MLXBF_I2C_SMBUS_MST_RES, 360 MLXBF_I2C_SMBUS_SLV_RES, 361 MLXBF_I2C_COREPLL_RES, 362 MLXBF_I2C_GPIO_RES, 363 MLXBF_I2C_END_RES 364}; 365 366/* Encapsulates timing parameters. */ 367struct mlxbf_i2c_timings { 368 u16 scl_high; /* Clock high period. */ 369 u16 scl_low; /* Clock low period. */ 370 u8 sda_rise; /* Data rise time. */ 371 u8 sda_fall; /* Data fall time. */ 372 u8 scl_rise; /* Clock rise time. */ 373 u8 scl_fall; /* Clock fall time. */ 374 u16 hold_start; /* Hold time after (REPEATED) START. */ 375 u16 hold_data; /* Data hold time. */ 376 u16 setup_start; /* REPEATED START condition setup time. */ 377 u16 setup_stop; /* STOP condition setup time. */ 378 u16 setup_data; /* Data setup time. */ 379 u16 pad; /* Padding. */ 380 u16 buf; /* Bus free time between STOP and START. */ 381 u16 thigh_max; /* Thigh max. */ 382 u32 timeout; /* Detect clock low timeout. */ 383}; 384 385struct mlxbf_i2c_smbus_operation { 386 u32 flags; 387 u32 length; /* Buffer length in bytes. */ 388 u8 *buffer; 389}; 390 391struct mlxbf_i2c_smbus_request { 392 u8 slave; 393 u8 operation_cnt; 394 struct mlxbf_i2c_smbus_operation operation[MLXBF_I2C_SMBUS_MAX_OP_CNT]; 395}; 396 397struct mlxbf_i2c_resource { 398 void __iomem *io; 399 struct resource *params; 400 struct mutex *lock; /* Mutex to protect mlxbf_i2c_resource. */ 401 u8 type; 402}; 403 404struct mlxbf_i2c_chip_info { 405 enum mlxbf_i2c_chip_type type; 406 /* Chip shared resources that are being used by the I2C controller. */ 407 struct mlxbf_i2c_resource *shared_res[MLXBF_I2C_SHARED_RES_MAX]; 408 409 /* Callback to calculate the core PLL frequency. */ 410 u64 (*calculate_freq)(struct mlxbf_i2c_resource *corepll_res); 411 412 /* Registers' address offset */ 413 u32 smbus_master_rs_bytes_off; 414 u32 smbus_master_fsm_off; 415}; 416 417struct mlxbf_i2c_priv { 418 const struct mlxbf_i2c_chip_info *chip; 419 struct i2c_adapter adap; 420 struct mlxbf_i2c_resource *smbus; 421 struct mlxbf_i2c_resource *timer; 422 struct mlxbf_i2c_resource *mst; 423 struct mlxbf_i2c_resource *slv; 424 struct mlxbf_i2c_resource *mst_cause; 425 struct mlxbf_i2c_resource *slv_cause; 426 struct mlxbf_i2c_resource *coalesce; 427 u64 frequency; /* Core frequency in Hz. */ 428 int bus; /* Physical bus identifier. */ 429 int irq; 430 struct i2c_client *slave[MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT]; 431 u32 resource_version; 432}; 433 434/* Core PLL frequency. */ 435static u64 mlxbf_i2c_corepll_frequency; 436 437static struct resource mlxbf_i2c_coalesce_tyu_params = 438 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COALESCE_TYU_ADDR, 439 MLXBF_I2C_COALESCE_TYU_SIZE, 440 "COALESCE_MEM"); 441static struct resource mlxbf_i2c_corepll_tyu_params = 442 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_TYU_ADDR, 443 MLXBF_I2C_COREPLL_TYU_SIZE, 444 "COREPLL_MEM"); 445static struct resource mlxbf_i2c_corepll_yu_params = 446 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_YU_ADDR, 447 MLXBF_I2C_COREPLL_YU_SIZE, 448 "COREPLL_MEM"); 449static struct resource mlxbf_i2c_corepll_rsh_yu_params = 450 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_COREPLL_RSH_YU_ADDR, 451 MLXBF_I2C_COREPLL_RSH_YU_SIZE, 452 "COREPLL_MEM"); 453static struct resource mlxbf_i2c_gpio_tyu_params = 454 MLXBF_I2C_RES_PARAMS(MLXBF_I2C_GPIO_TYU_ADDR, 455 MLXBF_I2C_GPIO_TYU_SIZE, 456 "GPIO_MEM"); 457 458static struct mutex mlxbf_i2c_coalesce_lock; 459static struct mutex mlxbf_i2c_corepll_lock; 460static struct mutex mlxbf_i2c_gpio_lock; 461 462static struct mlxbf_i2c_resource mlxbf_i2c_coalesce_res[] = { 463 [MLXBF_I2C_CHIP_TYPE_1] = { 464 .params = &mlxbf_i2c_coalesce_tyu_params, 465 .lock = &mlxbf_i2c_coalesce_lock, 466 .type = MLXBF_I2C_COALESCE_RES 467 }, 468 {} 469}; 470 471static struct mlxbf_i2c_resource mlxbf_i2c_corepll_res[] = { 472 [MLXBF_I2C_CHIP_TYPE_1] = { 473 .params = &mlxbf_i2c_corepll_tyu_params, 474 .lock = &mlxbf_i2c_corepll_lock, 475 .type = MLXBF_I2C_COREPLL_RES 476 }, 477 [MLXBF_I2C_CHIP_TYPE_2] = { 478 .params = &mlxbf_i2c_corepll_yu_params, 479 .lock = &mlxbf_i2c_corepll_lock, 480 .type = MLXBF_I2C_COREPLL_RES, 481 }, 482 [MLXBF_I2C_CHIP_TYPE_3] = { 483 .params = &mlxbf_i2c_corepll_rsh_yu_params, 484 .lock = &mlxbf_i2c_corepll_lock, 485 .type = MLXBF_I2C_COREPLL_RES, 486 } 487}; 488 489static struct mlxbf_i2c_resource mlxbf_i2c_gpio_res[] = { 490 [MLXBF_I2C_CHIP_TYPE_1] = { 491 .params = &mlxbf_i2c_gpio_tyu_params, 492 .lock = &mlxbf_i2c_gpio_lock, 493 .type = MLXBF_I2C_GPIO_RES 494 }, 495 {} 496}; 497 498static u8 mlxbf_i2c_bus_count; 499 500static struct mutex mlxbf_i2c_bus_lock; 501 502static bool mlxbf_i2c_smbus_transaction_success(u32 master_status, 503 u32 cause_status) 504{ 505 /* 506 * When transaction ended with STOP, all bytes were transmitted, 507 * and no NACK received, then the transaction ended successfully. 508 * On the other hand, when the GW is configured with the stop bit 509 * de-asserted then the SMBus expects the following GW configuration 510 * for transfer continuation. 511 */ 512 if ((cause_status & MLXBF_I2C_CAUSE_WAIT_FOR_FW_DATA) || 513 ((cause_status & MLXBF_I2C_CAUSE_TRANSACTION_ENDED) && 514 (master_status & MLXBF_I2C_SMBUS_STATUS_BYTE_CNT_DONE) && 515 !(master_status & MLXBF_I2C_SMBUS_STATUS_NACK_RCV))) 516 return true; 517 518 return false; 519} 520 521/* 522 * Poll SMBus master status and return transaction status, 523 * i.e. whether succeeded or failed. I2C and SMBus fault codes 524 * are returned as negative numbers from most calls, with zero 525 * or some positive number indicating a non-fault return. 526 */ 527static int mlxbf_i2c_smbus_check_status(struct mlxbf_i2c_priv *priv) 528{ 529 u32 master_status_bits; 530 u32 cause_status_bits; 531 u32 bits; 532 533 /* 534 * GW busy bit is raised by the driver and cleared by the HW 535 * when the transaction is completed. The busy bit is a good 536 * indicator of transaction status. So poll the busy bit, and 537 * then read the cause and master status bits to determine if 538 * errors occurred during the transaction. 539 */ 540 readl_poll_timeout_atomic(priv->mst->io + MLXBF_I2C_SMBUS_MASTER_GW, 541 bits, !(bits & MLXBF_I2C_MASTER_BUSY_BIT), 542 MLXBF_I2C_POLL_FREQ_IN_USEC, MLXBF_I2C_SMBUS_TIMEOUT); 543 544 /* Read cause status bits. */ 545 cause_status_bits = readl(priv->mst_cause->io + 546 MLXBF_I2C_CAUSE_ARBITER); 547 cause_status_bits &= MLXBF_I2C_CAUSE_MASTER_ARBITER_BITS_MASK; 548 549 /* 550 * Parse both Cause and Master GW bits, then return transaction status. 551 */ 552 553 master_status_bits = readl(priv->mst->io + 554 MLXBF_I2C_SMBUS_MASTER_STATUS); 555 master_status_bits &= MLXBF_I2C_SMBUS_MASTER_STATUS_MASK; 556 557 if (mlxbf_i2c_smbus_transaction_success(master_status_bits, 558 cause_status_bits)) 559 return 0; 560 561 /* 562 * In case of timeout on GW busy, the ISR will clear busy bit but 563 * transaction ended bits cause will not be set so the transaction 564 * fails. Then, we must check Master GW status bits. 565 */ 566 if ((master_status_bits & MLXBF_I2C_SMBUS_MASTER_STATUS_ERROR) && 567 (cause_status_bits & (MLXBF_I2C_CAUSE_TRANSACTION_ENDED | 568 MLXBF_I2C_CAUSE_M_GW_BUSY_FALL))) 569 return -EIO; 570 571 if (cause_status_bits & MLXBF_I2C_CAUSE_MASTER_STATUS_ERROR) 572 return -EAGAIN; 573 574 return -ETIMEDOUT; 575} 576 577static void mlxbf_i2c_smbus_write_data(struct mlxbf_i2c_priv *priv, 578 const u8 *data, u8 length, u32 addr, 579 bool is_master) 580{ 581 u8 offset, aligned_length; 582 u32 data32; 583 584 aligned_length = round_up(length, 4); 585 586 /* 587 * Copy data bytes from 4-byte aligned source buffer. 588 * Data copied to the Master GW Data Descriptor MUST be shifted 589 * left so the data starts at the MSB of the descriptor registers 590 * as required by the underlying hardware. Enable byte swapping 591 * when writing data bytes to the 32 * 32-bit HW Data registers 592 * a.k.a Master GW Data Descriptor. 593 */ 594 for (offset = 0; offset < aligned_length; offset += sizeof(u32)) { 595 data32 = *((u32 *)(data + offset)); 596 if (is_master) 597 iowrite32be(data32, priv->mst->io + addr + offset); 598 else 599 iowrite32be(data32, priv->slv->io + addr + offset); 600 } 601} 602 603static void mlxbf_i2c_smbus_read_data(struct mlxbf_i2c_priv *priv, 604 u8 *data, u8 length, u32 addr, 605 bool is_master) 606{ 607 u32 data32, mask; 608 u8 byte, offset; 609 610 mask = sizeof(u32) - 1; 611 612 /* 613 * Data bytes in the Master GW Data Descriptor are shifted left 614 * so the data starts at the MSB of the descriptor registers as 615 * set by the underlying hardware. Enable byte swapping while 616 * reading data bytes from the 32 * 32-bit HW Data registers 617 * a.k.a Master GW Data Descriptor. 618 */ 619 620 for (offset = 0; offset < (length & ~mask); offset += sizeof(u32)) { 621 if (is_master) 622 data32 = ioread32be(priv->mst->io + addr + offset); 623 else 624 data32 = ioread32be(priv->slv->io + addr + offset); 625 *((u32 *)(data + offset)) = data32; 626 } 627 628 if (!(length & mask)) 629 return; 630 631 if (is_master) 632 data32 = ioread32be(priv->mst->io + addr + offset); 633 else 634 data32 = ioread32be(priv->slv->io + addr + offset); 635 636 for (byte = 0; byte < (length & mask); byte++) { 637 data[offset + byte] = data32 & GENMASK(7, 0); 638 data32 = ror32(data32, MLXBF_I2C_SHIFT_8); 639 } 640} 641 642static int mlxbf_i2c_smbus_enable(struct mlxbf_i2c_priv *priv, u8 slave, 643 u8 len, u8 block_en, u8 pec_en, bool read, 644 bool stop) 645{ 646 u32 command = 0; 647 648 /* Set Master GW control word. */ 649 if (stop) 650 command |= MLXBF_I2C_MASTER_STOP_BIT; 651 if (read) { 652 command |= MLXBF_I2C_MASTER_ENABLE_READ; 653 command |= rol32(len, MLXBF_I2C_MASTER_READ_SHIFT); 654 } else { 655 command |= MLXBF_I2C_MASTER_ENABLE_WRITE; 656 command |= rol32(len, MLXBF_I2C_MASTER_WRITE_SHIFT); 657 } 658 command |= rol32(slave, MLXBF_I2C_MASTER_SLV_ADDR_SHIFT); 659 command |= rol32(block_en, MLXBF_I2C_MASTER_PARSE_EXP_SHIFT); 660 command |= rol32(pec_en, MLXBF_I2C_MASTER_SEND_PEC_SHIFT); 661 662 /* Clear status bits. */ 663 writel(0x0, priv->mst->io + MLXBF_I2C_SMBUS_MASTER_STATUS); 664 /* Set the cause data. */ 665 writel(~0x0, priv->mst_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR); 666 /* Zero PEC byte. */ 667 writel(0x0, priv->mst->io + MLXBF_I2C_SMBUS_MASTER_PEC); 668 /* Zero byte count. */ 669 writel(0x0, priv->mst->io + priv->chip->smbus_master_rs_bytes_off); 670 671 /* GW activation. */ 672 writel(command, priv->mst->io + MLXBF_I2C_SMBUS_MASTER_GW); 673 674 /* 675 * Poll master status and check status bits. An ACK is sent when 676 * completing writing data to the bus (Master 'byte_count_done' bit 677 * is set to 1). 678 */ 679 return mlxbf_i2c_smbus_check_status(priv); 680} 681 682static int 683mlxbf_i2c_smbus_start_transaction(struct mlxbf_i2c_priv *priv, 684 struct mlxbf_i2c_smbus_request *request) 685{ 686 u8 data_desc[MLXBF_I2C_MASTER_DATA_DESC_SIZE] = { 0 }; 687 u8 op_idx, data_idx, data_len, write_len, read_len; 688 struct mlxbf_i2c_smbus_operation *operation; 689 u8 read_en, write_en, block_en, pec_en; 690 bool stop_after_write = true; 691 u8 slave, addr; 692 u8 *read_buf; 693 u32 flags; 694 u32 bits; 695 int ret; 696 697 if (request->operation_cnt > MLXBF_I2C_SMBUS_MAX_OP_CNT) 698 return -EINVAL; 699 700 read_buf = NULL; 701 data_idx = 0; 702 read_en = 0; 703 write_en = 0; 704 write_len = 0; 705 read_len = 0; 706 block_en = 0; 707 pec_en = 0; 708 slave = request->slave & GENMASK(6, 0); 709 addr = slave << 1; 710 711 /* 712 * Try to acquire the smbus gw lock before any reads of the GW register since 713 * a read sets the lock. 714 */ 715 ret = readl_poll_timeout_atomic(priv->mst->io + MLXBF_I2C_SMBUS_MASTER_GW, 716 bits, !(bits & MLXBF_I2C_MASTER_LOCK_BIT), 717 MLXBF_I2C_POLL_FREQ_IN_USEC, 718 MLXBF_I2C_SMBUS_LOCK_POLL_TIMEOUT); 719 if (WARN_ON(ret)) 720 return -EBUSY; 721 722 /* 723 * SW must make sure that the SMBus Master GW is idle before starting 724 * a transaction. Accordingly, this call polls the Master FSM stop bit; 725 * it returns -ETIMEDOUT when the bit is asserted, 0 if not. 726 */ 727 ret = readl_poll_timeout_atomic(priv->mst->io + priv->chip->smbus_master_fsm_off, 728 bits, !(bits & MLXBF_I2C_SMBUS_MASTER_FSM_STOP_MASK), 729 MLXBF_I2C_POLL_FREQ_IN_USEC, MLXBF_I2C_SMBUS_TIMEOUT); 730 if (WARN_ON(ret)) { 731 ret = -EBUSY; 732 goto out_unlock; 733 } 734 735 /* Set first byte. */ 736 data_desc[data_idx++] = addr; 737 738 for (op_idx = 0; op_idx < request->operation_cnt; op_idx++) { 739 operation = &request->operation[op_idx]; 740 flags = operation->flags; 741 742 /* 743 * Note that read and write operations might be handled by a 744 * single command. If the MLXBF_I2C_F_SMBUS_OPERATION is set 745 * then write command byte and set the optional SMBus specific 746 * bits such as block_en and pec_en. These bits MUST be 747 * submitted by the first operation only. 748 */ 749 if (op_idx == 0 && flags & MLXBF_I2C_F_SMBUS_OPERATION) { 750 block_en = flags & MLXBF_I2C_F_SMBUS_BLOCK; 751 pec_en = flags & MLXBF_I2C_F_SMBUS_PEC; 752 } 753 754 if (flags & MLXBF_I2C_F_WRITE) { 755 write_en = 1; 756 write_len += operation->length; 757 if (data_idx + operation->length > 758 MLXBF_I2C_MASTER_DATA_DESC_SIZE) { 759 ret = -ENOBUFS; 760 goto out_unlock; 761 } 762 memcpy(data_desc + data_idx, 763 operation->buffer, operation->length); 764 data_idx += operation->length; 765 766 /* 767 * The stop condition can be skipped when writing on the bus 768 * to implement a repeated start condition on the next read 769 * as required for several SMBus and I2C operations. 770 */ 771 if (flags & MLXBF_I2C_F_WRITE_WITHOUT_STOP) 772 stop_after_write = false; 773 } 774 775 /* 776 * We assume that read operations are performed only once per 777 * SMBus transaction. *TBD* protect this statement so it won't 778 * be executed twice? or return an error if we try to read more 779 * than once? 780 */ 781 if (flags & MLXBF_I2C_F_READ) { 782 read_en = 1; 783 /* Subtract 1 as required by HW. */ 784 read_len = operation->length - 1; 785 read_buf = operation->buffer; 786 } 787 } 788 789 /* Set Master GW data descriptor. */ 790 data_len = write_len + 1; /* Add one byte of the slave address. */ 791 /* 792 * Note that data_len cannot be 0. Indeed, the slave address byte 793 * must be written to the data registers. 794 */ 795 mlxbf_i2c_smbus_write_data(priv, (const u8 *)data_desc, data_len, 796 MLXBF_I2C_MASTER_DATA_DESC_ADDR, true); 797 798 if (write_en) { 799 ret = mlxbf_i2c_smbus_enable(priv, slave, write_len, block_en, 800 pec_en, 0, stop_after_write); 801 if (ret) 802 goto out_unlock; 803 } 804 805 if (read_en) { 806 /* Write slave address to Master GW data descriptor. */ 807 mlxbf_i2c_smbus_write_data(priv, (const u8 *)&addr, 1, 808 MLXBF_I2C_MASTER_DATA_DESC_ADDR, true); 809 ret = mlxbf_i2c_smbus_enable(priv, slave, read_len, block_en, 810 pec_en, 1, true); 811 if (!ret) { 812 /* Get Master GW data descriptor. */ 813 mlxbf_i2c_smbus_read_data(priv, data_desc, read_len + 1, 814 MLXBF_I2C_MASTER_DATA_DESC_ADDR, true); 815 816 /* Get data from Master GW data descriptor. */ 817 memcpy(read_buf, data_desc, read_len + 1); 818 } 819 820 /* 821 * After a read operation the SMBus FSM ps (present state) 822 * needs to be 'manually' reset. This should be removed in 823 * next tag integration. 824 */ 825 writel(MLXBF_I2C_SMBUS_MASTER_FSM_PS_STATE_MASK, 826 priv->mst->io + priv->chip->smbus_master_fsm_off); 827 } 828 829out_unlock: 830 /* Clear the gw to clear the lock */ 831 writel(0, priv->mst->io + MLXBF_I2C_SMBUS_MASTER_GW); 832 833 return ret; 834} 835 836/* I2C SMBus protocols. */ 837 838static void 839mlxbf_i2c_smbus_quick_command(struct mlxbf_i2c_smbus_request *request, 840 u8 read) 841{ 842 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_1; 843 844 request->operation[0].length = 0; 845 request->operation[0].flags = MLXBF_I2C_F_WRITE; 846 request->operation[0].flags |= read ? MLXBF_I2C_F_READ : 0; 847} 848 849static void mlxbf_i2c_smbus_byte_func(struct mlxbf_i2c_smbus_request *request, 850 u8 *data, bool read, bool pec_check) 851{ 852 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_1; 853 854 request->operation[0].length = 1; 855 request->operation[0].length += pec_check; 856 857 request->operation[0].flags = MLXBF_I2C_F_SMBUS_OPERATION; 858 request->operation[0].flags |= read ? 859 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 860 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 861 862 request->operation[0].buffer = data; 863} 864 865static void 866mlxbf_i2c_smbus_data_byte_func(struct mlxbf_i2c_smbus_request *request, 867 u8 *command, u8 *data, bool read, bool pec_check) 868{ 869 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 870 871 request->operation[0].length = 1; 872 request->operation[0].flags = 873 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 874 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 875 request->operation[0].buffer = command; 876 877 request->operation[1].length = 1; 878 request->operation[1].length += pec_check; 879 request->operation[1].flags = read ? 880 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 881 request->operation[1].buffer = data; 882} 883 884static void 885mlxbf_i2c_smbus_data_word_func(struct mlxbf_i2c_smbus_request *request, 886 u8 *command, u8 *data, bool read, bool pec_check) 887{ 888 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 889 890 request->operation[0].length = 1; 891 request->operation[0].flags = 892 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 893 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 894 request->operation[0].buffer = command; 895 896 request->operation[1].length = 2; 897 request->operation[1].length += pec_check; 898 request->operation[1].flags = read ? 899 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 900 request->operation[1].buffer = data; 901} 902 903static void 904mlxbf_i2c_smbus_i2c_block_func(struct mlxbf_i2c_smbus_request *request, 905 u8 *command, u8 *data, u8 *data_len, bool read, 906 bool pec_check) 907{ 908 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 909 910 request->operation[0].length = 1; 911 request->operation[0].flags = 912 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 913 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 914 request->operation[0].buffer = command; 915 916 if (read) 917 request->operation[0].flags |= MLXBF_I2C_F_WRITE_WITHOUT_STOP; 918 919 /* 920 * As specified in the standard, the max number of bytes to read/write 921 * per block operation is 32 bytes. In Golan code, the controller can 922 * read up to 128 bytes and write up to 127 bytes. 923 */ 924 request->operation[1].length = 925 (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ? 926 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check; 927 request->operation[1].flags = read ? 928 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 929 /* 930 * Skip the first data byte, which corresponds to the number of bytes 931 * to read/write. 932 */ 933 request->operation[1].buffer = data + 1; 934 935 *data_len = request->operation[1].length; 936 937 /* Set the number of byte to read. This will be used by userspace. */ 938 if (read) 939 data[0] = *data_len; 940} 941 942static void mlxbf_i2c_smbus_block_func(struct mlxbf_i2c_smbus_request *request, 943 u8 *command, u8 *data, u8 *data_len, 944 bool read, bool pec_check) 945{ 946 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_2; 947 948 request->operation[0].length = 1; 949 request->operation[0].flags = 950 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 951 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK; 952 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 953 request->operation[0].buffer = command; 954 955 request->operation[1].length = 956 (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ? 957 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check; 958 request->operation[1].flags = read ? 959 MLXBF_I2C_F_READ : MLXBF_I2C_F_WRITE; 960 request->operation[1].buffer = data + 1; 961 962 *data_len = request->operation[1].length; 963 964 /* Set the number of bytes to read. This will be used by userspace. */ 965 if (read) 966 data[0] = *data_len; 967} 968 969static void 970mlxbf_i2c_smbus_process_call_func(struct mlxbf_i2c_smbus_request *request, 971 u8 *command, u8 *data, bool pec_check) 972{ 973 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_3; 974 975 request->operation[0].length = 1; 976 request->operation[0].flags = 977 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 978 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK; 979 request->operation[0].flags |= pec_check ? MLXBF_I2C_F_SMBUS_PEC : 0; 980 request->operation[0].buffer = command; 981 982 request->operation[1].length = 2; 983 request->operation[1].flags = MLXBF_I2C_F_WRITE; 984 request->operation[1].buffer = data; 985 986 request->operation[2].length = 3; 987 request->operation[2].flags = MLXBF_I2C_F_READ; 988 request->operation[2].buffer = data; 989} 990 991static void 992mlxbf_i2c_smbus_blk_process_call_func(struct mlxbf_i2c_smbus_request *request, 993 u8 *command, u8 *data, u8 *data_len, 994 bool pec_check) 995{ 996 u32 length; 997 998 request->operation_cnt = MLXBF_I2C_SMBUS_OP_CNT_3; 999 1000 request->operation[0].length = 1; 1001 request->operation[0].flags = 1002 MLXBF_I2C_F_SMBUS_OPERATION | MLXBF_I2C_F_WRITE; 1003 request->operation[0].flags |= MLXBF_I2C_F_SMBUS_BLOCK; 1004 request->operation[0].flags |= (pec_check) ? MLXBF_I2C_F_SMBUS_PEC : 0; 1005 request->operation[0].buffer = command; 1006 1007 length = (*data_len + pec_check > I2C_SMBUS_BLOCK_MAX) ? 1008 I2C_SMBUS_BLOCK_MAX : *data_len + pec_check; 1009 1010 request->operation[1].length = length - pec_check; 1011 request->operation[1].flags = MLXBF_I2C_F_WRITE; 1012 request->operation[1].buffer = data; 1013 1014 request->operation[2].length = length; 1015 request->operation[2].flags = MLXBF_I2C_F_READ; 1016 request->operation[2].buffer = data; 1017 1018 *data_len = length; /* including PEC byte. */ 1019} 1020 1021/* Initialization functions. */ 1022 1023static bool mlxbf_i2c_has_chip_type(struct mlxbf_i2c_priv *priv, u8 type) 1024{ 1025 return priv->chip->type == type; 1026} 1027 1028static struct mlxbf_i2c_resource * 1029mlxbf_i2c_get_shared_resource(struct mlxbf_i2c_priv *priv, u8 type) 1030{ 1031 const struct mlxbf_i2c_chip_info *chip = priv->chip; 1032 struct mlxbf_i2c_resource *res; 1033 u8 res_idx = 0; 1034 1035 for (res_idx = 0; res_idx < MLXBF_I2C_SHARED_RES_MAX; res_idx++) { 1036 res = chip->shared_res[res_idx]; 1037 if (res && res->type == type) 1038 return res; 1039 } 1040 1041 return NULL; 1042} 1043 1044static int mlxbf_i2c_init_resource(struct platform_device *pdev, 1045 struct mlxbf_i2c_resource **res, 1046 u8 type) 1047{ 1048 struct mlxbf_i2c_resource *tmp_res; 1049 struct device *dev = &pdev->dev; 1050 1051 if (!res || *res || type >= MLXBF_I2C_END_RES) 1052 return -EINVAL; 1053 1054 tmp_res = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource), 1055 GFP_KERNEL); 1056 if (!tmp_res) 1057 return -ENOMEM; 1058 1059 tmp_res->io = devm_platform_get_and_ioremap_resource(pdev, type, &tmp_res->params); 1060 if (IS_ERR(tmp_res->io)) { 1061 devm_kfree(dev, tmp_res); 1062 return PTR_ERR(tmp_res->io); 1063 } 1064 1065 tmp_res->type = type; 1066 1067 *res = tmp_res; 1068 1069 return 0; 1070} 1071 1072static u32 mlxbf_i2c_get_ticks(struct mlxbf_i2c_priv *priv, u64 nanoseconds, 1073 bool minimum) 1074{ 1075 u64 frequency; 1076 u32 ticks; 1077 1078 /* 1079 * Compute ticks as follow: 1080 * 1081 * Ticks 1082 * Time = --------- x 10^9 => Ticks = Time x Frequency x 10^-9 1083 * Frequency 1084 */ 1085 frequency = priv->frequency; 1086 ticks = div_u64(nanoseconds * frequency, MLXBF_I2C_FREQUENCY_1GHZ); 1087 /* 1088 * The number of ticks is rounded down and if minimum is equal to 1 1089 * then add one tick. 1090 */ 1091 if (minimum) 1092 ticks++; 1093 1094 return ticks; 1095} 1096 1097static u32 mlxbf_i2c_set_timer(struct mlxbf_i2c_priv *priv, u64 nsec, bool opt, 1098 u32 mask, u8 shift) 1099{ 1100 u32 val = (mlxbf_i2c_get_ticks(priv, nsec, opt) & mask) << shift; 1101 1102 return val; 1103} 1104 1105static void mlxbf_i2c_set_timings(struct mlxbf_i2c_priv *priv, 1106 const struct mlxbf_i2c_timings *timings) 1107{ 1108 u32 timer; 1109 1110 timer = mlxbf_i2c_set_timer(priv, timings->scl_high, 1111 false, MLXBF_I2C_MASK_16, 1112 MLXBF_I2C_SHIFT_0); 1113 timer |= mlxbf_i2c_set_timer(priv, timings->scl_low, 1114 false, MLXBF_I2C_MASK_16, 1115 MLXBF_I2C_SHIFT_16); 1116 writel(timer, priv->timer->io + 1117 MLXBF_I2C_SMBUS_TIMER_SCL_LOW_SCL_HIGH); 1118 1119 timer = mlxbf_i2c_set_timer(priv, timings->sda_rise, false, 1120 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_0); 1121 timer |= mlxbf_i2c_set_timer(priv, timings->sda_fall, false, 1122 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_8); 1123 timer |= mlxbf_i2c_set_timer(priv, timings->scl_rise, false, 1124 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_16); 1125 timer |= mlxbf_i2c_set_timer(priv, timings->scl_fall, false, 1126 MLXBF_I2C_MASK_8, MLXBF_I2C_SHIFT_24); 1127 writel(timer, priv->timer->io + 1128 MLXBF_I2C_SMBUS_TIMER_FALL_RISE_SPIKE); 1129 1130 timer = mlxbf_i2c_set_timer(priv, timings->hold_start, true, 1131 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1132 timer |= mlxbf_i2c_set_timer(priv, timings->hold_data, true, 1133 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1134 writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_TIMER_THOLD); 1135 1136 timer = mlxbf_i2c_set_timer(priv, timings->setup_start, true, 1137 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1138 timer |= mlxbf_i2c_set_timer(priv, timings->setup_stop, true, 1139 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1140 writel(timer, priv->timer->io + 1141 MLXBF_I2C_SMBUS_TIMER_TSETUP_START_STOP); 1142 1143 timer = mlxbf_i2c_set_timer(priv, timings->setup_data, true, 1144 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1145 writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_TIMER_TSETUP_DATA); 1146 1147 timer = mlxbf_i2c_set_timer(priv, timings->buf, false, 1148 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_0); 1149 timer |= mlxbf_i2c_set_timer(priv, timings->thigh_max, false, 1150 MLXBF_I2C_MASK_16, MLXBF_I2C_SHIFT_16); 1151 writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_THIGH_MAX_TBUF); 1152 1153 timer = mlxbf_i2c_set_timer(priv, timings->timeout, false, 1154 MLXBF_I2C_MASK_32, MLXBF_I2C_SHIFT_0); 1155 writel(timer, priv->timer->io + MLXBF_I2C_SMBUS_SCL_LOW_TIMEOUT); 1156} 1157 1158enum mlxbf_i2c_timings_config { 1159 MLXBF_I2C_TIMING_CONFIG_100KHZ, 1160 MLXBF_I2C_TIMING_CONFIG_400KHZ, 1161 MLXBF_I2C_TIMING_CONFIG_1000KHZ, 1162}; 1163 1164/* Timing values are in nanoseconds */ 1165static const struct mlxbf_i2c_timings mlxbf_i2c_timings[] = { 1166 [MLXBF_I2C_TIMING_CONFIG_100KHZ] = { 1167 .scl_high = 4810, 1168 .scl_low = 5000, 1169 .hold_start = 4000, 1170 .setup_start = 4800, 1171 .setup_stop = 4000, 1172 .setup_data = 250, 1173 .sda_rise = 50, 1174 .sda_fall = 50, 1175 .scl_rise = 50, 1176 .scl_fall = 50, 1177 .hold_data = 300, 1178 .buf = 20000, 1179 .thigh_max = 50000, 1180 .timeout = 35000000 1181 }, 1182 [MLXBF_I2C_TIMING_CONFIG_400KHZ] = { 1183 .scl_high = 1011, 1184 .scl_low = 1300, 1185 .hold_start = 600, 1186 .setup_start = 700, 1187 .setup_stop = 600, 1188 .setup_data = 100, 1189 .sda_rise = 50, 1190 .sda_fall = 50, 1191 .scl_rise = 50, 1192 .scl_fall = 50, 1193 .hold_data = 300, 1194 .buf = 20000, 1195 .thigh_max = 50000, 1196 .timeout = 35000000 1197 }, 1198 [MLXBF_I2C_TIMING_CONFIG_1000KHZ] = { 1199 .scl_high = 383, 1200 .scl_low = 460, 1201 .hold_start = 600, 1202 .setup_start = 260, 1203 .setup_stop = 260, 1204 .setup_data = 50, 1205 .sda_rise = 50, 1206 .sda_fall = 50, 1207 .scl_rise = 50, 1208 .scl_fall = 50, 1209 .hold_data = 300, 1210 .buf = 500, 1211 .thigh_max = 50000, 1212 .timeout = 35000000 1213 } 1214}; 1215 1216static int mlxbf_i2c_init_timings(struct platform_device *pdev, 1217 struct mlxbf_i2c_priv *priv) 1218{ 1219 enum mlxbf_i2c_timings_config config_idx; 1220 struct device *dev = &pdev->dev; 1221 u32 config_khz; 1222 1223 int ret; 1224 1225 ret = device_property_read_u32(dev, "clock-frequency", &config_khz); 1226 if (ret < 0) 1227 config_khz = I2C_MAX_STANDARD_MODE_FREQ; 1228 1229 switch (config_khz) { 1230 default: 1231 /* Default settings is 100 KHz. */ 1232 pr_warn("Illegal value %d: defaulting to 100 KHz\n", 1233 config_khz); 1234 fallthrough; 1235 case I2C_MAX_STANDARD_MODE_FREQ: 1236 config_idx = MLXBF_I2C_TIMING_CONFIG_100KHZ; 1237 break; 1238 1239 case I2C_MAX_FAST_MODE_FREQ: 1240 config_idx = MLXBF_I2C_TIMING_CONFIG_400KHZ; 1241 break; 1242 1243 case I2C_MAX_FAST_MODE_PLUS_FREQ: 1244 config_idx = MLXBF_I2C_TIMING_CONFIG_1000KHZ; 1245 break; 1246 } 1247 1248 mlxbf_i2c_set_timings(priv, &mlxbf_i2c_timings[config_idx]); 1249 1250 return 0; 1251} 1252 1253static int mlxbf_i2c_get_gpio(struct platform_device *pdev, 1254 struct mlxbf_i2c_priv *priv) 1255{ 1256 struct mlxbf_i2c_resource *gpio_res; 1257 struct device *dev = &pdev->dev; 1258 struct resource *params; 1259 resource_size_t size; 1260 1261 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES); 1262 if (!gpio_res) 1263 return -EPERM; 1264 1265 /* 1266 * The GPIO region in TYU space is shared among I2C busses. 1267 * This function MUST be serialized to avoid racing when 1268 * claiming the memory region and/or setting up the GPIO. 1269 */ 1270 lockdep_assert_held(gpio_res->lock); 1271 1272 /* Check whether the memory map exist. */ 1273 if (gpio_res->io) 1274 return 0; 1275 1276 params = gpio_res->params; 1277 size = resource_size(params); 1278 1279 if (!devm_request_mem_region(dev, params->start, size, params->name)) 1280 return -EFAULT; 1281 1282 gpio_res->io = devm_ioremap(dev, params->start, size); 1283 if (!gpio_res->io) { 1284 devm_release_mem_region(dev, params->start, size); 1285 return -ENOMEM; 1286 } 1287 1288 return 0; 1289} 1290 1291static int mlxbf_i2c_release_gpio(struct platform_device *pdev, 1292 struct mlxbf_i2c_priv *priv) 1293{ 1294 struct mlxbf_i2c_resource *gpio_res; 1295 struct device *dev = &pdev->dev; 1296 struct resource *params; 1297 1298 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES); 1299 if (!gpio_res) 1300 return 0; 1301 1302 mutex_lock(gpio_res->lock); 1303 1304 if (gpio_res->io) { 1305 /* Release the GPIO resource. */ 1306 params = gpio_res->params; 1307 devm_iounmap(dev, gpio_res->io); 1308 devm_release_mem_region(dev, params->start, 1309 resource_size(params)); 1310 } 1311 1312 mutex_unlock(gpio_res->lock); 1313 1314 return 0; 1315} 1316 1317static int mlxbf_i2c_get_corepll(struct platform_device *pdev, 1318 struct mlxbf_i2c_priv *priv) 1319{ 1320 struct mlxbf_i2c_resource *corepll_res; 1321 struct device *dev = &pdev->dev; 1322 struct resource *params; 1323 resource_size_t size; 1324 1325 corepll_res = mlxbf_i2c_get_shared_resource(priv, 1326 MLXBF_I2C_COREPLL_RES); 1327 if (!corepll_res) 1328 return -EPERM; 1329 1330 /* 1331 * The COREPLL region in TYU space is shared among I2C busses. 1332 * This function MUST be serialized to avoid racing when 1333 * claiming the memory region. 1334 */ 1335 lockdep_assert_held(corepll_res->lock); 1336 1337 /* Check whether the memory map exist. */ 1338 if (corepll_res->io) 1339 return 0; 1340 1341 params = corepll_res->params; 1342 size = resource_size(params); 1343 1344 if (!devm_request_mem_region(dev, params->start, size, params->name)) 1345 return -EFAULT; 1346 1347 corepll_res->io = devm_ioremap(dev, params->start, size); 1348 if (!corepll_res->io) { 1349 devm_release_mem_region(dev, params->start, size); 1350 return -ENOMEM; 1351 } 1352 1353 return 0; 1354} 1355 1356static int mlxbf_i2c_release_corepll(struct platform_device *pdev, 1357 struct mlxbf_i2c_priv *priv) 1358{ 1359 struct mlxbf_i2c_resource *corepll_res; 1360 struct device *dev = &pdev->dev; 1361 struct resource *params; 1362 1363 corepll_res = mlxbf_i2c_get_shared_resource(priv, 1364 MLXBF_I2C_COREPLL_RES); 1365 1366 mutex_lock(corepll_res->lock); 1367 1368 if (corepll_res->io) { 1369 /* Release the CorePLL resource. */ 1370 params = corepll_res->params; 1371 devm_iounmap(dev, corepll_res->io); 1372 devm_release_mem_region(dev, params->start, 1373 resource_size(params)); 1374 } 1375 1376 mutex_unlock(corepll_res->lock); 1377 1378 return 0; 1379} 1380 1381static int mlxbf_i2c_init_master(struct platform_device *pdev, 1382 struct mlxbf_i2c_priv *priv) 1383{ 1384 struct mlxbf_i2c_resource *gpio_res; 1385 struct device *dev = &pdev->dev; 1386 u32 config_reg; 1387 int ret; 1388 1389 /* This configuration is only needed for BlueField 1. */ 1390 if (!mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) 1391 return 0; 1392 1393 gpio_res = mlxbf_i2c_get_shared_resource(priv, MLXBF_I2C_GPIO_RES); 1394 if (!gpio_res) 1395 return -EPERM; 1396 1397 /* 1398 * The GPIO region in TYU space is shared among I2C busses. 1399 * This function MUST be serialized to avoid racing when 1400 * claiming the memory region and/or setting up the GPIO. 1401 */ 1402 1403 mutex_lock(gpio_res->lock); 1404 1405 ret = mlxbf_i2c_get_gpio(pdev, priv); 1406 if (ret < 0) { 1407 dev_err(dev, "Failed to get gpio resource"); 1408 mutex_unlock(gpio_res->lock); 1409 return ret; 1410 } 1411 1412 /* 1413 * TYU - Configuration for GPIO pins. Those pins must be asserted in 1414 * MLXBF_I2C_GPIO_0_FUNC_EN_0, i.e. GPIO 0 is controlled by HW, and must 1415 * be reset in MLXBF_I2C_GPIO_0_FORCE_OE_EN, i.e. GPIO_OE will be driven 1416 * instead of HW_OE. 1417 * For now, we do not reset the GPIO state when the driver is removed. 1418 * First, it is not necessary to disable the bus since we are using 1419 * the same busses. Then, some busses might be shared among Linux and 1420 * platform firmware; disabling the bus might compromise the system 1421 * functionality. 1422 */ 1423 config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0); 1424 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_ASSERT_PINS(priv->bus, 1425 config_reg); 1426 writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FUNC_EN_0); 1427 1428 config_reg = readl(gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN); 1429 config_reg = MLXBF_I2C_GPIO_SMBUS_GW_RESET_PINS(priv->bus, 1430 config_reg); 1431 writel(config_reg, gpio_res->io + MLXBF_I2C_GPIO_0_FORCE_OE_EN); 1432 1433 mutex_unlock(gpio_res->lock); 1434 1435 return 0; 1436} 1437 1438static u64 mlxbf_i2c_calculate_freq_from_tyu(struct mlxbf_i2c_resource *corepll_res) 1439{ 1440 u64 core_frequency; 1441 u8 core_od, core_r; 1442 u32 corepll_val; 1443 u16 core_f; 1444 1445 corepll_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1); 1446 1447 /* Get Core PLL configuration bits. */ 1448 core_f = FIELD_GET(MLXBF_I2C_COREPLL_CORE_F_TYU_MASK, corepll_val); 1449 core_od = FIELD_GET(MLXBF_I2C_COREPLL_CORE_OD_TYU_MASK, corepll_val); 1450 core_r = FIELD_GET(MLXBF_I2C_COREPLL_CORE_R_TYU_MASK, corepll_val); 1451 1452 /* 1453 * Compute PLL output frequency as follow: 1454 * 1455 * CORE_F + 1 1456 * PLL_OUT_FREQ = PLL_IN_FREQ * ---------------------------- 1457 * (CORE_R + 1) * (CORE_OD + 1) 1458 * 1459 * Where PLL_OUT_FREQ and PLL_IN_FREQ refer to CoreFrequency 1460 * and PadFrequency, respectively. 1461 */ 1462 core_frequency = MLXBF_I2C_PLL_IN_FREQ * (++core_f); 1463 1464 return div_u64(core_frequency, (++core_r) * (++core_od)); 1465} 1466 1467static u64 mlxbf_i2c_calculate_freq_from_yu(struct mlxbf_i2c_resource *corepll_res) 1468{ 1469 u32 corepll_reg1_val, corepll_reg2_val; 1470 u64 corepll_frequency; 1471 u8 core_od, core_r; 1472 u32 core_f; 1473 1474 corepll_reg1_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG1); 1475 corepll_reg2_val = readl(corepll_res->io + MLXBF_I2C_CORE_PLL_REG2); 1476 1477 /* Get Core PLL configuration bits */ 1478 core_f = FIELD_GET(MLXBF_I2C_COREPLL_CORE_F_YU_MASK, corepll_reg1_val); 1479 core_r = FIELD_GET(MLXBF_I2C_COREPLL_CORE_R_YU_MASK, corepll_reg1_val); 1480 core_od = FIELD_GET(MLXBF_I2C_COREPLL_CORE_OD_YU_MASK, corepll_reg2_val); 1481 1482 /* 1483 * Compute PLL output frequency as follow: 1484 * 1485 * CORE_F / 16384 1486 * PLL_OUT_FREQ = PLL_IN_FREQ * ---------------------------- 1487 * (CORE_R + 1) * (CORE_OD + 1) 1488 * 1489 * Where PLL_OUT_FREQ and PLL_IN_FREQ refer to CoreFrequency 1490 * and PadFrequency, respectively. 1491 */ 1492 corepll_frequency = (MLXBF_I2C_PLL_IN_FREQ * core_f) / MLNXBF_I2C_COREPLL_CONST; 1493 1494 return div_u64(corepll_frequency, (++core_r) * (++core_od)); 1495} 1496 1497static int mlxbf_i2c_calculate_corepll_freq(struct platform_device *pdev, 1498 struct mlxbf_i2c_priv *priv) 1499{ 1500 const struct mlxbf_i2c_chip_info *chip = priv->chip; 1501 struct mlxbf_i2c_resource *corepll_res; 1502 struct device *dev = &pdev->dev; 1503 u64 *freq = &priv->frequency; 1504 int ret; 1505 1506 corepll_res = mlxbf_i2c_get_shared_resource(priv, 1507 MLXBF_I2C_COREPLL_RES); 1508 if (!corepll_res) 1509 return -EPERM; 1510 1511 /* 1512 * First, check whether the TYU core Clock frequency is set. 1513 * The TYU core frequency is the same for all I2C busses; when 1514 * the first device gets probed the frequency is determined and 1515 * stored into a globally visible variable. So, first of all, 1516 * check whether the frequency is already set. Here, we assume 1517 * that the frequency is expected to be greater than 0. 1518 */ 1519 mutex_lock(corepll_res->lock); 1520 if (!mlxbf_i2c_corepll_frequency) { 1521 if (!chip->calculate_freq) { 1522 mutex_unlock(corepll_res->lock); 1523 return -EPERM; 1524 } 1525 1526 ret = mlxbf_i2c_get_corepll(pdev, priv); 1527 if (ret < 0) { 1528 dev_err(dev, "Failed to get corePLL resource"); 1529 mutex_unlock(corepll_res->lock); 1530 return ret; 1531 } 1532 1533 mlxbf_i2c_corepll_frequency = chip->calculate_freq(corepll_res); 1534 } 1535 mutex_unlock(corepll_res->lock); 1536 1537 *freq = mlxbf_i2c_corepll_frequency; 1538 1539 return 0; 1540} 1541 1542static int mlxbf_i2c_slave_enable(struct mlxbf_i2c_priv *priv, 1543 struct i2c_client *slave) 1544{ 1545 u8 reg, reg_cnt, byte, addr_tmp; 1546 u32 slave_reg, slave_reg_tmp; 1547 1548 if (!priv) 1549 return -EPERM; 1550 1551 reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2; 1552 1553 /* 1554 * Read the slave registers. There are 4 * 32-bit slave registers. 1555 * Each slave register can hold up to 4 * 8-bit slave configuration: 1556 * 1) A 7-bit address 1557 * 2) And a status bit (1 if enabled, 0 if not). 1558 * Look for the next available slave register slot. 1559 */ 1560 for (reg = 0; reg < reg_cnt; reg++) { 1561 slave_reg = readl(priv->slv->io + 1562 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4); 1563 /* 1564 * Each register holds 4 slave addresses. So, we have to keep 1565 * the byte order consistent with the value read in order to 1566 * update the register correctly, if needed. 1567 */ 1568 slave_reg_tmp = slave_reg; 1569 for (byte = 0; byte < 4; byte++) { 1570 addr_tmp = slave_reg_tmp & GENMASK(7, 0); 1571 1572 /* 1573 * If an enable bit is not set in the 1574 * MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG register, then the 1575 * slave address slot associated with that bit is 1576 * free. So set the enable bit and write the 1577 * slave address bits. 1578 */ 1579 if (!(addr_tmp & MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT)) { 1580 slave_reg &= ~(MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK << (byte * 8)); 1581 slave_reg |= (slave->addr << (byte * 8)); 1582 slave_reg |= MLXBF_I2C_SMBUS_SLAVE_ADDR_EN_BIT << (byte * 8); 1583 writel(slave_reg, priv->slv->io + 1584 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + 1585 (reg * 0x4)); 1586 1587 /* 1588 * Set the slave at the corresponding index. 1589 */ 1590 priv->slave[(reg * 4) + byte] = slave; 1591 1592 return 0; 1593 } 1594 1595 /* Parse next byte. */ 1596 slave_reg_tmp >>= 8; 1597 } 1598 } 1599 1600 return -EBUSY; 1601} 1602 1603static int mlxbf_i2c_slave_disable(struct mlxbf_i2c_priv *priv, u8 addr) 1604{ 1605 u8 addr_tmp, reg, reg_cnt, byte; 1606 u32 slave_reg, slave_reg_tmp; 1607 1608 reg_cnt = MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT >> 2; 1609 1610 /* 1611 * Read the slave registers. There are 4 * 32-bit slave registers. 1612 * Each slave register can hold up to 4 * 8-bit slave configuration: 1613 * 1) A 7-bit address 1614 * 2) And a status bit (1 if enabled, 0 if not). 1615 * Check if addr is present in the registers. 1616 */ 1617 for (reg = 0; reg < reg_cnt; reg++) { 1618 slave_reg = readl(priv->slv->io + 1619 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + reg * 0x4); 1620 1621 /* Check whether the address slots are empty. */ 1622 if (!slave_reg) 1623 continue; 1624 1625 /* 1626 * Check if addr matches any of the 4 slave addresses 1627 * in the register. 1628 */ 1629 slave_reg_tmp = slave_reg; 1630 for (byte = 0; byte < 4; byte++) { 1631 addr_tmp = slave_reg_tmp & MLXBF_I2C_SMBUS_SLAVE_ADDR_MASK; 1632 /* 1633 * Parse slave address bytes and check whether the 1634 * slave address already exists. 1635 */ 1636 if (addr_tmp == addr) { 1637 /* Clear the slave address slot. */ 1638 slave_reg &= ~(GENMASK(7, 0) << (byte * 8)); 1639 writel(slave_reg, priv->slv->io + 1640 MLXBF_I2C_SMBUS_SLAVE_ADDR_CFG + 1641 (reg * 0x4)); 1642 /* Free slave at the corresponding index */ 1643 priv->slave[(reg * 4) + byte] = NULL; 1644 1645 return 0; 1646 } 1647 1648 /* Parse next byte. */ 1649 slave_reg_tmp >>= 8; 1650 } 1651 } 1652 1653 return -ENXIO; 1654} 1655 1656static int mlxbf_i2c_init_coalesce(struct platform_device *pdev, 1657 struct mlxbf_i2c_priv *priv) 1658{ 1659 struct mlxbf_i2c_resource *coalesce_res; 1660 struct resource *params; 1661 resource_size_t size; 1662 int ret = 0; 1663 1664 /* 1665 * Unlike BlueField-1 platform, the coalesce registers is a dedicated 1666 * resource in the next generations of BlueField. 1667 */ 1668 if (mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) { 1669 coalesce_res = mlxbf_i2c_get_shared_resource(priv, 1670 MLXBF_I2C_COALESCE_RES); 1671 if (!coalesce_res) 1672 return -EPERM; 1673 1674 /* 1675 * The Cause Coalesce group in TYU space is shared among 1676 * I2C busses. This function MUST be serialized to avoid 1677 * racing when claiming the memory region. 1678 */ 1679 lockdep_assert_held(mlxbf_i2c_gpio_res->lock); 1680 1681 /* Check whether the memory map exist. */ 1682 if (coalesce_res->io) { 1683 priv->coalesce = coalesce_res; 1684 return 0; 1685 } 1686 1687 params = coalesce_res->params; 1688 size = resource_size(params); 1689 1690 if (!request_mem_region(params->start, size, params->name)) 1691 return -EFAULT; 1692 1693 coalesce_res->io = ioremap(params->start, size); 1694 if (!coalesce_res->io) { 1695 release_mem_region(params->start, size); 1696 return -ENOMEM; 1697 } 1698 1699 priv->coalesce = coalesce_res; 1700 1701 } else { 1702 ret = mlxbf_i2c_init_resource(pdev, &priv->coalesce, 1703 MLXBF_I2C_COALESCE_RES); 1704 } 1705 1706 return ret; 1707} 1708 1709static int mlxbf_i2c_release_coalesce(struct platform_device *pdev, 1710 struct mlxbf_i2c_priv *priv) 1711{ 1712 struct mlxbf_i2c_resource *coalesce_res; 1713 struct device *dev = &pdev->dev; 1714 struct resource *params; 1715 resource_size_t size; 1716 1717 coalesce_res = priv->coalesce; 1718 1719 if (coalesce_res->io) { 1720 params = coalesce_res->params; 1721 size = resource_size(params); 1722 if (mlxbf_i2c_has_chip_type(priv, MLXBF_I2C_CHIP_TYPE_1)) { 1723 mutex_lock(coalesce_res->lock); 1724 iounmap(coalesce_res->io); 1725 release_mem_region(params->start, size); 1726 mutex_unlock(coalesce_res->lock); 1727 } else { 1728 devm_release_mem_region(dev, params->start, size); 1729 } 1730 } 1731 1732 return 0; 1733} 1734 1735static int mlxbf_i2c_init_slave(struct platform_device *pdev, 1736 struct mlxbf_i2c_priv *priv) 1737{ 1738 struct device *dev = &pdev->dev; 1739 u32 int_reg; 1740 int ret; 1741 1742 /* Reset FSM. */ 1743 writel(0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_FSM); 1744 1745 /* 1746 * Enable slave cause interrupt bits. Drive 1747 * MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE and 1748 * MLXBF_I2C_CAUSE_WRITE_SUCCESS, these are enabled when an external 1749 * masters issue a Read and Write, respectively. But, clear all 1750 * interrupts first. 1751 */ 1752 writel(~0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR); 1753 int_reg = MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE; 1754 int_reg |= MLXBF_I2C_CAUSE_WRITE_SUCCESS; 1755 writel(int_reg, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_EVTEN0); 1756 1757 /* Finally, set the 'ready' bit to start handling transactions. */ 1758 writel(0x1, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_READY); 1759 1760 /* Initialize the cause coalesce resource. */ 1761 ret = mlxbf_i2c_init_coalesce(pdev, priv); 1762 if (ret < 0) { 1763 dev_err(dev, "failed to initialize cause coalesce\n"); 1764 return ret; 1765 } 1766 1767 return 0; 1768} 1769 1770static bool mlxbf_i2c_has_coalesce(struct mlxbf_i2c_priv *priv, bool *read, 1771 bool *write) 1772{ 1773 const struct mlxbf_i2c_chip_info *chip = priv->chip; 1774 u32 coalesce0_reg, cause_reg; 1775 u8 slave_shift, is_set; 1776 1777 *write = false; 1778 *read = false; 1779 1780 slave_shift = chip->type != MLXBF_I2C_CHIP_TYPE_1 ? 1781 MLXBF_I2C_CAUSE_YU_SLAVE_BIT : 1782 priv->bus + MLXBF_I2C_CAUSE_TYU_SLAVE_BIT; 1783 1784 coalesce0_reg = readl(priv->coalesce->io + MLXBF_I2C_CAUSE_COALESCE_0); 1785 is_set = coalesce0_reg & (1 << slave_shift); 1786 1787 if (!is_set) 1788 return false; 1789 1790 /* Check the source of the interrupt, i.e. whether a Read or Write. */ 1791 cause_reg = readl(priv->slv_cause->io + MLXBF_I2C_CAUSE_ARBITER); 1792 if (cause_reg & MLXBF_I2C_CAUSE_READ_WAIT_FW_RESPONSE) 1793 *read = true; 1794 else if (cause_reg & MLXBF_I2C_CAUSE_WRITE_SUCCESS) 1795 *write = true; 1796 1797 /* Clear cause bits. */ 1798 writel(~0x0, priv->slv_cause->io + MLXBF_I2C_CAUSE_OR_CLEAR); 1799 1800 return true; 1801} 1802 1803static struct i2c_client *mlxbf_i2c_get_slave_from_addr( 1804 struct mlxbf_i2c_priv *priv, u8 addr) 1805{ 1806 int i; 1807 1808 for (i = 0; i < MLXBF_I2C_SMBUS_SLAVE_ADDR_CNT; i++) { 1809 if (!priv->slave[i]) 1810 continue; 1811 1812 if (priv->slave[i]->addr == addr) 1813 return priv->slave[i]; 1814 } 1815 1816 return NULL; 1817} 1818 1819/* 1820 * Send byte to 'external' smbus master. This function is executed when 1821 * an external smbus master wants to read data from the BlueField. 1822 */ 1823static int mlxbf_i2c_irq_send(struct mlxbf_i2c_priv *priv, u8 recv_bytes) 1824{ 1825 u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 }; 1826 u8 write_size, pec_en, addr, value, byte_cnt; 1827 struct i2c_client *slave; 1828 u32 control32, data32; 1829 int ret = 0; 1830 1831 /* 1832 * Read the first byte received from the external master to 1833 * determine the slave address. This byte is located in the 1834 * first data descriptor register of the slave GW. 1835 */ 1836 data32 = ioread32be(priv->slv->io + 1837 MLXBF_I2C_SLAVE_DATA_DESC_ADDR); 1838 addr = (data32 & GENMASK(7, 0)) >> 1; 1839 1840 /* 1841 * Check if the slave address received in the data descriptor register 1842 * matches any of the slave addresses registered. If there is a match, 1843 * set the slave. 1844 */ 1845 slave = mlxbf_i2c_get_slave_from_addr(priv, addr); 1846 if (!slave) { 1847 ret = -ENXIO; 1848 goto clear_csr; 1849 } 1850 1851 /* 1852 * An I2C read can consist of a WRITE bit transaction followed by 1853 * a READ bit transaction. Indeed, slave devices often expect 1854 * the slave address to be followed by the internal address. 1855 * So, write the internal address byte first, and then, send the 1856 * requested data to the master. 1857 */ 1858 if (recv_bytes > 1) { 1859 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 1860 value = (data32 >> 8) & GENMASK(7, 0); 1861 ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, 1862 &value); 1863 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 1864 1865 if (ret < 0) 1866 goto clear_csr; 1867 } 1868 1869 /* 1870 * Send data to the master. Currently, the driver supports 1871 * READ_BYTE, READ_WORD and BLOCK READ protocols. The 1872 * hardware can send up to 128 bytes per transfer which is 1873 * the total size of the data registers. 1874 */ 1875 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value); 1876 1877 for (byte_cnt = 0; byte_cnt < MLXBF_I2C_SLAVE_DATA_DESC_SIZE; byte_cnt++) { 1878 data_desc[byte_cnt] = value; 1879 i2c_slave_event(slave, I2C_SLAVE_READ_PROCESSED, &value); 1880 } 1881 1882 /* Send a stop condition to the backend. */ 1883 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 1884 1885 /* Set the number of bytes to write to master. */ 1886 write_size = (byte_cnt - 1) & 0x7f; 1887 1888 /* Write data to Slave GW data descriptor. */ 1889 mlxbf_i2c_smbus_write_data(priv, data_desc, byte_cnt, 1890 MLXBF_I2C_SLAVE_DATA_DESC_ADDR, false); 1891 1892 pec_en = 0; /* Disable PEC since it is not supported. */ 1893 1894 /* Prepare control word. */ 1895 control32 = MLXBF_I2C_SLAVE_ENABLE; 1896 control32 |= rol32(write_size, MLXBF_I2C_SLAVE_WRITE_BYTES_SHIFT); 1897 control32 |= rol32(pec_en, MLXBF_I2C_SLAVE_SEND_PEC_SHIFT); 1898 1899 writel(control32, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_GW); 1900 1901 /* 1902 * Wait until the transfer is completed; the driver will wait 1903 * until the GW is idle, a cause will rise on fall of GW busy. 1904 */ 1905 readl_poll_timeout_atomic(priv->slv_cause->io + MLXBF_I2C_CAUSE_ARBITER, 1906 data32, data32 & MLXBF_I2C_CAUSE_S_GW_BUSY_FALL, 1907 MLXBF_I2C_POLL_FREQ_IN_USEC, MLXBF_I2C_SMBUS_TIMEOUT); 1908 1909clear_csr: 1910 /* Release the Slave GW. */ 1911 writel(0x0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); 1912 writel(0x0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_PEC); 1913 writel(0x1, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_READY); 1914 1915 return ret; 1916} 1917 1918/* 1919 * Receive bytes from 'external' smbus master. This function is executed when 1920 * an external smbus master wants to write data to the BlueField. 1921 */ 1922static int mlxbf_i2c_irq_recv(struct mlxbf_i2c_priv *priv, u8 recv_bytes) 1923{ 1924 u8 data_desc[MLXBF_I2C_SLAVE_DATA_DESC_SIZE] = { 0 }; 1925 struct i2c_client *slave; 1926 u8 value, byte, addr; 1927 int ret = 0; 1928 1929 /* Read data from Slave GW data descriptor. */ 1930 mlxbf_i2c_smbus_read_data(priv, data_desc, recv_bytes, 1931 MLXBF_I2C_SLAVE_DATA_DESC_ADDR, false); 1932 addr = data_desc[0] >> 1; 1933 1934 /* 1935 * Check if the slave address received in the data descriptor register 1936 * matches any of the slave addresses registered. 1937 */ 1938 slave = mlxbf_i2c_get_slave_from_addr(priv, addr); 1939 if (!slave) { 1940 ret = -EINVAL; 1941 goto clear_csr; 1942 } 1943 1944 /* 1945 * Notify the slave backend that an smbus master wants to write data 1946 * to the BlueField. 1947 */ 1948 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value); 1949 1950 /* Send the received data to the slave backend. */ 1951 for (byte = 1; byte < recv_bytes; byte++) { 1952 value = data_desc[byte]; 1953 ret = i2c_slave_event(slave, I2C_SLAVE_WRITE_RECEIVED, 1954 &value); 1955 if (ret < 0) 1956 break; 1957 } 1958 1959 /* 1960 * Send a stop event to the slave backend, to signal 1961 * the end of the write transactions. 1962 */ 1963 i2c_slave_event(slave, I2C_SLAVE_STOP, &value); 1964 1965clear_csr: 1966 /* Release the Slave GW. */ 1967 writel(0x0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); 1968 writel(0x0, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_PEC); 1969 writel(0x1, priv->slv->io + MLXBF_I2C_SMBUS_SLAVE_READY); 1970 1971 return ret; 1972} 1973 1974static irqreturn_t mlxbf_i2c_irq(int irq, void *ptr) 1975{ 1976 struct mlxbf_i2c_priv *priv = ptr; 1977 bool read, write, irq_is_set; 1978 u32 rw_bytes_reg; 1979 u8 recv_bytes; 1980 1981 /* 1982 * Read TYU interrupt register and determine the source of the 1983 * interrupt. Based on the source of the interrupt one of the 1984 * following actions are performed: 1985 * - Receive data and send response to master. 1986 * - Send data and release slave GW. 1987 * 1988 * Handle read/write transaction only. CRmaster and Iarp requests 1989 * are ignored for now. 1990 */ 1991 irq_is_set = mlxbf_i2c_has_coalesce(priv, &read, &write); 1992 if (!irq_is_set || (!read && !write)) { 1993 /* Nothing to do here, interrupt was not from this device. */ 1994 return IRQ_NONE; 1995 } 1996 1997 /* 1998 * The MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES includes the number of 1999 * bytes from/to master. These are defined by 8-bits each. If the lower 2000 * 8 bits are set, then the master expect to read N bytes from the 2001 * slave, if the higher 8 bits are sent then the slave expect N bytes 2002 * from the master. 2003 */ 2004 rw_bytes_reg = readl(priv->slv->io + 2005 MLXBF_I2C_SMBUS_SLAVE_RS_MASTER_BYTES); 2006 recv_bytes = (rw_bytes_reg >> 8) & GENMASK(7, 0); 2007 2008 /* 2009 * For now, the slave supports 128 bytes transfer. Discard remaining 2010 * data bytes if the master wrote more than 2011 * MLXBF_I2C_SLAVE_DATA_DESC_SIZE, i.e, the actual size of the slave 2012 * data descriptor. 2013 * 2014 * Note that we will never expect to transfer more than 128 bytes; as 2015 * specified in the SMBus standard, block transactions cannot exceed 2016 * 32 bytes. 2017 */ 2018 recv_bytes = recv_bytes > MLXBF_I2C_SLAVE_DATA_DESC_SIZE ? 2019 MLXBF_I2C_SLAVE_DATA_DESC_SIZE : recv_bytes; 2020 2021 if (read) 2022 mlxbf_i2c_irq_send(priv, recv_bytes); 2023 else 2024 mlxbf_i2c_irq_recv(priv, recv_bytes); 2025 2026 return IRQ_HANDLED; 2027} 2028 2029/* Return negative errno on error. */ 2030static s32 mlxbf_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr, 2031 unsigned short flags, char read_write, 2032 u8 command, int size, 2033 union i2c_smbus_data *data) 2034{ 2035 struct mlxbf_i2c_smbus_request request = { 0 }; 2036 struct mlxbf_i2c_priv *priv; 2037 bool read, pec; 2038 u8 byte_cnt; 2039 2040 request.slave = addr; 2041 2042 read = (read_write == I2C_SMBUS_READ); 2043 pec = flags & I2C_FUNC_SMBUS_PEC; 2044 2045 switch (size) { 2046 case I2C_SMBUS_QUICK: 2047 mlxbf_i2c_smbus_quick_command(&request, read); 2048 dev_dbg(&adap->dev, "smbus quick, slave 0x%02x\n", addr); 2049 break; 2050 2051 case I2C_SMBUS_BYTE: 2052 mlxbf_i2c_smbus_byte_func(&request, 2053 read ? &data->byte : &command, read, 2054 pec); 2055 dev_dbg(&adap->dev, "smbus %s byte, slave 0x%02x.\n", 2056 str_read_write(read), addr); 2057 break; 2058 2059 case I2C_SMBUS_BYTE_DATA: 2060 mlxbf_i2c_smbus_data_byte_func(&request, &command, &data->byte, 2061 read, pec); 2062 dev_dbg(&adap->dev, "smbus %s byte data at 0x%02x, slave 0x%02x.\n", 2063 str_read_write(read), command, addr); 2064 break; 2065 2066 case I2C_SMBUS_WORD_DATA: 2067 mlxbf_i2c_smbus_data_word_func(&request, &command, 2068 (u8 *)&data->word, read, pec); 2069 dev_dbg(&adap->dev, "smbus %s word data at 0x%02x, slave 0x%02x.\n", 2070 str_read_write(read), command, addr); 2071 break; 2072 2073 case I2C_SMBUS_I2C_BLOCK_DATA: 2074 byte_cnt = data->block[0]; 2075 mlxbf_i2c_smbus_i2c_block_func(&request, &command, data->block, 2076 &byte_cnt, read, pec); 2077 dev_dbg(&adap->dev, "i2c %s block data, %d bytes at 0x%02x, slave 0x%02x.\n", 2078 str_read_write(read), byte_cnt, command, addr); 2079 break; 2080 2081 case I2C_SMBUS_BLOCK_DATA: 2082 byte_cnt = read ? I2C_SMBUS_BLOCK_MAX : data->block[0]; 2083 mlxbf_i2c_smbus_block_func(&request, &command, data->block, 2084 &byte_cnt, read, pec); 2085 dev_dbg(&adap->dev, "smbus %s block data, %d bytes at 0x%02x, slave 0x%02x.\n", 2086 str_read_write(read), byte_cnt, command, addr); 2087 break; 2088 2089 case I2C_FUNC_SMBUS_PROC_CALL: 2090 mlxbf_i2c_smbus_process_call_func(&request, &command, 2091 (u8 *)&data->word, pec); 2092 dev_dbg(&adap->dev, "process call, wr/rd at 0x%02x, slave 0x%02x.\n", 2093 command, addr); 2094 break; 2095 2096 case I2C_FUNC_SMBUS_BLOCK_PROC_CALL: 2097 byte_cnt = data->block[0]; 2098 mlxbf_i2c_smbus_blk_process_call_func(&request, &command, 2099 data->block, &byte_cnt, 2100 pec); 2101 dev_dbg(&adap->dev, "block process call, wr/rd %d bytes, slave 0x%02x.\n", 2102 byte_cnt, addr); 2103 break; 2104 2105 default: 2106 dev_dbg(&adap->dev, "Unsupported I2C/SMBus command %d\n", 2107 size); 2108 return -EOPNOTSUPP; 2109 } 2110 2111 priv = i2c_get_adapdata(adap); 2112 2113 return mlxbf_i2c_smbus_start_transaction(priv, &request); 2114} 2115 2116static int mlxbf_i2c_reg_slave(struct i2c_client *slave) 2117{ 2118 struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 2119 struct device *dev = &slave->dev; 2120 int ret; 2121 2122 /* 2123 * Do not support ten bit chip address and do not use Packet Error 2124 * Checking (PEC). 2125 */ 2126 if (slave->flags & (I2C_CLIENT_TEN | I2C_CLIENT_PEC)) { 2127 dev_err(dev, "SMBus PEC and 10 bit address not supported\n"); 2128 return -EAFNOSUPPORT; 2129 } 2130 2131 ret = mlxbf_i2c_slave_enable(priv, slave); 2132 if (ret) 2133 dev_err(dev, "Surpassed max number of registered slaves allowed\n"); 2134 2135 return 0; 2136} 2137 2138static int mlxbf_i2c_unreg_slave(struct i2c_client *slave) 2139{ 2140 struct mlxbf_i2c_priv *priv = i2c_get_adapdata(slave->adapter); 2141 struct device *dev = &slave->dev; 2142 int ret; 2143 2144 /* 2145 * Unregister slave by: 2146 * 1) Disabling the slave address in hardware 2147 * 2) Freeing priv->slave at the corresponding index 2148 */ 2149 ret = mlxbf_i2c_slave_disable(priv, slave->addr); 2150 if (ret) 2151 dev_err(dev, "Unable to find slave 0x%x\n", slave->addr); 2152 2153 return ret; 2154} 2155 2156static u32 mlxbf_i2c_functionality(struct i2c_adapter *adap) 2157{ 2158 return MLXBF_I2C_FUNC_ALL; 2159} 2160 2161static struct mlxbf_i2c_chip_info mlxbf_i2c_chip[] = { 2162 [MLXBF_I2C_CHIP_TYPE_1] = { 2163 .type = MLXBF_I2C_CHIP_TYPE_1, 2164 .shared_res = { 2165 [0] = &mlxbf_i2c_coalesce_res[MLXBF_I2C_CHIP_TYPE_1], 2166 [1] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_1], 2167 [2] = &mlxbf_i2c_gpio_res[MLXBF_I2C_CHIP_TYPE_1] 2168 }, 2169 .calculate_freq = mlxbf_i2c_calculate_freq_from_tyu, 2170 .smbus_master_rs_bytes_off = MLXBF_I2C_YU_SMBUS_RS_BYTES, 2171 .smbus_master_fsm_off = MLXBF_I2C_YU_SMBUS_MASTER_FSM 2172 }, 2173 [MLXBF_I2C_CHIP_TYPE_2] = { 2174 .type = MLXBF_I2C_CHIP_TYPE_2, 2175 .shared_res = { 2176 [0] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_2] 2177 }, 2178 .calculate_freq = mlxbf_i2c_calculate_freq_from_yu, 2179 .smbus_master_rs_bytes_off = MLXBF_I2C_YU_SMBUS_RS_BYTES, 2180 .smbus_master_fsm_off = MLXBF_I2C_YU_SMBUS_MASTER_FSM 2181 }, 2182 [MLXBF_I2C_CHIP_TYPE_3] = { 2183 .type = MLXBF_I2C_CHIP_TYPE_3, 2184 .shared_res = { 2185 [0] = &mlxbf_i2c_corepll_res[MLXBF_I2C_CHIP_TYPE_3] 2186 }, 2187 .calculate_freq = mlxbf_i2c_calculate_freq_from_yu, 2188 .smbus_master_rs_bytes_off = MLXBF_I2C_RSH_YU_SMBUS_RS_BYTES, 2189 .smbus_master_fsm_off = MLXBF_I2C_RSH_YU_SMBUS_MASTER_FSM 2190 } 2191}; 2192 2193static const struct i2c_algorithm mlxbf_i2c_algo = { 2194 .smbus_xfer = mlxbf_i2c_smbus_xfer, 2195 .functionality = mlxbf_i2c_functionality, 2196 .reg_slave = mlxbf_i2c_reg_slave, 2197 .unreg_slave = mlxbf_i2c_unreg_slave, 2198}; 2199 2200static struct i2c_adapter_quirks mlxbf_i2c_quirks = { 2201 .max_read_len = MLXBF_I2C_MASTER_DATA_R_LENGTH, 2202 .max_write_len = MLXBF_I2C_MASTER_DATA_W_LENGTH, 2203}; 2204 2205static const struct acpi_device_id mlxbf_i2c_acpi_ids[] = { 2206 { "MLNXBF03", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_1] }, 2207 { "MLNXBF23", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_2] }, 2208 { "MLNXBF31", (kernel_ulong_t)&mlxbf_i2c_chip[MLXBF_I2C_CHIP_TYPE_3] }, 2209 {}, 2210}; 2211 2212MODULE_DEVICE_TABLE(acpi, mlxbf_i2c_acpi_ids); 2213 2214static int mlxbf_i2c_acpi_probe(struct device *dev, struct mlxbf_i2c_priv *priv) 2215{ 2216 const struct acpi_device_id *aid; 2217 u64 bus_id; 2218 int ret; 2219 2220 if (acpi_disabled) 2221 return -ENOENT; 2222 2223 aid = acpi_match_device(mlxbf_i2c_acpi_ids, dev); 2224 if (!aid) 2225 return -ENODEV; 2226 2227 priv->chip = (struct mlxbf_i2c_chip_info *)aid->driver_data; 2228 2229 ret = acpi_dev_uid_to_integer(ACPI_COMPANION(dev), &bus_id); 2230 if (ret) { 2231 dev_err(dev, "Cannot retrieve UID\n"); 2232 return ret; 2233 } 2234 2235 priv->bus = bus_id; 2236 2237 return 0; 2238} 2239 2240static int mlxbf_i2c_probe(struct platform_device *pdev) 2241{ 2242 struct device *dev = &pdev->dev; 2243 struct mlxbf_i2c_priv *priv; 2244 struct i2c_adapter *adap; 2245 u32 resource_version; 2246 int irq, ret; 2247 2248 priv = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_priv), GFP_KERNEL); 2249 if (!priv) 2250 return -ENOMEM; 2251 2252 ret = mlxbf_i2c_acpi_probe(dev, priv); 2253 if (ret < 0) 2254 return ret; 2255 2256 /* This property allows the driver to stay backward compatible with older 2257 * ACPI tables. 2258 * Starting BlueField-3 SoC, the "smbus" resource was broken down into 3 2259 * separate resources "timer", "master" and "slave". 2260 */ 2261 if (device_property_read_u32(dev, "resource_version", &resource_version)) 2262 resource_version = 0; 2263 2264 priv->resource_version = resource_version; 2265 2266 if (priv->chip->type < MLXBF_I2C_CHIP_TYPE_3 && resource_version == 0) { 2267 priv->timer = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource), GFP_KERNEL); 2268 if (!priv->timer) 2269 return -ENOMEM; 2270 2271 priv->mst = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource), GFP_KERNEL); 2272 if (!priv->mst) 2273 return -ENOMEM; 2274 2275 priv->slv = devm_kzalloc(dev, sizeof(struct mlxbf_i2c_resource), GFP_KERNEL); 2276 if (!priv->slv) 2277 return -ENOMEM; 2278 2279 ret = mlxbf_i2c_init_resource(pdev, &priv->smbus, 2280 MLXBF_I2C_SMBUS_RES); 2281 if (ret < 0) 2282 return dev_err_probe(dev, ret, "Cannot fetch smbus resource info"); 2283 2284 priv->timer->io = priv->smbus->io; 2285 priv->mst->io = priv->smbus->io + MLXBF_I2C_MST_ADDR_OFFSET; 2286 priv->slv->io = priv->smbus->io + MLXBF_I2C_SLV_ADDR_OFFSET; 2287 } else { 2288 ret = mlxbf_i2c_init_resource(pdev, &priv->timer, 2289 MLXBF_I2C_SMBUS_TIMER_RES); 2290 if (ret < 0) 2291 return dev_err_probe(dev, ret, "Cannot fetch timer resource info"); 2292 2293 ret = mlxbf_i2c_init_resource(pdev, &priv->mst, 2294 MLXBF_I2C_SMBUS_MST_RES); 2295 if (ret < 0) 2296 return dev_err_probe(dev, ret, "Cannot fetch master resource info"); 2297 2298 ret = mlxbf_i2c_init_resource(pdev, &priv->slv, 2299 MLXBF_I2C_SMBUS_SLV_RES); 2300 if (ret < 0) 2301 return dev_err_probe(dev, ret, "Cannot fetch slave resource info"); 2302 } 2303 2304 ret = mlxbf_i2c_init_resource(pdev, &priv->mst_cause, 2305 MLXBF_I2C_MST_CAUSE_RES); 2306 if (ret < 0) 2307 return dev_err_probe(dev, ret, "Cannot fetch cause master resource info"); 2308 2309 ret = mlxbf_i2c_init_resource(pdev, &priv->slv_cause, 2310 MLXBF_I2C_SLV_CAUSE_RES); 2311 if (ret < 0) 2312 return dev_err_probe(dev, ret, "Cannot fetch cause slave resource info"); 2313 2314 adap = &priv->adap; 2315 adap->owner = THIS_MODULE; 2316 adap->class = I2C_CLASS_HWMON; 2317 adap->algo = &mlxbf_i2c_algo; 2318 adap->quirks = &mlxbf_i2c_quirks; 2319 adap->dev.parent = dev; 2320 adap->dev.of_node = dev->of_node; 2321 adap->nr = priv->bus; 2322 2323 snprintf(adap->name, sizeof(adap->name), "i2c%d", adap->nr); 2324 i2c_set_adapdata(adap, priv); 2325 2326 /* Read Core PLL frequency. */ 2327 ret = mlxbf_i2c_calculate_corepll_freq(pdev, priv); 2328 if (ret < 0) { 2329 dev_err(dev, "cannot get core clock frequency\n"); 2330 /* Set to default value. */ 2331 priv->frequency = MLXBF_I2C_COREPLL_FREQ; 2332 } 2333 2334 /* 2335 * Initialize master. 2336 * Note that a physical bus might be shared among Linux and firmware 2337 * (e.g., ATF). Thus, the bus should be initialized and ready and 2338 * bus initialization would be unnecessary. This requires additional 2339 * knowledge about physical busses. But, since an extra initialization 2340 * does not really hurt, then keep the code as is. 2341 */ 2342 ret = mlxbf_i2c_init_master(pdev, priv); 2343 if (ret < 0) 2344 return dev_err_probe(dev, ret, "failed to initialize smbus master %d", 2345 priv->bus); 2346 2347 mlxbf_i2c_init_timings(pdev, priv); 2348 2349 mlxbf_i2c_init_slave(pdev, priv); 2350 2351 irq = platform_get_irq(pdev, 0); 2352 if (irq < 0) 2353 return irq; 2354 ret = devm_request_irq(dev, irq, mlxbf_i2c_irq, 2355 IRQF_SHARED | IRQF_PROBE_SHARED, 2356 dev_name(dev), priv); 2357 if (ret < 0) 2358 return dev_err_probe(dev, ret, "Cannot get irq %d\n", irq); 2359 2360 priv->irq = irq; 2361 2362 platform_set_drvdata(pdev, priv); 2363 2364 ret = i2c_add_numbered_adapter(adap); 2365 if (ret < 0) 2366 return ret; 2367 2368 mutex_lock(&mlxbf_i2c_bus_lock); 2369 mlxbf_i2c_bus_count++; 2370 mutex_unlock(&mlxbf_i2c_bus_lock); 2371 2372 return 0; 2373} 2374 2375static void mlxbf_i2c_remove(struct platform_device *pdev) 2376{ 2377 struct mlxbf_i2c_priv *priv = platform_get_drvdata(pdev); 2378 struct device *dev = &pdev->dev; 2379 struct resource *params; 2380 2381 if (priv->chip->type < MLXBF_I2C_CHIP_TYPE_3 && priv->resource_version == 0) { 2382 params = priv->smbus->params; 2383 devm_release_mem_region(dev, params->start, resource_size(params)); 2384 } else { 2385 params = priv->timer->params; 2386 devm_release_mem_region(dev, params->start, resource_size(params)); 2387 2388 params = priv->mst->params; 2389 devm_release_mem_region(dev, params->start, resource_size(params)); 2390 2391 params = priv->slv->params; 2392 devm_release_mem_region(dev, params->start, resource_size(params)); 2393 } 2394 2395 params = priv->mst_cause->params; 2396 devm_release_mem_region(dev, params->start, resource_size(params)); 2397 2398 params = priv->slv_cause->params; 2399 devm_release_mem_region(dev, params->start, resource_size(params)); 2400 2401 /* 2402 * Release shared resources. This should be done when releasing 2403 * the I2C controller. 2404 */ 2405 mutex_lock(&mlxbf_i2c_bus_lock); 2406 if (--mlxbf_i2c_bus_count == 0) { 2407 mlxbf_i2c_release_coalesce(pdev, priv); 2408 mlxbf_i2c_release_corepll(pdev, priv); 2409 mlxbf_i2c_release_gpio(pdev, priv); 2410 } 2411 mutex_unlock(&mlxbf_i2c_bus_lock); 2412 2413 devm_free_irq(dev, priv->irq, priv); 2414 2415 i2c_del_adapter(&priv->adap); 2416} 2417 2418static struct platform_driver mlxbf_i2c_driver = { 2419 .probe = mlxbf_i2c_probe, 2420 .remove = mlxbf_i2c_remove, 2421 .driver = { 2422 .name = "i2c-mlxbf", 2423 .acpi_match_table = ACPI_PTR(mlxbf_i2c_acpi_ids), 2424 }, 2425}; 2426 2427static int __init mlxbf_i2c_init(void) 2428{ 2429 mutex_init(&mlxbf_i2c_coalesce_lock); 2430 mutex_init(&mlxbf_i2c_corepll_lock); 2431 mutex_init(&mlxbf_i2c_gpio_lock); 2432 2433 mutex_init(&mlxbf_i2c_bus_lock); 2434 2435 return platform_driver_register(&mlxbf_i2c_driver); 2436} 2437module_init(mlxbf_i2c_init); 2438 2439static void __exit mlxbf_i2c_exit(void) 2440{ 2441 platform_driver_unregister(&mlxbf_i2c_driver); 2442 2443 mutex_destroy(&mlxbf_i2c_bus_lock); 2444 2445 mutex_destroy(&mlxbf_i2c_gpio_lock); 2446 mutex_destroy(&mlxbf_i2c_corepll_lock); 2447 mutex_destroy(&mlxbf_i2c_coalesce_lock); 2448} 2449module_exit(mlxbf_i2c_exit); 2450 2451MODULE_DESCRIPTION("Mellanox BlueField I2C bus driver"); 2452MODULE_AUTHOR("Khalil Blaiech <kblaiech@nvidia.com>"); 2453MODULE_AUTHOR("Asmaa Mnebhi <asmaa@nvidia.com>"); 2454MODULE_LICENSE("GPL v2");
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