i2c-k1.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (C) 2024-2025 Troy Mitchell <troymitchell988@gmail.com>
  4 */
  5
  6#include <linux/bitfield.h>
  7 #include <linux/clk.h>
  8 #include <linux/i2c.h>
  9 #include <linux/iopoll.h>
 10 #include <linux/module.h>
 11 #include <linux/of_address.h>
 12 #include <linux/platform_device.h>
 13
 14/* spacemit i2c registers */
 15#define SPACEMIT_ICR		 0x0		/* Control register */
 16#define SPACEMIT_ISR		 0x4		/* Status register */
 17#define SPACEMIT_IDBR		 0xc		/* Data buffer register */
 18#define SPACEMIT_IRCR		 0x18		/* Reset cycle counter */
 19#define SPACEMIT_IBMR		 0x1c		/* Bus monitor register */
 20
 21/* SPACEMIT_ICR register fields */
 22#define SPACEMIT_CR_START        BIT(0)		/* start bit */
 23#define SPACEMIT_CR_STOP         BIT(1)		/* stop bit */
 24#define SPACEMIT_CR_ACKNAK       BIT(2)		/* send ACK(0) or NAK(1) */
 25#define SPACEMIT_CR_TB           BIT(3)		/* transfer byte bit */
 26/* Bits 4-7 are reserved */
 27#define SPACEMIT_CR_MODE_FAST    BIT(8)		/* bus mode (master operation) */
 28/* Bit 9 is reserved */
 29#define SPACEMIT_CR_UR           BIT(10)	/* unit reset */
 30#define SPACEMIT_CR_RSTREQ	 BIT(11)	/* i2c bus reset request */
 31/* Bit 12 is reserved */
 32#define SPACEMIT_CR_SCLE         BIT(13)	/* master clock enable */
 33#define SPACEMIT_CR_IUE          BIT(14)	/* unit enable */
 34/* Bits 15-17 are reserved */
 35#define SPACEMIT_CR_ALDIE        BIT(18)	/* enable arbitration interrupt */
 36#define SPACEMIT_CR_DTEIE        BIT(19)	/* enable TX interrupts */
 37#define SPACEMIT_CR_DRFIE        BIT(20)	/* enable RX interrupts */
 38#define SPACEMIT_CR_GCD          BIT(21)	/* general call disable */
 39#define SPACEMIT_CR_BEIE         BIT(22)	/* enable bus error ints */
 40/* Bits 23-24 are reserved */
 41#define SPACEMIT_CR_MSDIE        BIT(25)	/* master STOP detected int enable */
 42#define SPACEMIT_CR_MSDE         BIT(26)	/* master STOP detected enable */
 43#define SPACEMIT_CR_TXDONEIE     BIT(27)	/* transaction done int enable */
 44#define SPACEMIT_CR_TXEIE        BIT(28)	/* transmit FIFO empty int enable */
 45#define SPACEMIT_CR_RXHFIE       BIT(29)	/* receive FIFO half-full int enable */
 46#define SPACEMIT_CR_RXFIE        BIT(30)	/* receive FIFO full int enable */
 47#define SPACEMIT_CR_RXOVIE       BIT(31)	/* receive FIFO overrun int enable */
 48
 49#define SPACEMIT_I2C_INT_CTRL_MASK	(SPACEMIT_CR_ALDIE | SPACEMIT_CR_DTEIE | \
 50					 SPACEMIT_CR_DRFIE | SPACEMIT_CR_BEIE | \
 51					 SPACEMIT_CR_TXDONEIE | SPACEMIT_CR_TXEIE | \
 52					 SPACEMIT_CR_RXHFIE | SPACEMIT_CR_RXFIE | \
 53					 SPACEMIT_CR_RXOVIE | SPACEMIT_CR_MSDIE)
 54
 55/* SPACEMIT_ISR register fields */
 56/* Bits 0-13 are reserved */
 57#define SPACEMIT_SR_ACKNAK       BIT(14)	/* ACK/NACK status */
 58#define SPACEMIT_SR_UB           BIT(15)	/* unit busy */
 59#define SPACEMIT_SR_IBB          BIT(16)	/* i2c bus busy */
 60#define SPACEMIT_SR_EBB          BIT(17)	/* early bus busy */
 61#define SPACEMIT_SR_ALD          BIT(18)	/* arbitration loss detected */
 62#define SPACEMIT_SR_ITE          BIT(19)	/* TX buffer empty */
 63#define SPACEMIT_SR_IRF          BIT(20)	/* RX buffer full */
 64#define SPACEMIT_SR_GCAD         BIT(21)	/* general call address detected */
 65#define SPACEMIT_SR_BED          BIT(22)	/* bus error no ACK/NAK */
 66#define SPACEMIT_SR_SAD          BIT(23)	/* slave address detected */
 67#define SPACEMIT_SR_SSD          BIT(24)	/* slave stop detected */
 68/* Bit 25 is reserved */
 69#define SPACEMIT_SR_MSD          BIT(26)	/* master stop detected */
 70#define SPACEMIT_SR_TXDONE       BIT(27)	/* transaction done */
 71#define SPACEMIT_SR_TXE          BIT(28)	/* TX FIFO empty */
 72#define SPACEMIT_SR_RXHF         BIT(29)	/* RX FIFO half-full */
 73#define SPACEMIT_SR_RXF          BIT(30)	/* RX FIFO full */
 74#define SPACEMIT_SR_RXOV         BIT(31)	/* RX FIFO overrun */
 75
 76#define SPACEMIT_I2C_INT_STATUS_MASK	(SPACEMIT_SR_RXOV | SPACEMIT_SR_RXF | SPACEMIT_SR_RXHF | \
 77					SPACEMIT_SR_TXE | SPACEMIT_SR_TXDONE | SPACEMIT_SR_MSD | \
 78					SPACEMIT_SR_SSD | SPACEMIT_SR_SAD | SPACEMIT_SR_BED | \
 79					SPACEMIT_SR_GCAD | SPACEMIT_SR_IRF | SPACEMIT_SR_ITE | \
 80					SPACEMIT_SR_ALD)
 81
 82#define SPACEMIT_RCR_SDA_GLITCH_NOFIX		BIT(7)		/* bypass the SDA glitch fix */
 83/* the cycles of SCL during bus reset */
 84#define SPACEMIT_RCR_FIELD_RST_CYC		GENMASK(3, 0)
 85
 86/* SPACEMIT_IBMR register fields */
 87#define SPACEMIT_BMR_SDA         BIT(0)		/* SDA line level */
 88#define SPACEMIT_BMR_SCL         BIT(1)		/* SCL line level */
 89
 90/* i2c bus recover timeout: us */
 91#define SPACEMIT_I2C_BUS_BUSY_TIMEOUT		100000
 92
 93#define SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ	100000	/* Hz */
 94#define SPACEMIT_I2C_MAX_FAST_MODE_FREQ		400000	/* Hz */
 95
 96#define SPACEMIT_SR_ERR	(SPACEMIT_SR_BED | SPACEMIT_SR_RXOV | SPACEMIT_SR_ALD)
 97
 98#define SPACEMIT_BUS_RESET_CLK_CNT_MAX		9
 99
100enum spacemit_i2c_state {
101	SPACEMIT_STATE_IDLE,
102	SPACEMIT_STATE_START,
103	SPACEMIT_STATE_READ,
104	SPACEMIT_STATE_WRITE,
105};
106
107/* i2c-spacemit driver's main struct */
108struct spacemit_i2c_dev {
109	struct device *dev;
110	struct i2c_adapter adapt;
111
112	/* hardware resources */
113	void __iomem *base;
114	int irq;
115	u32 clock_freq;
116
117	struct i2c_msg *msgs;
118	u32 msg_num;
119
120	/* index of the current message being processed */
121	u32 msg_idx;
122	u8 *msg_buf;
123	/* the number of unprocessed bytes remaining in the current message  */
124	u32 unprocessed;
125
126	enum spacemit_i2c_state state;
127	bool read;
128	struct completion complete;
129	u32 status;
130};
131
132static void spacemit_i2c_enable(struct spacemit_i2c_dev *i2c)
133{
134	u32 val;
135
136	val = readl(i2c->base + SPACEMIT_ICR);
137	val |= SPACEMIT_CR_IUE;
138	writel(val, i2c->base + SPACEMIT_ICR);
139}
140
141static void spacemit_i2c_disable(struct spacemit_i2c_dev *i2c)
142{
143	u32 val;
144
145	val = readl(i2c->base + SPACEMIT_ICR);
146	val &= ~SPACEMIT_CR_IUE;
147	writel(val, i2c->base + SPACEMIT_ICR);
148}
149
150static void spacemit_i2c_reset(struct spacemit_i2c_dev *i2c)
151{
152	writel(SPACEMIT_CR_UR, i2c->base + SPACEMIT_ICR);
153	udelay(5);
154	writel(0, i2c->base + SPACEMIT_ICR);
155}
156
157static int spacemit_i2c_handle_err(struct spacemit_i2c_dev *i2c)
158{
159	dev_dbg(i2c->dev, "i2c error status: 0x%08x\n", i2c->status);
160
161	/* Arbitration Loss Detected */
162	if (i2c->status & SPACEMIT_SR_ALD) {
163		spacemit_i2c_reset(i2c);
164		return -EAGAIN;
165	}
166
167	/* Bus Error No ACK/NAK */
168	if (i2c->status & SPACEMIT_SR_BED)
169		spacemit_i2c_reset(i2c);
170
171	return i2c->status & SPACEMIT_SR_ACKNAK ? -ENXIO : -EIO;
172}
173
174static void spacemit_i2c_conditionally_reset_bus(struct spacemit_i2c_dev *i2c)
175{
176	u32 status;
177	u8 clk_cnt;
178
179	/* if bus is locked, reset unit. 0: locked */
180	status = readl(i2c->base + SPACEMIT_IBMR);
181	if ((status & SPACEMIT_BMR_SDA) && (status & SPACEMIT_BMR_SCL))
182		return;
183
184	spacemit_i2c_reset(i2c);
185	usleep_range(10, 20);
186
187	for (clk_cnt = 0; clk_cnt < SPACEMIT_BUS_RESET_CLK_CNT_MAX; clk_cnt++) {
188		status = readl(i2c->base + SPACEMIT_IBMR);
189		if (status & SPACEMIT_BMR_SDA)
190			return;
191
192		/* There's nothing left to save here, we are about to exit */
193		writel(FIELD_PREP(SPACEMIT_RCR_FIELD_RST_CYC, 1),
194		       i2c->base + SPACEMIT_IRCR);
195		writel(SPACEMIT_CR_RSTREQ, i2c->base + SPACEMIT_ICR);
196		usleep_range(20, 30);
197	}
198
199	/* check sda again here */
200	status = readl(i2c->base + SPACEMIT_IBMR);
201	if (!(status & SPACEMIT_BMR_SDA))
202		dev_warn_ratelimited(i2c->dev, "unit reset failed\n");
203}
204
205static int spacemit_i2c_wait_bus_idle(struct spacemit_i2c_dev *i2c)
206{
207	int ret;
208	u32 val;
209
210	val = readl(i2c->base + SPACEMIT_ISR);
211	if (!(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB)))
212		return 0;
213
214	ret = readl_poll_timeout(i2c->base + SPACEMIT_ISR,
215				 val, !(val & (SPACEMIT_SR_UB | SPACEMIT_SR_IBB)),
216				 1500, SPACEMIT_I2C_BUS_BUSY_TIMEOUT);
217	if (ret)
218		spacemit_i2c_reset(i2c);
219
220	return ret;
221}
222
223static void spacemit_i2c_check_bus_release(struct spacemit_i2c_dev *i2c)
224{
225	/* in case bus is not released after transfer completes */
226	if (readl(i2c->base + SPACEMIT_ISR) & SPACEMIT_SR_EBB) {
227		spacemit_i2c_conditionally_reset_bus(i2c);
228		usleep_range(90, 150);
229	}
230}
231
232static inline void
233spacemit_i2c_clear_int_status(struct spacemit_i2c_dev *i2c, u32 mask)
234{
235	writel(mask & SPACEMIT_I2C_INT_STATUS_MASK, i2c->base + SPACEMIT_ISR);
236}
237
238static void spacemit_i2c_init(struct spacemit_i2c_dev *i2c)
239{
240	u32 val;
241
242	/*
243	 * Unmask interrupt bits for all xfer mode:
244	 * bus error, arbitration loss detected.
245	 * For transaction complete signal, we use master stop
246	 * interrupt, so we don't need to unmask SPACEMIT_CR_TXDONEIE.
247	 */
248	val = SPACEMIT_CR_BEIE | SPACEMIT_CR_ALDIE;
249
250	/*
251	 * Unmask interrupt bits for interrupt xfer mode:
252	 * When IDBR receives a byte, an interrupt is triggered.
253	 *
254	 * For the tx empty interrupt, it will be enabled in the
255	 * i2c_start function.
256	 * Otherwise, it will cause an erroneous empty interrupt before i2c_start.
257	 */
258	val |= SPACEMIT_CR_DRFIE;
259
260	if (i2c->clock_freq == SPACEMIT_I2C_MAX_FAST_MODE_FREQ)
261		val |= SPACEMIT_CR_MODE_FAST;
262
263	/* disable response to general call */
264	val |= SPACEMIT_CR_GCD;
265
266	/* enable SCL clock output */
267	val |= SPACEMIT_CR_SCLE;
268
269	/* enable master stop detected */
270	val |= SPACEMIT_CR_MSDE | SPACEMIT_CR_MSDIE;
271
272	writel(val, i2c->base + SPACEMIT_ICR);
273
274	/*
275	 * The glitch fix in the K1 I2C controller introduces a delay
276	 * on restart signals, so we disable the fix here.
277	 */
278	val = readl(i2c->base + SPACEMIT_IRCR);
279	val |= SPACEMIT_RCR_SDA_GLITCH_NOFIX;
280	writel(val, i2c->base + SPACEMIT_IRCR);
281
282	spacemit_i2c_clear_int_status(i2c, SPACEMIT_I2C_INT_STATUS_MASK);
283}
284
285static void spacemit_i2c_start(struct spacemit_i2c_dev *i2c)
286{
287	u32 target_addr_rw, val;
288	struct i2c_msg *cur_msg = i2c->msgs + i2c->msg_idx;
289
290	i2c->read = !!(cur_msg->flags & I2C_M_RD);
291
292	i2c->state = SPACEMIT_STATE_START;
293
294	target_addr_rw = (cur_msg->addr & 0x7f) << 1;
295	if (cur_msg->flags & I2C_M_RD)
296		target_addr_rw |= 1;
297
298	writel(target_addr_rw, i2c->base + SPACEMIT_IDBR);
299
300	/* send start pulse */
301	val = readl(i2c->base + SPACEMIT_ICR);
302	val &= ~SPACEMIT_CR_STOP;
303	val |= SPACEMIT_CR_START | SPACEMIT_CR_TB | SPACEMIT_CR_DTEIE;
304	writel(val, i2c->base + SPACEMIT_ICR);
305}
306
307static int spacemit_i2c_xfer_msg(struct spacemit_i2c_dev *i2c)
308{
309	unsigned long time_left;
310	struct i2c_msg *msg;
311
312	for (i2c->msg_idx = 0; i2c->msg_idx < i2c->msg_num; i2c->msg_idx++) {
313		msg = &i2c->msgs[i2c->msg_idx];
314		i2c->msg_buf = msg->buf;
315		i2c->unprocessed = msg->len;
316		i2c->status = 0;
317
318		reinit_completion(&i2c->complete);
319
320		spacemit_i2c_start(i2c);
321
322		time_left = wait_for_completion_timeout(&i2c->complete,
323							i2c->adapt.timeout);
324		if (!time_left) {
325			dev_err(i2c->dev, "msg completion timeout\n");
326			spacemit_i2c_conditionally_reset_bus(i2c);
327			spacemit_i2c_reset(i2c);
328			return -ETIMEDOUT;
329		}
330
331		if (i2c->status & SPACEMIT_SR_ERR)
332			return spacemit_i2c_handle_err(i2c);
333	}
334
335	return 0;
336}
337
338static bool spacemit_i2c_is_last_msg(struct spacemit_i2c_dev *i2c)
339{
340	if (i2c->msg_idx != i2c->msg_num - 1)
341		return false;
342
343	if (i2c->read)
344		return i2c->unprocessed == 1;
345
346	return !i2c->unprocessed;
347}
348
349static void spacemit_i2c_handle_write(struct spacemit_i2c_dev *i2c)
350{
351	/* if transfer completes, SPACEMIT_ISR will handle it */
352	if (i2c->status & SPACEMIT_SR_MSD)
353		return;
354
355	if (i2c->unprocessed) {
356		writel(*i2c->msg_buf++, i2c->base + SPACEMIT_IDBR);
357		i2c->unprocessed--;
358		return;
359	}
360
361	/* SPACEMIT_STATE_IDLE avoids trigger next byte */
362	i2c->state = SPACEMIT_STATE_IDLE;
363	complete(&i2c->complete);
364}
365
366static void spacemit_i2c_handle_read(struct spacemit_i2c_dev *i2c)
367{
368	if (i2c->unprocessed) {
369		*i2c->msg_buf++ = readl(i2c->base + SPACEMIT_IDBR);
370		i2c->unprocessed--;
371	}
372
373	/* if transfer completes, SPACEMIT_ISR will handle it */
374	if (i2c->status & (SPACEMIT_SR_MSD | SPACEMIT_SR_ACKNAK))
375		return;
376
377	/* it has to append stop bit in icr that read last byte */
378	if (i2c->unprocessed)
379		return;
380
381	/* SPACEMIT_STATE_IDLE avoids trigger next byte */
382	i2c->state = SPACEMIT_STATE_IDLE;
383	complete(&i2c->complete);
384}
385
386static void spacemit_i2c_handle_start(struct spacemit_i2c_dev *i2c)
387{
388	i2c->state = i2c->read ? SPACEMIT_STATE_READ : SPACEMIT_STATE_WRITE;
389	if (i2c->state == SPACEMIT_STATE_WRITE)
390		spacemit_i2c_handle_write(i2c);
391}
392
393static void spacemit_i2c_err_check(struct spacemit_i2c_dev *i2c)
394{
395	u32 val;
396
397	/*
398	 * Send transaction complete signal:
399	 * error happens, detect master stop
400	 */
401	if (!(i2c->status & (SPACEMIT_SR_ERR | SPACEMIT_SR_MSD)))
402		return;
403
404	/*
405	 * Here the transaction is already done, we don't need any
406	 * other interrupt signals from now, in case any interrupt
407	 * happens before spacemit_i2c_xfer to disable irq and i2c unit,
408	 * we mask all the interrupt signals and clear the interrupt
409	 * status.
410	 */
411	val = readl(i2c->base + SPACEMIT_ICR);
412	val &= ~SPACEMIT_I2C_INT_CTRL_MASK;
413	writel(val, i2c->base + SPACEMIT_ICR);
414
415	spacemit_i2c_clear_int_status(i2c, SPACEMIT_I2C_INT_STATUS_MASK);
416
417	i2c->state = SPACEMIT_STATE_IDLE;
418	complete(&i2c->complete);
419}
420
421static irqreturn_t spacemit_i2c_irq_handler(int irq, void *devid)
422{
423	struct spacemit_i2c_dev *i2c = devid;
424	u32 status, val;
425
426	status = readl(i2c->base + SPACEMIT_ISR);
427	if (!status)
428		return IRQ_HANDLED;
429
430	i2c->status = status;
431
432	spacemit_i2c_clear_int_status(i2c, status);
433
434	if (i2c->status & SPACEMIT_SR_ERR)
435		goto err_out;
436
437	val = readl(i2c->base + SPACEMIT_ICR);
438	val &= ~(SPACEMIT_CR_TB | SPACEMIT_CR_ACKNAK | SPACEMIT_CR_STOP | SPACEMIT_CR_START);
439
440	switch (i2c->state) {
441	case SPACEMIT_STATE_START:
442		spacemit_i2c_handle_start(i2c);
443		break;
444	case SPACEMIT_STATE_READ:
445		spacemit_i2c_handle_read(i2c);
446		break;
447	case SPACEMIT_STATE_WRITE:
448		spacemit_i2c_handle_write(i2c);
449		break;
450	default:
451		break;
452	}
453
454	if (i2c->state != SPACEMIT_STATE_IDLE) {
455		val |= SPACEMIT_CR_TB | SPACEMIT_CR_ALDIE;
456
457		if (spacemit_i2c_is_last_msg(i2c)) {
458			/* trigger next byte with stop */
459			val |= SPACEMIT_CR_STOP;
460
461			if (i2c->read)
462				val |= SPACEMIT_CR_ACKNAK;
463		}
464		writel(val, i2c->base + SPACEMIT_ICR);
465	}
466
467err_out:
468	spacemit_i2c_err_check(i2c);
469	return IRQ_HANDLED;
470}
471
472static void spacemit_i2c_calc_timeout(struct spacemit_i2c_dev *i2c)
473{
474	unsigned long timeout;
475	int idx = 0, cnt = 0;
476
477	for (; idx < i2c->msg_num; idx++)
478		cnt += (i2c->msgs + idx)->len + 1;
479
480	/*
481	 * Multiply by 9 because each byte in I2C transmission requires
482	 * 9 clock cycles: 8 bits of data plus 1 ACK/NACK bit.
483	 */
484	timeout = cnt * 9 * USEC_PER_SEC / i2c->clock_freq;
485
486	i2c->adapt.timeout = usecs_to_jiffies(timeout + USEC_PER_SEC / 10) / i2c->msg_num;
487}
488
489static int spacemit_i2c_xfer(struct i2c_adapter *adapt, struct i2c_msg *msgs, int num)
490{
491	struct spacemit_i2c_dev *i2c = i2c_get_adapdata(adapt);
492	int ret;
493
494	i2c->msgs = msgs;
495	i2c->msg_num = num;
496
497	spacemit_i2c_calc_timeout(i2c);
498
499	spacemit_i2c_init(i2c);
500
501	spacemit_i2c_enable(i2c);
502
503	ret = spacemit_i2c_wait_bus_idle(i2c);
504	if (!ret) {
505		ret = spacemit_i2c_xfer_msg(i2c);
506		if (ret < 0)
507			dev_dbg(i2c->dev, "i2c transfer error: %d\n", ret);
508	} else {
509		spacemit_i2c_check_bus_release(i2c);
510	}
511
512	spacemit_i2c_disable(i2c);
513
514	if (ret == -ETIMEDOUT || ret == -EAGAIN)
515		dev_err(i2c->dev, "i2c transfer failed, ret %d err 0x%lx\n",
516			  ret, i2c->status & SPACEMIT_SR_ERR);
517
518	return ret < 0 ? ret : num;
519}
520
521static u32 spacemit_i2c_func(struct i2c_adapter *adap)
522{
523	return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
524}
525
526static const struct i2c_algorithm spacemit_i2c_algo = {
527	.xfer = spacemit_i2c_xfer,
528	.functionality = spacemit_i2c_func,
529};
530
531static int spacemit_i2c_probe(struct platform_device *pdev)
532{
533	struct clk *clk;
534	struct device *dev = &pdev->dev;
535	struct device_node *of_node = pdev->dev.of_node;
536	struct spacemit_i2c_dev *i2c;
537	int ret;
538
539	i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
540	if (!i2c)
541		return -ENOMEM;
542
543	ret = of_property_read_u32(of_node, "clock-frequency", &i2c->clock_freq);
544	if (ret && ret != -EINVAL)
545		dev_warn(dev, "failed to read clock-frequency property: %d\n", ret);
546
547	/* For now, this driver doesn't support high-speed. */
548	if (!i2c->clock_freq || i2c->clock_freq > SPACEMIT_I2C_MAX_FAST_MODE_FREQ) {
549		dev_warn(dev, "unsupported clock frequency %u; using %u\n",
550			 i2c->clock_freq, SPACEMIT_I2C_MAX_FAST_MODE_FREQ);
551		i2c->clock_freq = SPACEMIT_I2C_MAX_FAST_MODE_FREQ;
552	} else if (i2c->clock_freq < SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ) {
553		dev_warn(dev, "unsupported clock frequency %u; using %u\n",
554			 i2c->clock_freq,  SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ);
555		i2c->clock_freq = SPACEMIT_I2C_MAX_STANDARD_MODE_FREQ;
556	}
557
558	i2c->dev = &pdev->dev;
559
560	i2c->base = devm_platform_ioremap_resource(pdev, 0);
561	if (IS_ERR(i2c->base))
562		return dev_err_probe(dev, PTR_ERR(i2c->base), "failed to do ioremap");
563
564	i2c->irq = platform_get_irq(pdev, 0);
565	if (i2c->irq < 0)
566		return dev_err_probe(dev, i2c->irq, "failed to get irq resource");
567
568	ret = devm_request_irq(i2c->dev, i2c->irq, spacemit_i2c_irq_handler,
569			       IRQF_NO_SUSPEND, dev_name(i2c->dev), i2c);
570	if (ret)
571		return dev_err_probe(dev, ret, "failed to request irq");
572
573	clk = devm_clk_get_enabled(dev, "func");
574	if (IS_ERR(clk))
575		return dev_err_probe(dev, PTR_ERR(clk), "failed to enable func clock");
576
577	clk = devm_clk_get_enabled(dev, "bus");
578	if (IS_ERR(clk))
579		return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock");
580
581	spacemit_i2c_reset(i2c);
582
583	i2c_set_adapdata(&i2c->adapt, i2c);
584	i2c->adapt.owner = THIS_MODULE;
585	i2c->adapt.algo = &spacemit_i2c_algo;
586	i2c->adapt.dev.parent = i2c->dev;
587	i2c->adapt.nr = pdev->id;
588
589	i2c->adapt.dev.of_node = of_node;
590
591	strscpy(i2c->adapt.name, "spacemit-i2c-adapter", sizeof(i2c->adapt.name));
592
593	init_completion(&i2c->complete);
594
595	platform_set_drvdata(pdev, i2c);
596
597	ret = i2c_add_numbered_adapter(&i2c->adapt);
598	if (ret)
599		return dev_err_probe(&pdev->dev, ret, "failed to add i2c adapter");
600
601	return 0;
602}
603
604static void spacemit_i2c_remove(struct platform_device *pdev)
605{
606	struct spacemit_i2c_dev *i2c = platform_get_drvdata(pdev);
607
608	i2c_del_adapter(&i2c->adapt);
609}
610
611static const struct of_device_id spacemit_i2c_of_match[] = {
612	{ .compatible = "spacemit,k1-i2c", },
613	{ /* sentinel */ }
614};
615MODULE_DEVICE_TABLE(of, spacemit_i2c_of_match);
616
617static struct platform_driver spacemit_i2c_driver = {
618	.probe = spacemit_i2c_probe,
619	.remove = spacemit_i2c_remove,
620	.driver = {
621		.name = "i2c-k1",
622		.of_match_table = spacemit_i2c_of_match,
623	},
624};
625module_platform_driver(spacemit_i2c_driver);
626
627MODULE_LICENSE("GPL");
628MODULE_DESCRIPTION("I2C bus driver for SpacemiT K1 SoC");